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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id d137-20020a63368f000000b00478c48cf73csm4375262pga.82.2023.02.27.13.33.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 13:33:33 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Fabiano Rosas , =?utf-8?q?Philippe?= =?utf-8?q?_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 01/14] target/arm: Normalize aarch64 gdbstub get/set function names Date: Mon, 27 Feb 2023 11:33:16 -1000 Message-Id: <20230227213329.793795-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227213329.793795-1-richard.henderson@linaro.org> References: <20230227213329.793795-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Make the form of the function names between fp and sve the same: - arm_gdb_*_svereg -> aarch64_gdb_*_sve_reg. - aarch64_fpu_gdb_*_reg -> aarch64_gdb_*_fpu_reg. Reviewed-by: Fabiano Rosas Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/internals.h | 8 ++++---- target/arm/gdbstub.c | 9 +++++---- target/arm/gdbstub64.c | 8 ++++---- 3 files changed, 13 insertions(+), 12 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 680c574717..fa21393ebc 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1342,10 +1342,10 @@ static inline uint64_t pmu_counter_mask(CPUARMState *env) } #ifdef TARGET_AARCH64 -int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg); -int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg); -int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg); -int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg); +int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg); +int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg); +int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg); +int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg); void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 2f806512d0..cf1c01e3cf 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -466,12 +466,13 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) */ #ifdef TARGET_AARCH64 if (isar_feature_aa64_sve(&cpu->isar)) { - gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_svereg, - arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs), + int nreg = arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs); + gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg, + aarch64_gdb_set_sve_reg, nreg, "sve-registers.xml", 0); } else { - gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, - aarch64_fpu_gdb_set_reg, + gdb_register_coprocessor(cs, aarch64_gdb_get_fpu_reg, + aarch64_gdb_set_fpu_reg, 34, "aarch64-fpu.xml", 0); } #endif diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 07a6746944..c598cb0375 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -72,7 +72,7 @@ int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) return 0; } -int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) +int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg) { switch (reg) { case 0 ... 31: @@ -92,7 +92,7 @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) } } -int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) +int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg) { switch (reg) { case 0 ... 31: @@ -116,7 +116,7 @@ int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) } } -int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg) +int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg) { ARMCPU *cpu = env_archcpu(env); @@ -164,7 +164,7 @@ int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg) return 0; } -int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg) +int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg) { ARMCPU *cpu = env_archcpu(env); From patchwork Mon Feb 27 21:33:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 657130 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp2584915wrb; Mon, 27 Feb 2023 13:37:11 -0800 (PST) X-Google-Smtp-Source: AK7set/Nu3KcnBWvQBfQAUL/NsKlXLkmOVEEV0eALf4ly5rbjeu2adq4Dy/eJU+9hFFbUSKKUwmc X-Received: by 2002:ad4:4ee6:0:b0:56e:a39f:f060 with SMTP id dv6-20020ad44ee6000000b0056ea39ff060mr2078568qvb.19.1677533830891; Mon, 27 Feb 2023 13:37:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677533830; cv=none; d=google.com; s=arc-20160816; b=p43kkIAICIUxvXU0UzQ32uORs90eMVByCEUqThRkdsxaIVsZByM0ex+PBTiE/K8isn fWjs7ThR+9YZfenFr9CHY801llR5YYGlN8Cc0bVRfr9mGGsdnVL1Ir2uYK1LAe4TbY67 0AZ+KQMIZlj4Br8StkYQVVkD3cu2aaIKqqz2I+oNfhvSahORdx4WMQ7DPYLekXHp86p7 yAxoc3vv/zKzuE9cFzBXs0rQXHOZbu5mylQOuxVihIAopnG9Fpvxxle6UadNYf1JavRZ XXF2fp/KHr+fvQHZQNZpKFn665ceFC9aguWydP5Q548z4c4p4pekFeiwAHjDpTEe3tI1 vEGg== ARC-Message-Signature: i=1; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id d137-20020a63368f000000b00478c48cf73csm4375262pga.82.2023.02.27.13.33.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 13:33:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Fabiano Rosas , =?utf-8?q?Philippe?= =?utf-8?q?_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 02/14] target/arm: Unexport arm_gen_dynamic_sysreg_xml Date: Mon, 27 Feb 2023 11:33:17 -1000 Message-Id: <20230227213329.793795-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227213329.793795-1-richard.henderson@linaro.org> References: <20230227213329.793795-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This function is not used outside gdbstub.c. Reviewed-by: Fabiano Rosas Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/cpu.h | 1 - target/arm/gdbstub.c | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 12b1082537..32ca6c9a0d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1116,7 +1116,6 @@ int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); * Helpers to dynamically generates XML descriptions of the sysregs * and SVE registers. Returns the number of registers in each set. */ -int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg); int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); /* Returns the dynamically generated XML for the gdb stub. diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index cf1c01e3cf..52581e9784 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -305,7 +305,7 @@ static void arm_register_sysreg_for_xml(gpointer key, gpointer value, } } -int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg) +static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg) { ARMCPU *cpu = ARM_CPU(cs); GString *s = g_string_new(NULL); From patchwork Mon Feb 27 21:33:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 657131 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp2584956wrb; Mon, 27 Feb 2023 13:37:15 -0800 (PST) X-Google-Smtp-Source: AK7set8Xt7L8WxE7pIOovGuCix+3gzKCawHe2lZuDSRjxFHheO08K+aMAV8y1BeJy9jW0q/bikK/ X-Received: by 2002:a05:622a:14d2:b0:3bf:ce2f:576c with SMTP id u18-20020a05622a14d200b003bfce2f576cmr1037168qtx.66.1677533835809; Mon, 27 Feb 2023 13:37:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677533835; cv=none; d=google.com; s=arc-20160816; b=XfvcOl3YoZMr9p49R/xo7A24RfxezORqrKfLz62/Eer6bWIUDIo1zmt8kJk1gApjkQ RL8c+rvpAlotRJIdTzhheffCCL4HWU3XiwGYn3DJs4rYJZpZvf+SCFS/xQQ55BOpeo9o mPOR0KCib8QN5wkaM5R1EIgcFZS9NXMMpc9iOprOelm9ZZlVSfqlicaY764oCk8pfGwH fyGXjqOueiom7a21ieSlwUj4y2N637VMH5mpXTtuyL27wgZjEUUNCyqtWWQU+VK5iKLI +e1m+Du6nHIOUnbeJ4FM4Lqf2RX3Jk6dNo066+Ws2oE43DzoXrk5Jq5CWC6VnnFJBQpC LdKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=S1Xf3inqsr/wtX3faUEiH0u2ljaxoLVvIIynuke4Aqg=; b=BuMk7wHwfuuw7xJhh/X1RclktvV148bzSKRoosKSk2Bhn2hMnKrp4jixnDc+aRR5+r 0tYX6DC2PvTJ3QXCVALfUYJ/116Dp7ATQWVJWxpMnhNReUBqo2rYwQ0oxJKuwo9h/U57 EzlN+M425vJ+ASqrJQ1XTJkyFOGzTm1hKoXIj7TCyyrFNlv98vvjdzqo+CyDj1PWthgr bhF5F7hk3bPuXvyhqM9peqt7ECf3ysVgjLvwOzYGmC173tycfn5RVQpX1wdKVpcragT9 j1q5hDqkA41GEfE0rXPppEFJ5wfe9tldsy2guQrmj/e2I024DXWtkNTiSIc0s1/qcauz N5TQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=C2GGY3bf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id d137-20020a63368f000000b00478c48cf73csm4375262pga.82.2023.02.27.13.33.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 13:33:36 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Fabiano Rosas , =?utf-8?q?Philippe?= =?utf-8?q?_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 03/14] target/arm: Move arm_gen_dynamic_svereg_xml to gdbstub64.c Date: Mon, 27 Feb 2023 11:33:18 -1000 Message-Id: <20230227213329.793795-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227213329.793795-1-richard.henderson@linaro.org> References: <20230227213329.793795-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The function is only used for aarch64, so move it to the file that has the other aarch64 gdbstub stuff. Move the declaration to internals.h. Reviewed-by: Fabiano Rosas Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/cpu.h | 6 --- target/arm/internals.h | 1 + target/arm/gdbstub.c | 120 ----------------------------------------- target/arm/gdbstub64.c | 118 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 119 insertions(+), 126 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 32ca6c9a0d..059fe62eaa 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1112,12 +1112,6 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -/* - * Helpers to dynamically generates XML descriptions of the sysregs - * and SVE registers. Returns the number of registers in each set. - */ -int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); - /* Returns the dynamically generated XML for the gdb stub. * Returns a pointer to the XML contents for the specified XML file or NULL * if the XML name doesn't match the predefined one. diff --git a/target/arm/internals.h b/target/arm/internals.h index fa21393ebc..725244d72d 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1342,6 +1342,7 @@ static inline uint64_t pmu_counter_mask(CPUARMState *env) } #ifdef TARGET_AARCH64 +int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg); int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg); int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg); diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 52581e9784..bf8aff7824 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -322,126 +322,6 @@ static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg) return cpu->dyn_sysreg_xml.num; } -struct TypeSize { - const char *gdb_type; - int size; - const char sz, suffix; -}; - -static const struct TypeSize vec_lanes[] = { - /* quads */ - { "uint128", 128, 'q', 'u' }, - { "int128", 128, 'q', 's' }, - /* 64 bit */ - { "ieee_double", 64, 'd', 'f' }, - { "uint64", 64, 'd', 'u' }, - { "int64", 64, 'd', 's' }, - /* 32 bit */ - { "ieee_single", 32, 's', 'f' }, - { "uint32", 32, 's', 'u' }, - { "int32", 32, 's', 's' }, - /* 16 bit */ - { "ieee_half", 16, 'h', 'f' }, - { "uint16", 16, 'h', 'u' }, - { "int16", 16, 'h', 's' }, - /* bytes */ - { "uint8", 8, 'b', 'u' }, - { "int8", 8, 'b', 's' }, -}; - - -int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) -{ - ARMCPU *cpu = ARM_CPU(cs); - GString *s = g_string_new(NULL); - DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; - g_autoptr(GString) ts = g_string_new(""); - int i, j, bits, reg_width = (cpu->sve_max_vq * 128); - info->num = 0; - g_string_printf(s, ""); - g_string_append_printf(s, ""); - g_string_append_printf(s, ""); - - /* First define types and totals in a whole VL */ - for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { - int count = reg_width / vec_lanes[i].size; - g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix); - g_string_append_printf(s, - "", - ts->str, vec_lanes[i].gdb_type, count); - } - /* - * Now define a union for each size group containing unsigned and - * signed and potentially float versions of each size from 128 to - * 8 bits. - */ - for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { - const char suf[] = { 'q', 'd', 's', 'h', 'b' }; - g_string_append_printf(s, "", suf[i]); - for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) { - if (vec_lanes[j].size == bits) { - g_string_append_printf(s, "", - vec_lanes[j].suffix, - vec_lanes[j].sz, vec_lanes[j].suffix); - } - } - g_string_append(s, ""); - } - /* And now the final union of unions */ - g_string_append(s, ""); - for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { - const char suf[] = { 'q', 'd', 's', 'h', 'b' }; - g_string_append_printf(s, "", - suf[i], suf[i]); - } - g_string_append(s, ""); - - /* Finally the sve prefix type */ - g_string_append_printf(s, - "", - reg_width / 8); - - /* Then define each register in parts for each vq */ - for (i = 0; i < 32; i++) { - g_string_append_printf(s, - "", - i, reg_width, base_reg++); - info->num++; - } - /* fpscr & status registers */ - g_string_append_printf(s, "", base_reg++); - g_string_append_printf(s, "", base_reg++); - info->num += 2; - - for (i = 0; i < 16; i++) { - g_string_append_printf(s, - "", - i, cpu->sve_max_vq * 16, base_reg++); - info->num++; - } - g_string_append_printf(s, - "", - cpu->sve_max_vq * 16, base_reg++); - g_string_append_printf(s, - "", - base_reg++); - info->num += 2; - g_string_append_printf(s, ""); - cpu->dyn_svereg_xml.desc = g_string_free(s, false); - - return cpu->dyn_svereg_xml.num; -} - - const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) { ARMCPU *cpu = ARM_CPU(cs); diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index c598cb0375..59fb5465d5 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -209,3 +209,121 @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg) return 0; } + +struct TypeSize { + const char *gdb_type; + short size; + char sz, suffix; +}; + +static const struct TypeSize vec_lanes[] = { + /* quads */ + { "uint128", 128, 'q', 'u' }, + { "int128", 128, 'q', 's' }, + /* 64 bit */ + { "ieee_double", 64, 'd', 'f' }, + { "uint64", 64, 'd', 'u' }, + { "int64", 64, 'd', 's' }, + /* 32 bit */ + { "ieee_single", 32, 's', 'f' }, + { "uint32", 32, 's', 'u' }, + { "int32", 32, 's', 's' }, + /* 16 bit */ + { "ieee_half", 16, 'h', 'f' }, + { "uint16", 16, 'h', 'u' }, + { "int16", 16, 'h', 's' }, + /* bytes */ + { "uint8", 8, 'b', 'u' }, + { "int8", 8, 'b', 's' }, +}; + +int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) +{ + ARMCPU *cpu = ARM_CPU(cs); + GString *s = g_string_new(NULL); + DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; + g_autoptr(GString) ts = g_string_new(""); + int i, j, bits, reg_width = (cpu->sve_max_vq * 128); + info->num = 0; + g_string_printf(s, ""); + g_string_append_printf(s, ""); + g_string_append_printf(s, ""); + + /* First define types and totals in a whole VL */ + for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { + int count = reg_width / vec_lanes[i].size; + g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix); + g_string_append_printf(s, + "", + ts->str, vec_lanes[i].gdb_type, count); + } + /* + * Now define a union for each size group containing unsigned and + * signed and potentially float versions of each size from 128 to + * 8 bits. + */ + for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { + const char suf[] = { 'q', 'd', 's', 'h', 'b' }; + g_string_append_printf(s, "", suf[i]); + for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) { + if (vec_lanes[j].size == bits) { + g_string_append_printf(s, "", + vec_lanes[j].suffix, + vec_lanes[j].sz, vec_lanes[j].suffix); + } + } + g_string_append(s, ""); + } + /* And now the final union of unions */ + g_string_append(s, ""); + for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { + const char suf[] = { 'q', 'd', 's', 'h', 'b' }; + g_string_append_printf(s, "", + suf[i], suf[i]); + } + g_string_append(s, ""); + + /* Finally the sve prefix type */ + g_string_append_printf(s, + "", + reg_width / 8); + + /* Then define each register in parts for each vq */ + for (i = 0; i < 32; i++) { + g_string_append_printf(s, + "", + i, reg_width, base_reg++); + info->num++; + } + /* fpscr & status registers */ + g_string_append_printf(s, "", base_reg++); + g_string_append_printf(s, "", base_reg++); + info->num += 2; + + for (i = 0; i < 16; i++) { + g_string_append_printf(s, + "", + i, cpu->sve_max_vq * 16, base_reg++); + info->num++; + } + g_string_append_printf(s, + "", + cpu->sve_max_vq * 16, base_reg++); + g_string_append_printf(s, + "", + base_reg++); + info->num += 2; + g_string_append_printf(s, ""); + info->desc = g_string_free(s, false); + + return info->num; +} From patchwork Mon Feb 27 21:33:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 657129 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp2584869wrb; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id d137-20020a63368f000000b00478c48cf73csm4375262pga.82.2023.02.27.13.33.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 13:33:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Fabiano Rosas , Peter Maydell Subject: [PATCH v3 04/14] target/arm: Split out output_vector_union_type Date: Mon, 27 Feb 2023 11:33:19 -1000 Message-Id: <20230227213329.793795-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227213329.793795-1-richard.henderson@linaro.org> References: <20230227213329.793795-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Create a subroutine for creating the union of unions of the various type sizes that a vector may contain. Reviewed-by: Fabiano Rosas Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/gdbstub64.c | 83 +++++++++++++++++++++++------------------- 1 file changed, 45 insertions(+), 38 deletions(-) diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 59fb5465d5..811833d8de 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -210,44 +210,39 @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg) return 0; } -struct TypeSize { - const char *gdb_type; - short size; - char sz, suffix; -}; - -static const struct TypeSize vec_lanes[] = { - /* quads */ - { "uint128", 128, 'q', 'u' }, - { "int128", 128, 'q', 's' }, - /* 64 bit */ - { "ieee_double", 64, 'd', 'f' }, - { "uint64", 64, 'd', 'u' }, - { "int64", 64, 'd', 's' }, - /* 32 bit */ - { "ieee_single", 32, 's', 'f' }, - { "uint32", 32, 's', 'u' }, - { "int32", 32, 's', 's' }, - /* 16 bit */ - { "ieee_half", 16, 'h', 'f' }, - { "uint16", 16, 'h', 'u' }, - { "int16", 16, 'h', 's' }, - /* bytes */ - { "uint8", 8, 'b', 'u' }, - { "int8", 8, 'b', 's' }, -}; - -int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) +static void output_vector_union_type(GString *s, int reg_width) { - ARMCPU *cpu = ARM_CPU(cs); - GString *s = g_string_new(NULL); - DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; + struct TypeSize { + const char *gdb_type; + short size; + char sz, suffix; + }; + + static const struct TypeSize vec_lanes[] = { + /* quads */ + { "uint128", 128, 'q', 'u' }, + { "int128", 128, 'q', 's' }, + /* 64 bit */ + { "ieee_double", 64, 'd', 'f' }, + { "uint64", 64, 'd', 'u' }, + { "int64", 64, 'd', 's' }, + /* 32 bit */ + { "ieee_single", 32, 's', 'f' }, + { "uint32", 32, 's', 'u' }, + { "int32", 32, 's', 's' }, + /* 16 bit */ + { "ieee_half", 16, 'h', 'f' }, + { "uint16", 16, 'h', 'u' }, + { "int16", 16, 'h', 's' }, + /* bytes */ + { "uint8", 8, 'b', 'u' }, + { "int8", 8, 'b', 's' }, + }; + + static const char suf[] = { 'q', 'd', 's', 'h', 'b' }; + g_autoptr(GString) ts = g_string_new(""); - int i, j, bits, reg_width = (cpu->sve_max_vq * 128); - info->num = 0; - g_string_printf(s, ""); - g_string_append_printf(s, ""); - g_string_append_printf(s, ""); + int i, j, bits; /* First define types and totals in a whole VL */ for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { @@ -263,7 +258,6 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) * 8 bits. */ for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { - const char suf[] = { 'q', 'd', 's', 'h', 'b' }; g_string_append_printf(s, "", suf[i]); for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) { if (vec_lanes[j].size == bits) { @@ -277,11 +271,24 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) /* And now the final union of unions */ g_string_append(s, ""); for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { - const char suf[] = { 'q', 'd', 's', 'h', 'b' }; g_string_append_printf(s, "", suf[i], suf[i]); } g_string_append(s, ""); +} + +int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) +{ + ARMCPU *cpu = ARM_CPU(cs); + GString *s = g_string_new(NULL); + DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; + int i, reg_width = (cpu->sve_max_vq * 128); + info->num = 0; + g_string_printf(s, ""); + g_string_append_printf(s, ""); + g_string_append_printf(s, ""); + + output_vector_union_type(s, reg_width); /* Finally the sve prefix type */ g_string_append_printf(s, From patchwork Mon Feb 27 21:33:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 657121 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp2584160wrb; Mon, 27 Feb 2023 13:35:14 -0800 (PST) X-Google-Smtp-Source: AK7set9yRHJLYFU7qNAPAv90bB5ZAl/p59Hg4TbzBcKN+iw1hJZO6/HVkqYDUkAWokDbwBblsOyn X-Received: by 2002:a05:6214:1d29:b0:56f:47f:bbe3 with SMTP id f9-20020a0562141d2900b0056f047fbbe3mr1982324qvd.4.1677533714462; Mon, 27 Feb 2023 13:35:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677533714; cv=none; d=google.com; s=arc-20160816; b=u4azvbEH4bFdXdxS4QeGKIJd2CWGbPlRF6lZ8eXGX5edYzxnjRvsrUi6vhSqd3mEb6 z9k8fvXFvOCkT5+J/IQ1FtxAVGA+QrQfLHyQK/TSun6KDkXzIAYzq0xxJDgj3jXrRpPy 7nT8+sLri6uVCkd5kvSmf17P7zMFYJ8Yq+jtny7MsD/CsYWboNz87f+/PeW89WB+7kzn 5ZkrXAikkpNzhZnRapFEXWON9tcJNgFwDdFUHZsw2DaILBBQeeeqQD55N6mD5drGM+HP TgmTFfhARNL1VsrlhGWna6g1Jkz4dHa/Bc+e6WoftKH9Q02pF71NlxSSb5eUL0vaDAd9 +FkA== ARC-Message-Signature: i=1; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id d137-20020a63368f000000b00478c48cf73csm4375262pga.82.2023.02.27.13.33.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 13:33:39 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 05/14] target/arm: Simplify register counting in arm_gen_dynamic_svereg_xml Date: Mon, 27 Feb 2023 11:33:20 -1000 Message-Id: <20230227213329.793795-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227213329.793795-1-richard.henderson@linaro.org> References: <20230227213329.793795-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Rather than increment base_reg and num, compute num from the change to base_reg at the end. Clean up some nearby comments. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/gdbstub64.c | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 811833d8de..070ba20d99 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -277,32 +277,35 @@ static void output_vector_union_type(GString *s, int reg_width) g_string_append(s, ""); } -int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) +int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg) { ARMCPU *cpu = ARM_CPU(cs); GString *s = g_string_new(NULL); DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; - int i, reg_width = (cpu->sve_max_vq * 128); - info->num = 0; + int reg_width = cpu->sve_max_vq * 128; + int base_reg = orig_base_reg; + int i; + g_string_printf(s, ""); g_string_append_printf(s, ""); g_string_append_printf(s, ""); + /* Create the vector union type. */ output_vector_union_type(s, reg_width); - /* Finally the sve prefix type */ + /* Create the predicate vector type. */ g_string_append_printf(s, "", reg_width / 8); - /* Then define each register in parts for each vq */ + /* Define the vector registers. */ for (i = 0; i < 32; i++) { g_string_append_printf(s, "", i, reg_width, base_reg++); - info->num++; } + /* fpscr & status registers */ g_string_append_printf(s, "", base_reg++); - info->num += 2; + /* Define the predicate registers. */ for (i = 0; i < 16; i++) { g_string_append_printf(s, "", i, cpu->sve_max_vq * 16, base_reg++); - info->num++; } g_string_append_printf(s, "", cpu->sve_max_vq * 16, base_reg++); + + /* Define the vector length pseudo-register. */ g_string_append_printf(s, "", base_reg++); - info->num += 2; - g_string_append_printf(s, ""); - info->desc = g_string_free(s, false); + g_string_append_printf(s, ""); + + info->desc = g_string_free(s, false); + info->num = base_reg - orig_base_reg; return info->num; } From patchwork Mon Feb 27 21:33:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 657120 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp2584158wrb; Mon, 27 Feb 2023 13:35:14 -0800 (PST) X-Google-Smtp-Source: AK7set97BnuBLoiQtvu0P7oozI+M9XNq+5VO3xL46Uo/LuJZSI+Da7hxYYxuzBKokqRGaEWvqKkB X-Received: by 2002:a05:6214:1313:b0:537:7bd7:29d4 with SMTP id pn19-20020a056214131300b005377bd729d4mr1977185qvb.47.1677533714391; Mon, 27 Feb 2023 13:35:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677533714; cv=none; d=google.com; s=arc-20160816; b=SDrPjhUQZnGxjsiLsGPCqzn2DBNj3c2RPIpROWgwPtIWH/VtnUvVQTikZ/IRerqQJf s6fwIo33zlwdtZOuZXP/WmghXGuA8mmGlL+X8Ahg02mM7FudIO//iaBGZpeC6Zo8SwNU 8OZJ2jl9Ahsl9ctBMUoMgRx64JRx7L99cS/DWaXZtO0rvtOaILKlANou9oWYYEzvcUyy x4bohYXatTh9iVArm8TuGoiXnkOEnXvcfKtmFs4awkVbdnqVdgCsbTdShs48tWboazif Dcm1eqe9WKBzdWhEuiNah7+eIgpmsPJsio0hIe4XjMZz9VZb9ODdTkztPuaolKBiIqsZ TF3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=FVJHbUykgOVOv7t67KB4t0GKsC8KJ/J9KiSQxpR45pA=; b=OJ9rrgZYzFTUJ7/votr8O7qhATnyq7OUJ8aLTvt3q4zcM5rgGBO3DqDsa5A/2x7MF4 HBPzfNMxwUHLN6MazxnFIJtLyYH7iIIFjoXGKmL2p+Rv0CotDUD3xXhbiLOCP0JK5QX2 dLdmYqr9blo+bxymFtlV4Z4vFht8AocWZANAwX1Q/cX3ppvK1xY/F7OgSh9iB6UpqYib CaEv1o/ba7ctZKl2uF+2g+x4xGyH41af9mQvc7Xc0oFuBCa1zGWiu2zuD4AIrpdoujUh YZTPQrWFyccRYwQVfoO8WdC+XNJh8BsfrucRwTO2X3M4uahAzHp5VtHNSp86OpOseNFE 4xgQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=agjmA4MT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id d137-20020a63368f000000b00478c48cf73csm4375262pga.82.2023.02.27.13.33.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 13:33:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Fabiano Rosas , =?utf-8?q?Philippe?= =?utf-8?q?_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 06/14] target/arm: Hoist pred_width in arm_gen_dynamic_svereg_xml Date: Mon, 27 Feb 2023 11:33:21 -1000 Message-Id: <20230227213329.793795-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227213329.793795-1-richard.henderson@linaro.org> References: <20230227213329.793795-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Reviewed-by: Fabiano Rosas Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/gdbstub64.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 070ba20d99..895e19f084 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -283,6 +283,7 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg) GString *s = g_string_new(NULL); DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; int reg_width = cpu->sve_max_vq * 128; + int pred_width = cpu->sve_max_vq * 16; int base_reg = orig_base_reg; int i; @@ -319,13 +320,13 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg) g_string_append_printf(s, "", - i, cpu->sve_max_vq * 16, base_reg++); + i, pred_width, base_reg++); } g_string_append_printf(s, "", - cpu->sve_max_vq * 16, base_reg++); + pred_width, base_reg++); /* Define the vector length pseudo-register. */ g_string_append_printf(s, From patchwork Mon Feb 27 21:33:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 657118 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp2584000wrb; Mon, 27 Feb 2023 13:34:42 -0800 (PST) X-Google-Smtp-Source: AK7set+KDXsPPAVAEOeGAKgPWR2L9qBFvupw+7JKmT4Y7PwMaPRu6ZBBfwkraNa7G0OAfEvul9Md X-Received: by 2002:a05:622a:178c:b0:3bf:d149:8966 with SMTP id s12-20020a05622a178c00b003bfd1498966mr1113298qtk.62.1677533682240; Mon, 27 Feb 2023 13:34:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677533682; cv=none; d=google.com; s=arc-20160816; b=WljRvvwe7Q9FqdfXcfa1kNn8x155o1H3y5o1Z0YVTf3eBDyJnxHeMvsafE/t6TLD6G tcvhDiPddIi75k3ZPTGIiZxZKkB06werMDfcsdk0h6Dc2tD1SjevQcSnl66PW1ePb1nR zvfUzZpHi94A2HwJd6D/82XztnRxPb8J6AsUCrCOcEKGBvJi7uyVW0+mzdXCKYRZkGIc wl4newugR3ccnIuWxjvuiGIN4g7qvQBdzPQhFXCDuavqF7bfec6U0oB94kYLgZbBZqNE jirfmL9KERsd3ZfNaq1YgmG0fKiugIUBeNpdJ7QywpYp/z2tu/sz75Vr0rsqY8cUAEPx QVvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=atup5JzD1u28pHb0Z+S8hkpRI38cVehaAA91hoO5SKs=; b=iaL7brtj8HTGv3duXX8dJtDtKVb3xYHq5ZYwajrYjdx5fW21SEepqaqg01mR3zbzUA T3Bz0rjG6RfYGh+zbN8SBuKlL6KDemZdeFL7l535pvD5Sf/5lEuhvfo3qB7pSRX3uYD+ /p6Y0jenQc6H8M/JXSct83Q0tum/ctPe0Qq7rdMlnrmOSyt3PNZybTxfPqeaYY9QRLiM 27ph37rNS8rsQe7OGxi9vg5fph+1wUxHxy4h2wJgNWN0FKP+Yzd95zb8WPzvEm6nMQTc 0DcQilAZ0A26J16/Qxj6jxenZvV/D9AL8ntChWrTSQwF9Pvc+ZPE/q5cQ5z31uhpPGI0 RY8A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=twBrrDzk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id d137-20020a63368f000000b00478c48cf73csm4375262pga.82.2023.02.27.13.33.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 13:33:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 07/14] target/arm: Fix svep width in arm_gen_dynamic_svereg_xml Date: Mon, 27 Feb 2023 11:33:22 -1000 Message-Id: <20230227213329.793795-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227213329.793795-1-richard.henderson@linaro.org> References: <20230227213329.793795-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Define svep based on the size of the predicates, not the primary vector registers. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/gdbstub64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 895e19f084..d0e1305f6f 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -297,7 +297,7 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg) /* Create the predicate vector type. */ g_string_append_printf(s, "", - reg_width / 8); + pred_width / 8); /* Define the vector registers. */ for (i = 0; i < 32; i++) { From patchwork Mon Feb 27 21:33:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 657119 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp2584118wrb; Mon, 27 Feb 2023 13:35:07 -0800 (PST) X-Google-Smtp-Source: AK7set89L63LMYE3WJ6adkUMlTyKJGxe55Ge0WahjcEf7YSjwHyzJRdbDomlAVLqGy2Dv1WHx3Ft X-Received: by 2002:ac8:5b81:0:b0:3b8:6ca4:bb23 with SMTP id a1-20020ac85b81000000b003b86ca4bb23mr1450619qta.15.1677533707389; Mon, 27 Feb 2023 13:35:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677533707; cv=none; d=google.com; s=arc-20160816; b=IwwLOhHpRwVf0m+FJ/RK/dBgxCB6bnKiXoh1jpD1x6haibEm/w/KnXmy1jb8rjXzpB oJPn0pqluvbXsjKkmeFvB+A2mjmAlij0VbKIa7QXjNFjMTTHr8pTFy/lDhZW2TeCOpBv ZVZrZXHlV86BacmCBGRFTfGnYKmIuuibxn9FA8eCg7FDsyo0Kcf7WsooGLf/oagq3jTH al3vbA2VcHUOOKUpgEQBg0/ce5gwrD11uaUU8QXCsF0OSnbAu/zkdkhVzJKe87oeGC4l mRwc+HQfH99wOLTbtBJ/dJdneGFg87tXN5HvYqw0TKePwBl4yYtgd/g7DdPW519Lqkjs vxlw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=nOAolGlh8kDAOh/uhG+3SdQD/T+2gl27uDkMfKRTxeI=; b=MFApyO3O5K/FoVN6N/Lm11L1MH8WIb/yqRx++G1G7FpvpVIjTpUIxDl+sygILcjgRb yKUMvJxy65L6AdriwHKbtoTKPCO3fSVZmXCMfVX9wqEobhLfio34rszlCc0MzRcXFUm3 U3UtjH0BnbRAbh+/qY4dK0FL32IyRosaysRYzg5j1+X4+Sgybx8lMY6O5tydpOhmCF6q cigIfuxZTzLxyScMn6/Uc1Bv9TtEvd45BO7m+3gSrg+ZNa/01aOto6Rzr1+vvG+2NXj5 mRljkJIfZ1ZSn1S3Xg+zAKfp5R7T6gJOm47Rl93fKND+DRIoBHhNSRSryb4HvVrudGP5 cPlQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jdfw+yjb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id d137-20020a63368f000000b00478c48cf73csm4375262pga.82.2023.02.27.13.33.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 13:33:44 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 08/14] target/arm: Add name argument to output_vector_union_type Date: Mon, 27 Feb 2023 11:33:23 -1000 Message-Id: <20230227213329.793795-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227213329.793795-1-richard.henderson@linaro.org> References: <20230227213329.793795-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This will make the function usable between SVE and SME. Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/gdbstub64.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index d0e1305f6f..36166bf81e 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -210,7 +210,8 @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg) return 0; } -static void output_vector_union_type(GString *s, int reg_width) +static void output_vector_union_type(GString *s, int reg_width, + const char *name) { struct TypeSize { const char *gdb_type; @@ -240,39 +241,38 @@ static void output_vector_union_type(GString *s, int reg_width) }; static const char suf[] = { 'q', 'd', 's', 'h', 'b' }; - - g_autoptr(GString) ts = g_string_new(""); int i, j, bits; /* First define types and totals in a whole VL */ for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { - int count = reg_width / vec_lanes[i].size; - g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix); g_string_append_printf(s, - "", - ts->str, vec_lanes[i].gdb_type, count); + "", + name, vec_lanes[i].sz, vec_lanes[i].suffix, + vec_lanes[i].gdb_type, reg_width / vec_lanes[i].size); } + /* * Now define a union for each size group containing unsigned and * signed and potentially float versions of each size from 128 to * 8 bits. */ for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { - g_string_append_printf(s, "", suf[i]); + g_string_append_printf(s, "", name, suf[i]); for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) { if (vec_lanes[j].size == bits) { - g_string_append_printf(s, "", - vec_lanes[j].suffix, + g_string_append_printf(s, "", + vec_lanes[j].suffix, name, vec_lanes[j].sz, vec_lanes[j].suffix); } } g_string_append(s, ""); } + /* And now the final union of unions */ - g_string_append(s, ""); + g_string_append_printf(s, "", name); for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { - g_string_append_printf(s, "", - suf[i], suf[i]); + g_string_append_printf(s, "", + suf[i], name, suf[i]); } g_string_append(s, ""); } @@ -292,7 +292,7 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg) g_string_append_printf(s, ""); /* Create the vector union type. */ - output_vector_union_type(s, reg_width); + output_vector_union_type(s, reg_width, "svev"); /* Create the predicate vector type. */ g_string_append_printf(s, From patchwork Mon Feb 27 21:33:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 657123 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp2584360wrb; Mon, 27 Feb 2023 13:35:42 -0800 (PST) X-Google-Smtp-Source: AK7set9nyspyyPyTShjJQNkt88uAr4+g5NFHi4MMbJuuFOLeYWCeOUtzEm0mRhYiVsntlPd1x9Jm X-Received: by 2002:ac8:58c3:0:b0:3b8:6824:e3ef with SMTP id u3-20020ac858c3000000b003b86824e3efmr1211370qta.48.1677533742270; Mon, 27 Feb 2023 13:35:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677533742; cv=none; d=google.com; s=arc-20160816; b=jaZj5neDfuUjugMmCyLAXuCugeEkEQcSUuz7vjj49xOAm/K7dw1vrBIseQEpUfj1Pj CKf3HpSCiKhQIKrSGGCU1HbTDxdj0CA3hjxnfQyhfpERcTjvwqo41/t8VMRJkUisUhji ie96JFpym6Z3TT8IV7GIB42DgHICSGGYM0+9MknyOpG6jJ4WBJWwZJecZh4otydxgdVT /taHEZ2jhkO9Iz7nQfeKD1XRjU2BuMhEDTYvMVdmgE0/G341WqwyGlfv1G3QdyJtu9wv WGBMe4ePg1GBLRDWx/ru1gk8tyZ4EZIIxTx1X/VGkLRa4szzSGeTOVXE4GS1cWPT87OZ xy+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ktLcLczpC5J61u+Wz7S4IYVLAaoqvKihU89wRw7bX20=; b=gOWrwPGJ6/1pOSNpJm4MeTVBi16ZDq1nWMBA5JTOe28nklPpVyYPDDYfhhTchKBsIL 0N8fhsiN3nK/7sGmVhTXRP/VMOKBzDNmAzxYEtPQyN6zSJVG1Rdj31espwLu8EBCZSxx aMUAbNw+J4xdtUKXvf63F/FKX3TK7aOvgdNfE8xK+D/ugKvqOD6XaB72cnrC4bx/aNJn 9QRnZPnhV13wJyyG7IdffK64CAUT+eUltjfGr3XDDAfoA4KLlMMwcuzvKR2HoETvfmAR QbC7rkBEU1zJdgXHSist+hoq3xuBh7pCdCX5nL3yJqiiARsqMtDaklyXiUINB4rqoqeq CVpA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=p63P1GiZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id d137-20020a63368f000000b00478c48cf73csm4375262pga.82.2023.02.27.13.33.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 13:33:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 09/14] target/arm: Simplify iteration over bit widths Date: Mon, 27 Feb 2023 11:33:24 -1000 Message-Id: <20230227213329.793795-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227213329.793795-1-richard.henderson@linaro.org> References: <20230227213329.793795-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Order suf[] by the log8 of the width. Use ARRAY_SIZE instead of hard-coding 128. This changes the order of the union definitions, but retains the order of the union-of-union members. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/gdbstub64.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 36166bf81e..3d9e9e97c8 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -240,8 +240,8 @@ static void output_vector_union_type(GString *s, int reg_width, { "int8", 8, 'b', 's' }, }; - static const char suf[] = { 'q', 'd', 's', 'h', 'b' }; - int i, j, bits; + static const char suf[] = { 'b', 'h', 's', 'd', 'q' }; + int i, j; /* First define types and totals in a whole VL */ for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { @@ -256,7 +256,9 @@ static void output_vector_union_type(GString *s, int reg_width, * signed and potentially float versions of each size from 128 to * 8 bits. */ - for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { + for (i = 0; i < ARRAY_SIZE(suf); i++) { + int bits = 8 << i; + g_string_append_printf(s, "", name, suf[i]); for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) { if (vec_lanes[j].size == bits) { @@ -270,7 +272,7 @@ static void output_vector_union_type(GString *s, int reg_width, /* And now the final union of unions */ g_string_append_printf(s, "", name); - for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { + for (i = ARRAY_SIZE(suf) - 1; i >= 0; i--) { g_string_append_printf(s, "", suf[i], name, suf[i]); } From patchwork Mon Feb 27 21:33:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 657124 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp2584703wrb; Mon, 27 Feb 2023 13:36:38 -0800 (PST) X-Google-Smtp-Source: AK7set8dcVewKl+1Pggy4kqvym9zdhReW27R9ma7U88sATkFG6CUR+orXjq4/LsVUyKMI3m9Lq6x X-Received: by 2002:a05:622a:30b:b0:3bf:d9f3:debe with SMTP id q11-20020a05622a030b00b003bfd9f3debemr1002796qtw.59.1677533797919; Mon, 27 Feb 2023 13:36:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677533797; cv=none; d=google.com; s=arc-20160816; b=BFejv/y5e07fLh9rv8AvxQt8nerIyvxF8Cz0xXxGP2pZJssqF7jrbOiXSioIz+LaYU b3YTs35f3dpZZDsfhf6aJovU95u5jjOmciD/EiGYTwX4ens9yT/IWgYvOG8epf2FlzRS Wsi0B04uuYvfieaJ5CveMoGH5aSeOL6knWExgdaDGmbrUxp1bFVnmXN9lf07VR2kkVnV kyfoQkd3xkV2oc0yct0QsGB77YcncPaEqfbV2rChci9dzSSVxeIazF/dBAr+4yTwo8+7 TaI+LaPXPWeAurn34XuJjzW84XTsgoiJVGSYnthTGwoELyKX6+jLhD34PscOUfXw71kD 06cg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=MvN6MH9XtbRDVN7/usi5kmILWEamfWIGeSaIRJTwC88=; b=v2wwD5xghvB7UcnRLhEyscgqmbB1f+G/2ymEX0AoOd5ikeSBJq/d2DS4lXhPfxjOad JUoNmUmUzc5QhdLSSeMu9AyfPb0IPGnq5gtJ20w+wARbu95EwKmKJ0PyojotipqPvy0B rSi0u/rKhddvnoC3zpgofrsGSVdd/81nLnzteQGwd1nsMSL1YhzjzC89J4630mw1hdld gf61ZZ6QGUTZjvG6SEj5XdJUp9sSpSz8W6R2fQVNXZKz2XtRYN6NB+knZGdhkzcfRjrx ryCMRuuQ61gX720xNWNqfXpG5lZceV2KLvPaYXeaQTVr/YkMxNN1UmcdazlGV47y8dv2 rMLQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=n0wJg8do; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id d137-20020a63368f000000b00478c48cf73csm4375262pga.82.2023.02.27.13.33.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 13:33:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 10/14] target/arm: Create pauth_ptr_mask Date: Mon, 27 Feb 2023 11:33:25 -1000 Message-Id: <20230227213329.793795-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227213329.793795-1-richard.henderson@linaro.org> References: <20230227213329.793795-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Keep the logic for pauth within pauth_helper.c, and expose a helper function for use with the gdbstub pac extension. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 10 ++++++++++ target/arm/tcg/pauth_helper.c | 26 ++++++++++++++++++++++---- 2 files changed, 32 insertions(+), 4 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 725244d72d..c02dd59743 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1366,6 +1366,16 @@ int exception_target_el(CPUARMState *env); bool arm_singlestep_active(CPUARMState *env); bool arm_generate_debug_exceptions(CPUARMState *env); +/** + * pauth_ptr_mask: + * @env: cpu context + * @ptr: selects between TTBR0 and TTBR1 + * @data: selects between TBI and TBID + * + * Return a mask of the bits of @ptr that contain the authentication code. + */ +uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data); + /* Add the cpreg definitions for debug related system registers */ void define_debug_regs(ARMCPU *cpu); diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c index d0483bf051..20f347332d 100644 --- a/target/arm/tcg/pauth_helper.c +++ b/target/arm/tcg/pauth_helper.c @@ -339,14 +339,32 @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, return pac | ext | ptr; } -static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param) +static uint64_t pauth_ptr_mask_internal(ARMVAParameters param) { - /* Note that bit 55 is used whether or not the regime has 2 ranges. */ - uint64_t extfield = sextract64(ptr, 55, 1); int bot_pac_bit = 64 - param.tsz; int top_pac_bit = 64 - 8 * param.tbi; - return deposit64(ptr, bot_pac_bit, top_pac_bit - bot_pac_bit, extfield); + return MAKE_64BIT_MASK(bot_pac_bit, top_pac_bit - bot_pac_bit); +} + +static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param) +{ + uint64_t mask = pauth_ptr_mask_internal(param); + + /* Note that bit 55 is used whether or not the regime has 2 ranges. */ + if (extract64(ptr, 55, 1)) { + return ptr | mask; + } else { + return ptr & ~mask; + } +} + +uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data) +{ + ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); + ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data); + + return pauth_ptr_mask_internal(param); } static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier, From patchwork Mon Feb 27 21:33:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 657128 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp2584825wrb; Mon, 27 Feb 2023 13:36:58 -0800 (PST) X-Google-Smtp-Source: AK7set9LM3P900+lQdM10BAw0p+PK3YL/+X2uNEfniUacmhEAv69F7kRD5ESCaVpYjsv9kaIysjr X-Received: by 2002:a05:622a:50:b0:3bf:c6c9:2f29 with SMTP id y16-20020a05622a005000b003bfc6c92f29mr1558719qtw.27.1677533818123; Mon, 27 Feb 2023 13:36:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677533818; cv=none; d=google.com; s=arc-20160816; b=yFbg4twp7VcfBORHZUlGdAps7XtTV8wO0oyc5cWaz4Rwy1xoawU6KPq+1HyEX67ai/ O2VvhjH90AVrs+D7omOUH3zLlGyh53WkRyj+uu9szBodo16PikbwNjqJf8MKjrUQyYZX E/evG+lSKCsJeunFpHk4x1Cfz+3zsEItRlIGBTjz7F6gYNcYux3zcqDBwiJJbNORtO5Y G2UGuSna6N6LXJhTGI9zInlpBogIsyetGq9gVkAOnW8QJk6kF3Zl0rpWBOZSipINe8Ht ZU6aALOswNfb6MOkxvgpbRiA31jw8v8OPkYmZbI+OIxlczrvWVks2jIYvNDzDK9ewxcr kY3w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=lGHYHFO7atPDP15MVjfGq01WPHLD9Q8qsF/rVBYljso=; b=eux5pAU/5tvSx3Jq4prrl5lLcIXZbH0GFlU+bnjFr00i+gz1o/ieTed9vHpjvA0zO5 cAZACihz5awL4XjiRyIzi0s/Cu07LCIiAMuIb1UIliWePC95HJVWLM3XL5jrfW0Gq3xf djTHfapamHkTs5fjrO81dfJnMEyChO6+2kgPhsbRgxUKvpzUI0zdBckO3D99Jk045O67 9pWhUQ5vpmsFjIuIfP3QkCt78gyBOrxUdpFZnBbdmctvJInEsNP8LqSaAJuns466JySR dq0qjga7o+HgziFvuZKf5png5KGX7d4L7k6z+ZVEnPksMbze6cy1f2H6kFk6BsnZkg1g si+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bdk14H7j; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id d137-20020a63368f000000b00478c48cf73csm4375262pga.82.2023.02.27.13.33.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 13:33:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 11/14] target/arm: Implement gdbstub pauth extension Date: Mon, 27 Feb 2023 11:33:26 -1000 Message-Id: <20230227213329.793795-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227213329.793795-1-richard.henderson@linaro.org> References: <20230227213329.793795-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1044; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1044.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The extension is primarily defined by the Linux kernel NT_ARM_PAC_MASK ptrace register set. The original gdb feature consists of two masks, data and code, which are used to mask out the authentication code within a pointer. Following discussion with Luis Machado, add two more masks in order to support pointers within the high half of the address space (i.e. TTBR1 vs TTBR0). Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1105 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- configs/targets/aarch64-linux-user.mak | 2 +- configs/targets/aarch64-softmmu.mak | 2 +- configs/targets/aarch64_be-linux-user.mak | 2 +- target/arm/internals.h | 2 ++ target/arm/gdbstub.c | 5 ++++ target/arm/gdbstub64.c | 34 +++++++++++++++++++++++ gdb-xml/aarch64-pauth.xml | 15 ++++++++++ 7 files changed, 59 insertions(+), 3 deletions(-) create mode 100644 gdb-xml/aarch64-pauth.xml diff --git a/configs/targets/aarch64-linux-user.mak b/configs/targets/aarch64-linux-user.mak index db552f1839..ba8bc5fe3f 100644 --- a/configs/targets/aarch64-linux-user.mak +++ b/configs/targets/aarch64-linux-user.mak @@ -1,6 +1,6 @@ TARGET_ARCH=aarch64 TARGET_BASE_ARCH=arm -TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml +TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml TARGET_HAS_BFLT=y CONFIG_SEMIHOSTING=y CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/configs/targets/aarch64-softmmu.mak b/configs/targets/aarch64-softmmu.mak index d489e6da83..b4338e9568 100644 --- a/configs/targets/aarch64-softmmu.mak +++ b/configs/targets/aarch64-softmmu.mak @@ -1,5 +1,5 @@ TARGET_ARCH=aarch64 TARGET_BASE_ARCH=arm TARGET_SUPPORTS_MTTCG=y -TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml +TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml gdb-xml/aarch64-pauth.xml TARGET_NEED_FDT=y diff --git a/configs/targets/aarch64_be-linux-user.mak b/configs/targets/aarch64_be-linux-user.mak index dc78044fb1..acb5620cdb 100644 --- a/configs/targets/aarch64_be-linux-user.mak +++ b/configs/targets/aarch64_be-linux-user.mak @@ -1,7 +1,7 @@ TARGET_ARCH=aarch64 TARGET_BASE_ARCH=arm TARGET_BIG_ENDIAN=y -TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml +TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml TARGET_HAS_BFLT=y CONFIG_SEMIHOSTING=y CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/target/arm/internals.h b/target/arm/internals.h index c02dd59743..97271117a4 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1347,6 +1347,8 @@ int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg); int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg); int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg); int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg); +int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg); +int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg); void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index bf8aff7824..062c8d447a 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -355,6 +355,11 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) aarch64_gdb_set_fpu_reg, 34, "aarch64-fpu.xml", 0); } + if (isar_feature_aa64_pauth(&cpu->isar)) { + gdb_register_coprocessor(cs, aarch64_gdb_get_pauth_reg, + aarch64_gdb_set_pauth_reg, + 4, "aarch64-pauth.xml", 0); + } #endif } else { if (arm_feature(env, ARM_FEATURE_NEON)) { diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 3d9e9e97c8..3bee892fb7 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -210,6 +210,40 @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg) return 0; } +int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg) +{ + switch (reg) { + case 0: /* pauth_dmask */ + case 1: /* pauth_cmask */ + case 2: /* pauth_dmask_high */ + case 3: /* pauth_cmask_high */ + /* + * Note that older versions of this feature only contained + * pauth_{d,c}mask, for use with Linux user processes, and + * thus exclusively in the low half of the address space. + * + * To support system mode, and to debug kernels, two new regs + * were added to cover the high half of the address space. + * For the purpose of pauth_ptr_mask, we can use any well-formed + * address within the address space half -- here, 0 and -1. + */ + { + bool is_data = !(reg & 1); + bool is_high = reg & 2; + uint64_t mask = pauth_ptr_mask(env, -is_high, is_data); + return gdb_get_reg64(buf, mask); + } + default: + return 0; + } +} + +int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg) +{ + /* All pseudo registers are read-only. */ + return 0; +} + static void output_vector_union_type(GString *s, int reg_width, const char *name) { diff --git a/gdb-xml/aarch64-pauth.xml b/gdb-xml/aarch64-pauth.xml new file mode 100644 index 0000000000..24af5f903c --- /dev/null +++ b/gdb-xml/aarch64-pauth.xml @@ -0,0 +1,15 @@ + + + + + + + + + + + From patchwork Mon Feb 27 21:33:27 2023 Content-Type: text/plain; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id d137-20020a63368f000000b00478c48cf73csm4375262pga.82.2023.02.27.13.33.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 13:33:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, David Reiss , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v3 12/14] target/arm: Export arm_v7m_mrs_control Date: Mon, 27 Feb 2023 11:33:27 -1000 Message-Id: <20230227213329.793795-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227213329.793795-1-richard.henderson@linaro.org> References: <20230227213329.793795-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: David Reiss Allow the function to be used outside of m_helper.c. Rename with an "arm_" prefix. Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: David Reiss [rth: Split out of a larger patch] Signed-off-by: Richard Henderson --- target/arm/internals.h | 3 +++ target/arm/tcg/m_helper.c | 6 +++--- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 97271117a4..0f2c48ad4b 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1355,6 +1355,9 @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); #endif +/* Read the CONTROL register as the MRS instruction would. */ +uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure); + #ifdef CONFIG_USER_ONLY static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } #else diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index f94e87e728..03be79e7bf 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -56,7 +56,7 @@ static uint32_t v7m_mrs_xpsr(CPUARMState *env, uint32_t reg, unsigned el) return xpsr_read(env) & mask; } -static uint32_t v7m_mrs_control(CPUARMState *env, uint32_t secure) +uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure) { uint32_t value = env->v7m.control[secure]; @@ -93,7 +93,7 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) case 0 ... 7: /* xPSR sub-fields */ return v7m_mrs_xpsr(env, reg, 0); case 20: /* CONTROL */ - return v7m_mrs_control(env, 0); + return arm_v7m_mrs_control(env, 0); default: /* Unprivileged reads others as zero. */ return 0; @@ -2465,7 +2465,7 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) case 0 ... 7: /* xPSR sub-fields */ return v7m_mrs_xpsr(env, reg, el); case 20: /* CONTROL */ - return v7m_mrs_control(env, env->v7m.secure); + return arm_v7m_mrs_control(env, env->v7m.secure); case 0x94: /* CONTROL_NS */ /* * We have to handle this here because unprivileged Secure code From patchwork Mon Feb 27 21:33:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 657117 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp2583874wrb; Mon, 27 Feb 2023 13:34:21 -0800 (PST) X-Google-Smtp-Source: AK7set/VjA9T3iZvZXl7MNUlBVTa4/qE4dKbu0+R6OUhXstOz2aCtUuXaZ6l+vChEiKKQF32QLRB X-Received: by 2002:ac8:4e83:0:b0:3bf:c665:657 with SMTP id 3-20020ac84e83000000b003bfc6650657mr1473543qtp.8.1677533660962; Mon, 27 Feb 2023 13:34:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677533660; cv=none; d=google.com; s=arc-20160816; b=xqm2CyWex1Z8qAJ+n4czxwHMNi8CvKaDrxdRsMVog5qTR7JMG+/SQ7MaOKr31st9KD CFJHDMmywpJcP7CbWw98DHVzjuwcyCtrbjDCSYSKV/tydzB+1C4pdg+/st97ABRHSIHY FjfB5pqrhxVKzHC5LGZjmyGqc12hyZ+hjIat9ZMo6OkDOHf/IlO0aLrQ52uqVtHp+6GN AJ+3QOSiCle08wvgixr09Ms2ypAPuoJ4mo/72KZvwD7SXpoade3h/JFMNsjxI59Gt+hI SCvJQ79l8p6QzhRynr4Iyb/jVvpQ76K59ixqZ9ZbGWQbZIze7PL9wPO/l+kJTOnih81W hctw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Gzda5oQR/y3ZJNB/XMuzlrQozokO4StfuSmG6A2xeiQ=; b=Q+afowjMHmyn3sb9/Zlo7cyxxtxUEwY4XxS40M+dWTwVjmIAPcU9FWCKbg10PQipU2 rBoGxrVSVdQdvOTP2jFTqI0ziv9ZOOtQQXXk06TuEWiLocd1jdeKhr3wsMfhk24iM77E vJrh+DsdizjM5a41ZmNkkKMEcPQruf2GBDQt77AhOHVAzvyohdz+coJRpRLl+ivWkE7k hsDWtPC0D57z5GvNjYeV3tSZ5fM1jBnrP0cM6Xo2/RgFEg1Z4WQf+o/Xvfg9iaGWCZD4 vUECgMGF7wr++MSripRegjKSAExlS5ApnomhGOwD352SyVrl/3UGO/92YEtkZ1jYUDn8 AW3Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Z0EKF9br; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id d137-20020a63368f000000b00478c48cf73csm4375262pga.82.2023.02.27.13.33.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 13:33:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, David Reiss , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v3 13/14] target/arm: Export arm_v7m_get_sp_ptr Date: Mon, 27 Feb 2023 11:33:28 -1000 Message-Id: <20230227213329.793795-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227213329.793795-1-richard.henderson@linaro.org> References: <20230227213329.793795-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: David Reiss Allow the function to be used outside of m_helper.c. Move to be outside of ifndef CONFIG_USER_ONLY block. Rename from get_v7m_sp_ptr. Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: David Reiss [rth: Split out of a larger patch] Signed-off-by: Richard Henderson --- target/arm/internals.h | 10 +++++ target/arm/tcg/m_helper.c | 84 +++++++++++++++++++-------------------- 2 files changed, 51 insertions(+), 43 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 0f2c48ad4b..a03748aa10 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1358,6 +1358,16 @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); /* Read the CONTROL register as the MRS instruction would. */ uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure); +/* + * Return a pointer to the location where we currently store the + * stack pointer for the requested security state and thread mode. + * This pointer will become invalid if the CPU state is updated + * such that the stack pointers are switched around (eg changing + * the SPSEL control bit). + */ +uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure, + bool threadmode, bool spsel); + #ifdef CONFIG_USER_ONLY static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } #else diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index 03be79e7bf..081fc3f5f7 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -650,42 +650,6 @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) arm_rebuild_hflags(env); } -static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode, - bool spsel) -{ - /* - * Return a pointer to the location where we currently store the - * stack pointer for the requested security state and thread mode. - * This pointer will become invalid if the CPU state is updated - * such that the stack pointers are switched around (eg changing - * the SPSEL control bit). - * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode(). - * Unlike that pseudocode, we require the caller to pass us in the - * SPSEL control bit value; this is because we also use this - * function in handling of pushing of the callee-saves registers - * part of the v8M stack frame (pseudocode PushCalleeStack()), - * and in the tailchain codepath the SPSEL bit comes from the exception - * return magic LR value from the previous exception. The pseudocode - * opencodes the stack-selection in PushCalleeStack(), but we prefer - * to make this utility function generic enough to do the job. - */ - bool want_psp = threadmode && spsel; - - if (secure == env->v7m.secure) { - if (want_psp == v7m_using_psp(env)) { - return &env->regs[13]; - } else { - return &env->v7m.other_sp; - } - } else { - if (want_psp) { - return &env->v7m.other_ss_psp; - } else { - return &env->v7m.other_ss_msp; - } - } -} - static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure, uint32_t *pvec) { @@ -810,8 +774,8 @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain, !mode; mmu_idx = arm_v7m_mmu_idx_for_secstate_and_priv(env, M_REG_S, priv); - frame_sp_p = get_v7m_sp_ptr(env, M_REG_S, mode, - lr & R_V7M_EXCRET_SPSEL_MASK); + frame_sp_p = arm_v7m_get_sp_ptr(env, M_REG_S, mode, + lr & R_V7M_EXCRET_SPSEL_MASK); want_psp = mode && (lr & R_V7M_EXCRET_SPSEL_MASK); if (want_psp) { limit = env->v7m.psplim[M_REG_S]; @@ -1656,10 +1620,8 @@ static void do_v7m_exception_exit(ARMCPU *cpu) * use 'frame_sp_p' after we do something that makes it invalid. */ bool spsel = env->v7m.control[return_to_secure] & R_V7M_CONTROL_SPSEL_MASK; - uint32_t *frame_sp_p = get_v7m_sp_ptr(env, - return_to_secure, - !return_to_handler, - spsel); + uint32_t *frame_sp_p = arm_v7m_get_sp_ptr(env, return_to_secure, + !return_to_handler, spsel); uint32_t frameptr = *frame_sp_p; bool pop_ok = true; ARMMMUIdx mmu_idx; @@ -1965,7 +1927,7 @@ static bool do_v7m_function_return(ARMCPU *cpu) threadmode = !arm_v7m_is_handler_mode(env); spsel = env->v7m.control[M_REG_S] & R_V7M_CONTROL_SPSEL_MASK; - frame_sp_p = get_v7m_sp_ptr(env, true, threadmode, spsel); + frame_sp_p = arm_v7m_get_sp_ptr(env, true, threadmode, spsel); frameptr = *frame_sp_p; /* @@ -2900,3 +2862,39 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) } #endif /* !CONFIG_USER_ONLY */ + +uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure, bool threadmode, + bool spsel) +{ + /* + * Return a pointer to the location where we currently store the + * stack pointer for the requested security state and thread mode. + * This pointer will become invalid if the CPU state is updated + * such that the stack pointers are switched around (eg changing + * the SPSEL control bit). + * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode(). + * Unlike that pseudocode, we require the caller to pass us in the + * SPSEL control bit value; this is because we also use this + * function in handling of pushing of the callee-saves registers + * part of the v8M stack frame (pseudocode PushCalleeStack()), + * and in the tailchain codepath the SPSEL bit comes from the exception + * return magic LR value from the previous exception. The pseudocode + * opencodes the stack-selection in PushCalleeStack(), but we prefer + * to make this utility function generic enough to do the job. + */ + bool want_psp = threadmode && spsel; + + if (secure == env->v7m.secure) { + if (want_psp == v7m_using_psp(env)) { + return &env->regs[13]; + } else { + return &env->v7m.other_sp; + } + } else { + if (want_psp) { + return &env->v7m.other_ss_psp; + } else { + return &env->v7m.other_ss_msp; + } + } +} From patchwork Mon Feb 27 21:33:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 657122 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp2584165wrb; Mon, 27 Feb 2023 13:35:15 -0800 (PST) X-Google-Smtp-Source: AK7set/H8G+w4zwxk8rbkc+t90cDlHn39OkGdWZp5LykYzBS1p2veBn6NsEkeEcjgDIySBZT1+BP X-Received: by 2002:a05:622a:110f:b0:3b4:79f8:26c3 with SMTP id e15-20020a05622a110f00b003b479f826c3mr1347526qty.33.1677533714988; Mon, 27 Feb 2023 13:35:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677533714; cv=none; d=google.com; s=arc-20160816; b=GUlamZhipVEaHkn5VqSOt0c1dnPj38ssYU6U37e8wU7OToz/WChnry4NGHmvWecTsS VlwpgWSsEgK82RTVGpr+yiqU5rpum5dX0PzO2/Gen1b9QuLSiA3TlW1fu+gyR+2uL1Ws SJW4i+ieQ2VbNj0uvFIAtaG1PYHAk9v7MK0+OiMYjoXd7T2E2AqkMOZSD3/zV3zOUnEP GKlOY2U6tODXxE2rqbjIAfeYgQaRQ6ar+4CmSysQ8ctkmswPX7q4HWaSRLvwTabB2c/G oKEiy7EJD9d0WCya9ZzDo+UlBZ3VKkrj0BcvbHqly11bn+qoV2gVgnkpbH752mjU6IL9 vBMQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=sjZqTaUdPrCEIBQBnlQoRyAJsBDKtnJU1VZAEsiRUE4=; b=gUAz9IyB+ylbM8L72rieSzPLuUxMUjRf7sqbQ6RhLcjW1Ec6k6A8kvnr2W1qQOd1fr imdg2eLlQ7i4CG1nzefXVGsIcuavq+yQrHNxkmm5XFzZrpO94u3m8zI0S4/OHpwumSWk AlC4oreZkMLdrrdzGf7YXY7Fqqb3ps3DjwGCKHS2qmRoWrW8EDvExpk2oJgIcWemkN4U qLo3gsxSP6jqgRwEIjoOpgi1+DYJBvKlARwGIzDEb6cwb6q+kBS2ogzK114E+fMNbw2C IuJjfhe7baeS8H+26T986k+yKFU8OLUQk5c+f/sjyOvYY09NNtI2QbRK3+mFle91matk A9hg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AGmsmoIS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id d137-20020a63368f000000b00478c48cf73csm4375262pga.82.2023.02.27.13.33.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 13:33:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, David Reiss Subject: [PATCH v3 14/14] target/arm: Implement gdbstub m-profile systemreg and secext Date: Mon, 27 Feb 2023 11:33:29 -1000 Message-Id: <20230227213329.793795-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227213329.793795-1-richard.henderson@linaro.org> References: <20230227213329.793795-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The upstream gdb xml only implements {MSP,PSP}{,_NS,S}, but go ahead and implement the other system registers as well. Since there is significant overlap between the two, implement them with common code. The only exception is the systemreg view of CONTROL, which merges the banked bits as per MRS. Signed-off-by: David Reiss [rth: Substatial rewrite using enumerator and shared code.] Signed-off-by: Richard Henderson --- target/arm/cpu.h | 2 + target/arm/gdbstub.c | 178 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 180 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 059fe62eaa..6e97a256fb 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -869,6 +869,8 @@ struct ArchCPU { DynamicGDBXMLInfo dyn_sysreg_xml; DynamicGDBXMLInfo dyn_svereg_xml; + DynamicGDBXMLInfo dyn_m_systemreg_xml; + DynamicGDBXMLInfo dyn_m_secextreg_xml; /* Timers used by the generic (architected) timer */ QEMUTimer *gt_timer[NUM_GTIMERS]; diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 062c8d447a..3f799f5d05 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -322,6 +322,164 @@ static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg) return cpu->dyn_sysreg_xml.num; } +typedef enum { + M_SYSREG_MSP, + M_SYSREG_PSP, + M_SYSREG_PRIMASK, + M_SYSREG_CONTROL, + M_SYSREG_BASEPRI, + M_SYSREG_FAULTMASK, + M_SYSREG_MSPLIM, + M_SYSREG_PSPLIM, +} MProfileSysreg; + +static const struct { + const char *name; + int feature; +} m_sysreg_def[] = { + [M_SYSREG_MSP] = { "msp", ARM_FEATURE_M }, + [M_SYSREG_PSP] = { "psp", ARM_FEATURE_M }, + [M_SYSREG_PRIMASK] = { "primask", ARM_FEATURE_M }, + [M_SYSREG_CONTROL] = { "control", ARM_FEATURE_M }, + [M_SYSREG_BASEPRI] = { "basepri", ARM_FEATURE_M_MAIN }, + [M_SYSREG_FAULTMASK] = { "faultmask", ARM_FEATURE_M_MAIN }, + [M_SYSREG_MSPLIM] = { "msplim", ARM_FEATURE_V8 }, + [M_SYSREG_PSPLIM] = { "psplim", ARM_FEATURE_V8 }, +}; + +static uint32_t *m_sysreg_ptr(CPUARMState *env, MProfileSysreg reg, bool sec) +{ + uint32_t *ptr; + + switch (reg) { + case M_SYSREG_MSP: + ptr = arm_v7m_get_sp_ptr(env, sec, false, true); + break; + case M_SYSREG_PSP: + ptr = arm_v7m_get_sp_ptr(env, sec, true, true); + break; + case M_SYSREG_MSPLIM: + ptr = &env->v7m.msplim[sec]; + break; + case M_SYSREG_PSPLIM: + ptr = &env->v7m.psplim[sec]; + break; + case M_SYSREG_PRIMASK: + ptr = &env->v7m.primask[sec]; + break; + case M_SYSREG_BASEPRI: + ptr = &env->v7m.basepri[sec]; + break; + case M_SYSREG_FAULTMASK: + ptr = &env->v7m.faultmask[sec]; + break; + case M_SYSREG_CONTROL: + ptr = &env->v7m.control[sec]; + break; + default: + return NULL; + } + return arm_feature(env, m_sysreg_def[reg].feature) ? ptr : NULL; +} + +static int m_sysreg_get(CPUARMState *env, GByteArray *buf, + MProfileSysreg reg, bool secure) +{ + uint32_t *ptr = m_sysreg_ptr(env, reg, secure); + + if (ptr == NULL) { + return 0; + } + return gdb_get_reg32(buf, *ptr); +} + +static int arm_gdb_get_m_systemreg(CPUARMState *env, GByteArray *buf, int reg) +{ + /* + * Here, we emulate MRS instruction, where CONTROL has a mix of + * banked and non-banked bits. + */ + if (reg == M_SYSREG_CONTROL) { + return gdb_get_reg32(buf, arm_v7m_mrs_control(env, env->v7m.secure)); + } + return m_sysreg_get(env, buf, reg, env->v7m.secure); +} + +static int arm_gdb_set_m_systemreg(CPUARMState *env, uint8_t *buf, int reg) +{ + return 0; /* TODO */ +} + +static int arm_gen_dynamic_m_systemreg_xml(CPUState *cs, int orig_base_reg) +{ + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + GString *s = g_string_new(NULL); + int base_reg = orig_base_reg; + int i; + + g_string_printf(s, ""); + g_string_append_printf(s, ""); + g_string_append_printf(s, "\n"); + + for (i = 0; i < ARRAY_SIZE(m_sysreg_def); i++) { + if (arm_feature(env, m_sysreg_def[i].feature)) { + g_string_append_printf(s, + "\n", + m_sysreg_def[i].name, base_reg++); + } + } + + g_string_append_printf(s, ""); + cpu->dyn_m_systemreg_xml.desc = g_string_free(s, false); + cpu->dyn_m_systemreg_xml.num = base_reg - orig_base_reg; + + return cpu->dyn_m_systemreg_xml.num; +} + +#ifndef CONFIG_USER_ONLY +/* + * For user-only, we see the non-secure registers via m_systemreg above. + * For secext, encode the non-secure view as even and secure view as odd. + */ +static int arm_gdb_get_m_secextreg(CPUARMState *env, GByteArray *buf, int reg) +{ + return m_sysreg_get(env, buf, reg >> 1, reg & 1); +} + +static int arm_gdb_set_m_secextreg(CPUARMState *env, uint8_t *buf, int reg) +{ + return 0; /* TODO */ +} + +static int arm_gen_dynamic_m_secextreg_xml(CPUState *cs, int orig_base_reg) +{ + ARMCPU *cpu = ARM_CPU(cs); + GString *s = g_string_new(NULL); + int base_reg = orig_base_reg; + int i; + + g_string_printf(s, ""); + g_string_append_printf(s, ""); + g_string_append_printf(s, "\n"); + + for (i = 0; i < ARRAY_SIZE(m_sysreg_def); i++) { + g_string_append_printf(s, + "\n", + m_sysreg_def[i].name, base_reg++); + g_string_append_printf(s, + "\n", + m_sysreg_def[i].name, base_reg++); + } + + g_string_append_printf(s, ""); + cpu->dyn_m_secextreg_xml.desc = g_string_free(s, false); + cpu->dyn_m_secextreg_xml.num = base_reg - orig_base_reg; + + return cpu->dyn_m_secextreg_xml.num; +} +#endif + const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) { ARMCPU *cpu = ARM_CPU(cs); @@ -330,6 +488,12 @@ const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) return cpu->dyn_sysreg_xml.desc; } else if (strcmp(xmlname, "sve-registers.xml") == 0) { return cpu->dyn_svereg_xml.desc; + } else if (strcmp(xmlname, "arm-m-system.xml") == 0) { + return cpu->dyn_m_systemreg_xml.desc; +#ifndef CONFIG_USER_ONLY + } else if (strcmp(xmlname, "arm-m-secext.xml") == 0) { + return cpu->dyn_m_secextreg_xml.desc; +#endif } return NULL; } @@ -389,4 +553,18 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs), "system-registers.xml", 0); + if (arm_feature(env, ARM_FEATURE_M)) { + gdb_register_coprocessor(cs, + arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg, + arm_gen_dynamic_m_systemreg_xml(cs, cs->gdb_num_regs), + "arm-m-system.xml", 0); +#ifndef CONFIG_USER_ONLY + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { + gdb_register_coprocessor(cs, + arm_gdb_get_m_secextreg, arm_gdb_set_m_secextreg, + arm_gen_dynamic_m_secextreg_xml(cs, cs->gdb_num_regs), + "arm-m-secext.xml", 0); + } +#endif + } }