From patchwork Fri Feb 24 10:58:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 657291 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E6A9C61DA3 for ; Fri, 24 Feb 2023 11:00:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229898AbjBXLA3 (ORCPT ); Fri, 24 Feb 2023 06:00:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33694 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229750AbjBXK7x (ORCPT ); Fri, 24 Feb 2023 05:59:53 -0500 Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CCC7239B8C for ; Fri, 24 Feb 2023 02:59:20 -0800 (PST) Received: by mail-pj1-x102c.google.com with SMTP id q31-20020a17090a17a200b0023750b69614so2275029pja.5 for ; Fri, 24 Feb 2023 02:59:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7g1uqAd+GBvLWxylp13ChAu3aZ2qmP9sP5D+Fm30PJ4=; b=xMS93kYtTEWQdbX6qfOwCbcRYIGnoaDf2QJDnzsBG1pI8dHP/gX61gX4fLgH/twQzJ /XYaG0UG2ZbcmamgvygW+VMhACiR0ijaXbGnqHdojoFsXmF1pUX+yOkQGUqG2hKUdOE1 Yluzn+n+d81WXnsnHRCJmIuo2lvf+6VzZzYvcRHDXhF9I7+gv7ARITZ57947CHWinHn7 fi2BhJDcGjuwrKoVxcrJ4r8zbaBTpKm83kP5a28aqeRygtjRVQzRssVxqNtrTnS7FjtS 5pclT3FRd82lh5EuexCw1XznkKdhrrd2yv1XHxfaeZ7RqTU/l7gDAaWGEnGhCmu64iOA us+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7g1uqAd+GBvLWxylp13ChAu3aZ2qmP9sP5D+Fm30PJ4=; b=fKLvEFQPA8DU6rV+I55eWo5D7FkJp8sv8yQB0k08k8aVk6JOGAaDPTuc3KY5oFgaC6 NaPlYqyqiwBayp2Ri/UeOARodgE1VXQ/AHPW/ViXaroEAxbCuerZzWs8OndF8XqJQE/b IDre4GRBLMgOdWG5wgGnoFKRJeXmmbros/HjR/UAxTbSBA6FrroKjuF9XPM88g4rxiHe jLS7A79QDsVK3eyatB9lzzgPAWK4dNKRoECAQpr3CKzyD7ZKR1Uko4GH6AwgnM8P1zww stFjNEJTvWIMN0QF7np3JP7iTFEXYCe9ZgVBkY69WBZqrW+do5eWZcJwl/lt8/PaucwY 2keA== X-Gm-Message-State: AO0yUKW/UgYF3igsz3cMLAENLv/P5QNs4ZVNAD66qaWLCfI/E8eyxc9K dra4jilpc1wIGXuzWDyheiUWVIMohyvQaqQ= X-Google-Smtp-Source: AK7set+ZDd7rHtMLxF526vFXCKgB89SNppmXHQaAki0dC4fMRkmaETiCaGeFktgQlPL46hfmwQY7bw== X-Received: by 2002:a17:90a:188:b0:237:3dfb:9095 with SMTP id 8-20020a17090a018800b002373dfb9095mr9674382pjc.6.1677236360228; Fri, 24 Feb 2023 02:59:20 -0800 (PST) Received: from localhost.localdomain ([117.217.187.3]) by smtp.gmail.com with ESMTPSA id gd5-20020a17090b0fc500b00233cde36909sm1263853pjb.21.2023.02.24.02.59.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 02:59:19 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org Cc: konrad.dybcio@linaro.org, bhelgaas@google.com, kishon@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam , Krzysztof Kozlowski Subject: [PATCH v2 01/13] dt-bindings: PCI: qcom: Update maintainers entry Date: Fri, 24 Feb 2023 16:28:54 +0530 Message-Id: <20230224105906.16540-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230224105906.16540-1-manivannan.sadhasivam@linaro.org> References: <20230224105906.16540-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Stan is no longer working with MMSOL and expressed his interest to not continue maintaining Qcom PCIe driver. Since I took over the driver maintainership, I'm stepping in to maintain the binding also. Acked-by: Krzysztof Kozlowski Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index a5859bb3dc28..a3639920fcbb 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -8,7 +8,7 @@ title: Qualcomm PCI express root complex maintainers: - Bjorn Andersson - - Stanimir Varbanov + - Manivannan Sadhasivam description: | Qualcomm PCIe root complex controller is based on the Synopsys DesignWare From patchwork Fri Feb 24 10:58:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 656328 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90D52C64ED8 for ; Fri, 24 Feb 2023 11:00:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230098AbjBXLAb (ORCPT ); Fri, 24 Feb 2023 06:00:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60308 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229641AbjBXK7z (ORCPT ); Fri, 24 Feb 2023 05:59:55 -0500 Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 864445D469 for ; Fri, 24 Feb 2023 02:59:25 -0800 (PST) Received: by mail-pj1-x102c.google.com with SMTP id k21-20020a17090aaa1500b002376652e160so2340024pjq.0 for ; Fri, 24 Feb 2023 02:59:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uGDet0K+1/m01Mue6GMZv5iNZBwdpYi4DRLEmHhKT40=; b=wzykzWTLm9WRroHFoG0Wi4/XZv56thmYBqfYcTMsjRvlgFIqS7YEcL35e6oZhoDeTX 3iZRGY2Qj1zBi0n4Ds3Q9wWRoRQCHAHJtnggV4VvKboWqiHGa0a7So9m9rN5Yl8p/evu cF9l87jWQ0FHeQFwLjYeevwF+dvbUSgO/jVW1rUrmvT3qcKt5ulkUyDD/+wNzPBc9mCb kqvPxj3z4FBMBgcsSp12n1L3AnTJlNbpS+tDJWKlIHsPxSVmjmOAlNW1/TWKObSDwMhg b3SbhF7WiUVvgYLj9kIwU+AkuSMLl9PT2tneUhCIC/v0JlFH5zOHDmeaSgPtKSEKfjI3 xnBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uGDet0K+1/m01Mue6GMZv5iNZBwdpYi4DRLEmHhKT40=; b=NXK8wRvze0TouZmv1M+eyeifn9U2Hc4sux8DWOFMvSahmko6wH5cQppO8tOvqz254b eYBknXC9i6DaV24TINGzv6mEMLFM1uBwJByQ346BuYmVHxbuVoxjtd1USYPHPBEpOWn3 Fnu976IYXz/A2jjt5WGCJIutTI7atjNtpilpz9LqPOksE+CIyOzTJLh27FHcoxjuDnIj qyU20ZTmGwAwFf74Japyi8685RPhIThP6AadejeIk5Ot33cErz3ygjtnTyYNRTME17vc yYjNgAth9auGGP0X/1yHEyutNtDM+0efOxBirF1FTaV0ET02Ni7y3fL2seX6HpPSqjeo HfNA== X-Gm-Message-State: AO0yUKXHuU8NAqseO4+xx0VGoffodfnuUWevpbb3PMFpkZ3y+F58Q9tI KyBie4Oo3bjxi6hxHj4lR/iv X-Google-Smtp-Source: AK7set+6mGj4VAtYdGIkQ1vBWDtOV7gy94BYTfFVLAt8JxLm/NlVJr/LsvVWmNSRz2bjH20PvJiRDw== X-Received: by 2002:a17:90b:388a:b0:234:1645:5266 with SMTP id mu10-20020a17090b388a00b0023416455266mr17301662pjb.30.1677236364970; Fri, 24 Feb 2023 02:59:24 -0800 (PST) Received: from localhost.localdomain ([117.217.187.3]) by smtp.gmail.com with ESMTPSA id gd5-20020a17090b0fc500b00233cde36909sm1263853pjb.21.2023.02.24.02.59.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 02:59:24 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org Cc: konrad.dybcio@linaro.org, bhelgaas@google.com, kishon@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 02/13] dt-bindings: PCI: qcom: Add iommu properties Date: Fri, 24 Feb 2023 16:28:55 +0530 Message-Id: <20230224105906.16540-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230224105906.16540-1-manivannan.sadhasivam@linaro.org> References: <20230224105906.16540-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Most of the PCIe controllers require iommu support to function properly. So let's add them to the binding. Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index a3639920fcbb..f48d0792aa57 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -64,6 +64,11 @@ properties: dma-coherent: true + iommus: + maxItems: 1 + + iommu-map: true + interconnects: maxItems: 2 From patchwork Fri Feb 24 10:58:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 657290 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22D6CC6FA9D for ; Fri, 24 Feb 2023 11:00:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230110AbjBXLAe (ORCPT ); Fri, 24 Feb 2023 06:00:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60386 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229808AbjBXK75 (ORCPT ); Fri, 24 Feb 2023 05:59:57 -0500 Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1BFB63A870 for ; Fri, 24 Feb 2023 02:59:30 -0800 (PST) Received: by mail-pl1-x62f.google.com with SMTP id ko13so16989870plb.13 for ; Fri, 24 Feb 2023 02:59:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wzdP0f8Dd/LfcCPdQr780PzK2RvZAJKB5vPc2XD3ufA=; b=mByJV+JaU1+Ltx80aDVz38O8fe/liFVHft/qdrSEETLmITXc0LZv5kudxwrQJHEM4E 2RP0gsLabTBSZH79fsU3NEHMCeOW0Iqr1TcZhzUE9B7tGDss784ZxY3AotfpkL6jWX2/ 6HMJBJEt7J+vIZ5LMgqVreWGU2Lcz8u/UgO9U8zBTWamxRmKNBZJP6YfXSnA2eN4iPk/ X15O/ck2XYbJCcauOyeuXxchQlLYNaOq7J6UOFE9O5V7S0FVHzlkswu9pzD1R5IausqO 535j2BWGe7lKIRbK/nef5No9zFZ7ku4gO34mFvnolSNCGNgFpU9xfpODylons+mkw7YN tlQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wzdP0f8Dd/LfcCPdQr780PzK2RvZAJKB5vPc2XD3ufA=; b=dEqbcBWkDDj8XIMYtvs25WCtdXwXI5HriIMIjquIK4jghJHZkqhWIJjVcVnyVmOiwv V8+A82nNwe8jB8ILOK/v/Hy2WpmaVojiHYF1RmQQaGf5oiuap6bInEGQk9nuJPYMziMW rPeo2eec2zkxu+LyKrqL7yDAseNDDGNIzpntcdWwhDL8oB7iVz1+a9O+TopNYYOCTzFd XdC+K4Bn8M18H0YLACvIeB4eKHgBd3/1Ns2BivSTj0c51v003qLjXZml0T3keRytnczp 8P+qLJ+tGt3JL8YT0Wa9XUL6YSQ8WJumZWCE3CefzJcOWq/p+cQqq7g3H4i5DmfAJsuD Ixjw== X-Gm-Message-State: AO0yUKUK+P7BqSZKYJTMqQjDtqWzzV6NPUJpIxT0dIoAzoYkyh3Rfer0 08k10JgWaRpYivHJZ92JXwLw X-Google-Smtp-Source: AK7set/00/XkHimswh8A/lTlMaf9uljLO9Xk++JlggP7Y2nYgIaIkn/kcVov3dPdmMzyvCxW50D7Yg== X-Received: by 2002:a17:90b:4a4d:b0:234:148:4b27 with SMTP id lb13-20020a17090b4a4d00b0023401484b27mr18089652pjb.17.1677236369819; Fri, 24 Feb 2023 02:59:29 -0800 (PST) Received: from localhost.localdomain ([117.217.187.3]) by smtp.gmail.com with ESMTPSA id gd5-20020a17090b0fc500b00233cde36909sm1263853pjb.21.2023.02.24.02.59.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 02:59:29 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org Cc: konrad.dybcio@linaro.org, bhelgaas@google.com, kishon@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam , Krzysztof Kozlowski Subject: [PATCH v2 03/13] dt-bindings: PCI: qcom: Add SDX55 SoC Date: Fri, 24 Feb 2023 16:28:56 +0530 Message-Id: <20230224105906.16540-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230224105906.16540-1-manivannan.sadhasivam@linaro.org> References: <20230224105906.16540-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for the PCIe controller on the Qcom SDX55 SoC to the binding. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Manivannan Sadhasivam --- .../devicetree/bindings/pci/qcom,pcie.yaml | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index f48d0792aa57..3bba1ef3cff5 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -30,6 +30,7 @@ properties: - qcom,pcie-sc8180x - qcom,pcie-sc8280xp - qcom,pcie-sdm845 + - qcom,pcie-sdx55 - qcom,pcie-sm8150 - qcom,pcie-sm8250 - qcom,pcie-sm8450-pcie0 @@ -199,6 +200,7 @@ allOf: - qcom,pcie-sc7280 - qcom,pcie-sc8180x - qcom,pcie-sc8280xp + - qcom,pcie-sdx55 - qcom,pcie-sm8250 - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 @@ -646,6 +648,32 @@ allOf: items: - const: pci # PCIe core reset + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sdx55 + then: + properties: + clocks: + minItems: 7 + maxItems: 7 + clock-names: + items: + - const: pipe # PIPE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: sleep # PCIe Sleep clock + resets: + maxItems: 1 + reset-names: + items: + - const: pci # PCIe core reset + - if: properties: compatible: From patchwork Fri Feb 24 10:58:57 2023 Content-Type: text/plain; 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Fri, 24 Feb 2023 02:59:34 -0800 (PST) Received: from localhost.localdomain ([117.217.187.3]) by smtp.gmail.com with ESMTPSA id gd5-20020a17090b0fc500b00233cde36909sm1263853pjb.21.2023.02.24.02.59.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 02:59:34 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org Cc: konrad.dybcio@linaro.org, bhelgaas@google.com, kishon@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam , Krzysztof Kozlowski Subject: [PATCH v2 04/13] dt-bindings: PCI: qcom-ep: Fix the unit address used in example Date: Fri, 24 Feb 2023 16:28:57 +0530 Message-Id: <20230224105906.16540-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230224105906.16540-1-manivannan.sadhasivam@linaro.org> References: <20230224105906.16540-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Unit address of PCIe EP node should be 0x1c00000 as it has to match the first address specified in the reg property. Fixes: 31c9ef002580 ("dt-bindings: PCI: Add Qualcomm PCIe Endpoint controller") Reviewed-by: Krzysztof Kozlowski Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index 8d7eb51edcb4..c1800e44f3da 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -164,7 +164,7 @@ examples: #include #include #include - pcie_ep: pcie-ep@40000000 { + pcie_ep: pcie-ep@1c00000 { compatible = "qcom,sdx55-pcie-ep"; reg = <0x01c00000 0x3000>, <0x40000000 0xf1d>, From patchwork Fri Feb 24 10:58:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 656327 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55E1AC64ED8 for ; Fri, 24 Feb 2023 11:00:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230178AbjBXLAq (ORCPT ); Fri, 24 Feb 2023 06:00:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60446 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229877AbjBXLAC (ORCPT ); Fri, 24 Feb 2023 06:00:02 -0500 Received: from mail-pj1-x102d.google.com (mail-pj1-x102d.google.com [IPv6:2607:f8b0:4864:20::102d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 82A072112 for ; Fri, 24 Feb 2023 02:59:39 -0800 (PST) Received: by mail-pj1-x102d.google.com with SMTP id nw10-20020a17090b254a00b00233d7314c1cso2457028pjb.5 for ; Fri, 24 Feb 2023 02:59:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HWzirrIvAlApajl/8IV1ns6ZR5N3zHdUYEWFW4EUTxg=; b=WgOeZtrMpNQF82N0RyIc81DA7VMhg2aTHO705wMUkzAOKMcpPDq4HnFy+6rJ79goQl XNaMXIDP0Dt9f9O4gKyK5whJQajwOWI4heuAtMtu0MHIFvQMjxIB6o2qm3iu0+P3NuoT iCr3q7PM0ssSOC1j7dlYZT5IeubFl+m/ew+OKFzWDK+N+5+c/EttEfavRQozx7z+Ur9s o06VmypjZOtiMx9hOaHGxCu4Bnk0vutR2HNR/3yC3dIjqNmDvjuYzTqGuRq5tsr6K5Js XHvbuWZQoS9UQRGDxo8tpJnceeWCyB59Cp/Qw874Yuxc4HwOeQ3MgLuw+FUmlSudVMNT AhQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HWzirrIvAlApajl/8IV1ns6ZR5N3zHdUYEWFW4EUTxg=; b=JgZjryduRNfObaNoaztqInVwOY//7/MA653/QnqKzgkLuM62sLd9Vi1pf2rie66kX6 YjYvpratBbBEI4aBasvqOneFzcPkpmC/E2JLBld3hpMbDjgpzJkZT/grKsP5Th/uWH8e 3gdVuuQdD+WeBDOZp/TqP59x3039pt1iyCfUl5KP1AbTkk8KDJQfd44WcYw4QLwrCx00 TPQss+gnQTBL5pXmJZF1tEJMHbORHkjQRFjeR3sk4C5bCxceZ7fkzFMYQOmWuST04E+/ nuJVcACbacKhAn/ygF4EoKnUG3maFgfPl4XBn7P3Oz/n7sbYAwfVOqxU/ncNpjD6c2EB GZGQ== X-Gm-Message-State: AO0yUKXqw1XKBuqlndoK2svLb2frilHGZ7ap3PrDXtmdB1x5FriJbPOb RrxWYOJlxhn0ayEiSMUm+rVT X-Google-Smtp-Source: AK7set+l3dhsbG5Ta+Ua0gyUgpw/rOM23btJEBVdGna8A6wwbUpMKgPonBx504ritBoktuwXOwg9CQ== X-Received: by 2002:a17:90b:4d09:b0:233:b849:7e79 with SMTP id mw9-20020a17090b4d0900b00233b8497e79mr18207543pjb.4.1677236378979; Fri, 24 Feb 2023 02:59:38 -0800 (PST) Received: from localhost.localdomain ([117.217.187.3]) by smtp.gmail.com with ESMTPSA id gd5-20020a17090b0fc500b00233cde36909sm1263853pjb.21.2023.02.24.02.59.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 02:59:38 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org Cc: konrad.dybcio@linaro.org, bhelgaas@google.com, kishon@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 05/13] ARM: dts: qcom: sdx55: Fix the unit address of PCIe EP node Date: Fri, 24 Feb 2023 16:28:58 +0530 Message-Id: <20230224105906.16540-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230224105906.16540-1-manivannan.sadhasivam@linaro.org> References: <20230224105906.16540-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Unit address of PCIe EP node should be 0x1c00000 as it has to match the first address specified in the reg property. This also requires sorting the node in the ascending order. Fixes: e6b69813283f ("ARM: dts: qcom: sdx55: Add support for PCIe EP") Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55.dtsi | 78 +++++++++++++++---------------- 1 file changed, 39 insertions(+), 39 deletions(-) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 93d71aff3fab..e84ca795cae6 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -303,6 +303,45 @@ qpic_nand: nand-controller@1b30000 { status = "disabled"; }; + pcie_ep: pcie-ep@1c00000 { + compatible = "qcom,sdx55-pcie-ep"; + reg = <0x01c00000 0x3000>, + <0x40000000 0xf1d>, + <0x40000f20 0xc8>, + <0x40001000 0x1000>, + <0x40200000 0x100000>, + <0x01c03000 0x3000>; + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", + "mmio"; + + qcom,perst-regs = <&tcsr 0xb258 0xb270>; + + clocks = <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_SLEEP_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>; + clock-names = "aux", "cfg", "bus_master", "bus_slave", + "slave_q2a", "sleep", "ref"; + + interrupts = , + ; + interrupt-names = "global", "doorbell"; + reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; + resets = <&gcc GCC_PCIE_BCR>; + reset-names = "core"; + power-domains = <&gcc PCIE_GDSC>; + phys = <&pcie0_lane>; + phy-names = "pciephy"; + max-link-speed = <3>; + num-lanes = <2>; + + status = "disabled"; + }; + pcie0_phy: phy@1c07000 { compatible = "qcom,sdx55-qmp-pcie-phy"; reg = <0x01c07000 0x1c4>; @@ -400,45 +439,6 @@ sdhc_1: mmc@8804000 { status = "disabled"; }; - pcie_ep: pcie-ep@40000000 { - compatible = "qcom,sdx55-pcie-ep"; - reg = <0x01c00000 0x3000>, - <0x40000000 0xf1d>, - <0x40000f20 0xc8>, - <0x40001000 0x1000>, - <0x40200000 0x100000>, - <0x01c03000 0x3000>; - reg-names = "parf", "dbi", "elbi", "atu", "addr_space", - "mmio"; - - qcom,perst-regs = <&tcsr 0xb258 0xb270>; - - clocks = <&gcc GCC_PCIE_AUX_CLK>, - <&gcc GCC_PCIE_CFG_AHB_CLK>, - <&gcc GCC_PCIE_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_SLV_AXI_CLK>, - <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, - <&gcc GCC_PCIE_SLEEP_CLK>, - <&gcc GCC_PCIE_0_CLKREF_CLK>; - clock-names = "aux", "cfg", "bus_master", "bus_slave", - "slave_q2a", "sleep", "ref"; - - interrupts = , - ; - interrupt-names = "global", "doorbell"; - reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; - resets = <&gcc GCC_PCIE_BCR>; - reset-names = "core"; - power-domains = <&gcc PCIE_GDSC>; - phys = <&pcie0_lane>; - phy-names = "pciephy"; - max-link-speed = <3>; - num-lanes = <2>; - - status = "disabled"; - }; - remoteproc_mpss: remoteproc@4080000 { compatible = "qcom,sdx55-mpss-pas"; reg = <0x04080000 0x4040>; From patchwork Fri Feb 24 10:58:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 657288 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4ABF9C64ED8 for ; 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Fri, 24 Feb 2023 02:59:43 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org Cc: konrad.dybcio@linaro.org, bhelgaas@google.com, kishon@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 06/13] ARM: dts: qcom: sdx55: Rename pcie0_{phy/lane} to pcie_{phy/lane} Date: Fri, 24 Feb 2023 16:28:59 +0530 Message-Id: <20230224105906.16540-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230224105906.16540-1-manivannan.sadhasivam@linaro.org> References: <20230224105906.16540-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org There is only one PCIe PHY in this SoC, so there is no need to add an index to the suffix. This also matches the naming convention of the PCIe controller. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts | 2 +- arch/arm/boot/dts/qcom-sdx55.dtsi | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts index ac8b4626ae9a..b7ee0237608f 100644 --- a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts +++ b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts @@ -242,7 +242,7 @@ &ipa { memory-region = <&ipa_fw_mem>; }; -&pcie0_phy { +&pcie_phy { status = "okay"; vdda-phy-supply = <&vreg_l1e_bb_1p2>; diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index e84ca795cae6..a1f4a7b0904a 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -334,7 +334,7 @@ pcie_ep: pcie-ep@1c00000 { resets = <&gcc GCC_PCIE_BCR>; reset-names = "core"; power-domains = <&gcc PCIE_GDSC>; - phys = <&pcie0_lane>; + phys = <&pcie_lane>; phy-names = "pciephy"; max-link-speed = <3>; num-lanes = <2>; @@ -342,7 +342,7 @@ pcie_ep: pcie-ep@1c00000 { status = "disabled"; }; - pcie0_phy: phy@1c07000 { + pcie_phy: phy@1c07000 { compatible = "qcom,sdx55-qmp-pcie-phy"; reg = <0x01c07000 0x1c4>; #address-cells = <1>; @@ -362,7 +362,7 @@ pcie0_phy: phy@1c07000 { status = "disabled"; - pcie0_lane: lanes@1c06000 { + pcie_lane: lanes@1c06000 { reg = <0x01c06000 0x104>, /* tx0 */ <0x01c06200 0x328>, /* rx0 */ <0x01c07200 0x1e8>, /* pcs */ From patchwork Fri Feb 24 10:59:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 656326 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 734EEC61DA3 for ; Fri, 24 Feb 2023 11:01:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230006AbjBXLBN (ORCPT ); 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Fri, 24 Feb 2023 02:59:48 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org Cc: konrad.dybcio@linaro.org, bhelgaas@google.com, kishon@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 07/13] ARM: dts: qcom: sdx55: Add support for PCIe RC controller Date: Fri, 24 Feb 2023 16:29:00 +0530 Message-Id: <20230224105906.16540-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230224105906.16540-1-manivannan.sadhasivam@linaro.org> References: <20230224105906.16540-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The PCIe controller in SDX55 can act as the RC controller also. Let's add support for it. Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55.dtsi | 82 +++++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index a1f4a7b0904a..b411c4ae34c3 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -303,6 +303,88 @@ qpic_nand: nand-controller@1b30000 { status = "disabled"; }; + pcie_rc: pcie@1c00000 { + compatible = "qcom,pcie-sdx55"; + reg = <0x01c00000 0x3000>, + <0x40000000 0xf1d>, + <0x40000f20 0xc8>, + <0x40001000 0x1000>, + <0x40100000 0x100000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x40300000 0x0 0x3fd00000>; + + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "msi8"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 141 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 0 144 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_PIPE_CLK>, + <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_SLEEP_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "sleep"; + + assigned-clocks = <&gcc GCC_PCIE_AUX_CLK>; + assigned-clock-rates = <19200000>; + + iommus = <&apps_smmu 0x0200 0x0f>; + iommu-map = <0x0 &apps_smmu 0x0200 0x1>, + <0x100 &apps_smmu 0x0201 0x1>, + <0x200 &apps_smmu 0x0202 0x1>, + <0x300 &apps_smmu 0x0203 0x1>, + <0x400 &apps_smmu 0x0204 0x1>; + + resets = <&gcc GCC_PCIE_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_GDSC>; + + phys = <&pcie_lane>; + phy-names = "pciephy"; + + status = "disabled"; + }; + pcie_ep: pcie-ep@1c00000 { compatible = "qcom,sdx55-pcie-ep"; reg = <0x01c00000 0x3000>, From patchwork Fri Feb 24 10:59:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 657287 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B8C1C61DA3 for ; Fri, 24 Feb 2023 11:01:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230263AbjBXLBT (ORCPT ); Fri, 24 Feb 2023 06:01:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60546 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229676AbjBXLAR (ORCPT ); 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Fri, 24 Feb 2023 02:59:52 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org Cc: konrad.dybcio@linaro.org, bhelgaas@google.com, kishon@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 08/13] ARM: dts: qcom: sdx55: List the property values vertically Date: Fri, 24 Feb 2023 16:29:01 +0530 Message-Id: <20230224105906.16540-9-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230224105906.16540-1-manivannan.sadhasivam@linaro.org> References: <20230224105906.16540-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org To align with the rest of the devicetree files and the relative properties, let's list the values of properties such as {reg/clock/interrupt}-names vertically. Suggested-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55.dtsi | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index b411c4ae34c3..61fdd601fc26 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -393,7 +393,11 @@ pcie_ep: pcie-ep@1c00000 { <0x40001000 0x1000>, <0x40200000 0x100000>, <0x01c03000 0x3000>; - reg-names = "parf", "dbi", "elbi", "atu", "addr_space", + reg-names = "parf", + "dbi", + "elbi", + "atu", + "addr_space", "mmio"; qcom,perst-regs = <&tcsr 0xb258 0xb270>; @@ -405,12 +409,18 @@ pcie_ep: pcie-ep@1c00000 { <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, <&gcc GCC_PCIE_SLEEP_CLK>, <&gcc GCC_PCIE_0_CLKREF_CLK>; - clock-names = "aux", "cfg", "bus_master", "bus_slave", - "slave_q2a", "sleep", "ref"; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "sleep", + "ref"; interrupts = , ; - interrupt-names = "global", "doorbell"; + interrupt-names = "global", + "doorbell"; reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; resets = <&gcc GCC_PCIE_BCR>; @@ -434,7 +444,10 @@ pcie_phy: phy@1c07000 { <&gcc GCC_PCIE_CFG_AHB_CLK>, <&gcc GCC_PCIE_0_CLKREF_CLK>, <&gcc GCC_PCIE_RCHNG_PHY_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "refgen"; + clock-names = "aux", + "cfg_ahb", + "ref", + "refgen"; resets = <&gcc GCC_PCIE_PHY_BCR>; reset-names = "phy"; From patchwork Fri Feb 24 10:59:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 656325 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBCE6C6FA9D for ; Fri, 24 Feb 2023 11:01:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230077AbjBXLBU (ORCPT ); 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Fri, 24 Feb 2023 02:59:56 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org Cc: konrad.dybcio@linaro.org, bhelgaas@google.com, kishon@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 09/13] ARM: dts: qcom: sdx55-t55: Enable PCIe RC support Date: Fri, 24 Feb 2023 16:29:02 +0530 Message-Id: <20230224105906.16540-10-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230224105906.16540-1-manivannan.sadhasivam@linaro.org> References: <20230224105906.16540-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable PCIe RC support on Thundercomm T55 board. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio --- arch/arm/boot/dts/qcom-sdx55-t55.dts | 42 ++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55-t55.dts b/arch/arm/boot/dts/qcom-sdx55-t55.dts index 7ed8feb99afb..6339af791b0b 100644 --- a/arch/arm/boot/dts/qcom-sdx55-t55.dts +++ b/arch/arm/boot/dts/qcom-sdx55-t55.dts @@ -242,6 +242,23 @@ &ipa { memory-region = <&ipa_fw_mem>; }; +&pcie_phy { + vdda-phy-supply = <&vreg_l1e_bb_1p2>; + vdda-pll-supply = <&vreg_l4e_bb_0p875>; + + status = "okay"; +}; + +&pcie_rc { + perst-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 53 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&pcie_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + &qpic_bam { status = "ok"; }; @@ -265,6 +282,31 @@ &remoteproc_mpss { memory-region = <&mpss_adsp_mem>; }; +&tlmm { + pcie_default: pcie-default-state { + clkreq-pins { + pins = "gpio56"; + function = "pcie_clkreq"; + drive-strength = <2>; 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Fri, 24 Feb 2023 03:00:01 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org Cc: konrad.dybcio@linaro.org, bhelgaas@google.com, kishon@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 10/13] ARM: dts: qcom: sdx55-t55: Move "status" property down Date: Fri, 24 Feb 2023 16:29:03 +0530 Message-Id: <20230224105906.16540-11-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230224105906.16540-1-manivannan.sadhasivam@linaro.org> References: <20230224105906.16540-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org To align with rest of the devicetree files, let's move the "status" property down Suggested-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55-t55.dts | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/qcom-sdx55-t55.dts b/arch/arm/boot/dts/qcom-sdx55-t55.dts index 6339af791b0b..67e366700105 100644 --- a/arch/arm/boot/dts/qcom-sdx55-t55.dts +++ b/arch/arm/boot/dts/qcom-sdx55-t55.dts @@ -237,9 +237,9 @@ &blsp1_uart3 { }; &ipa { - status = "okay"; - memory-region = <&ipa_fw_mem>; + + status = "okay"; }; &pcie_phy { @@ -278,8 +278,9 @@ nand@0 { }; &remoteproc_mpss { - status = "okay"; memory-region = <&mpss_adsp_mem>; + + status = "okay"; }; &tlmm { @@ -308,16 +309,18 @@ wake-pins { }; &usb_hsphy { - status = "okay"; vdda-pll-supply = <&vreg_l4e_bb_0p875>; vdda33-supply = <&vreg_l10e_3p1>; vdda18-supply = <&vreg_l5e_bb_1p7>; + + status = "okay"; }; &usb_qmpphy { - status = "okay"; vdda-phy-supply = <&vreg_l4e_bb_0p875>; vdda-pll-supply = <&vreg_l1e_bb_1p2>; + + status = "okay"; }; &usb { From patchwork Fri Feb 24 10:59:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 656324 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B34CC6FA9D for ; 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Fri, 24 Feb 2023 03:00:06 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org Cc: konrad.dybcio@linaro.org, bhelgaas@google.com, kishon@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 11/13] phy: qcom-qmp-pcie: Split out EP related init sequence for SDX55 Date: Fri, 24 Feb 2023 16:29:04 +0530 Message-Id: <20230224105906.16540-12-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230224105906.16540-1-manivannan.sadhasivam@linaro.org> References: <20230224105906.16540-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In preparation for adding RC support, let's split out the EP related init sequence so that the common sequence could be reused by RC as well. Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 42 ++++++++++++++++-------- 1 file changed, 28 insertions(+), 14 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 1b136a87053f..f526f73f76ef 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1122,10 +1122,25 @@ static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = { }; static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), +}; + +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a), QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a), QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19), @@ -1133,8 +1148,6 @@ static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03), QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03), QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f), QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02), QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff), @@ -1146,21 +1159,11 @@ static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01), QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56), QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d), QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b), QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), }; static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = { @@ -1212,6 +1215,9 @@ static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13), QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01), QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), +}; + +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_pcs_misc_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), }; @@ -2003,6 +2009,14 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { .pcs_misc = sdx55_qmp_pcie_pcs_misc_tbl, .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), }, + + .tbls_ep = &(const struct qmp_phy_cfg_tbls) { + .serdes = sdx55_qmp_pcie_ep_serdes_tbl, + .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_serdes_tbl), + .pcs_misc = sdx55_qmp_pcie_ep_pcs_misc_tbl, + .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_pcs_misc_tbl), + }, + .clk_list = sdm845_pciephy_clk_l, .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), .reset_list = sdm845_pciephy_reset_l, From patchwork Fri Feb 24 10:59:05 2023 Content-Type: text/plain; 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Fri, 24 Feb 2023 03:00:11 -0800 (PST) Received: from localhost.localdomain ([117.217.187.3]) by smtp.gmail.com with ESMTPSA id gd5-20020a17090b0fc500b00233cde36909sm1263853pjb.21.2023.02.24.03.00.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 03:00:11 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org Cc: konrad.dybcio@linaro.org, bhelgaas@google.com, kishon@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 12/13] phy: qcom-qmp-pcie: Add RC init sequence for SDX55 Date: Fri, 24 Feb 2023 16:29:05 +0530 Message-Id: <20230224105906.16540-13-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230224105906.16540-1-manivannan.sadhasivam@linaro.org> References: <20230224105906.16540-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add PCIe RC init sequence making use of the common init sequence. The RC mode additionally requires REFCLK_DRV_DSBL bit to set during powerup and powerdown. Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 49 ++++++++++++++++++- .../qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h | 2 + 2 files changed, 50 insertions(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index f526f73f76ef..9d92facd47a6 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1138,6 +1138,41 @@ static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), }; +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xce), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x97), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE1, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0d), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0xc3), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0xd0), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xd8), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x20), +}; + static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), @@ -1217,6 +1252,11 @@ static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), }; +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_pcs_misc_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), +}; + static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_pcs_misc_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), @@ -2010,6 +2050,13 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), }, + .tbls_rc = &(const struct qmp_phy_cfg_tbls) { + .serdes = sdx55_qmp_pcie_rc_serdes_tbl, + .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_rc_serdes_tbl), + .pcs_misc = sdx55_qmp_pcie_rc_pcs_misc_tbl, + .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_rc_pcs_misc_tbl), + }, + .tbls_ep = &(const struct qmp_phy_cfg_tbls) { .serdes = sdx55_qmp_pcie_ep_serdes_tbl, .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_serdes_tbl), @@ -2025,7 +2072,7 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), .regs = sm8250_pcie_regs_layout, - .pwrdn_ctrl = SW_PWRDN, + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .phy_status = PHYSTATUS_4_20, }; diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h index af273602998e..ac872a9eff9a 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h @@ -6,6 +6,8 @@ #ifndef QCOM_PHY_QMP_PCS_PCIE_V4_20_H_ #define QCOM_PHY_QMP_PCS_PCIE_V4_20_H_ +#define QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c +#define QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090 #define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0 #define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0 #define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4 From patchwork Fri Feb 24 10:59:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 656323 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68D60C64ED8 for ; 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Fri, 24 Feb 2023 03:00:16 -0800 (PST) Received: from localhost.localdomain ([117.217.187.3]) by smtp.gmail.com with ESMTPSA id gd5-20020a17090b0fc500b00233cde36909sm1263853pjb.21.2023.02.24.03.00.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 03:00:16 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org Cc: konrad.dybcio@linaro.org, bhelgaas@google.com, kishon@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 13/13] PCI: qcom: Add support for SDX55 SoC Date: Fri, 24 Feb 2023 16:29:06 +0530 Message-Id: <20230224105906.16540-14-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230224105906.16540-1-manivannan.sadhasivam@linaro.org> References: <20230224105906.16540-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for SDX55 SoC reusing the 1.9.0 config. The PCIe controller is of version 1.10.0 but it is compatible with the 1.9.0 config. This SoC also requires "sleep" clock which is added as an optional clock in the driver, since it is not required on other SoCs. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 77e5dc7b88ad..659df73114dd 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -182,7 +182,7 @@ struct qcom_pcie_resources_2_3_3 { /* 6 clocks typically, 7 for sm8250 */ struct qcom_pcie_resources_2_7_0 { - struct clk_bulk_data clks[12]; + struct clk_bulk_data clks[13]; int num_clks; struct regulator_bulk_data supplies[2]; struct reset_control *pci_reset; @@ -1208,6 +1208,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) res->clks[idx++].id = "noc_aggr_4"; res->clks[idx++].id = "noc_aggr_south_sf"; res->clks[idx++].id = "cnoc_qx"; + res->clks[idx++].id = "sleep"; num_opt_clks = idx - num_clks; res->num_clks = idx; @@ -1824,6 +1825,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-sc8180x", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sc8280xp", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sdm845", .data = &cfg_2_7_0 }, + { .compatible = "qcom,pcie-sdx55", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8150", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 },