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[83.9.32.99]) by smtp.gmail.com with ESMTPSA id i19-20020a056512007300b004dd7fefd2c8sm524046lfo.242.2023.02.24.05.08.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 05:08:01 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Sebastian Reichel , Stephan Gerhold , Luca Weiss , Iskren Chernev , Conor Dooley , Chanho Park , Lorenzo Pieralisi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] dt-bindings: arm: Add Cortex-A78C and X1C Date: Fri, 24 Feb 2023 14:07:57 +0100 Message-Id: <20230224130759.45579-1-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add compatibles for the Cortex-A78C and X1C cores found in some recent flagship designs. Signed-off-by: Konrad Dybcio Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/cpus.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index c145f6a035ee..a9bbe2b74b5d 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -139,6 +139,7 @@ properties: - arm,cortex-a77 - arm,cortex-a78 - arm,cortex-a78ae + - arm,cortex-a78c - arm,cortex-a510 - arm,cortex-a710 - arm,cortex-a715 @@ -151,6 +152,7 @@ properties: - arm,cortex-r5 - arm,cortex-r7 - arm,cortex-x1 + - arm,cortex-x1c - arm,cortex-x2 - arm,cortex-x3 - arm,neoverse-e1 From patchwork Fri Feb 24 13:07:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 657284 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F328CC6FA99 for ; Fri, 24 Feb 2023 13:08:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229584AbjBXNII (ORCPT ); Fri, 24 Feb 2023 08:08:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39164 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230163AbjBXNIH (ORCPT ); Fri, 24 Feb 2023 08:08:07 -0500 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A9EEE12BD0 for ; Fri, 24 Feb 2023 05:08:05 -0800 (PST) Received: by mail-lf1-x12e.google.com with SMTP id g17so5108331lfv.4 for ; Fri, 24 Feb 2023 05:08:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1677244084; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EPreAIsPBs0vo9Qsm+CM5kGjxjzbL2RRreZgJMx8oPk=; b=cJdEzQNdVzHBlQVlfDkZ4stM6P+/jhwF5aDU9BVUr5epgTQZrsOmTCdIcFh3ew1/Ui eFeGRMjuHUErKRT6h/3VN26wS6UoJ8FdId4RY+dEFNfkPr7VH8G1auSMMLNsT6NCR27W m6xWUU3u9lkIHwT9BKScyBCbFXBPGWwJHF5wPEvPdgnqPeMIsA970HoTRrTKt64t9JLP vQfrmFfo1UBtYE6oExAtVX12C3I0K4Ks0dnnEaCMMuUadrDXZ/xf2NyqK5vIrGafb673 vOprKJVEGlz6nrcYNLMFj4pMufGbn7EuakGc/6LWEaL3Rfa/gA/bzpttKMp0XbTZqFHJ 82bQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1677244084; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EPreAIsPBs0vo9Qsm+CM5kGjxjzbL2RRreZgJMx8oPk=; b=ALcGLbPzyD9P3sj7R+2c3ZmcTF8kIwtlO32obCZgTGgc0sVmo3TeUCQgZk1iMUUFnH sbT6kQyH3GyU7jdFol/OI081v0N+agHGTZ7n2tpA34TPPRNXQoZv78BWAK2mPufvyDXR DWcFw+s2Y16JT5wfjtTXvIXrrEXTjrknW8M64rqHESMu2OcqElEYDUwwSVHm9DZcHeYO rklmszWMmo7LVgJTzwZ2/A2KYARBVwycKYxAbfYFeg6t0G0GWPLdIx1+BdmBseASw+gF tsjtIjToC8kfkD4rR6lJz+t+/0XtKLWC4kA53cusvGDvRdRbhsgbRk7VoY0xabUCEf7V i0aw== X-Gm-Message-State: AO0yUKV9xsLEqKThSc9CUfSPPJYly/6QY1MEyWDsTE1Zqz2c60WrkBEl FeMUKKfiG03q+KAlHcOz0l4fnw== X-Google-Smtp-Source: AK7set8+cjo3A4v4txcKI1tpKNOIYdz++lPbFizEkFnGvQRsMB9gq98YcsVIBQ02klbWKAU+VDL43w== X-Received: by 2002:ac2:48b7:0:b0:4db:3a6f:df17 with SMTP id u23-20020ac248b7000000b004db3a6fdf17mr5132455lfg.51.1677244083883; Fri, 24 Feb 2023 05:08:03 -0800 (PST) Received: from localhost.localdomain (abym99.neoplus.adsl.tpnet.pl. [83.9.32.99]) by smtp.gmail.com with ESMTPSA id i19-20020a056512007300b004dd7fefd2c8sm524046lfo.242.2023.02.24.05.08.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 05:08:03 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Sebastian Reichel , Stephan Gerhold , Luca Weiss , Iskren Chernev , Conor Dooley , Chanho Park , Lorenzo Pieralisi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] arm64: dts: qcom: sc8280xp: Use correct CPU compatibles Date: Fri, 24 Feb 2023 14:07:58 +0100 Message-Id: <20230224130759.45579-2-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230224130759.45579-1-konrad.dybcio@linaro.org> References: <20230224130759.45579-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Cores 0-3 are CA78C r0p0, cores 4-7 are CX1C r0p0. Use the correct compatibles instead of the placeholder qcom,kryo. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 0d02599d8867..9c186ba55cdc 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -43,7 +43,7 @@ cpus { CPU0: cpu@0 { device_type = "cpu"; - compatible = "qcom,kryo"; + compatible = "arm,cortex-a78c"; reg = <0x0 0x0>; enable-method = "psci"; capacity-dmips-mhz = <602>; @@ -67,7 +67,7 @@ L3_0: l3-cache { CPU1: cpu@100 { device_type = "cpu"; - compatible = "qcom,kryo"; + compatible = "arm,cortex-a78c"; reg = <0x0 0x100>; enable-method = "psci"; capacity-dmips-mhz = <602>; @@ -87,7 +87,7 @@ L2_100: l2-cache { CPU2: cpu@200 { device_type = "cpu"; - compatible = "qcom,kryo"; + compatible = "arm,cortex-a78c"; reg = <0x0 0x200>; enable-method = "psci"; capacity-dmips-mhz = <602>; @@ -107,7 +107,7 @@ L2_200: l2-cache { CPU3: cpu@300 { device_type = "cpu"; - compatible = "qcom,kryo"; + compatible = "arm,cortex-a78c"; reg = <0x0 0x300>; enable-method = "psci"; capacity-dmips-mhz = <602>; @@ -127,7 +127,7 @@ L2_300: l2-cache { CPU4: cpu@400 { device_type = "cpu"; - compatible = "qcom,kryo"; + compatible = "arm,cortex-x1c"; reg = <0x0 0x400>; enable-method = "psci"; capacity-dmips-mhz = <1024>; @@ -147,7 +147,7 @@ L2_400: l2-cache { CPU5: cpu@500 { device_type = "cpu"; - compatible = "qcom,kryo"; + compatible = "arm,cortex-x1c"; reg = <0x0 0x500>; enable-method = "psci"; capacity-dmips-mhz = <1024>; @@ -167,7 +167,7 @@ L2_500: l2-cache { CPU6: cpu@600 { device_type = "cpu"; - compatible = "qcom,kryo"; + compatible = "arm,cortex-x1c"; reg = <0x0 0x600>; enable-method = "psci"; capacity-dmips-mhz = <1024>; @@ -187,7 +187,7 @@ L2_600: l2-cache { CPU7: cpu@700 { device_type = "cpu"; - compatible = "qcom,kryo"; + compatible = "arm,cortex-x1c"; reg = <0x0 0x700>; enable-method = "psci"; capacity-dmips-mhz = <1024>;