From patchwork Fri Feb 24 16:26:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 657281 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F790C7EE2F for ; Fri, 24 Feb 2023 16:26:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229642AbjBXQ0h (ORCPT ); Fri, 24 Feb 2023 11:26:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229610AbjBXQ0f (ORCPT ); Fri, 24 Feb 2023 11:26:35 -0500 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E44DE6A7B6 for ; Fri, 24 Feb 2023 08:26:34 -0800 (PST) Received: by mail-wr1-x434.google.com with SMTP id t15so14608254wrz.7 for ; Fri, 24 Feb 2023 08:26:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FYNxCoy2kO8Df1US+5U8F6a2dVH3sUiqyDcA4T+cIdk=; b=En6Si0WFgSuFebHftBEO8bUQY7IXWNBN8xsTRVwkNrqnPGfu+D8r/lYQcuhdU8YUPP YgRH44w/1MWw8wEHfpe7mB7OWrRWbLHMGvuyPv/WSDum94YBwysEwpw552laUM2K8L0d +MDRijxrej0aeRLxf7Dpl5bA/cOZoff5DCrhZQxXe/4cSN1FUxqlpPAN+JRo7AirD5yI Ro09nnO6q3z/UwhLgl8D6zfK0a74bGu8FTaYZC7G2OENX6Np7Iq1jKSklpL/ttYjDV2C /oEpU0uEhBUEj0TwxlCeOsnYfqM6POjbCpx8+P+YDm4rVgAHYhcNYxyNh/U6nn8ZmT9F V3iQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FYNxCoy2kO8Df1US+5U8F6a2dVH3sUiqyDcA4T+cIdk=; b=8LLAXhWdFpZA63o+sE8Z+xPXK1C0pZUmAJvZLFV4ONqUZz1gKyQUAXLUh0SwNRjysd WO9vc3ruzHpquB1HbhGEvWZKNSQeLasopIaQ5dM4auWP4aXMOev0qYnEPMphoOzs6V7c OSnVrLr21vlKmxRKHV/ZvrOWXJlrjsyxIh5/cPSNJXFluckw9KkVfDdnUD2Gsojew9Et kkmw8BQoP6cQTVk63p8MOZnZItB8BLmqSweFsV3zdu/Bm/atm8oaWHdNFDJa+qOwiwbD gdwVpSRDEYB9yfcV+INMU1ZZGdhmQSxzCZ1pHbcD+bko75Bmny3NSbo3fNkSuwuygPzg n2tw== X-Gm-Message-State: AO0yUKWSQ4TTeVCkSUv5EmFGF/2gLEjtSjN7UQkJ6Z5s+ih7bgQUXp2D 3YnSqf9xmrVJIy95hYodQfXQzQ== X-Google-Smtp-Source: AK7set/GnWAY+QoOE4/JlyN7MAfKde64aupvlOHt32saZ6ryvyjf7Edvr9vRivLB3FGJ0yazaa1Mkw== X-Received: by 2002:a5d:5512:0:b0:2c7:1210:feaa with SMTP id b18-20020a5d5512000000b002c71210feaamr5381917wrv.26.1677255993449; Fri, 24 Feb 2023 08:26:33 -0800 (PST) Received: from localhost (2001-1ae9-1c2-4c00-20f-c6b4-1e57-7965.ip6.tmcz.cz. [2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id t16-20020a5d5350000000b002c53cc7504csm10368171wrv.78.2023.02.24.08.26.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 08:26:33 -0800 (PST) From: Andrew Jones To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, devicetree@vger.kernel.org Cc: 'Conor Dooley ' , 'Paul Walmsley ' , 'Palmer Dabbelt ' , 'Sudip Mukherjee ' , 'Ben Dooks ' , 'Atish Patra ' , 'Albert Ou ' , 'Anup Patel ' , 'Krzysztof Kozlowski ' , 'Rob Herring ' , 'Jisheng Zhang ' , 'Heiko Stuebner ' Subject: [PATCH v6 1/8] RISC-V: alternatives: Support patching multiple insns in assembly Date: Fri, 24 Feb 2023 17:26:24 +0100 Message-Id: <20230224162631.405473-2-ajones@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230224162631.405473-1-ajones@ventanamicro.com> References: <20230224162631.405473-1-ajones@ventanamicro.com> MIME-Version: 1.0 Content-type: text/plain Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org As pointed out in commit d374a16539b1 ("RISC-V: fix compile error from deduplicated __ALTERNATIVE_CFG_2"), we need quotes around parameters passed to macros within macros to avoid spaces being interpreted as separators. ALT_NEW_CONTENT was trying to handle this by defining new_c has a vararg, but this isn't sufficient for calling ALTERNATIVE() from assembly with multiple instructions in the new/old sequences. Remove the vararg "hack" and use quotes. Signed-off-by: Andrew Jones Reviewed-by: Conor Dooley --- arch/riscv/include/asm/alternative-macros.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/include/asm/alternative-macros.h index 993a44a8fdac..b8c55fb3ab2c 100644 --- a/arch/riscv/include/asm/alternative-macros.h +++ b/arch/riscv/include/asm/alternative-macros.h @@ -14,7 +14,7 @@ .4byte \patch_id .endm -.macro ALT_NEW_CONTENT vendor_id, patch_id, enable = 1, new_c : vararg +.macro ALT_NEW_CONTENT vendor_id, patch_id, enable = 1, new_c .if \enable .pushsection .alternative, "a" ALT_ENTRY 886b, 888f, \vendor_id, \patch_id, 889f - 888f @@ -41,13 +41,13 @@ \old_c .option pop 887 : - ALT_NEW_CONTENT \vendor_id, \patch_id, \enable, \new_c + ALT_NEW_CONTENT \vendor_id, \patch_id, \enable, "\new_c" .endm .macro ALTERNATIVE_CFG_2 old_c, new_c_1, vendor_id_1, patch_id_1, enable_1, \ new_c_2, vendor_id_2, patch_id_2, enable_2 ALTERNATIVE_CFG "\old_c", "\new_c_1", \vendor_id_1, \patch_id_1, \enable_1 - ALT_NEW_CONTENT \vendor_id_2, \patch_id_2, \enable_2, \new_c_2 + ALT_NEW_CONTENT \vendor_id_2, \patch_id_2, \enable_2, "\new_c_2" .endm #define __ALTERNATIVE_CFG(...) ALTERNATIVE_CFG __VA_ARGS__ From patchwork Fri Feb 24 16:26:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 657280 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40786C7EE2D for ; Fri, 24 Feb 2023 16:26:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229738AbjBXQ0q (ORCPT ); Fri, 24 Feb 2023 11:26:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53824 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229610AbjBXQ0h (ORCPT ); Fri, 24 Feb 2023 11:26:37 -0500 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3886E6EB0B for ; Fri, 24 Feb 2023 08:26:36 -0800 (PST) Received: by mail-wr1-x436.google.com with SMTP id q16so4153532wrw.2 for ; Fri, 24 Feb 2023 08:26:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=K7rGW7hYEauj0lEHNx054QYhURQUQQG6A8fMOX9HH84=; b=RKqYoE96klcsM5eA//F76t0V+zO9OQvwwBKBQ77Ld8n2SOHHJSGhBHre9+TrbmLg+o dc34CetaLatRWo/FVB1zzFELNGy8JhmmN9Qa+JXiXcOnXDr137/7bPD7R8XGC3p8k4/j NKlIDe+e4cDuGoIQl+28FOOiIz6lDS+GG2UkxoCBmhdjLMGw4n/yrFvnHU0zL9IJJe1/ 0SH4qE47mmAZWUiXuU6sg2VJBsAbDco/MSTG0tBoPkemCdtlp99mNEwwz0MuRWQvnwPt Xp+OH3iSZn6RKtfuy79sG1xBGhuhhlRp8bxCrqAr7RhYZ+vsSxYdKovagshJpdo0I2ef E0Vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=K7rGW7hYEauj0lEHNx054QYhURQUQQG6A8fMOX9HH84=; b=fMJjmmBBhvkVxjD6O6VV8mvGbCZ9FCZz0/YFhurjtB0TULozitrbvfSFRJOlUq3+UX sADfiYrdIJ8qF6FwQisk7GXziBFXNzTmjePJcwwIsZUzAue+C9dR9ztzstrHO/fBICcW RTtQjfBxKEIZl0cdSUBB1ZxA3UffNzjD0tG0I29vQFd/+/QVW1WsyfaNjcEvnKuozahX 9kJr+k15cMUH2pjRR5DooAajj8jYngycJcYlQPoN3MyCNq1wt+mSYm6HfNPHLUnq+cEq M94zofQ2HirgjzYukP+tqGlbS8+wiA/6NIrU6Lswtgb48XpyqsXhuH+Ec8WkzzFcNZmW 1ywg== X-Gm-Message-State: AO0yUKXWxZZ8b+YveVDc0kIiSQykkSWvEJvJaVZVjJjZ3d6Nq94VrB0n oPCKIeqLeti9mS4Ugg3RGZQmbw== X-Google-Smtp-Source: AK7set9db9FJqAXFvqnxkWNWao+YM41d9TaJzN8ugnsztfkd9yIZbvWR8jbKEB5MZVXaCknWRUaPNg== X-Received: by 2002:a5d:504f:0:b0:2bf:942b:ddc with SMTP id h15-20020a5d504f000000b002bf942b0ddcmr13630182wrt.55.1677255994674; Fri, 24 Feb 2023 08:26:34 -0800 (PST) Received: from localhost (2001-1ae9-1c2-4c00-20f-c6b4-1e57-7965.ip6.tmcz.cz. [2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id t26-20020a05600c2f9a00b003eae73f0fc1sm3307797wmn.18.2023.02.24.08.26.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 08:26:34 -0800 (PST) From: Andrew Jones To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, devicetree@vger.kernel.org Cc: 'Conor Dooley ' , 'Paul Walmsley ' , 'Palmer Dabbelt ' , 'Sudip Mukherjee ' , 'Ben Dooks ' , 'Atish Patra ' , 'Albert Ou ' , 'Anup Patel ' , 'Krzysztof Kozlowski ' , 'Rob Herring ' , 'Jisheng Zhang ' , 'Heiko Stuebner ' Subject: [PATCH v6 2/8] RISC-V: Factor out body of riscv_init_cbom_blocksize loop Date: Fri, 24 Feb 2023 17:26:25 +0100 Message-Id: <20230224162631.405473-3-ajones@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230224162631.405473-1-ajones@ventanamicro.com> References: <20230224162631.405473-1-ajones@ventanamicro.com> MIME-Version: 1.0 Content-type: text/plain Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Refactor riscv_init_cbom_blocksize() to prepare for it to be used for both cbom block size and cboz block size. Signed-off-by: Andrew Jones Reviewed-by: Heiko Stuebner Reviewed-by: Conor Dooley --- arch/riscv/mm/cacheflush.c | 45 +++++++++++++++++++++----------------- 1 file changed, 25 insertions(+), 20 deletions(-) diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c index 3cc07ed45aeb..eaf23fc14966 100644 --- a/arch/riscv/mm/cacheflush.c +++ b/arch/riscv/mm/cacheflush.c @@ -98,34 +98,39 @@ void flush_icache_pte(pte_t pte) unsigned int riscv_cbom_block_size; EXPORT_SYMBOL_GPL(riscv_cbom_block_size); +static void cbo_get_block_size(struct device_node *node, + const char *name, u32 *block_size, + unsigned long *first_hartid) +{ + unsigned long hartid; + u32 val; + + if (riscv_of_processor_hartid(node, &hartid)) + return; + + if (of_property_read_u32(node, name, &val)) + return; + + if (!*block_size) { + *block_size = val; + *first_hartid = hartid; + } else if (*block_size != val) { + pr_warn("%s mismatched between harts %lu and %lu\n", + name, *first_hartid, hartid); + } +} + void riscv_init_cbom_blocksize(void) { struct device_node *node; unsigned long cbom_hartid; - u32 val, probed_block_size; - int ret; + u32 probed_block_size; probed_block_size = 0; for_each_of_cpu_node(node) { - unsigned long hartid; - - ret = riscv_of_processor_hartid(node, &hartid); - if (ret) - continue; - /* set block-size for cbom extension if available */ - ret = of_property_read_u32(node, "riscv,cbom-block-size", &val); - if (ret) - continue; - - if (!probed_block_size) { - probed_block_size = val; - cbom_hartid = hartid; - } else { - if (probed_block_size != val) - pr_warn("cbom-block-size mismatched between harts %lu and %lu\n", - cbom_hartid, hartid); - } + cbo_get_block_size(node, "riscv,cbom-block-size", + &probed_block_size, &cbom_hartid); } if (probed_block_size) From patchwork Fri Feb 24 16:26:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 656317 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C87F1C7EE31 for ; Fri, 24 Feb 2023 16:26:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229763AbjBXQ0r (ORCPT ); Fri, 24 Feb 2023 11:26:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53684 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229688AbjBXQ0k (ORCPT ); Fri, 24 Feb 2023 11:26:40 -0500 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 625606A7AF for ; Fri, 24 Feb 2023 08:26:37 -0800 (PST) Received: by mail-wm1-x32c.google.com with SMTP id k37so66170wms.0 for ; Fri, 24 Feb 2023 08:26:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/ulHjChwX0EpCdPBQp6OD2TjDP7InY37wU45TsSAj1w=; b=Hqo7fu1B4xqPawDMyW66q3vces/lc1k8SQ+c8oQEtP6S3LvATJfoIKXuRYcluW7sfy +ugmVcqInbSAczNkKhfdWaI3i8SO4YOZWvKcrdtgk6OIuxNLt2RkpXwslwuEonv9zXph vxeHEaoiDJOu4nqWOCTZ6P2mXWns/DP9NTw5VBWS/trQxmwUIZ1F0pmY4RQA/Xh7rfTl rtBrfIN/Px2t1plT6ZbP2YvAzk1H1PV5QkTHqcBEwHvcN5EwRy+lX5NfhLqVAOjH74mh ZSM+9eG0NGdZSqiMlM8N2QbPkiKSDr8QRwjKSQKha5gxA+Vd9I+jXViZAqAIzsIpkZ7e IK6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/ulHjChwX0EpCdPBQp6OD2TjDP7InY37wU45TsSAj1w=; b=PowqP856JPwGUlSNgsPjiciM743uRUwOCM01EA7yRioETgE0o0GQaPqc3yO0b69IgM RLm6qv066zzdl0QPB6VEjcF/lx7iTYXAlx27rm26gAoFvbrQlqzOBxQJZiqQ4bUws5pB Cn6SVZiIuT7FzwsJ9VqQC51eBd3sgGYMn1Qzs2sr3AfUqcSCxH+NCDKwYuzBrvPUxGa0 FkeEEbsZ527Bb1jtfBQZtecT2LsixDOsQP+GtHKDGrA2yCdNgQg+eTtWHd5I34gYyUcG qIX3DpeAgC1QYzakoHnTTJYhS3YHwM6HxfFNBCpluXLSiA1iC1ULopHEVkqgN7XeArdd P+JQ== X-Gm-Message-State: AO0yUKXIPm7PFevonNzw1ZjtjqXaJGTbY2vT9jCTYlaZLC1DeQRJd1YH Z8JS2V8JZlFi/iYYU8WBRuZfOw== X-Google-Smtp-Source: AK7set8zVxc5qiCueExOLHTCFNNzolxFPSj234tIjv7/zx7MafBbdDpFH8c7Yoswk3smf5KklatbGA== X-Received: by 2002:a05:600c:331b:b0:3eb:2da4:f32d with SMTP id q27-20020a05600c331b00b003eb2da4f32dmr1107776wmp.26.1677255995904; Fri, 24 Feb 2023 08:26:35 -0800 (PST) Received: from localhost (2001-1ae9-1c2-4c00-20f-c6b4-1e57-7965.ip6.tmcz.cz. [2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id t25-20020a7bc3d9000000b003e896d953a8sm3377129wmj.17.2023.02.24.08.26.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 08:26:35 -0800 (PST) From: Andrew Jones To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, devicetree@vger.kernel.org Cc: 'Conor Dooley ' , 'Paul Walmsley ' , 'Palmer Dabbelt ' , 'Sudip Mukherjee ' , 'Ben Dooks ' , 'Atish Patra ' , 'Albert Ou ' , 'Anup Patel ' , 'Krzysztof Kozlowski ' , 'Rob Herring ' , 'Jisheng Zhang ' , 'Heiko Stuebner ' Subject: [PATCH v6 3/8] dt-bindings: riscv: Document cboz-block-size Date: Fri, 24 Feb 2023 17:26:26 +0100 Message-Id: <20230224162631.405473-4-ajones@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230224162631.405473-1-ajones@ventanamicro.com> References: <20230224162631.405473-1-ajones@ventanamicro.com> MIME-Version: 1.0 Content-type: text/plain Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Zicboz operation (cbo.zero) operates on a block-size defined for the cpu-core. While we already have the riscv,cbom-block-size property, it only provides the block size for Zicbom operations. Even though it's likely Zicboz and Zicbom will use the same size, that's not required by the specification. Create another property specifically for Zicboz. Cc: Rob Herring Signed-off-by: Andrew Jones Reviewed-by: Conor Dooley Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 001931d526ec..f24cf9601c6e 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -72,6 +72,11 @@ properties: description: The blocksize in bytes for the Zicbom cache operations. + riscv,cboz-block-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The blocksize in bytes for the Zicboz cache operations. + riscv,isa: description: Identifies the specific RISC-V instruction set architecture From patchwork Fri Feb 24 16:26:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 657279 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72069C7EE23 for ; Fri, 24 Feb 2023 16:26:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229779AbjBXQ0r (ORCPT ); Fri, 24 Feb 2023 11:26:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53824 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229630AbjBXQ0p (ORCPT ); Fri, 24 Feb 2023 11:26:45 -0500 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DCD626ADE1 for ; Fri, 24 Feb 2023 08:26:38 -0800 (PST) Received: by mail-wr1-x435.google.com with SMTP id l25so14095545wrb.3 for ; Fri, 24 Feb 2023 08:26:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dbdPBOzzPYzUW7R/pezDgOGaiAEFQuXRsOtgnDBQFk4=; b=UV0emYXoBdJT27zo07mpFRgP47HFrrkzCdPAE2IF+ljnUcWeCB+QdRhSMUZYtmHeUT BbvjmiMAzv7zmLkN1pG+62nPCAoaaGSZQYaPzO4ESn1DJE1fsqvjmqTWKW0HTkHGk9Rq U2Z+pdIW21je+7Yugu0i5Dxim5B1n/z+VfY2wWcdI8ZmaIPu8hvxmsJILWwd/I1if06e 6jhJU0sJROWLKuEsQEF1W3dVxdpGkpMIzgN79kV+doivKZ444hE/Og4inPnLkrM9eBCE nLicS71uUR8gvtz0xGgJDs90jinhK3hD9y4CDTtj4zsqtGK1xVjSP67d4dnufrI8rnqP FwhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dbdPBOzzPYzUW7R/pezDgOGaiAEFQuXRsOtgnDBQFk4=; b=1JYaWa1+LR1OmJ19gBi/h08Nbm43+uuaL5TT/RVW8W/WJLIeCFUFWlDU7xVR5QmpvF Dwa0WyVzU33Sp1hIXV0ykL+1+XY7FeHJV2QLMr3RmsFaoeKHs+U+ABfgrWYGDj8d0+93 YCuS29C8Zw7DNMdqHuNqM+vi+rBlhkY2ARHgRtO1nSZpbOZlz10QAobqJfg6hD+RVbzx bTg3yGqD9u78XjeWCvZ71DMSEzMpF2pFdh4vF6o1NMU/sq7dOKR81sd/YFidilksJffS 8i4hRWx6iGtAF59XdUQtvnTmyw1L8Y+lPN0hL6SzE68HX2SzoqoGuiDaQ/hcRcYAax+e QpVA== X-Gm-Message-State: AO0yUKV3bZKVDAp7+JZekx9/6dfFA5nmmiODG5THNPD38X2+ezbTr9mB e+mt/vgvWCH3BlwR9RyGXhYUXg== X-Google-Smtp-Source: AK7set9W+IJgMgm8MUii/vuWSBmohf3LUCoVdSgiqdilF8D2R8yuYJCXwcKt5dPltMDNFz6zm9pP9w== X-Received: by 2002:a5d:4ec9:0:b0:2c7:7b7:eed2 with SMTP id s9-20020a5d4ec9000000b002c707b7eed2mr10581390wrv.69.1677255997316; Fri, 24 Feb 2023 08:26:37 -0800 (PST) Received: from localhost (2001-1ae9-1c2-4c00-20f-c6b4-1e57-7965.ip6.tmcz.cz. [2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id l11-20020adff48b000000b002c592535839sm13524154wro.17.2023.02.24.08.26.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 08:26:36 -0800 (PST) From: Andrew Jones To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, devicetree@vger.kernel.org Cc: 'Conor Dooley ' , 'Paul Walmsley ' , 'Palmer Dabbelt ' , 'Sudip Mukherjee ' , 'Ben Dooks ' , 'Atish Patra ' , 'Albert Ou ' , 'Anup Patel ' , 'Krzysztof Kozlowski ' , 'Rob Herring ' , 'Jisheng Zhang ' , 'Heiko Stuebner ' Subject: [PATCH v6 4/8] RISC-V: Add Zicboz detection and block size parsing Date: Fri, 24 Feb 2023 17:26:27 +0100 Message-Id: <20230224162631.405473-5-ajones@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230224162631.405473-1-ajones@ventanamicro.com> References: <20230224162631.405473-1-ajones@ventanamicro.com> MIME-Version: 1.0 Content-type: text/plain Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Parse "riscv,cboz-block-size" from the DT by piggybacking on Zicbom's riscv_init_cbom_blocksize(). Additionally check the DT for the presence of the "zicboz" extension and, when it's present, validate the parsed cboz block size as we do Zicbom's cbom block size with riscv_isa_extension_check(). Signed-off-by: Andrew Jones Reviewed-by: Heiko Stuebner Reviewed-by: Conor Dooley --- arch/riscv/include/asm/cacheflush.h | 3 ++- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpu.c | 1 + arch/riscv/kernel/cpufeature.c | 10 ++++++++++ arch/riscv/kernel/setup.c | 2 +- arch/riscv/mm/cacheflush.c | 23 +++++++++++++++-------- 6 files changed, 30 insertions(+), 10 deletions(-) diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h index 03e3b95ae6da..8091b8bf4883 100644 --- a/arch/riscv/include/asm/cacheflush.h +++ b/arch/riscv/include/asm/cacheflush.h @@ -50,7 +50,8 @@ void flush_icache_mm(struct mm_struct *mm, bool local); #endif /* CONFIG_SMP */ extern unsigned int riscv_cbom_block_size; -void riscv_init_cbom_blocksize(void); +extern unsigned int riscv_cboz_block_size; +void riscv_init_cbo_blocksizes(void); #ifdef CONFIG_RISCV_DMA_NONCOHERENT void riscv_noncoherent_supported(void); diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 8f3994a7f0ca..a96d3d7d7d28 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -42,6 +42,7 @@ #define RISCV_ISA_EXT_ZBB 30 #define RISCV_ISA_EXT_ZICBOM 31 #define RISCV_ISA_EXT_ZIHINTPAUSE 32 +#define RISCV_ISA_EXT_ZICBOZ 33 #define RISCV_ISA_EXT_MAX 64 #define RISCV_ISA_EXT_NAME_LEN_MAX 32 diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 8400f0cc9704..1b0411280141 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -186,6 +186,7 @@ arch_initcall(riscv_cpuinfo_init); */ static struct riscv_isa_ext_data isa_ext_arr[] = { __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), + __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ), __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 6569d963fc7d..538779d03311 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -74,6 +74,15 @@ static bool riscv_isa_extension_check(int id) return false; } return true; + case RISCV_ISA_EXT_ZICBOZ: + if (!riscv_cboz_block_size) { + pr_err("Zicboz detected in ISA string, but no cboz-block-size found\n"); + return false; + } else if (!is_power_of_2(riscv_cboz_block_size)) { + pr_err("cboz-block-size present, but is not a power-of-2\n"); + return false; + } + return true; } return true; @@ -222,6 +231,7 @@ void __init riscv_fill_hwcap(void) SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB); SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM); + SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ); SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE); } #undef SET_ISA_EXT_MAP diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index 376d2827e736..5d3184cbf518 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -297,7 +297,7 @@ void __init setup_arch(char **cmdline_p) setup_smp(); #endif - riscv_init_cbom_blocksize(); + riscv_init_cbo_blocksizes(); riscv_fill_hwcap(); apply_boot_alternatives(); if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM) && diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c index eaf23fc14966..ba4832bb949b 100644 --- a/arch/riscv/mm/cacheflush.c +++ b/arch/riscv/mm/cacheflush.c @@ -98,6 +98,9 @@ void flush_icache_pte(pte_t pte) unsigned int riscv_cbom_block_size; EXPORT_SYMBOL_GPL(riscv_cbom_block_size); +unsigned int riscv_cboz_block_size; +EXPORT_SYMBOL_GPL(riscv_cboz_block_size); + static void cbo_get_block_size(struct device_node *node, const char *name, u32 *block_size, unsigned long *first_hartid) @@ -120,19 +123,23 @@ static void cbo_get_block_size(struct device_node *node, } } -void riscv_init_cbom_blocksize(void) +void riscv_init_cbo_blocksizes(void) { + unsigned long cbom_hartid, cboz_hartid; + u32 cbom_block_size = 0, cboz_block_size = 0; struct device_node *node; - unsigned long cbom_hartid; - u32 probed_block_size; - probed_block_size = 0; for_each_of_cpu_node(node) { - /* set block-size for cbom extension if available */ + /* set block-size for cbom and/or cboz extension if available */ cbo_get_block_size(node, "riscv,cbom-block-size", - &probed_block_size, &cbom_hartid); + &cbom_block_size, &cbom_hartid); + cbo_get_block_size(node, "riscv,cboz-block-size", + &cboz_block_size, &cboz_hartid); } - if (probed_block_size) - riscv_cbom_block_size = probed_block_size; + if (cbom_block_size) + riscv_cbom_block_size = cbom_block_size; + + if (cboz_block_size) + riscv_cboz_block_size = cboz_block_size; } From patchwork Fri Feb 24 16:26:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 656316 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2029C7EE32 for ; Fri, 24 Feb 2023 16:26:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229669AbjBXQ0t (ORCPT ); Fri, 24 Feb 2023 11:26:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54190 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229742AbjBXQ0q (ORCPT ); Fri, 24 Feb 2023 11:26:46 -0500 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 20F3270ED3 for ; Fri, 24 Feb 2023 08:26:40 -0800 (PST) Received: by mail-wr1-x42e.google.com with SMTP id l1so14215810wry.10 for ; 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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id a18-20020adfe5d2000000b002be505ab59asm14229155wrn.97.2023.02.24.08.26.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 08:26:38 -0800 (PST) From: Andrew Jones To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, devicetree@vger.kernel.org Cc: 'Conor Dooley ' , 'Paul Walmsley ' , 'Palmer Dabbelt ' , 'Sudip Mukherjee ' , 'Ben Dooks ' , 'Atish Patra ' , 'Albert Ou ' , 'Anup Patel ' , 'Krzysztof Kozlowski ' , 'Rob Herring ' , 'Jisheng Zhang ' , 'Heiko Stuebner ' Subject: [PATCH v6 5/8] RISC-V: cpufeatures: Put the upper 16 bits of patch ID to work Date: Fri, 24 Feb 2023 17:26:28 +0100 Message-Id: <20230224162631.405473-6-ajones@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230224162631.405473-1-ajones@ventanamicro.com> References: <20230224162631.405473-1-ajones@ventanamicro.com> MIME-Version: 1.0 Content-type: text/plain Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org cpufeature IDs are consecutive integers starting at 26, so a 32-bit patch ID allows an aircraft carrier load of feature IDs. Repurposing the upper 16 bits still leaves a boat load of feature IDs and gains 16 bits which may be used to control patching on a per patch-site basis. This will be initially used in Zicboz's application to clear_page(), as Zicboz's block size must also be considered. In that case, the upper 16-bit value's role will be to convey the maximum block size which the Zicboz clear_page() implementation supports. cpufeature patch sites which need to check for the existence or absence of other cpufeatures may also be able to make use of this. Signed-off-by: Andrew Jones Reviewed-by: Conor Dooley --- arch/riscv/include/asm/alternative.h | 4 +++ arch/riscv/kernel/cpufeature.c | 37 +++++++++++++++++++++++++--- 2 files changed, 37 insertions(+), 4 deletions(-) diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/alternative.h index c8dea9e94310..58ccd2f8cab7 100644 --- a/arch/riscv/include/asm/alternative.h +++ b/arch/riscv/include/asm/alternative.h @@ -13,10 +13,14 @@ #ifdef CONFIG_RISCV_ALTERNATIVE #include +#include #include #include #include +#define PATCH_ID_CPUFEATURE_ID(p) lower_16_bits(p) +#define PATCH_ID_CPUFEATURE_VALUE(p) upper_16_bits(p) + #define RISCV_ALTERNATIVES_BOOT 0 /* alternatives applied during regular boot */ #define RISCV_ALTERNATIVES_MODULE 1 /* alternatives applied during module-init */ #define RISCV_ALTERNATIVES_EARLY_BOOT 2 /* alternatives applied before mmu start */ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 538779d03311..d424cd76beb1 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -274,12 +274,35 @@ void __init riscv_fill_hwcap(void) } #ifdef CONFIG_RISCV_ALTERNATIVE +/* + * Alternative patch sites consider 48 bits when determining when to patch + * the old instruction sequence with the new. These bits are broken into a + * 16-bit vendor ID and a 32-bit patch ID. A non-zero vendor ID means the + * patch site is for an erratum, identified by the 32-bit patch ID. When + * the vendor ID is zero, the patch site is for a cpufeature. cpufeatures + * further break down patch ID into two 16-bit numbers. The lower 16 bits + * are the cpufeature ID and the upper 16 bits are used for a value specific + * to the cpufeature and patch site. If the upper 16 bits are zero, then it + * implies no specific value is specified. cpufeatures that want to control + * patching on a per-site basis will provide non-zero values and implement + * checks here. The checks return true when patching should be done, and + * false otherwise. + */ +static bool riscv_cpufeature_patch_check(u16 id, u16 value) +{ + if (!value) + return true; + + return false; +} + void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin, struct alt_entry *end, unsigned int stage) { struct alt_entry *alt; void *oldptr, *altptr; + u16 id, value; if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) return; @@ -287,13 +310,19 @@ void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin, for (alt = begin; alt < end; alt++) { if (alt->vendor_id != 0) continue; - if (alt->patch_id >= RISCV_ISA_EXT_MAX) { - WARN(1, "This extension id:%d is not in ISA extension list", - alt->patch_id); + + id = PATCH_ID_CPUFEATURE_ID(alt->patch_id); + + if (id >= RISCV_ISA_EXT_MAX) { + WARN(1, "This extension id:%d is not in ISA extension list", id); continue; } - if (!__riscv_isa_extension_available(NULL, alt->patch_id)) + if (!__riscv_isa_extension_available(NULL, id)) + continue; + + value = PATCH_ID_CPUFEATURE_VALUE(alt->patch_id); + if (!riscv_cpufeature_patch_check(id, value)) continue; oldptr = ALT_OLD_PTR(alt); From patchwork Fri Feb 24 16:26:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 657278 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A968C7EE2D for ; Fri, 24 Feb 2023 16:26:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229535AbjBXQ0u (ORCPT ); Fri, 24 Feb 2023 11:26:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229749AbjBXQ0q (ORCPT ); Fri, 24 Feb 2023 11:26:46 -0500 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A30966EB10 for ; Fri, 24 Feb 2023 08:26:41 -0800 (PST) Received: by mail-wm1-x333.google.com with SMTP id ay29-20020a05600c1e1d00b003e9f4c2b623so2557406wmb.3 for ; Fri, 24 Feb 2023 08:26:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Q2P2JQFCkCvwqQ+izE3XFcbD2hXA/JB7nAY/h1d8raI=; b=RMWMWkVoB3LRLO0tinT5AnaXIJm3ODgGdXH4+VsQohW/FaOKu1obC6iDEG0UjOaG+m sWXmE89bNrwvmFq/g4ekXOiBJRGqEbPms321SWNwDscwmK7fxLPD0u7dGOmafXG+FZ4e WhZMtYzAzobepUS6BB9Px/Xl3UAWX9ZilQejogz2RhCOcC77vHjriOxPVxzksApcAHMR VjHVV425lHIvWxxnrGj8WC39bRBlvCSIisVW7duRdvgtrEWaA6nAD2pu2qpCHs4JUxSY kM0feNjdKxhoBqZLeZhuLbG0tZdHUxaK0m4Wf8LsSmrEBu22y0GLUDZaPXYalxo7KWTq HAwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Q2P2JQFCkCvwqQ+izE3XFcbD2hXA/JB7nAY/h1d8raI=; b=iG8FO+eg4b3YRzLI3R23opwbLdFGM7IRmQViqg2vI9Bnlb+MJmey4rjGhNDnBem07W Wmwe2rdbtVoozOauOOMgH3rTF9/L05e5wEGKOZpFsGwq1+KRYk3hZm0mWG8HVi70MhrZ 4ZMTkzzD8nDlUebt9lkUcMu0mmw3l6LAaYeXSzpg619ap2o1oRaThaEcGz9C0N4au3Kj 3vzCn5GEKWZFV4s4fmm1mJHLAp5sek1i1w5Z87xQrW9PSEMENMiSm8xcIngIkl20tKdi pCb7jnLftuPpEEeI6Bf0h9cDCki5/SDltuz+U1LKrNoWJSqVYxaSzeGPG9WRa6zSRz7H v3Zw== X-Gm-Message-State: AO0yUKVz90v634cWIi49AuEaCKp7fvdefO5uzNw06U/h7EaZWhw8ZlF4 THpxvO0BG8hWew8gG5y0JDtrtg== X-Google-Smtp-Source: AK7set+LVMfzBlUl+ospJ9FT85y8/nybf3TYDjnZSzHtvowRG/uoPyt4FaaFXBM+Cp5KCIiqQ82b6Q== X-Received: by 2002:a05:600c:715:b0:3eb:2b88:a290 with SMTP id i21-20020a05600c071500b003eb2b88a290mr1136814wmn.28.1677256000084; Fri, 24 Feb 2023 08:26:40 -0800 (PST) Received: from localhost (2001-1ae9-1c2-4c00-20f-c6b4-1e57-7965.ip6.tmcz.cz. [2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id ja18-20020a05600c557200b003eb0d6f48f3sm2669244wmb.27.2023.02.24.08.26.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 08:26:39 -0800 (PST) From: Andrew Jones To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, devicetree@vger.kernel.org Cc: 'Conor Dooley ' , 'Paul Walmsley ' , 'Palmer Dabbelt ' , 'Sudip Mukherjee ' , 'Ben Dooks ' , 'Atish Patra ' , 'Albert Ou ' , 'Anup Patel ' , 'Krzysztof Kozlowski ' , 'Rob Herring ' , 'Jisheng Zhang ' , 'Heiko Stuebner ' Subject: [PATCH v6 6/8] RISC-V: Use Zicboz in clear_page when available Date: Fri, 24 Feb 2023 17:26:29 +0100 Message-Id: <20230224162631.405473-7-ajones@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230224162631.405473-1-ajones@ventanamicro.com> References: <20230224162631.405473-1-ajones@ventanamicro.com> MIME-Version: 1.0 Content-type: text/plain Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Using memset() to zero a 4K page takes 563 total instructions, where 20 are branches. clear_page(), with Zicboz and a 64 byte block size, takes 169 total instructions, where 4 are branches and 33 are nops. Even though the block size is a variable, thanks to alternatives, we can still implement a Duff device without having to do any preliminary calculations. This is achieved by using the alternatives' cpufeature value (the upper 16 bits of patch_id). The value used is the maximum zicboz block size order accepted at the patch site. This enables us to stop patching / unrolling when 4K bytes have been zeroed (we would loop and continue after 4K if the page size would be larger) For 4K pages, unrolling 16 times allows block sizes of 64 and 128 to only loop a few times and larger block sizes to not loop at all. Since cbo.zero doesn't take an offset, we also need an 'add' after each instruction, making the loop body 112 to 160 bytes. Hopefully this is small enough to not cause icache misses. Signed-off-by: Andrew Jones Acked-by: Conor Dooley --- arch/riscv/Kconfig | 13 ++++++ arch/riscv/include/asm/insn-def.h | 4 ++ arch/riscv/include/asm/page.h | 6 ++- arch/riscv/kernel/cpufeature.c | 11 +++++ arch/riscv/lib/Makefile | 1 + arch/riscv/lib/clear_page.S | 74 +++++++++++++++++++++++++++++++ 6 files changed, 108 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/lib/clear_page.S diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index aa951fe2bc56..f715aa39c465 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -458,6 +458,19 @@ config RISCV_ISA_ZICBOM If you don't know what to do here, say Y. +config RISCV_ISA_ZICBOZ + bool "Zicboz extension support for faster zeroing of memory" + depends on !XIP_KERNEL && MMU + select RISCV_ALTERNATIVE + default y + help + Enable the use of the ZICBOZ extension (cbo.zero instruction) + when available. + + The Zicboz extension is used for faster zeroing of memory. + + If you don't know what to do here, say Y. + config TOOLCHAIN_HAS_ZIHINTPAUSE bool default y diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/insn-def.h index e01ab51f50d2..6960beb75f32 100644 --- a/arch/riscv/include/asm/insn-def.h +++ b/arch/riscv/include/asm/insn-def.h @@ -192,4 +192,8 @@ INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \ RS1(base), SIMM12(2)) +#define CBO_zero(base) \ + INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \ + RS1(base), SIMM12(4)) + #endif /* __ASM_INSN_DEF_H */ diff --git a/arch/riscv/include/asm/page.h b/arch/riscv/include/asm/page.h index 9f432c1b5289..ccd168fe29d2 100644 --- a/arch/riscv/include/asm/page.h +++ b/arch/riscv/include/asm/page.h @@ -49,10 +49,14 @@ #ifndef __ASSEMBLY__ +#ifdef CONFIG_RISCV_ISA_ZICBOZ +void clear_page(void *page); +#else #define clear_page(pgaddr) memset((pgaddr), 0, PAGE_SIZE) +#endif #define copy_page(to, from) memcpy((to), (from), PAGE_SIZE) -#define clear_user_page(pgaddr, vaddr, page) memset((pgaddr), 0, PAGE_SIZE) +#define clear_user_page(pgaddr, vaddr, page) clear_page(pgaddr) #define copy_user_page(vto, vfrom, vaddr, topg) \ memcpy((vto), (vfrom), PAGE_SIZE) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index d424cd76beb1..8e7b0d703841 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -293,6 +293,17 @@ static bool riscv_cpufeature_patch_check(u16 id, u16 value) if (!value) return true; + switch (id) { + case RISCV_ISA_EXT_ZICBOZ: + /* + * Zicboz alternative applications provide the maximum + * supported block size order, or zero when it doesn't + * matter. If the current block size exceeds the maximum, + * then the alternative cannot be applied. + */ + return riscv_cboz_block_size <= (1U << value); + } + return false; } diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index 6c74b0bedd60..26cb2502ecf8 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -8,5 +8,6 @@ lib-y += strlen.o lib-y += strncmp.o lib-$(CONFIG_MMU) += uaccess.o lib-$(CONFIG_64BIT) += tishift.o +lib-$(CONFIG_RISCV_ISA_ZICBOZ) += clear_page.o obj-$(CONFIG_FUNCTION_ERROR_INJECTION) += error-inject.o diff --git a/arch/riscv/lib/clear_page.S b/arch/riscv/lib/clear_page.S new file mode 100644 index 000000000000..d7a256eb53f4 --- /dev/null +++ b/arch/riscv/lib/clear_page.S @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023 Ventana Micro Systems Inc. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define CBOZ_ALT(order, old, new) \ + ALTERNATIVE(old, new, 0, \ + ((order) << 16) | RISCV_ISA_EXT_ZICBOZ, \ + CONFIG_RISCV_ISA_ZICBOZ) + +/* void clear_page(void *page) */ +SYM_FUNC_START(clear_page) + li a2, PAGE_SIZE + + /* + * If Zicboz isn't present, or somehow has a block + * size larger than 4K, then fallback to memset. + */ + CBOZ_ALT(12, "j .Lno_zicboz", "nop") + + lw a1, riscv_cboz_block_size + add a2, a0, a2 +.Lzero_loop: + CBO_zero(a0) + add a0, a0, a1 + CBOZ_ALT(11, "bltu a0, a2, .Lzero_loop; ret", "nop; nop") + CBO_zero(a0) + add a0, a0, a1 + CBOZ_ALT(10, "bltu a0, a2, .Lzero_loop; ret", "nop; nop") + CBO_zero(a0) + add a0, a0, a1 + CBO_zero(a0) + add a0, a0, a1 + CBOZ_ALT(9, "bltu a0, a2, .Lzero_loop; ret", "nop; nop") + CBO_zero(a0) + add a0, a0, a1 + CBO_zero(a0) + add a0, a0, a1 + CBO_zero(a0) + add a0, a0, a1 + CBO_zero(a0) + add a0, a0, a1 + CBOZ_ALT(8, "bltu a0, a2, .Lzero_loop; ret", "nop; nop") + CBO_zero(a0) + add a0, a0, a1 + CBO_zero(a0) + add a0, a0, a1 + CBO_zero(a0) + add a0, a0, a1 + CBO_zero(a0) + add a0, a0, a1 + CBO_zero(a0) + add a0, a0, a1 + CBO_zero(a0) + add a0, a0, a1 + CBO_zero(a0) + add a0, a0, a1 + CBO_zero(a0) + add a0, a0, a1 + bltu a0, a2, .Lzero_loop + ret +.Lno_zicboz: + li a1, 0 + tail __memset +SYM_FUNC_END(clear_page) +EXPORT_SYMBOL(clear_page) From patchwork Fri Feb 24 16:26:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 656315 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 597C7C7EE2D for ; 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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id y7-20020a1c4b07000000b003daf672a616sm3318597wma.22.2023.02.24.08.26.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 08:26:41 -0800 (PST) From: Andrew Jones To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, devicetree@vger.kernel.org Cc: 'Conor Dooley ' , 'Paul Walmsley ' , 'Palmer Dabbelt ' , 'Sudip Mukherjee ' , 'Ben Dooks ' , 'Atish Patra ' , 'Albert Ou ' , 'Anup Patel ' , 'Krzysztof Kozlowski ' , 'Rob Herring ' , 'Jisheng Zhang ' , 'Heiko Stuebner ' , Anup Patel Subject: [PATCH v6 7/8] RISC-V: KVM: Provide UAPI for Zicboz block size Date: Fri, 24 Feb 2023 17:26:30 +0100 Message-Id: <20230224162631.405473-8-ajones@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230224162631.405473-1-ajones@ventanamicro.com> References: <20230224162631.405473-1-ajones@ventanamicro.com> MIME-Version: 1.0 Content-type: text/plain Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org We're about to allow guests to use the Zicboz extension. KVM userspace needs to know the cache block size in order to properly advertise it to the guest. Provide a virtual config register for userspace to get it with the GET_ONE_REG API, but setting it cannot be supported, so disallow SET_ONE_REG. Signed-off-by: Andrew Jones Reviewed-by: Conor Dooley Reviewed-by: Anup Patel --- arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/vcpu.c | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index 92af6f3f057c..c1a1bb0fa91c 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -52,6 +52,7 @@ struct kvm_riscv_config { unsigned long mvendorid; unsigned long marchid; unsigned long mimpid; + unsigned long zicboz_block_size; }; /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 7c08567097f0..e5126cefbc87 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -276,6 +276,11 @@ static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu, return -EINVAL; reg_val = riscv_cbom_block_size; break; + case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size): + if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOZ)) + return -EINVAL; + reg_val = riscv_cboz_block_size; + break; case KVM_REG_RISCV_CONFIG_REG(mvendorid): reg_val = vcpu->arch.mvendorid; break; @@ -347,6 +352,8 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu, break; case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size): return -EOPNOTSUPP; + case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size): + return -EOPNOTSUPP; case KVM_REG_RISCV_CONFIG_REG(mvendorid): if (!vcpu->arch.ran_atleast_once) vcpu->arch.mvendorid = reg_val; From patchwork Fri Feb 24 16:26:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 657277 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF6DDC7EE23 for ; Fri, 24 Feb 2023 16:27:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229630AbjBXQ07 (ORCPT ); Fri, 24 Feb 2023 11:26:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53850 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229796AbjBXQ0r (ORCPT ); Fri, 24 Feb 2023 11:26:47 -0500 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0CD436A7B1 for ; Fri, 24 Feb 2023 08:26:43 -0800 (PST) Received: by mail-wm1-x32f.google.com with SMTP id az36so40786wmb.1 for ; Fri, 24 Feb 2023 08:26:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LQSbWzdXITTUFGVPTFXHGgENmDgXWQs7cxb8n6vTRIg=; b=WYvJAh+G6x6Vlax3zUgVMCE5aXia8pEEMHFNGJZMetpJPvr3AFrx1UrS6bgxuRlFYl fKHzZw7I1iDnhJfcYXRJMf2tEm+ZJ9hg9Y9xvmFG0rEb3OHivpXDTV/Pv03X1YkRFJQg cbhwwMKK2Os8sLmFRb9cWh9yW0rtwGZ1XOO6VV2JHqQJcZXesoRzsQ/jkNjoZhsX5hFc an+IAXJ+TN2el+6ea9OJWLW1AkRFD/P6PCHlro7SkO1WYB5j4XTQXRdS2f1dodDMbojn oPldkG8xv0UfVfz/WGB0PliCkOlM8q8dpFBruuPPq2KUYDZovFmzoaf1b6hAYSUzqwoz y1tA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LQSbWzdXITTUFGVPTFXHGgENmDgXWQs7cxb8n6vTRIg=; b=1sz6Vkx4CaoblNqJCjAloNEYs8UxkXBzq8rZbhILSaaBJBvPutXbiV5HSXD1CQ4nvy Dwbdthg2lJUTrOYnpVAlq1SOqJE4eVoSThP3Rwky+kfgQcQY+m9gKHCmXcN85Yl14JBQ HA0J1M3NykfOyoVvMh8CjB8n/fB6gQ3XQUSJ/BCk9HUuQAClhc4kAjrmAJ2YI/0zL270 bM3YbfUTulG3BocpPP6VyMkPVhh/hz2TK/jR2Yc8d94Z5pWN+p1Q0IRWdrg5qvTeM46Q b0rQ8FqN4LcgEf66323zj7vPXRfDzP70KDWQwFvqYl6ZGckzpapsW3cn2nKT556hjriT j1PQ== X-Gm-Message-State: AO0yUKW3FjqIIuyJOi39Hg0vY8ZJBzRLSWLy84IjhVd+K2Jb/vxOuErR IjT6mTeUe2mcy/hyeA9P/OU8Lw== X-Google-Smtp-Source: AK7set+B4L+KEhB/KyLIkSH6PHaVRqL2xDGuGkTQosj7QgMJ6o2wSVbxw27nLBgEAAEMmRkOdbvzag== X-Received: by 2002:a05:600c:354c:b0:3df:9858:c03a with SMTP id i12-20020a05600c354c00b003df9858c03amr178485wmq.15.1677256002565; Fri, 24 Feb 2023 08:26:42 -0800 (PST) Received: from localhost (2001-1ae9-1c2-4c00-20f-c6b4-1e57-7965.ip6.tmcz.cz. [2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id j22-20020a5d4536000000b002c5a07e940csm13820864wra.33.2023.02.24.08.26.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 08:26:42 -0800 (PST) From: Andrew Jones To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, devicetree@vger.kernel.org Cc: 'Conor Dooley ' , 'Paul Walmsley ' , 'Palmer Dabbelt ' , 'Sudip Mukherjee ' , 'Ben Dooks ' , 'Atish Patra ' , 'Albert Ou ' , 'Anup Patel ' , 'Krzysztof Kozlowski ' , 'Rob Herring ' , 'Jisheng Zhang ' , 'Heiko Stuebner ' , Anup Patel Subject: [PATCH v6 8/8] RISC-V: KVM: Expose Zicboz to the guest Date: Fri, 24 Feb 2023 17:26:31 +0100 Message-Id: <20230224162631.405473-9-ajones@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230224162631.405473-1-ajones@ventanamicro.com> References: <20230224162631.405473-1-ajones@ventanamicro.com> MIME-Version: 1.0 Content-type: text/plain Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Guests may use the cbo.zero instruction when the CPU has the Zicboz extension and the hypervisor sets henvcfg.CBZE. Add Zicboz support for KVM guests which may be enabled and disabled from KVM userspace using the ISA extension ONE_REG API. Signed-off-by: Andrew Jones Reviewed-by: Conor Dooley Reviewed-by: Anup Patel Acked-by: Anup Patel --- arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/vcpu.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index c1a1bb0fa91c..e44c1e90eaa7 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -106,6 +106,7 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_SVINVAL, KVM_RISCV_ISA_EXT_ZIHINTPAUSE, KVM_RISCV_ISA_EXT_ZICBOM, + KVM_RISCV_ISA_EXT_ZICBOZ, KVM_RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index e5126cefbc87..198ee86cad38 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -63,6 +63,7 @@ static const unsigned long kvm_isa_ext_arr[] = { KVM_ISA_EXT_ARR(SVPBMT), KVM_ISA_EXT_ARR(ZIHINTPAUSE), KVM_ISA_EXT_ARR(ZICBOM), + KVM_ISA_EXT_ARR(ZICBOZ), }; static unsigned long kvm_riscv_vcpu_base2isa_ext(unsigned long base_ext) @@ -865,6 +866,9 @@ static void kvm_riscv_vcpu_update_config(const unsigned long *isa) if (riscv_isa_extension_available(isa, ZICBOM)) henvcfg |= (ENVCFG_CBIE | ENVCFG_CBCFE); + if (riscv_isa_extension_available(isa, ZICBOZ)) + henvcfg |= ENVCFG_CBZE; + csr_write(CSR_HENVCFG, henvcfg); #ifdef CONFIG_32BIT csr_write(CSR_HENVCFGH, henvcfg >> 32);