From patchwork Thu Feb 23 04:21:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 656136 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C08E3C61DA4 for ; Thu, 23 Feb 2023 04:23:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233183AbjBWEXC (ORCPT ); Wed, 22 Feb 2023 23:23:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35158 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232944AbjBWEWc (ORCPT ); Wed, 22 Feb 2023 23:22:32 -0500 Received: from mail-ot1-x32a.google.com (mail-ot1-x32a.google.com [IPv6:2607:f8b0:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1547C4AFD9 for ; Wed, 22 Feb 2023 20:21:23 -0800 (PST) Received: by mail-ot1-x32a.google.com with SMTP id q11-20020a056830440b00b00693c1a62101so1352734otv.0 for ; Wed, 22 Feb 2023 20:21:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=v+KyrF1DXPa/BBYyuptUwg7+QHC/Wtb90A7GWVnf/LQ=; b=F42rBy0uNCTG5FsGgWJ7gvpyDmSYfo3yFM5gZac73TMYx+LrwX1jO7AwW9dyjHka0h rnHYGX9Wz5vnkb7lNdAosUAC4awxAvzZNGPYxxmbUkBwAdaZMya9euLYtRK5z9j8f+47 TITlZAVhSxWZeTGAjCFg4QLmHwOg+gl5HJyOR6cP71MeSXdW5OkaIbQ9cMf/ZG/zrDTc +fP8NP7Qcz5t1OvWj1iB4G1vHMUZijn1ik1LoNN3MsA92wmsTfB7uNoI57WowQUtAw9e 2gUvAok7e8ZywAy2RfIzRREBCY01wJaBM26hgusDPeAy5CcVpckpu/USushlNF0j1M22 wD0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=v+KyrF1DXPa/BBYyuptUwg7+QHC/Wtb90A7GWVnf/LQ=; b=QANMqQv0dQU2/CNo3AUxxqunoYcuoIiJb7XkZGJl1c0oeZXmGNL38L6iHc0UYBWN7T Hhvx1dKpvuqujBytxUgVryF/TQ+qSREe93HBPdHSK6nQ2RlC62g4XSkBA/+tDdAHmbet 5Ah7O51YJkpcadx3wx7sIq+xCy2J0GbunOPNu8hbcrXtXiFdWFIGPQH9TzTHvTBHMMMF /QnZQowgFbJ2TqPPCn6t4TURjKLhKQE3aW59iCZUuFuQzPMXIP0EZxUxM4ZzSwWD4c7n 52+peNoLIwOHpQi+B9GiwFG8w7srAx5uhplmTtYZ+xiwV9zcsP9EvjyYMfd3TlRZgXnn WYlw== X-Gm-Message-State: AO0yUKVagX1bvX80ifwO47yRgvzrEEoCLtK6E+u71d18qmhpP2Mtbzqo 4c6mRCdHJOM/qsnCDYDg/TAitw== X-Google-Smtp-Source: AK7set+jvVKbzwVqAV0SPhuE7cVbyzq+q+DqSnejyIwB+JA1S1TT05zoCY2O7j66FLwanJ04I8nKMQ== X-Received: by 2002:a9d:1788:0:b0:690:ece7:62d2 with SMTP id j8-20020a9d1788000000b00690ece762d2mr2237610otj.19.1677126079713; Wed, 22 Feb 2023 20:21:19 -0800 (PST) Received: from localhost ([136.49.140.41]) by smtp.gmail.com with ESMTPSA id l3-20020a9d5503000000b00693c66c0692sm1708793oth.29.2023.02.22.20.21.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 20:21:19 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Chanwoo Choi , Sylwester Nawrocki , Rob Herring Cc: David Virag , Chanho Park , Alim Akhtar , Sumit Semwal , Tomasz Figa , Michael Turquette , Stephen Boyd , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/6] dt-bindings: clock: exynos850: Add Exynos850 CMU_G3D Date: Wed, 22 Feb 2023 22:21:28 -0600 Message-Id: <20230223042133.26551-2-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230223042133.26551-1-semen.protsenko@linaro.org> References: <20230223042133.26551-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org CMU_G3D generates Gondul GPU and bus clocks for BLK_G3D. Add clock indices and binding documentation for CMU_G3D. Acked-by: Rob Herring Signed-off-by: Sam Protsenko --- Changes in v2: - Rebased on top of most recent soc/for-next tree - Added Rob Herring Acked-by tag .../clock/samsung,exynos850-clock.yaml | 19 ++++++++++++++++++ include/dt-bindings/clock/exynos850.h | 20 ++++++++++++++++++- 2 files changed, 38 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml index 141cf173f87d..8aa87b8c1b33 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml @@ -37,6 +37,7 @@ properties: - samsung,exynos850-cmu-cmgp - samsung,exynos850-cmu-core - samsung,exynos850-cmu-dpu + - samsung,exynos850-cmu-g3d - samsung,exynos850-cmu-hsi - samsung,exynos850-cmu-is - samsung,exynos850-cmu-mfcmscl @@ -169,6 +170,24 @@ allOf: - const: oscclk - const: dout_dpu + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-g3d + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: G3D clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_g3d_switch + - if: properties: compatible: diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h index 88d5289883d3..8bb62e43fd60 100644 --- a/include/dt-bindings/clock/exynos850.h +++ b/include/dt-bindings/clock/exynos850.h @@ -85,7 +85,10 @@ #define CLK_DOUT_MFCMSCL_M2M 73 #define CLK_DOUT_MFCMSCL_MCSC 74 #define CLK_DOUT_MFCMSCL_JPEG 75 -#define TOP_NR_CLK 76 +#define CLK_MOUT_G3D_SWITCH 76 +#define CLK_GOUT_G3D_SWITCH 77 +#define CLK_DOUT_G3D_SWITCH 78 +#define TOP_NR_CLK 79 /* CMU_APM */ #define CLK_RCO_I3C_PMIC 1 @@ -195,6 +198,21 @@ #define CLK_GOUT_SYSREG_CMGP_PCLK 15 #define CMGP_NR_CLK 16 +/* CMU_G3D */ +#define CLK_FOUT_G3D_PLL 1 +#define CLK_MOUT_G3D_PLL 2 +#define CLK_MOUT_G3D_SWITCH_USER 3 +#define CLK_MOUT_G3D_BUSD 4 +#define CLK_DOUT_G3D_BUSP 5 +#define CLK_GOUT_G3D_CMU_G3D_PCLK 6 +#define CLK_GOUT_G3D_GPU_CLK 7 +#define CLK_GOUT_G3D_TZPC_PCLK 8 +#define CLK_GOUT_G3D_GRAY2BIN_CLK 9 +#define CLK_GOUT_G3D_BUSD_CLK 10 +#define CLK_GOUT_G3D_BUSP_CLK 11 +#define CLK_GOUT_G3D_SYSREG_PCLK 12 +#define G3D_NR_CLK 13 + /* CMU_HSI */ #define CLK_MOUT_HSI_BUS_USER 1 #define CLK_MOUT_HSI_MMC_CARD_USER 2 From patchwork Thu Feb 23 04:21:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 656135 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D49E9C678DB for ; Thu, 23 Feb 2023 04:23:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233319AbjBWEXF (ORCPT ); Wed, 22 Feb 2023 23:23:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35164 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233222AbjBWEWg (ORCPT ); Wed, 22 Feb 2023 23:22:36 -0500 Received: from mail-ot1-x334.google.com (mail-ot1-x334.google.com [IPv6:2607:f8b0:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D21A448E03 for ; Wed, 22 Feb 2023 20:21:27 -0800 (PST) Received: by mail-ot1-x334.google.com with SMTP id t7-20020a9d5907000000b00690ecb95d46so2113975oth.2 for ; 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Wed, 22 Feb 2023 20:21:22 -0800 (PST) Received: from localhost ([136.49.140.41]) by smtp.gmail.com with ESMTPSA id y7-20020a9d5187000000b0068bb7bd2668sm2225332otg.73.2023.02.22.20.21.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 20:21:21 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Chanwoo Choi , Sylwester Nawrocki , Rob Herring Cc: David Virag , Chanho Park , Alim Akhtar , Sumit Semwal , Tomasz Figa , Michael Turquette , Stephen Boyd , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/6] clk: samsung: clk-pll: Implement pll0818x PLL type Date: Wed, 22 Feb 2023 22:21:30 -0600 Message-Id: <20230223042133.26551-4-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230223042133.26551-1-semen.protsenko@linaro.org> References: <20230223042133.26551-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org pll0818x PLL is used in Exynos850 SoC for CMU_G3D PLL. Operation-wise, pll0818x is the same as pll0822x. The only difference is: - pl0822x is integer PLL with Middle FVCO (950 to 2400 MHz) - pl0818x is integer PLL with Low FVCO (600 to 1200 MHz) Add pll0818x type as an alias to pll0822x. Reviewed-by: Chanho Park Signed-off-by: Sam Protsenko --- Changes in v2: - Rebased on top of most recent soc/for-next tree - Added Chanho Park Reviewed-by tag drivers/clk/samsung/clk-pll.c | 1 + drivers/clk/samsung/clk-pll.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 5ceac4c25c1c..74934c6182ce 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -1314,6 +1314,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, init.ops = &samsung_pll35xx_clk_ops; break; case pll_1417x: + case pll_0818x: case pll_0822x: pll->enable_offs = PLL0822X_ENABLE_SHIFT; pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT; diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index 5d5a58d40e7e..0725d485c6ee 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -34,6 +34,7 @@ enum samsung_pll_type { pll_1451x, pll_1452x, pll_1460x, + pll_0818x, pll_0822x, pll_0831x, pll_142xx, From patchwork Thu Feb 23 04:21:32 2023 Content-Type: text/plain; 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Wed, 22 Feb 2023 20:21:24 -0800 (PST) Received: from localhost ([136.49.140.41]) by smtp.gmail.com with ESMTPSA id q127-20020acac085000000b0037d813cd612sm1988674oif.43.2023.02.22.20.21.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 20:21:23 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Chanwoo Choi , Sylwester Nawrocki , Rob Herring Cc: David Virag , Chanho Park , Alim Akhtar , Sumit Semwal , Tomasz Figa , Michael Turquette , Stephen Boyd , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/6] clk: samsung: exynos850: Add AUD and HSI main gate clocks Date: Wed, 22 Feb 2023 22:21:32 -0600 Message-Id: <20230223042133.26551-6-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230223042133.26551-1-semen.protsenko@linaro.org> References: <20230223042133.26551-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add main gate clocks for controlling AUD and HSI CMUs: - gout_aud_cmu_aud_pclk - gout_hsi_cmu_hsi_pclk Those clocks were marked as CLK_IGNORE_UNUSED, as system hangs on boot otherwise. While at it, add missing PPMU (Performance Profiling Monitor Unit) clocks for CMU_HSI. Signed-off-by: Sam Protsenko Reviewed-by: Chanho Park --- Changes in v2: - Rebased on top of most recent soc/for-next tree - Added comment for CLK_IGNORE_UNUSED flag usage drivers/clk/samsung/clk-exynos850.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-exynos850.c index 601fe05e8555..6ab5fa8c2ef3 100644 --- a/drivers/clk/samsung/clk-exynos850.c +++ b/drivers/clk/samsung/clk-exynos850.c @@ -674,6 +674,7 @@ static const struct samsung_cmu_info apm_cmu_info __initconst = { #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4 0x2014 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5 0x2018 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6 0x201c +#define CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK 0x2020 #define CLK_CON_GAT_GOUT_AUD_ABOX_ACLK 0x2048 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY 0x204c #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB 0x2050 @@ -729,6 +730,7 @@ static const unsigned long aud_clk_regs[] __initconst = { CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4, CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5, CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6, + CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK, CLK_CON_GAT_GOUT_AUD_ABOX_ACLK, CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY, CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB, @@ -848,6 +850,9 @@ static const struct samsung_div_clock aud_div_clks[] __initconst = { }; static const struct samsung_gate_clock aud_gate_clks[] __initconst = { + GATE(CLK_GOUT_AUD_CMU_AUD_PCLK, "gout_aud_cmu_aud_pclk", + "dout_aud_busd", + CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK, 21, CLK_IGNORE_UNUSED, 0), GATE(CLK_GOUT_AUD_CA32_CCLK, "gout_aud_ca32_cclk", "mout_aud_cpu_hch", CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32, 21, 0, 0), GATE(CLK_GOUT_AUD_ASB_CCLK, "gout_aud_asb_cclk", "dout_aud_cpu_aclk", @@ -1116,12 +1121,15 @@ static const struct samsung_cmu_info g3d_cmu_info __initconst = { #define PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER 0x0610 #define PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER 0x0620 #define CLK_CON_MUX_MUX_CLK_HSI_RTC 0x1000 +#define CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK 0x2000 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV 0x2008 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50 0x200c #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26 0x2010 #define CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK 0x2018 #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK 0x2024 #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN 0x2028 +#define CLK_CON_GAT_GOUT_HSI_PPMU_ACLK 0x202c +#define CLK_CON_GAT_GOUT_HSI_PPMU_PCLK 0x2030 #define CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK 0x2038 #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20 0x203c #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY 0x2040 @@ -1131,12 +1139,15 @@ static const unsigned long hsi_clk_regs[] __initconst = { PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER, PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER, CLK_CON_MUX_MUX_CLK_HSI_RTC, + CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK, CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, + CLK_CON_GAT_GOUT_HSI_PPMU_ACLK, + CLK_CON_GAT_GOUT_HSI_PPMU_PCLK, CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, @@ -1162,6 +1173,10 @@ static const struct samsung_mux_clock hsi_mux_clks[] __initconst = { }; static const struct samsung_gate_clock hsi_gate_clks[] __initconst = { + /* TODO: Should be enabled in corresponding driver */ + GATE(CLK_GOUT_HSI_CMU_HSI_PCLK, "gout_hsi_cmu_hsi_pclk", + "mout_hsi_bus_user", + CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0), GATE(CLK_GOUT_USB_RTC_CLK, "gout_usb_rtc", "mout_hsi_rtc", CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 21, 0, 0), GATE(CLK_GOUT_USB_REF_CLK, "gout_usb_ref", "mout_hsi_usb20drd_user", @@ -1176,6 +1191,10 @@ static const struct samsung_gate_clock hsi_gate_clks[] __initconst = { GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin", "mout_hsi_mmc_card_user", CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 21, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_HSI_PPMU_ACLK, "gout_hsi_ppmu_aclk", "mout_hsi_bus_user", + CLK_CON_GAT_GOUT_HSI_PPMU_ACLK, 21, 0, 0), + GATE(CLK_GOUT_HSI_PPMU_PCLK, "gout_hsi_ppmu_pclk", "mout_hsi_bus_user", + CLK_CON_GAT_GOUT_HSI_PPMU_PCLK, 21, 0, 0), GATE(CLK_GOUT_SYSREG_HSI_PCLK, "gout_sysreg_hsi_pclk", "mout_hsi_bus_user", CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 21, 0, 0),