From patchwork Thu Feb 23 12:06:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 656057 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6491C61DA4 for ; Thu, 23 Feb 2023 12:06:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233437AbjBWMGw (ORCPT ); Thu, 23 Feb 2023 07:06:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32958 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233348AbjBWMGv (ORCPT ); Thu, 23 Feb 2023 07:06:51 -0500 Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [IPv6:2a00:1450:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24A3B54543 for ; Thu, 23 Feb 2023 04:06:49 -0800 (PST) Received: by mail-lj1-x22d.google.com with SMTP id f16so10556233ljq.10 for ; Thu, 23 Feb 2023 04:06:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=7GfFVek+ElBU/x4Gj7bclUI24uP1/zbAkUCH7g+3I3E=; b=SFzlXW25c2p4gmoVDowFXTsP5M8MKa9SLmR9b6XVCY+h18lAKnP8yoYhiEZ0+jdxXo RO+5/lzqt4SUkwxXvwRV3Yx4FoS48uKXXeqKv4cuVg5pO91p8hHIN+jLA9wlnWMHsgXC R/Gm0Ev8ftdKzILltKVZlw3gvE4RTsmDwRlhvwSzjRUXj/Ydih6ZG4fQpToXwpnSwnd6 k9nxQHFzkYI6FcohI0E5yzAXuKWRK2KerIvUDB3jW44Rtm87LO4hNhSLmxl/m7wLsxa+ lmpjA2lfRabtij/IW2dEzn0J9K2WsQSvlXsCNAhSiW83Wn3o8xK8aM6NDu9ajLNZWgVP kwJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7GfFVek+ElBU/x4Gj7bclUI24uP1/zbAkUCH7g+3I3E=; b=VIMCgqTSVbxqnY6T8Bvw8IEma0nfFzHhUv8A3lh8w05UwCdRc5NZ8/nzlZUYAWXXel IpwbSEwXF+BBb7Cupi4hrvrnIqZl/NvochodpYBK02tIS7Kiz2rH27JYH8FE007G+qNm eHoJIYzWTF5Q+Q1JJgpqD4R7V6NHEXIb/w6hGOlb7GO6/1AvSAV8LhUIqfdpVqLFaQux Sjy7mvSPamsqupnuArBlkheFddxFbI/eYXNkGSrTrohRzip8Hnm31tRSj3QPXIo9YxDE BmCazOTPL5cioDhV//f1z0no64uXr3m3DiNF6rR0YBniY/nXwVgh/T54exRi2IMgk+4d z23w== X-Gm-Message-State: AO0yUKWCDakhRoFc6IUO18TBpJj3h1JUi9LneQ3LNCjJnNe4zT1VxZ5S 34xRS0t0oGudhwb5iZUDOLXChw== X-Google-Smtp-Source: AK7set/R8hp0OHle8W9yidCEv0lkrsZraNX5wicXprVVmMdsiLMN7wglCaVXpAb3H22Bb1WLOAP1KA== X-Received: by 2002:a2e:a408:0:b0:293:4e57:2bd4 with SMTP id p8-20020a2ea408000000b002934e572bd4mr4273974ljn.8.1677154007553; Thu, 23 Feb 2023 04:06:47 -0800 (PST) Received: from [192.168.1.101] (abxi151.neoplus.adsl.tpnet.pl. [83.9.2.151]) by smtp.gmail.com with ESMTPSA id h23-20020a2ea497000000b0029599744c02sm414838lji.75.2023.02.23.04.06.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Feb 2023 04:06:47 -0800 (PST) From: Konrad Dybcio Date: Thu, 23 Feb 2023 13:06:36 +0100 Subject: [PATCH v3 02/15] dt-bindings: display/msm/gmu: Add GMU wrapper MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v3-2-5be55a336819@linaro.org> References: <20230223-topic-gmuwrapper-v3-0-5be55a336819@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v3-0-5be55a336819@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1677154003; l=2667; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=jy8JJ/4jpW1OOt7PFexguPcdOFWIzV/3CRPopFhMDDQ=; b=dRvrwjzYmrX1k0lskf2jeL30yaDbqDq+7qdA9yECMw94dbVSOYzqxXXt3wtV3xaxyycXAe7tcqkV pt9s2rj4A+e0HjnTBfiV51jBmIDjMDD6C9/u0io1VJ3L6Qlr3dC1 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org GMU wrapper is essentially a register space within the GPU, which Linux sees as a dumbed-down regular GMU: there's no clocks, interrupts, multiple regs, iommus and OPP. Document it. Signed-off-by: Konrad Dybcio --- .../devicetree/bindings/display/msm/gmu.yaml | 49 ++++++++++++++++------ 1 file changed, 37 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml index ab14e81cb050..021373e686e1 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml @@ -19,16 +19,18 @@ description: | properties: compatible: - items: - - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$' - - const: qcom,adreno-gmu + oneOf: + - items: + - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$' + - const: qcom,adreno-gmu + - const: qcom,adreno-gmu-wrapper reg: - minItems: 3 + minItems: 1 maxItems: 4 reg-names: - minItems: 3 + minItems: 1 maxItems: 4 clocks: @@ -44,7 +46,6 @@ properties: - description: GMU HFI interrupt - description: GMU interrupt - interrupt-names: items: - const: hfi @@ -72,14 +73,8 @@ required: - compatible - reg - reg-names - - clocks - - clock-names - - interrupts - - interrupt-names - power-domains - power-domain-names - - iommus - - operating-points-v2 additionalProperties: false @@ -216,6 +211,27 @@ allOf: - const: cxo - const: axi - const: memnoc + - if: + properties: + compatible: + contains: + const: qcom,adreno-gmu-wrapper + then: + properties: + reg: + items: + - description: GMU wrapper register space + reg-names: + items: + - const: gmu + else: + required: + - clocks + - clock-names + - interrupts + - interrupt-names + - iommus + - operating-points-v2 examples: - | @@ -249,3 +265,12 @@ examples: iommus = <&adreno_smmu 5>; operating-points-v2 = <&gmu_opp_table>; }; + + gmu_wrapper: gmu@596a000 { + compatible = "qcom,adreno-gmu-wrapper"; + reg = <0x0596a000 0x30000>; + reg-names = "gmu"; + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", "gx"; + }; From patchwork Thu Feb 23 12:06:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 656056 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C1DAC64ED6 for ; Thu, 23 Feb 2023 12:07:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234034AbjBWMHF (ORCPT ); Thu, 23 Feb 2023 07:07:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33136 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233844AbjBWMGz (ORCPT ); Thu, 23 Feb 2023 07:06:55 -0500 Received: from mail-lj1-x22b.google.com (mail-lj1-x22b.google.com [IPv6:2a00:1450:4864:20::22b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 973FC55C00 for ; Thu, 23 Feb 2023 04:06:52 -0800 (PST) Received: by mail-lj1-x22b.google.com with SMTP id z5so10623659ljc.8 for ; Thu, 23 Feb 2023 04:06:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=yok0nZYCkQzxSnQH2ARjVTx35nRR0F5PEOqTZ3qXsIg=; b=fjK9mQMHjiJBcH8lJSmhfwJ1guQBiffFrAHUEesmbGMfPi/qxDnZpY3mWklZQR2i5E 9ZmXJQTOXcr7O0tCcKP+Erhi3ddwYBq213n6EZGB9LST6IfqqthXYvFXKB9iyrBGpc3w RTZJX8bVzX7Og3UDQme1cZPCp7Gg2KEKLewRMAu2I63yiU0zycPPZEkXo6NpB0UApNDr SojQ830IEskj/eMyJ3+3uYh6Apx97KNjqpHUp9YZx33s8MUEoArR7hOh+yb2q3nvHQIS IRo7XbwDrgSIVRLBrH91OEJm3E/WeMws0yKA0yXdjwOAKj6X4qwtiOalRU3SymRuNIzb OOMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yok0nZYCkQzxSnQH2ARjVTx35nRR0F5PEOqTZ3qXsIg=; b=kCNVR98S2vrtZCrnKp5rpfrTPFlyxBSuA/G93h/mPWsbAppU/3jitvsPhL16bUmXuQ K4L+AK8qtyZyt4tXIMvY6ByEaONQ90/ZYY5jVcsEgAQmclkb4jMR6p740wOEspkI1qHF Lrqcyrr8ooy313q7qCD9vBG2LYQotWtv/RtYEQaC2i6gsJQpmraELgbz3ek4zCXN962W gHVxK6TJh6P5SQPpzEiE+VYSOk3W5wXkb1+zmpG5oDJBii6uZXNT/lbT+nXB81N66cKU 7IWYSF8Bzn9inaIJxMKCtFuuf6eB2sxgaz7HUzDLZUIS+5AvdP31DM9rMAZ80niTrvku LGhg== X-Gm-Message-State: AO0yUKVCQ9ayx25K9xhJnTMig1XTLlmDv0OSB79E0jYJqFf7NO+JdzIs ZcwGkjDN6V57SSqbYFdRwGBVJw== X-Google-Smtp-Source: AK7set9+muLeS8omBNFXVt2ooyArZ9d0ehG53aDdyK1AO7H7lGgWfu/kVblTx/Iozx6yBlLtZMmIpQ== X-Received: by 2002:a2e:9c83:0:b0:294:6b6b:a107 with SMTP id x3-20020a2e9c83000000b002946b6ba107mr4037985lji.11.1677154010724; Thu, 23 Feb 2023 04:06:50 -0800 (PST) Received: from [192.168.1.101] (abxi151.neoplus.adsl.tpnet.pl. [83.9.2.151]) by smtp.gmail.com with ESMTPSA id h23-20020a2ea497000000b0029599744c02sm414838lji.75.2023.02.23.04.06.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Feb 2023 04:06:50 -0800 (PST) From: Konrad Dybcio Date: Thu, 23 Feb 2023 13:06:38 +0100 Subject: [PATCH v3 04/15] drm/msm/a6xx: Extend and explain UBWC config MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v3-4-5be55a336819@linaro.org> References: <20230223-topic-gmuwrapper-v3-0-5be55a336819@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v3-0-5be55a336819@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1677154003; l=3668; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=ZV6EzEXHb+xbzACmaZ/VhfWA/cvjDBSL9a0mYvB+qs0=; b=U8fHI/+kFCvPN7Wm7L36lKFckvIw+eIRkpTnbaEaoxftwLkSrzu/4cRmFI28a+6RxntgwF57AOFJ 1wiSJ9CMC3+J6psEFNrwSJbYv2TK08N8snTCel/+DC1oT+KlmbL+ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Rename lower_bit to hbb_lo and explain what it signifies. Add explanations (wherever possible to other tunables). Sort the variable definition and assignment alphabetically. Port setting min_access_length, ubwc_mode and hbb_hi from downstream. Set default values for all of the tunables to zero, as they should be. Values were validated against downstream and will be fixed up in separate commits so as not to make this one even more messy. A618 remains untouched (left at hw defaults) in this patch. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 55 ++++++++++++++++++++++++++++------- 1 file changed, 45 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index c5f5d0bb3fdc..bdae341e0a7c 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -786,39 +786,74 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) static void a6xx_set_ubwc_config(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); - u32 lower_bit = 2; + /* Unknown, introduced with A640/680 */ u32 amsbc = 0; + /* + * The Highest Bank Bit value represents the bit of the highest DDR bank. + * We then subtract 13 from it (13 is the minimum value allowed by hw) and + * write the lowest two bits of the remaining value as hbb_lo and the + * one above it as hbb_hi to the hardware. The default values (when HBB is + * not specified) are 0, 0. + */ + u32 hbb_hi = 0; + u32 hbb_lo = 0; + /* Whether the minimum access length is 64 bits */ + u32 min_acc_len = 0; + /* Unknown, introduced with A650 family, related to UBWC mode/ver 4 */ u32 rgb565_predicator = 0; + /* Unknown, introduced with A650 family */ u32 uavflagprd_inv = 0; + /* Entirely magic, per-GPU-gen value */ + u32 ubwc_mode = 0; /* a618 is using the hw default values */ if (adreno_is_a618(adreno_gpu)) return; - if (adreno_is_a640_family(adreno_gpu)) + if (adreno_is_a619(adreno_gpu)) { + /* HBB = 14 */ + hbb_lo = 1; + } + + if (adreno_is_a630(adreno_gpu)) { + /* HBB = 15 */ + hbb_lo = 2; + } + + if (adreno_is_a640_family(adreno_gpu)) { amsbc = 1; + /* HBB = 15 */ + hbb_lo = 2; + } if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) { - /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ - lower_bit = 3; amsbc = 1; + /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ + /* HBB = 16 */ + hbb_lo = 3; rgb565_predicator = 1; uavflagprd_inv = 2; } if (adreno_is_7c3(adreno_gpu)) { - lower_bit = 1; amsbc = 1; + /* HBB is unset in downstream DTS, defaulting to 0 */ rgb565_predicator = 1; uavflagprd_inv = 2; } gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, - rgb565_predicator << 11 | amsbc << 4 | lower_bit << 1); - gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, lower_bit << 1); - gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, - uavflagprd_inv << 4 | lower_bit << 1); - gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, lower_bit << 21); + rgb565_predicator << 11 | hbb_hi << 10 | amsbc << 4 | + min_acc_len << 3 | hbb_lo << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, hbb_hi << 4 | + min_acc_len << 3 | hbb_lo << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, hbb_hi << 10 | + uavflagprd_inv << 4 | min_acc_len << 3 | + hbb_lo << 1 | ubwc_mode); + + gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, min_acc_len << 23 | hbb_lo << 21); } static int a6xx_cp_init(struct msm_gpu *gpu) From patchwork Thu Feb 23 12:06:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 656055 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA531C6FA99 for ; Thu, 23 Feb 2023 12:07:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233937AbjBWMHJ (ORCPT ); Thu, 23 Feb 2023 07:07:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33632 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233803AbjBWMHF (ORCPT ); Thu, 23 Feb 2023 07:07:05 -0500 Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 032CE54A0D for ; Thu, 23 Feb 2023 04:06:55 -0800 (PST) Received: by mail-lj1-x236.google.com with SMTP id z5so10623803ljc.8 for ; Thu, 23 Feb 2023 04:06:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=C2DkiOzFvqlB7+TWcEMrrrEcX0lZ3dVU5NgfPePd3XY=; b=efFeIEoRxtiwlRt4E84hxWjWFgZ8KMsAJkCidihuG+M3eZe7QV62rT5onTi9rAglPM HSxhPLUpgWlsnU/R2rCa452wWwxrWYayL092HzdLdt3653XgJo2wweouLP2L7HAuVUcT Cww+HYGkwT/z6qg/+52NeomA9jThkbIxBtzKJJccWGCq0FREgvqohMzFH3wJE+pbsAo/ jzElWjR6zZ4y8yXBiTvCYJsbMDgPRI+3zHwhVEDpSnQ8tACNh/PuBblokUvHytT2pkEc t/hV7lheaBUeGCWz8KRnXT6TnMCB9EKl4y3PI1PCbmXAkjpA/97OK9ulpOByP3wxyCVb eirg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=C2DkiOzFvqlB7+TWcEMrrrEcX0lZ3dVU5NgfPePd3XY=; b=n/pxC7mePfK8RJxVl5BsR3FP0OYX+GIYL2XVQrqP1qMswukbU8sq7Nfo8HSv6GbE9N Djf02C0htXB/jmdZDPkLDudBls73fSXv+EwJxmPQC6UkEu/EgVC4nJqj1QmQsrhvS0g/ HQ8JnFVGDJzrBV2AQXtDs21F70cUvdVxDxokM5Ut76gLqM5s6lVaF7B/KCUmIeXag86u 7FCQqHUni2hq/3fCLNeu2X/0u+mMARTsTtHlhNqf3LYfKz8XhFwwVQXtyxpotGip5Wak qJxaygmyWCRsMitsyJRgrQX0+yvNN+IYGCxEhaFbgIDRyPCOUhUST8NnJE4ws7anOR8e XcOw== X-Gm-Message-State: AO0yUKUXyE6MFeltkj09XO90d0jlQQneFbEp7ZfwCQ48DHUhWtZeilTK 3mTOUNpr61ndI0I0T9iNQSokCA== X-Google-Smtp-Source: AK7set8+aozCdUsK9/A1dkHtq39HEuFqMzrwj0hVRPwFQ8fRu8JTjjYapM8hXr5CoBmrSc5n2EkIvw== X-Received: by 2002:a2e:a0d7:0:b0:290:6af2:2aac with SMTP id f23-20020a2ea0d7000000b002906af22aacmr3936791ljm.28.1677154014119; Thu, 23 Feb 2023 04:06:54 -0800 (PST) Received: from [192.168.1.101] (abxi151.neoplus.adsl.tpnet.pl. [83.9.2.151]) by smtp.gmail.com with ESMTPSA id h23-20020a2ea497000000b0029599744c02sm414838lji.75.2023.02.23.04.06.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Feb 2023 04:06:53 -0800 (PST) From: Konrad Dybcio Date: Thu, 23 Feb 2023 13:06:40 +0100 Subject: [PATCH v3 06/15] drm/msm/a6xx: Remove both GBIF and RBBM GBIF halt on hw init MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v3-6-5be55a336819@linaro.org> References: <20230223-topic-gmuwrapper-v3-0-5be55a336819@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v3-0-5be55a336819@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1677154003; l=1251; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=rP7wPgzCBRL4O8RjqZW82yCjEqeUwKMvFLJUSz0sk4w=; b=t1dDTvbESCNHgHAYmBv6IMnTLBnwneLOTRz1mF8VO3Y2mx1isDo8k3MOwjLqk/aVELjI0UZ5VVbf aPLaEhokA/k0s+GpA7f0O2MxMoiZNsGLLyrtJRa30jB5kDjx7zqA X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Currently we're only deasserting REG_A6XX_RBBM_GBIF_HALT, but we also need REG_A6XX_GBIF_HALT to be set to 0. For GMU-equipped GPUs this is done in a6xx_bus_clear_pending_transactions(), but for the GMU-less ones we have to do it *somewhere*. Unhalting both side by side sounds like a good plan and it won't cause any issues if it's unnecessary. Also, add a memory barrier to ensure it's gone through. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index d8e7ef181e39..a8b727b82389 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1029,8 +1029,12 @@ static int hw_init(struct msm_gpu *gpu) } /* Clear GBIF halt in case GX domain was not collapsed */ - if (a6xx_has_gbif(adreno_gpu)) + if (a6xx_has_gbif(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0); + /* Let's make extra sure that the GPU can access the memory.. */ + mb(); + } gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); From patchwork Thu Feb 23 12:06:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 656054 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0DEEC636D6 for ; Thu, 23 Feb 2023 12:07:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234199AbjBWMHZ (ORCPT ); Thu, 23 Feb 2023 07:07:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33612 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233976AbjBWMHI (ORCPT ); Thu, 23 Feb 2023 07:07:08 -0500 Received: from mail-lj1-x22f.google.com (mail-lj1-x22f.google.com [IPv6:2a00:1450:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4A2A55A3BF for ; Thu, 23 Feb 2023 04:06:59 -0800 (PST) Received: by mail-lj1-x22f.google.com with SMTP id y14so3479859ljq.4 for ; Thu, 23 Feb 2023 04:06:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=GvZeNfvOUQPeEpcnjioWicSAL+EBvhIjqvMtIvnQJHs=; b=HRlRXdk3Yp7kwuY7pL/ClDeQPi6NaS5W3hvbT9fCYlJflgElIzjUt5L9mtYZxlRDD+ rh8PrhaNyIrFPZc9trAKj+wOQnmvNF10u0ihUtZubVZqwo8rkhMG8CxwednRgv6pPnV7 HZdmAv+teAsYfpfC4KGMHuRYZdh0lclLnG+gnN8R4uLsbTBLYkgkl6jJ/D8AUe3ONk4t A61T1otlg6w6I3uKNqO2O5J+MYii92xb8MCov3rGzcYYBZdaMjQgO0bfR6h2E2bWVxDG aYOwDIRAXX9MDO3WH/jd6s4z5VHnW02apYrYeaTJkZBdcSfiTA2/9J/MogVOznv9MIjw xdQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GvZeNfvOUQPeEpcnjioWicSAL+EBvhIjqvMtIvnQJHs=; b=tkANJR0ljlvqj0Sichh1oHU878PBBKBVyCav3jj4esxgavWnyRzgu0lapzSA3B9YR9 AA48YtAf+RYZ41COdvuJm3Tg9EzhYDSVArmgi4kglKRBTldebLQen1/HSv9McTtLONmZ oyux4OP2V9YPZF0Gdx3zeKUElNOxxmlFT7Cq+vZPaBoMh2YfyMX4F8c/g92h4IiDor9h FiDCogTZNqNqXE5MsVu1xmX+h92OCU+cYg9SxSpQGpwtrxTbMFGsUIKHvF5kyi+Vh5TS FxhHWTyny2F4x8ZBSgpYytnbjQrI6Mj1FSxljOWborPA/anZhTuAyPXSPwZRaW1b9DZ4 vmZA== X-Gm-Message-State: AO0yUKV9ouL4VOSV1A15Qy9gQwAwgFjBrULlLUBcdwM3DWbRUaU2WO6E jzo0vSzld7CzB90PeAMLz57GiA== X-Google-Smtp-Source: AK7set/epSP42VlsXxdl0YHnW7iwHGfA/kT2M58WOzRCP3V1MVLgkBilh5e3X92n2SlsnO/mdHihhQ== X-Received: by 2002:a05:651c:210:b0:290:7169:5bd7 with SMTP id y16-20020a05651c021000b0029071695bd7mr4726635ljn.44.1677154018795; Thu, 23 Feb 2023 04:06:58 -0800 (PST) Received: from [192.168.1.101] (abxi151.neoplus.adsl.tpnet.pl. [83.9.2.151]) by smtp.gmail.com with ESMTPSA id h23-20020a2ea497000000b0029599744c02sm414838lji.75.2023.02.23.04.06.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Feb 2023 04:06:58 -0800 (PST) From: Konrad Dybcio Date: Thu, 23 Feb 2023 13:06:43 +0100 Subject: [PATCH v3 09/15] drm/msm/a6xx: Add A610 support MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v3-9-5be55a336819@linaro.org> References: <20230223-topic-gmuwrapper-v3-0-5be55a336819@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v3-0-5be55a336819@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1677154003; l=10114; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=l3UPsuv3BNpqle5KdNAQT/5ssfPQPt3sGkrNv1s+XL8=; b=1dlz9sQsQMuuUDGCCYbDGovyKgZ2Wn8aBfUdE76JXgC6UqjENaNSci+od2271sCaY5/zP3b1TzE/ pN7hgoKAD1+eFwCSXOsABvLTDjn5egE/xhI4tIdEzWjNSTLk6hrO X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org A610 is one of (if not the) lowest-tier SKUs in the A6XX family. It features no GMU, as it's implemented solely on SoCs with SMD_RPM. What's more interesting is that it does not feature a VDDGX line either, being powered solely by VDDCX and has an unfortunate hardware quirk that makes its reset line broken - after a couple of assert/ deassert cycles, it will hang for good and will not wake up again. This GPU requires mesa changes for proper rendering, and lots of them at that. The command streams are quite far away from any other A6XX GPU and hence it needs special care. This patch was validated both by running an (incomplete) downstream mesa with some hacks (frames rendered correctly, though some instructions made the GPU hangcheck which is expected - garbage in, garbage out) and by replaying RD traces captured with the downstream KGSL driver - no crashes there, ever. Add support for this GPU on the kernel side, which comes down to pretty simply adding A612 HWCG tables, altering a few values and adding a special case for handling the reset line. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 97 +++++++++++++++++++++++++++--- drivers/gpu/drm/msm/adreno/adreno_device.c | 12 ++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 8 ++- 3 files changed, 107 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 0859a6f463f9..b5017c56fa1b 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -254,6 +254,56 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) a6xx_flush(gpu, ring); } +const struct adreno_reglist a612_hwcg[] = { + {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, + {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081}, + {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf}, + {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, + {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, + {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, + {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222}, + {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, + {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00}, + {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022}, + {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, + {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, + {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, + {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, + {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222}, + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, + {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, + {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, + {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, + {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, + {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, + {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, + {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, + {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, + {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, + {}, +}; + /* For a615 family (a615, a616, a618 and a619) */ const struct adreno_reglist a615_hwcg[] = { {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, @@ -604,6 +654,8 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) if (adreno_is_a630(adreno_gpu)) clock_cntl_on = 0x8aa8aa02; + else if (adreno_is_a610(adreno_gpu)) + clock_cntl_on = 0xaaa8aa82; else clock_cntl_on = 0x8aa8aa82; @@ -812,6 +864,13 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) /* Entirely magic, per-GPU-gen value */ u32 ubwc_mode = 0; + if (adreno_is_a610(adreno_gpu)) { + /* HBB = 14 */ + hbb_lo = 1; + min_acc_len = 1; + ubwc_mode = 1; + } + /* a618 is using the hw default values */ if (adreno_is_a618(adreno_gpu)) return; @@ -1074,13 +1133,13 @@ static int hw_init(struct msm_gpu *gpu) a6xx_set_hwcg(gpu, true); /* VBIF/GBIF start*/ - if (adreno_is_a640_family(adreno_gpu) || + if (adreno_is_a610(adreno_gpu) || + adreno_is_a640_family(adreno_gpu) || adreno_is_a650_family(adreno_gpu)) { gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620); gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620); gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620); gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); - gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x3); } else { gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3); @@ -1111,18 +1170,26 @@ static int hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804); gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4); - if (adreno_is_a640_family(adreno_gpu) || - adreno_is_a650_family(adreno_gpu)) + if (adreno_is_a640_family(adreno_gpu) || adreno_is_a650_family(adreno_gpu)) { gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140); - else + gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); + } else if (adreno_is_a610(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x00800060); + gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x40201b16); + } else { gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0); - gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); + gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); + } if (adreno_is_a660_family(adreno_gpu)) gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020); /* Setting the mem pool size */ - gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128); + if (adreno_is_a610(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 48); + gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 47); + } else + gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128); /* Setting the primFifo thresholds default values, * and vccCacheSkipDis=1 bit (0x200) for A640 and newer @@ -1133,6 +1200,8 @@ static int hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200); else if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200); + else if (adreno_is_a610(adreno_gpu)) + gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00080000); else gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00180000); @@ -1148,8 +1217,10 @@ static int hw_init(struct msm_gpu *gpu) a6xx_set_ubwc_config(gpu); /* Enable fault detection */ - gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, - (1 << 30) | 0x1fffff); + if (adreno_is_a610(adreno_gpu)) + gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3ffff); + else + gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x1fffff); gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1); @@ -1383,6 +1454,14 @@ static void a6xx_recover(struct msm_gpu *gpu) /* Software-reset the GPU */ if (adreno_has_gmu_wrapper(adreno_gpu)) { + /* 11nm chips (i.e. A610-hosting ones) have HW issues with the reset line */ + if (!adreno_is_a610(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, 1); + gpu_read(gpu, REG_A6XX_RBBM_SW_RESET_CMD); + udelay(100); + gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, 0); + } + if (adreno_is_a619_holi(adreno_gpu)) { gpu_write(gpu, 0x18, GPR0_GBIF_HALT_REQUEST); spin_until((gpu_read(gpu, REG_A6XX_RBBM_VBIF_GX_RESET_STATUS) & diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index dfb43741ea32..95053ac29398 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -253,6 +253,18 @@ static const struct adreno_info gpulist[] = { .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, .init = a5xx_gpu_init, .zapfw = "a540_zap.mdt", + }, { + .rev = ADRENO_REV(6, 1, 0, ANY_ID), + .revn = 610, + .name = "A610", + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + }, + .gmem = (SZ_128K + SZ_4K), + .inactive_period = 500, + .init = a6xx_gpu_init, + .zapfw = "a610_zap.mdt", + .hwcg = a612_hwcg, }, { .rev = ADRENO_REV(6, 1, 8, ANY_ID), .revn = 618, diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 92ece15ec7d8..27c30a7694f4 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -55,7 +55,8 @@ struct adreno_reglist { u32 value; }; -extern const struct adreno_reglist a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[]; +extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[]; +extern const struct adreno_reglist a660_hwcg[]; struct adreno_info { struct adreno_rev rev; @@ -242,6 +243,11 @@ static inline int adreno_is_a540(struct adreno_gpu *gpu) return gpu->revn == 540; } +static inline int adreno_is_a610(struct adreno_gpu *gpu) +{ + return gpu->revn == 610; +} + static inline int adreno_is_a618(struct adreno_gpu *gpu) { return gpu->revn == 618; From patchwork Thu Feb 23 12:06:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 656053 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0C2FC61DA4 for ; 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[83.9.2.151]) by smtp.gmail.com with ESMTPSA id h23-20020a2ea497000000b0029599744c02sm414838lji.75.2023.02.23.04.06.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Feb 2023 04:07:00 -0800 (PST) From: Konrad Dybcio Date: Thu, 23 Feb 2023 13:06:44 +0100 Subject: [PATCH v3 10/15] drm/msm/a6xx: Fix A680 highest bank bit value MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v3-10-5be55a336819@linaro.org> References: <20230223-topic-gmuwrapper-v3-0-5be55a336819@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v3-0-5be55a336819@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1677154003; l=1043; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=XyF/fIhqGhaqw/LSLnLQoZLpoApnz2Tm2KTMjRETKS0=; b=KNcnjoD9rWmy5mT4YH7OnatzxLE4iAZRwnM2y6dLWueGTxPwo3uCMS0NPrLwqJpUq5uh442AJSwo cgRHrMA2AlIAq7g9yAw9JnDnekIYxgGTePs30xvYuP3cIFpemrAR X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org According to the vendor sources, it's equal to 16, which makes hbb_lo equal to 3. Fixes: 840d10b64dad ("drm: msm: Add 680 gpu to the adreno gpu list") Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index b5017c56fa1b..2c4afecdd213 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -885,12 +885,18 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) hbb_lo = 2; } - if (adreno_is_a640_family(adreno_gpu)) { + if (adreno_is_a640(adreno_gpu)) { amsbc = 1; /* HBB = 15 */ hbb_lo = 2; } + if (adreno_is_a680(adreno_gpu)) { + amsbc = 1; + /* HBB = 16 */ + hbb_lo = 3; + } + if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) { amsbc = 1; /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ From patchwork Thu Feb 23 12:06:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 656052 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56ED5C64ED8 for ; Thu, 23 Feb 2023 12:07:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232565AbjBWMHn (ORCPT ); Thu, 23 Feb 2023 07:07:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33676 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234127AbjBWMHZ (ORCPT ); Thu, 23 Feb 2023 07:07:25 -0500 Received: from mail-lj1-x22c.google.com (mail-lj1-x22c.google.com [IPv6:2a00:1450:4864:20::22c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D938B72E53 for ; Thu, 23 Feb 2023 04:07:03 -0800 (PST) Received: by mail-lj1-x22c.google.com with SMTP id b13so11569732ljf.6 for ; Thu, 23 Feb 2023 04:07:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=kU1DhHqljkZnMyZ8L0mfvbfdXEv07yxf2+yc3rbwTBA=; b=PYQZM3L2LumSLyw8wcCvEpFKJeoS7thhe/+9xJHxQtEQ4+LobuF5sEKheGM5Bhgv9a wbMdwBtRz0l3SS6hA/rhcWf6qMjaYrkGPrV5YgMreAsrt3oE0XzzWYR1PXuoxcyVxJd8 HHbq8ShTi/kMCc9B8S2NuGipD3j3rBrDAAgh1i52he9oNhp4UcQPk51PF2eUkELBpire wwHD5B/5vmh9rwmXtLhJ+NQt+t6Qmh60cnNfjGbtWIVlSV9zw9v4sRZx8SSY/lUTOMrJ L3nQnAlfQy1Rfx4iBNKjUxK1tHP++eLtew8HYpB8EImTjZKM+eUdOrgLNxOQl26Fiq0E tapg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kU1DhHqljkZnMyZ8L0mfvbfdXEv07yxf2+yc3rbwTBA=; b=yU5911qlTbJd+/6xedtZS2emtr5+99Q0qcj3xx0YYzcZh0VpmEcLsMLuRoGKfaK16G 0//e16cR61WU3xzkmbL5L7rd5SaVYttDnljMuDV9LG0jWF2YsOUJTlnPacWN6/ghmlwM tkWeDo4P11ukyGxQOxTQrUYhQ8bH1rs0463lLbu+AsRT9oCoq66h/X9Oe/OYSRQhYmJj ssGjkNxJmHTMUu28+oQDE7aYzhRTljlX6Q9Z+1QxJ2bMWkpDNalFC4r5Rmv86HWJF0zn Mk4iGoULaYeG9+zZi39WvC0ci4A0KDsYqEHpXEto9RI7GJmYtXyD67urHVeEGgvpzZ37 z7uw== X-Gm-Message-State: AO0yUKWyZ2wGXAUl4ksZnLmboRjRKchALwB5M8duv1etwyQvrXyj6f6d HChdv60kajyAFGrFkUwO7EosKg== X-Google-Smtp-Source: AK7set+VgAFb/5QtFiJTtVw7Lkm+EfmrUhUt6x98C5jyNKNo/8vE0EAKnvJZmYI876jSaQ6jtDZ1Uw== X-Received: by 2002:a05:651c:158c:b0:295:9d2c:c5b5 with SMTP id h12-20020a05651c158c00b002959d2cc5b5mr1217095ljq.12.1677154023428; Thu, 23 Feb 2023 04:07:03 -0800 (PST) Received: from [192.168.1.101] (abxi151.neoplus.adsl.tpnet.pl. [83.9.2.151]) by smtp.gmail.com with ESMTPSA id h23-20020a2ea497000000b0029599744c02sm414838lji.75.2023.02.23.04.07.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Feb 2023 04:07:03 -0800 (PST) From: Konrad Dybcio Date: Thu, 23 Feb 2023 13:06:46 +0100 Subject: [PATCH v3 12/15] drm/msm/a6xx: Use "else if" in GPU speedbin rev matching MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v3-12-5be55a336819@linaro.org> References: <20230223-topic-gmuwrapper-v3-0-5be55a336819@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v3-0-5be55a336819@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1677154003; l=1434; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=diEdpVPV98iDyAF3qtuCIpbTUiF49iB6aIjsVbWV6Sw=; b=ZkCJF5gp9SXq5tTFz0avDKLTNJiqFPEk/lO8lIguPILtj3GJe8qp7Dwgbk2fVNK0eKEvODJDTQ+H O5dIDuC/BSYaR/lZLPu4xYN+7gJPClPMteoXtQm13k4Gtpt8w4mQ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The GPU can only be one at a time. Turn a series of ifs into if + elseifs to save some CPU cycles. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index eb24be772934..f694acca931c 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2222,16 +2222,16 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse) if (adreno_cmp_rev(ADRENO_REV(6, 1, 8, ANY_ID), rev)) val = a618_get_speed_bin(fuse); - if (adreno_cmp_rev(ADRENO_REV(6, 1, 9, ANY_ID), rev)) + else if (adreno_cmp_rev(ADRENO_REV(6, 1, 9, ANY_ID), rev)) val = a619_get_speed_bin(fuse); - if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev)) + else if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev)) val = adreno_7c3_get_speed_bin(fuse); - if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev)) + else if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev)) val = a640_get_speed_bin(fuse); - if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev)) + else if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev)) val = a650_get_speed_bin(fuse); if (val == UINT_MAX) { From patchwork Thu Feb 23 12:06:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 656051 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2F3CC636D6 for ; Thu, 23 Feb 2023 12:07:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234134AbjBWMHx (ORCPT ); Thu, 23 Feb 2023 07:07:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33916 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234147AbjBWMHa (ORCPT ); Thu, 23 Feb 2023 07:07:30 -0500 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5D78754548 for ; Thu, 23 Feb 2023 04:07:11 -0800 (PST) Received: by mail-lf1-x12b.google.com with SMTP id r27so11391498lfe.10 for ; Thu, 23 Feb 2023 04:07:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=SZ/xGzExvk13wbA4qbsvWe1ebWJNBnGJT8JbIK1eSfo=; b=GtD3uY6KVcOgkOy/CR8IknJL9LBoGlgXIYEaGeOKc0CRIfEwXT4DtWQO9jXwzMwbPF L2JeagzDKYh5+FsEjmID5ErNMkfMwwbjsnj73bNf/54dcBQLLEEO7y2Qy0ZsHGIgH9pv 1n+GSDq2loo5S+XmYEEuqL7X1JtY8rIXGTP1qKgfu7FPfRRpBVsvzieJfDYmNAlyTx7Z 5+pHzJgt1RbiaabHkywWJ7j0Iy9PKUw60/o8u/wbQK0os3388Ib3aifKtF5ZnIJdrmLc 6PcqOrecwlT6BBgkFsYLLcbLepAYVzOEWfA654vlQTKYk4ucX9WZYRthAjPF4TEaQgK4 6G3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SZ/xGzExvk13wbA4qbsvWe1ebWJNBnGJT8JbIK1eSfo=; b=KgR6gLBjTh+wb7PLxAHei6L7U8rK/DTTfH9CKbJnVI5C9+TbfBobriRN84h2HNRWGw kpIgTq3VGdK93Iubhy1TGT73vj5VzOq5z7OzCkg0r3dd+RxVNrgV5hprBvFFjFr9hEwj mFBZTjgHhIFVRoEEE+qPyv3bcGY6clC781C76Z9LjyLl1GGH+J3JqCw/ZsKXr6i0gZKq 5+AdQXtFm8Un9umXXppaUaAyFPTlo5T6QKDnOqAb+lVIuhlThHuNEK9O0nVyoeJjCEF1 bjLG/npYmOpzwYv0ytj1+ezlpm3u1521cKhbk2yddE54s3xH8Lfp2uRubiNGiZYckxhI ewvQ== X-Gm-Message-State: AO0yUKX4ovxFNz9xyfCNqjYdxvg9a5dA/7aw2OchWq7mLja6zU6vedLC iMTTUl4M9Oj06MFAYNJvpckCmQ== X-Google-Smtp-Source: AK7set85M6q9Qseas9oAZzSpJrj3R3yandRl8Q//18ZT9N2L1yKHvcS8kTOKNPxbLGdtL+pCZaX0Lw== X-Received: by 2002:a19:700d:0:b0:4dc:554b:d27e with SMTP id h13-20020a19700d000000b004dc554bd27emr3475770lfc.65.1677154024955; Thu, 23 Feb 2023 04:07:04 -0800 (PST) Received: from [192.168.1.101] (abxi151.neoplus.adsl.tpnet.pl. [83.9.2.151]) by smtp.gmail.com with ESMTPSA id h23-20020a2ea497000000b0029599744c02sm414838lji.75.2023.02.23.04.07.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Feb 2023 04:07:04 -0800 (PST) From: Konrad Dybcio Date: Thu, 23 Feb 2023 13:06:47 +0100 Subject: [PATCH v3 13/15] drm/msm/a6xx: Use adreno_is_aXYZ macros in speedbin matching MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v3-13-5be55a336819@linaro.org> References: <20230223-topic-gmuwrapper-v3-0-5be55a336819@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v3-0-5be55a336819@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Clark , Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1677154003; l=4256; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=0V7/WcL1MABzv4zFeEQKs26sXQyT+kVWIiROsyIVolM=; b=D9HkDWtlsgD+vquVTDXjCdgIkGfxQXGREpBvyo4fJHN0h6p2nPKn83JtZsrqh0vEaY1HAeDwTV3K dCCpYpXNDdj3E2EvvGzpO//FKJ+LItrMDGREeje+rheuWwsQAJ9R X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Before transitioning to using per-SoC and not per-Adreno speedbin fuse values (need another patchset to land elsewhere), a good improvement/stopgap solution is to use adreno_is_aXYZ macros in place of explicit revision matching. Do so to allow differentiating between A619 and A619_holi. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 18 +++++++++--------- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 14 ++++++++++++-- 2 files changed, 21 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index f694acca931c..d49b649ebecf 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2215,23 +2215,23 @@ static u32 adreno_7c3_get_speed_bin(u32 fuse) return UINT_MAX; } -static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse) +static u32 fuse_to_supp_hw(struct device *dev, struct adreno_gpu *adreno_gpu, u32 fuse) { u32 val = UINT_MAX; - if (adreno_cmp_rev(ADRENO_REV(6, 1, 8, ANY_ID), rev)) + if (adreno_is_a618(adreno_gpu)) val = a618_get_speed_bin(fuse); - else if (adreno_cmp_rev(ADRENO_REV(6, 1, 9, ANY_ID), rev)) + else if (adreno_is_a619(adreno_gpu)) val = a619_get_speed_bin(fuse); - else if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev)) + else if (adreno_is_7c3(adreno_gpu)) val = adreno_7c3_get_speed_bin(fuse); - else if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev)) + else if (adreno_is_a640(adreno_gpu)) val = a640_get_speed_bin(fuse); - else if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev)) + else if (adreno_is_a650(adreno_gpu)) val = a650_get_speed_bin(fuse); if (val == UINT_MAX) { @@ -2244,7 +2244,7 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse) return (1 << val); } -static int a6xx_set_supported_hw(struct device *dev, struct adreno_rev rev) +static int a6xx_set_supported_hw(struct device *dev, struct adreno_gpu *adreno_gpu) { u32 supp_hw; u32 speedbin; @@ -2263,7 +2263,7 @@ static int a6xx_set_supported_hw(struct device *dev, struct adreno_rev rev) return ret; } - supp_hw = fuse_to_supp_hw(dev, rev, speedbin); + supp_hw = fuse_to_supp_hw(dev, adreno_gpu, speedbin); ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); if (ret) @@ -2382,7 +2382,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) if (!adreno_has_gmu_wrapper(adreno_gpu)) a6xx_llc_slices_init(pdev, a6xx_gpu); - ret = a6xx_set_supported_hw(&pdev->dev, config->rev); + ret = a6xx_set_supported_hw(&pdev->dev, adreno_gpu); if (ret) { a6xx_destroy(&(a6xx_gpu->base.base)); return ERR_PTR(ret); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 27c30a7694f4..da9f45a13b5d 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -268,9 +268,9 @@ static inline int adreno_is_a630(struct adreno_gpu *gpu) return gpu->revn == 630; } -static inline int adreno_is_a640_family(struct adreno_gpu *gpu) +static inline int adreno_is_a640(struct adreno_gpu *gpu) { - return (gpu->revn == 640) || (gpu->revn == 680); + return gpu->revn == 640; } static inline int adreno_is_a650(struct adreno_gpu *gpu) @@ -289,6 +289,11 @@ static inline int adreno_is_a660(struct adreno_gpu *gpu) return gpu->revn == 660; } +static inline int adreno_is_a680(struct adreno_gpu *gpu) +{ + return gpu->revn == 680; +} + /* check for a615, a616, a618, a619 or any derivatives */ static inline int adreno_is_a615_family(struct adreno_gpu *gpu) { @@ -306,6 +311,11 @@ static inline int adreno_is_a650_family(struct adreno_gpu *gpu) return gpu->revn == 650 || gpu->revn == 620 || adreno_is_a660_family(gpu); } +static inline int adreno_is_a640_family(struct adreno_gpu *gpu) +{ + return adreno_is_a640(gpu) || adreno_is_a680(gpu); +} + u64 adreno_private_address_space_size(struct msm_gpu *gpu); int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, uint32_t param, uint64_t *value, uint32_t *len);