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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id e187-20020a6369c4000000b004b1fef0bf16sm5992850pgc.73.2023.02.23.12.43.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Feb 2023 12:43:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH 01/13] target/sparc: Use tlb_set_page_full Date: Thu, 23 Feb 2023 10:43:30 -1000 Message-Id: <20230223204342.1093632-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230223204342.1093632-1-richard.henderson@linaro.org> References: <20230223204342.1093632-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Pass CPUTLBEntryFull to get_physical_address instead of a collection of pointers. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Acked-by: Mark Cave-Ayland --- Cc: Mark Cave-Ayland Cc: Artyom Tarasenko --- target/sparc/mmu_helper.c | 121 +++++++++++++++++--------------------- 1 file changed, 54 insertions(+), 67 deletions(-) diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 158ec2ae8f..a98dd0abd4 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -64,10 +64,9 @@ static const int perm_table[2][8] = { } }; -static int get_physical_address(CPUSPARCState *env, hwaddr *physical, - int *prot, int *access_index, MemTxAttrs *attrs, - target_ulong address, int rw, int mmu_idx, - target_ulong *page_size) +static int get_physical_address(CPUSPARCState *env, CPUTLBEntryFull *full, + int *access_index, target_ulong address, + int rw, int mmu_idx) { int access_perms = 0; hwaddr pde_ptr; @@ -80,20 +79,20 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical, is_user = mmu_idx == MMU_USER_IDX; if (mmu_idx == MMU_PHYS_IDX) { - *page_size = TARGET_PAGE_SIZE; + full->lg_page_size = TARGET_PAGE_BITS; /* Boot mode: instruction fetches are taken from PROM */ if (rw == 2 && (env->mmuregs[0] & env->def.mmu_bm)) { - *physical = env->prom_addr | (address & 0x7ffffULL); - *prot = PAGE_READ | PAGE_EXEC; + full->phys_addr = env->prom_addr | (address & 0x7ffffULL); + full->prot = PAGE_READ | PAGE_EXEC; return 0; } - *physical = address; - *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; + full->phys_addr = address; + full->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; return 0; } *access_index = ((rw & 1) << 2) | (rw & 2) | (is_user ? 0 : 1); - *physical = 0xffffffffffff0000ULL; + full->phys_addr = 0xffffffffffff0000ULL; /* SPARC reference MMU table walk: Context table->L1->L2->PTE */ /* Context base + context number */ @@ -157,16 +156,17 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical, case 2: /* L3 PTE */ page_offset = 0; } - *page_size = TARGET_PAGE_SIZE; + full->lg_page_size = TARGET_PAGE_BITS; break; case 2: /* L2 PTE */ page_offset = address & 0x3f000; - *page_size = 0x40000; + full->lg_page_size = 18; } break; case 2: /* L1 PTE */ page_offset = address & 0xfff000; - *page_size = 0x1000000; + full->lg_page_size = 24; + break; } } @@ -188,16 +188,16 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical, } /* the page can be put in the TLB */ - *prot = perm_table[is_user][access_perms]; + full->prot = perm_table[is_user][access_perms]; if (!(pde & PG_MODIFIED_MASK)) { /* only set write access if already dirty... otherwise wait for dirty access */ - *prot &= ~PAGE_WRITE; + full->prot &= ~PAGE_WRITE; } /* Even if large ptes, we map only one 4KB page in the cache to avoid filling it too fast */ - *physical = ((hwaddr)(pde & PTE_ADDR_MASK) << 4) + page_offset; + full->phys_addr = ((hwaddr)(pde & PTE_ADDR_MASK) << 4) + page_offset; return error_code; } @@ -208,11 +208,9 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, { SPARCCPU *cpu = SPARC_CPU(cs); CPUSPARCState *env = &cpu->env; - hwaddr paddr; + CPUTLBEntryFull full = {}; target_ulong vaddr; - target_ulong page_size; - int error_code = 0, prot, access_index; - MemTxAttrs attrs = {}; + int error_code = 0, access_index; /* * TODO: If we ever need tlb_vaddr_to_host for this target, @@ -223,16 +221,15 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, assert(!probe); address &= TARGET_PAGE_MASK; - error_code = get_physical_address(env, &paddr, &prot, &access_index, &attrs, - address, access_type, - mmu_idx, &page_size); + error_code = get_physical_address(env, &full, &access_index, + address, access_type, mmu_idx); vaddr = address; if (likely(error_code == 0)) { qemu_log_mask(CPU_LOG_MMU, "Translate at %" VADDR_PRIx " -> " HWADDR_FMT_plx ", vaddr " TARGET_FMT_lx "\n", - address, paddr, vaddr); - tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size); + address, full.phys_addr, vaddr); + tlb_set_page_full(cs, mmu_idx, vaddr, &full); return true; } @@ -247,8 +244,8 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, permissions. If no mapping is available, redirect accesses to neverland. Fake/overridden mappings will be flushed when switching to normal mode. */ - prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; - tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, TARGET_PAGE_SIZE); + full.prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; + tlb_set_page_full(cs, mmu_idx, vaddr, &full); return true; } else { if (access_type == MMU_INST_FETCH) { @@ -545,8 +542,7 @@ static uint64_t build_sfsr(CPUSPARCState *env, int mmu_idx, int rw) return sfsr; } -static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical, - int *prot, MemTxAttrs *attrs, +static int get_physical_address_data(CPUSPARCState *env, CPUTLBEntryFull *full, target_ulong address, int rw, int mmu_idx) { CPUState *cs = env_cpu(env); @@ -579,11 +575,12 @@ static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical, for (i = 0; i < 64; i++) { /* ctx match, vaddr match, valid? */ - if (ultrasparc_tag_match(&env->dtlb[i], address, context, physical)) { + if (ultrasparc_tag_match(&env->dtlb[i], address, context, + &full->phys_addr)) { int do_fault = 0; if (TTE_IS_IE(env->dtlb[i].tte)) { - attrs->byte_swap = true; + full->attrs.byte_swap = true; } /* access ok? */ @@ -616,9 +613,9 @@ static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical, } if (!do_fault) { - *prot = PAGE_READ; + full->prot = PAGE_READ; if (TTE_IS_W_OK(env->dtlb[i].tte)) { - *prot |= PAGE_WRITE; + full->prot |= PAGE_WRITE; } TTE_SET_USED(env->dtlb[i].tte); @@ -645,8 +642,7 @@ static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical, return 1; } -static int get_physical_address_code(CPUSPARCState *env, hwaddr *physical, - int *prot, MemTxAttrs *attrs, +static int get_physical_address_code(CPUSPARCState *env, CPUTLBEntryFull *full, target_ulong address, int mmu_idx) { CPUState *cs = env_cpu(env); @@ -681,7 +677,7 @@ static int get_physical_address_code(CPUSPARCState *env, hwaddr *physical, for (i = 0; i < 64; i++) { /* ctx match, vaddr match, valid? */ if (ultrasparc_tag_match(&env->itlb[i], - address, context, physical)) { + address, context, &full->phys_addr)) { /* access ok? */ if (TTE_IS_PRIV(env->itlb[i].tte) && is_user) { /* Fault status register */ @@ -708,7 +704,7 @@ static int get_physical_address_code(CPUSPARCState *env, hwaddr *physical, return 1; } - *prot = PAGE_EXEC; + full->prot = PAGE_EXEC; TTE_SET_USED(env->itlb[i].tte); return 0; } @@ -722,14 +718,13 @@ static int get_physical_address_code(CPUSPARCState *env, hwaddr *physical, return 1; } -static int get_physical_address(CPUSPARCState *env, hwaddr *physical, - int *prot, int *access_index, MemTxAttrs *attrs, - target_ulong address, int rw, int mmu_idx, - target_ulong *page_size) +static int get_physical_address(CPUSPARCState *env, CPUTLBEntryFull *full, + int *access_index, target_ulong address, + int rw, int mmu_idx) { /* ??? We treat everything as a small page, then explicitly flush everything when an entry is evicted. */ - *page_size = TARGET_PAGE_SIZE; + full->lg_page_size = TARGET_PAGE_BITS; /* safety net to catch wrong softmmu index use from dynamic code */ if (env->tl > 0 && mmu_idx != MMU_NUCLEUS_IDX) { @@ -747,17 +742,15 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical, } if (mmu_idx == MMU_PHYS_IDX) { - *physical = ultrasparc_truncate_physical(address); - *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; + full->phys_addr = ultrasparc_truncate_physical(address); + full->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; return 0; } if (rw == 2) { - return get_physical_address_code(env, physical, prot, attrs, address, - mmu_idx); + return get_physical_address_code(env, full, address, mmu_idx); } else { - return get_physical_address_data(env, physical, prot, attrs, address, - rw, mmu_idx); + return get_physical_address_data(env, full, address, rw, mmu_idx); } } @@ -768,25 +761,17 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, { SPARCCPU *cpu = SPARC_CPU(cs); CPUSPARCState *env = &cpu->env; - target_ulong vaddr; - hwaddr paddr; - target_ulong page_size; - MemTxAttrs attrs = {}; - int error_code = 0, prot, access_index; + CPUTLBEntryFull full = {}; + int error_code = 0, access_index; address &= TARGET_PAGE_MASK; - error_code = get_physical_address(env, &paddr, &prot, &access_index, &attrs, - address, access_type, - mmu_idx, &page_size); + error_code = get_physical_address(env, &full, &access_index, + address, access_type, mmu_idx); if (likely(error_code == 0)) { - vaddr = address; - - trace_mmu_helper_mmu_fault(address, paddr, mmu_idx, env->tl, + trace_mmu_helper_mmu_fault(address, full.phys_addr, mmu_idx, env->tl, env->dmmu.mmu_primary_context, env->dmmu.mmu_secondary_context); - - tlb_set_page_with_attrs(cs, vaddr, paddr, attrs, prot, mmu_idx, - page_size); + tlb_set_page_full(cs, mmu_idx, address, &full); return true; } if (probe) { @@ -888,12 +873,14 @@ void dump_mmu(CPUSPARCState *env) static int cpu_sparc_get_phys_page(CPUSPARCState *env, hwaddr *phys, target_ulong addr, int rw, int mmu_idx) { - target_ulong page_size; - int prot, access_index; - MemTxAttrs attrs = {}; + CPUTLBEntryFull full = {}; + int access_index, ret; - return get_physical_address(env, phys, &prot, &access_index, &attrs, addr, - rw, mmu_idx, &page_size); + ret = get_physical_address(env, &full, &access_index, addr, rw, mmu_idx); + if (ret == 0) { + *phys = full.phys_addr; + } + return ret; } #if defined(TARGET_SPARC64) From patchwork Thu Feb 23 20:43:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 656007 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp539834wrb; Thu, 23 Feb 2023 12:47:05 -0800 (PST) X-Google-Smtp-Source: AK7set9aQkC/74FzbzNuqzK6HKuf/ljfYT5YdokjXa7BPRKU0U+kDrczhyY6X6NlMIaNLzBee0cV X-Received: by 2002:a05:622a:1b92:b0:3b8:2ce4:3e9 with SMTP id bp18-20020a05622a1b9200b003b82ce403e9mr21800585qtb.32.1677185225356; Thu, 23 Feb 2023 12:47:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677185225; cv=none; d=google.com; s=arc-20160816; b=mcOxJSUwEVB1siR8Nvxnmj5tB9BBpowuTJenFnjCK9UNvD9RnfswmM+efkc9i0PgcK yuiQgkLf31F3zvQ5CcKBu2pLfp1Yl3ditB7CIMeOOs0xQiet6TfqpUVpULsXLJ8qk3vF fsxsiLhU5pBV7EVTsQHbS9FQY4943qfOB7ajlFjsy6T6kfHA5MIKEFFoIYBr5j1ClsDu pHgxJq99TK+7N5bf5KjfoueWV/cjhYkH891EeNoMbLWOFzidPMWOhVM59yYMzQWaM7FT TsRuYpaSEYntJnHMRjB7/CndHckGBJIfns11EurOzV/F9O+28mQof/kcXlnNKEN9TnHS aSTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=m3uf45aNqmoWHA7BxhgBMDgfKLKR3Hs0LkS31+eiMNU=; b=jPDRaJFJiuHrlcI3u3yqUBkGCj+EzcP4sCzy7+DzS/Mfw5N4e7Ze+QOvwBHrC8N8Q0 iZOgECmz7mOF9yN924Bt6JQbYLaGighKrLJJWM3W45byRVzfUhpfblE8eh3dYWOfhyLj Uy22tt6NFa1qUqAxdT1Lee1eI1z4ceRTBANIy7zV9y9LsVa9WOujGQpIlPxZEQkjtUCT unYbMXWNZCgJtEMZJzvz70xMlnXFithG2H+Ei0cLQrJx8t+iqHdnsNIsQEN2/2NR7Ag0 wEfmbaInbsXHfaBgGux4HyzwG+fHMrfZ8IOdxVCRxDsDvjnjDNgzaPPdpMBHi5OKxeVh TrFA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xFJK81G6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id e187-20020a6369c4000000b004b1fef0bf16sm5992850pgc.73.2023.02.23.12.43.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Feb 2023 12:43:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 02/13] accel/tcg: Retain prot flags from tlb_fill Date: Thu, 23 Feb 2023 10:43:31 -1000 Message-Id: <20230223204342.1093632-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230223204342.1093632-1-richard.henderson@linaro.org> References: <20230223204342.1093632-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org While changes are made to prot within tlb_set_page_full, they are an implementation detail of softmmu. Retain the original for any target use of probe_access_full. Fixes: 4047368938f6 ("accel/tcg: Introduce tlb_set_page_full") Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- accel/tcg/cputlb.c | 1 - 1 file changed, 1 deletion(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index d7ca90e3b4..169adc0262 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1251,7 +1251,6 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, desc->fulltlb[index] = *full; desc->fulltlb[index].xlat_section = iotlb - vaddr_page; desc->fulltlb[index].phys_addr = paddr_page; - desc->fulltlb[index].prot = prot; /* Now calculate the new entry */ tn.addend = addend - vaddr_page; From patchwork Thu Feb 23 20:43:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 656006 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp539624wrb; Thu, 23 Feb 2023 12:46:40 -0800 (PST) X-Google-Smtp-Source: AK7set8FqU6XwElUcSmhwKmBGxgNyA5v/ieYB8tykbPAKfSSAFjYF9+3JZ+MduahCXNF6yFFGDv9 X-Received: by 2002:a05:6214:4011:b0:537:9e59:3997 with SMTP id kd17-20020a056214401100b005379e593997mr25514998qvb.51.1677185199821; Thu, 23 Feb 2023 12:46:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677185199; cv=none; d=google.com; s=arc-20160816; b=Gm+a7q5XKuuW6bcPTt+SHD5F0aXZFOG5KkQWIIEDbrE8qx+RsW/pUdOHlqoTnH2rGw q1dGZ+TWanUsx6LkeLF5fGd3Tccnc9AgKA/XFEZTXMQWR6Ngqw/oP5ndWxm9NE6J/sNe OAwwVCxvO0ccIPI7Xue7mEBTkVVehrDGdDEiereEH1pxNDdq5n638TPluVI55A/ckZbF iA4IpCHxmx2ZK/P8QHpJnXsT3gc+2S+pFckm6SjUx+5Yi0ylBNhZnZhDbMn+PC//L24T Ou1x9MDJ/ZIklBmbn9jd2IWFJyZ/v4dYgfQEcDJuEhdDqsM8j0Hh2zTo8N++LyC3gRz9 +bBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=z2QI1lNn/XT+gr65A4/6/WrKy8DpP4zP5U+ng+Laukk=; b=rfsfpZ+qhQceV7MLmGTy+epabhbHAD0h5K7mmvj/Rr9h39mEY80LRNGoDP/0B5jigM nm1xp+wICmrwFIPCHAHUxBDEUI7GqThsNCZxDxsn20ulBO6dNBt+EXdkNB6qVfRurCI4 +F0A3+qddjbWgqyINsvaa01ZWcYLO9ZexAA9fOf7F0QVO6g9PZ5S9KJxQ41qqVIsBlTl 7uZl97CVT7W19Ao+fXk1+lAzukqLk/YfeTXDm1YJ1dKFcitVLNJgfNvgGZk1lGzdzxBD UyggsKeVcqCrV6m1RnHlJrgi+AfrdDLIDBfoVcyQGJXYYqPoUWqcvLRdi1t6daJrzyeH V8LA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ir61O+kR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id e187-20020a6369c4000000b004b1fef0bf16sm5992850pgc.73.2023.02.23.12.43.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Feb 2023 12:43:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 03/13] accel/tcg: Store some tlb flags in CPUTLBEntryFull Date: Thu, 23 Feb 2023 10:43:32 -1000 Message-Id: <20230223204342.1093632-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230223204342.1093632-1-richard.henderson@linaro.org> References: <20230223204342.1093632-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We have run out of bits we can use within the CPUTLBEntry comparators, as TLB_FLAGS_MASK cannot overlap alignment. Store slow_flags[] in CPUTLBEntryFull, and merge with the flags from the comparator. A new TLB_FORCE_SLOW bit is set within the comparator as an indication that the slow path must be used. Move TLB_BSWAP to TLB_SLOW_FLAGS_MASK. Since we are out of bits, we cannot create a new bit without moving an old one. Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 21 ++++++++-- include/exec/cpu-defs.h | 6 +++ accel/tcg/cputlb.c | 93 ++++++++++++++++++++++++----------------- 3 files changed, 77 insertions(+), 43 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 2eb1176538..080cb3112e 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -380,17 +380,30 @@ CPUArchState *cpu_copy(CPUArchState *env); #define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3)) /* Set if TLB entry contains a watchpoint. */ #define TLB_WATCHPOINT (1 << (TARGET_PAGE_BITS_MIN - 4)) -/* Set if TLB entry requires byte swap. */ -#define TLB_BSWAP (1 << (TARGET_PAGE_BITS_MIN - 5)) +/* Set if the slow path must be used; more flags in CPUTLBEntryFull. */ +#define TLB_FORCE_SLOW (1 << (TARGET_PAGE_BITS_MIN - 5)) /* Set if TLB entry writes ignored. */ #define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 6)) -/* Use this mask to check interception with an alignment mask +/* + * Use this mask to check interception with an alignment mask * in a TCG backend. */ #define TLB_FLAGS_MASK \ (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \ - | TLB_WATCHPOINT | TLB_BSWAP | TLB_DISCARD_WRITE) + | TLB_WATCHPOINT | TLB_FORCE_SLOW | TLB_DISCARD_WRITE) + +/* + * Flags stored in CPUTLBEntryFull.slow_flags[x]. + * TLB_FORCE_SLOW must be set in CPUTLBEntry.addr_idx[x]. + */ +/* Set if TLB entry requires byte swap. */ +#define TLB_BSWAP (1 << 0) + +#define TLB_SLOW_FLAGS_MASK TLB_BSWAP + +/* The two sets of flags must not overlap. */ +QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK); /** * tlb_hit_page: return true if page aligned @addr is a hit against the diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 7ce3bcb06b..ef10c625d4 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -170,6 +170,12 @@ typedef struct CPUTLBEntryFull { /* @lg_page_size contains the log2 of the page size. */ uint8_t lg_page_size; + /* + * Additional tlb flags for use by the slow path. If non-zero, + * the corresponding CPUTLBEntry comparator must have TLB_FORCE_SLOW. + */ + uint8_t slow_flags[3]; + /* * Allow target-specific additions to this structure. * This may be used to cache items from the guest cpu diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 169adc0262..e9848b3ab6 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1106,6 +1106,24 @@ static void tlb_add_large_page(CPUArchState *env, int mmu_idx, env_tlb(env)->d[mmu_idx].large_page_mask = lp_mask; } +static inline void tlb_set_compare(CPUTLBEntryFull *full, CPUTLBEntry *ent, + target_ulong address, int flags, + MMUAccessType access_type, bool enable) +{ + if (enable) { + address |= flags & TLB_FLAGS_MASK; + flags &= TLB_SLOW_FLAGS_MASK; + if (flags) { + address |= TLB_FORCE_SLOW; + } + } else { + address = -1; + flags = 0; + } + ent->addr_idx[access_type] = address; + full->slow_flags[access_type] = flags; +} + /* * Add a new TLB entry. At most one entry for a given virtual address * is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the @@ -1121,9 +1139,7 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, CPUTLB *tlb = env_tlb(env); CPUTLBDesc *desc = &tlb->d[mmu_idx]; MemoryRegionSection *section; - unsigned int index; - target_ulong address; - target_ulong write_address; + unsigned int index, read_flags, write_flags; uintptr_t addend; CPUTLBEntry *te, tn; hwaddr iotlb, xlat, sz, paddr_page; @@ -1152,13 +1168,13 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, " prot=%x idx=%d\n", vaddr, full->phys_addr, prot, mmu_idx); - address = vaddr_page; + read_flags = 0; if (full->lg_page_size < TARGET_PAGE_BITS) { /* Repeat the MMU check and TLB fill on every access. */ - address |= TLB_INVALID_MASK; + read_flags |= TLB_INVALID_MASK; } if (full->attrs.byte_swap) { - address |= TLB_BSWAP; + read_flags |= TLB_BSWAP; } is_ram = memory_region_is_ram(section->mr); @@ -1172,7 +1188,7 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, addend = 0; } - write_address = address; + write_flags = read_flags; if (is_ram) { iotlb = memory_region_get_ram_addr(section->mr) + xlat; /* @@ -1181,9 +1197,9 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, */ if (prot & PAGE_WRITE) { if (section->readonly) { - write_address |= TLB_DISCARD_WRITE; + write_flags |= TLB_DISCARD_WRITE; } else if (cpu_physical_memory_is_clean(iotlb)) { - write_address |= TLB_NOTDIRTY; + write_flags |= TLB_NOTDIRTY; } } } else { @@ -1194,9 +1210,9 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, * Reads to romd devices go through the ram_ptr found above, * but of course reads to I/O must go through MMIO. */ - write_address |= TLB_MMIO; + write_flags |= TLB_MMIO; if (!is_romd) { - address = write_address; + read_flags = write_flags; } } @@ -1249,36 +1265,27 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, * vaddr we add back in io_readx()/io_writex()/get_page_addr_code(). */ desc->fulltlb[index] = *full; - desc->fulltlb[index].xlat_section = iotlb - vaddr_page; - desc->fulltlb[index].phys_addr = paddr_page; + full = &desc->fulltlb[index]; + full->xlat_section = iotlb - vaddr_page; + full->phys_addr = paddr_page; /* Now calculate the new entry */ tn.addend = addend - vaddr_page; - if (prot & PAGE_READ) { - tn.addr_read = address; - if (wp_flags & BP_MEM_READ) { - tn.addr_read |= TLB_WATCHPOINT; - } - } else { - tn.addr_read = -1; - } - if (prot & PAGE_EXEC) { - tn.addr_code = address; - } else { - tn.addr_code = -1; - } + tlb_set_compare(full, &tn, vaddr_page, read_flags, + MMU_INST_FETCH, prot & PAGE_EXEC); - tn.addr_write = -1; - if (prot & PAGE_WRITE) { - tn.addr_write = write_address; - if (prot & PAGE_WRITE_INV) { - tn.addr_write |= TLB_INVALID_MASK; - } - if (wp_flags & BP_MEM_WRITE) { - tn.addr_write |= TLB_WATCHPOINT; - } + if (wp_flags & BP_MEM_READ) { + read_flags |= TLB_WATCHPOINT; } + tlb_set_compare(full, &tn, vaddr_page, read_flags, + MMU_DATA_LOAD, prot & PAGE_READ); + + if (wp_flags & BP_MEM_WRITE) { + write_flags |= TLB_WATCHPOINT; + } + tlb_set_compare(full, &tn, vaddr_page, write_flags, MMU_DATA_STORE, + (prot & PAGE_WRITE) && !(prot & PAGE_WRITE_INV)); copy_tlb_helper_locked(te, &tn); tlb_n_used_entries_inc(env, mmu_idx); @@ -1508,7 +1515,8 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr, CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr); target_ulong tlb_addr = tlb_read_idx(entry, access_type); target_ulong page_addr = addr & TARGET_PAGE_MASK; - int flags = TLB_FLAGS_MASK; + int flags = TLB_FLAGS_MASK & ~TLB_FORCE_SLOW; + CPUTLBEntryFull *full; if (!tlb_hit_page(tlb_addr, page_addr)) { if (!victim_tlb_hit(env, mmu_idx, index, access_type, page_addr)) { @@ -1537,7 +1545,8 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr, } flags &= tlb_addr; - *pfull = &env_tlb(env)->d[mmu_idx].fulltlb[index]; + *pfull = full = &env_tlb(env)->d[mmu_idx].fulltlb[index]; + flags |= full->slow_flags[access_type]; /* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */ if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY))) { @@ -1744,6 +1753,8 @@ static bool mmu_lookup1(CPUArchState *env, MMULookupPageData *data, CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr); target_ulong tlb_addr = tlb_read_idx(entry, access_type); bool maybe_resized = false; + CPUTLBEntryFull *full; + int flags; /* If the TLB entry is for a different page, reload and try again. */ if (!tlb_hit(tlb_addr, addr)) { @@ -1757,8 +1768,12 @@ static bool mmu_lookup1(CPUArchState *env, MMULookupPageData *data, tlb_addr = tlb_read_idx(entry, access_type) & ~TLB_INVALID_MASK; } - data->flags = tlb_addr & TLB_FLAGS_MASK; - data->full = &env_tlb(env)->d[mmu_idx].fulltlb[index]; + full = &env_tlb(env)->d[mmu_idx].fulltlb[index]; + flags = tlb_addr & (TLB_FLAGS_MASK & ~TLB_FORCE_SLOW); + flags |= full->slow_flags[access_type]; + + data->full = full; + data->flags = flags; /* Compute haddr speculatively; depending on flags it might be invalid. */ data->haddr = (void *)((uintptr_t)addr + entry->addend); From patchwork Thu Feb 23 20:43:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 656000 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp539195wrb; Thu, 23 Feb 2023 12:45:33 -0800 (PST) X-Google-Smtp-Source: AK7set/KtUeASdJFIwK8wbOmU16FDmUHIj5IrdbVVmilyDQMRuzyqSfVT8Q3klE2kmOp/n3UDe+z X-Received: by 2002:ad4:4ee3:0:b0:56e:ac97:85da with SMTP id dv3-20020ad44ee3000000b0056eac9785damr18991484qvb.30.1677185132840; Thu, 23 Feb 2023 12:45:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677185132; cv=none; d=google.com; s=arc-20160816; b=TVQVx8n85k2Yui0zSPHdAhXFFYXVsUA6uBHoRBaYIXv9+ZeZCDNnd+4GWgBkSlA4Dp 9ZCmVjxqE2z7wLaWWKfATbDUfgbUwexvzynIH7+chcdtToL7z2S/fb21iZ9maKMGISLQ ggdeuHI1u74HcIxhO7eRahHy3JiT39W0LPEMNPJhlAr0nyooLWMNmo5lZiLHznyRIrX/ gFNV2oLDUGoKqVxJxmCJ3yuxLYYnv9U936GxKdCqB+3b+WxAFpiormF6ow5DBAaVbzJ3 vh/lJaBu5w24wW8fEmbOzP0W61Sy56zm5+IAoV0XyIHou96hHxCDe8xw8Axki6/QPbpa Gtpw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=1INiv+c7X4ecZzReDySXjMWltTGp1DftJNOlKz8t3fU=; b=CQ31s8/u1P0E6Aoq1xwSt3GYHqg3c3ozIJFmXg5fSdMP6/Waek/pr4kk7BJPe0vAI1 W0ARc9Srrf/Udd2F2KD7TyzAYF/ybAdnf3VhRCSknKnlQldGyf2XgYrbwKmVsRUzrIkA ObtN622vLnD8i8yI+CJRdoXxnb4IRgK25qp1ozBPKVdYcBTuPUgkWkie/NACUL7v+2Ak uhnfVVwNTd4tLunVfA4if4od85JIfnGispN2lDaev1LUGkSmna9UiG/rhWGZG8DF7X/c h58BWRhfg1wxCo+GlF8PHh6vN54qsj2+6X95S7ukc89rIvd348UhebtOrDJ34L0mILVL VPlQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Ud/t8ow4"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id e187-20020a6369c4000000b004b1fef0bf16sm5992850pgc.73.2023.02.23.12.43.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Feb 2023 12:43:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 04/13] accel/tcg: Honor TLB_DISCARD_WRITE in atomic_mmu_lookup Date: Thu, 23 Feb 2023 10:43:33 -1000 Message-Id: <20230223204342.1093632-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230223204342.1093632-1-richard.henderson@linaro.org> References: <20230223204342.1093632-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Using an atomic write or read-write insn on ROM is basically a happens-never case. Handle it via stop-the-world, which will generate non-atomic serial code, where we can correctly ignore the write while producing the correct read result. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- accel/tcg/cputlb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index e9848b3ab6..74ad8e0876 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1974,7 +1974,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, } /* Notice an IO access or a needs-MMU-lookup access */ - if (unlikely(tlb_addr & TLB_MMIO)) { + if (unlikely(tlb_addr & (TLB_MMIO | TLB_DISCARD_WRITE))) { /* There's really nothing that can be done to support this apart from stop-the-world. */ goto stop_the_world; From patchwork Thu Feb 23 20:43:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 656004 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp539576wrb; Thu, 23 Feb 2023 12:46:32 -0800 (PST) X-Google-Smtp-Source: AK7set8dwZ3jsrgKRpbaoy+0bMBy0N4ZcAzySkFmzs2zf+bI7a3OaTvKZOb87iykXcvQBtglCrJF X-Received: by 2002:a05:6214:e62:b0:56e:c0df:8492 with SMTP id jz2-20020a0562140e6200b0056ec0df8492mr24535301qvb.31.1677185192714; Thu, 23 Feb 2023 12:46:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677185192; cv=none; d=google.com; s=arc-20160816; b=Jk8lHmGFh8QGzZ1OIrirS2wLmBann7AC/L1QdhyhlOFLY+gxEEsgeSyATtJW5m8J9C 1a5I2ubTWwCAjLfHhKGowRsGrooGqkH+2GlGTX8rAja/q2M9SA6cGlMlI6Rjk8mkO/Sp Y4ribKt1+fDxAjtB/g3flkNa7MfuOaqc47W2LzzcA/0UdyCFL9fL79LLztOowXzEtiTX RC6kWYCRjqT+r6eo3HYm2vM1k21n6MEJDR8Ob5vSLqiAYLR1FM1tMEzGkQ766srHsd3m CWNCQdyANhgfFeAn9ZTgAYBKuGvvp3SsKY9NyEjH63hK2Jda/vS75AhwqDADeuTmYIa4 +X+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=uCfgSwaCWGjVH4XmiAS5xzTjPaTu2Mc57Kv2qaU5lRM=; b=zAWpYeuU0VWCcjNaHzAYq3o2JIYkblDXi8yb815pggcsVZATCmibJlVGX07qYDBJZ2 xoNDN65b0ntAck1Pu60cgZmGQK6Cqm84lguC3yCi81nCyTMuiSNy54WdUco6Bx74KHSg En5u5KanRAkVbvjGb2TgvUTsSRxjJGfXq0cHAbwI4d61XPXp2tyakWI8y+hw9iGxxMqy BwBebVqo69HSuEDTCnyJyYvfMsaNhnCgqL+7uYk1a/tNut5tYnMTHjJew5F7VyU8yGxw cuzfYr0Mt2Ce0gmpv32jVvbkGCg6k7Pvz08nzxrfHSny2U63bBfUew5D2iLbWHQmtf3u DYsg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="n89/wfw9"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id e187-20020a6369c4000000b004b1fef0bf16sm5992850pgc.73.2023.02.23.12.43.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Feb 2023 12:43:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 05/13] softmmu/physmem: Check watchpoints for read+write at once Date: Thu, 23 Feb 2023 10:43:34 -1000 Message-Id: <20230223204342.1093632-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230223204342.1093632-1-richard.henderson@linaro.org> References: <20230223204342.1093632-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Atomic operations are read-modify-write, and we'd like to be able to test both read and write with one call. This is easy enough, with BP_MEM_READ | BP_MEM_WRITE. Add BP_HIT_SHIFT to make it easy to set BP_WATCHPOINT_HIT_*. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h | 7 ++++--- softmmu/physmem.c | 19 ++++++++++--------- 2 files changed, 14 insertions(+), 12 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 2417597236..2f85ba14b3 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -921,9 +921,10 @@ void cpu_single_step(CPUState *cpu, int enabled); #define BP_GDB 0x10 #define BP_CPU 0x20 #define BP_ANY (BP_GDB | BP_CPU) -#define BP_WATCHPOINT_HIT_READ 0x40 -#define BP_WATCHPOINT_HIT_WRITE 0x80 -#define BP_WATCHPOINT_HIT (BP_WATCHPOINT_HIT_READ | BP_WATCHPOINT_HIT_WRITE) +#define BP_HIT_SHIFT 6 +#define BP_WATCHPOINT_HIT_READ (BP_MEM_READ << BP_HIT_SHIFT) +#define BP_WATCHPOINT_HIT_WRITE (BP_MEM_WRITE << BP_HIT_SHIFT) +#define BP_WATCHPOINT_HIT (BP_MEM_ACCESS << BP_HIT_SHIFT) int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, CPUBreakpoint **breakpoint); diff --git a/softmmu/physmem.c b/softmmu/physmem.c index cb998cdf23..c4f62dee60 100644 --- a/softmmu/physmem.c +++ b/softmmu/physmem.c @@ -915,9 +915,12 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, /* this is currently used only by ARM BE32 */ addr = cc->tcg_ops->adjust_watchpoint_address(cpu, addr, len); } + + assert((flags & ~BP_MEM_ACCESS) == 0); QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { - if (watchpoint_address_matches(wp, addr, len) - && (wp->flags & flags)) { + int hit_flags = wp->flags & flags; + + if (hit_flags && watchpoint_address_matches(wp, addr, len)) { if (replay_running_debug()) { /* * replay_breakpoint reads icount. @@ -936,16 +939,14 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, replay_breakpoint(); return; } - if (flags == BP_MEM_READ) { - wp->flags |= BP_WATCHPOINT_HIT_READ; - } else { - wp->flags |= BP_WATCHPOINT_HIT_WRITE; - } + + wp->flags |= hit_flags << BP_HIT_SHIFT; wp->hitaddr = MAX(addr, wp->vaddr); wp->hitattrs = attrs; - if (wp->flags & BP_CPU && cc->tcg_ops->debug_check_watchpoint && - !cc->tcg_ops->debug_check_watchpoint(cpu, wp)) { + if (wp->flags & BP_CPU + && cc->tcg_ops->debug_check_watchpoint + && !cc->tcg_ops->debug_check_watchpoint(cpu, wp)) { wp->flags &= ~BP_WATCHPOINT_HIT; continue; } From patchwork Thu Feb 23 20:43:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 656005 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp539628wrb; Thu, 23 Feb 2023 12:46:40 -0800 (PST) X-Google-Smtp-Source: AK7set/V67wTGZz2cnLTHijANnvJMWfulmUuUSmiBWlwHKuDsdJiXnuCr8PH6y8A+naMyllk1UG4 X-Received: by 2002:a05:6214:3016:b0:56b:eceb:2d9d with SMTP id ke22-20020a056214301600b0056beceb2d9dmr24770817qvb.36.1677185200242; Thu, 23 Feb 2023 12:46:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677185200; cv=none; d=google.com; s=arc-20160816; b=aWwPHL3rw8JdVgkR7+YjJunnm4MWjPPGC09Kba6ztq4/cf1u9IjG4qUSLjpaIpQyqv KC2J9pKDKBGf3JAVMB9rej7ITE6kVKgtrOcgUApuTaQH8LctNyAygOATz+yaN2IRz89t KQ6Px/TZruJn4nPkKBq4p/PnJmojLhF1RlTNWJIOk+1TbzHM+xUhYzD4nNiLYtga0hbe VHDCFFDa1Vsa27iBFsnNWXPCc4OGI94u7suWDM9DO7ITjZY5WEXXDkJtsH+CBPUZp9o8 wMEG0+qD25IIQgs3k3QiQm0e8fXIEm+CmYdO0fyFTe4ecQKaRZkITfYIxsxrY5oQsXsI lvtw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=fgeja5IA7DWdfWMaQJS17wRQUp+VgamC4WOakECeEuY=; b=RLFY/LOS79Pdpl8xRsUyzIx51VVxT1TXfT4SAaMuLl28tTBdl2k3phI1pyLsBXo+ub T/fKE7WPK2HIwclTIA6PMMUvLAdZclnlQ+cTLFHe3+XedkrvxYTHaGthSzNbhAGbw67S fz1HTd+zfHs8MooXFgOqYpAtVfv92oQ1eeTt6rIV+c+nvFKsVuKPXkQxPTPmJ6hSgTQZ NABRrb3fqj6ncXTRi+Km5QJy6G+tK+EEkaUAXNSZSYczblCmmxGoHvwF4bT3CFU/npJ2 4gGLQJ2uZj66qfCwAon778V7ewS1dZIvEnTMiSJK4YIrhjruFQJt0dv249NItGgxYLNn UH/A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ir9tHoG4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id e187-20020a6369c4000000b004b1fef0bf16sm5992850pgc.73.2023.02.23.12.43.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Feb 2023 12:43:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 06/13] accel/tcg: Trigger watchpoints from atomic_mmu_lookup Date: Thu, 23 Feb 2023 10:43:35 -1000 Message-Id: <20230223204342.1093632-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230223204342.1093632-1-richard.henderson@linaro.org> References: <20230223204342.1093632-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Fixes a bug in that we weren't reporting these changes. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- accel/tcg/cputlb.c | 40 +++++++++++++++++++++++++++++----------- 1 file changed, 29 insertions(+), 11 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 74ad8e0876..e0765c8c10 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1908,6 +1908,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, CPUTLBEntry *tlbe; target_ulong tlb_addr; void *hostaddr; + CPUTLBEntryFull *full; tcg_debug_assert(mmu_idx < NB_MMU_MODES); @@ -1947,17 +1948,26 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, tlb_addr = tlb_addr_write(tlbe) & ~TLB_INVALID_MASK; } - /* Let the guest notice RMW on a write-only page. */ - if ((prot & PAGE_READ) && - unlikely(tlbe->addr_read != (tlb_addr & ~TLB_NOTDIRTY))) { - tlb_fill(env_cpu(env), addr, size, - MMU_DATA_LOAD, mmu_idx, retaddr); + if (prot & PAGE_READ) { /* - * Since we don't support reads and writes to different addresses, - * and we do have the proper page loaded for write, this shouldn't - * ever return. But just in case, handle via stop-the-world. + * Let the guest notice RMW on a write-only page. + * We have just verified that the page is writable. + * Subpage lookups may have left TLB_INVALID_MASK set, + * but addr_read will only be -1 if PAGE_READ was unset. */ - goto stop_the_world; + if (unlikely(tlbe->addr_read == -1)) { + tlb_fill(env_cpu(env), addr, size, + MMU_DATA_LOAD, mmu_idx, retaddr); + /* + * Since we don't support reads and writes to different + * addresses, and we do have the proper page loaded for + * write, this shouldn't ever return. But just in case, + * handle via stop-the-world. + */ + goto stop_the_world; + } + /* Collect TLB_WATCHPOINT for read. */ + tlb_addr |= tlbe->addr_read; } } else /* if (prot & PAGE_READ) */ { tlb_addr = tlbe->addr_read; @@ -1981,10 +1991,18 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, } hostaddr = (void *)((uintptr_t)addr + tlbe->addend); + full = &env_tlb(env)->d[mmu_idx].fulltlb[index]; if (unlikely(tlb_addr & TLB_NOTDIRTY)) { - notdirty_write(env_cpu(env), addr, size, - &env_tlb(env)->d[mmu_idx].fulltlb[index], retaddr); + notdirty_write(env_cpu(env), addr, size, full, retaddr); + } + + if (unlikely(tlb_addr & TLB_WATCHPOINT)) { + QEMU_BUILD_BUG_ON(PAGE_READ != BP_MEM_READ); + QEMU_BUILD_BUG_ON(PAGE_WRITE != BP_MEM_WRITE); + /* therefore prot == watchpoint bits */ + cpu_check_watchpoint(env_cpu(env), addr, size, + full->attrs, prot, retaddr); } return hostaddr; From patchwork Thu Feb 23 20:43:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655998 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp539065wrb; Thu, 23 Feb 2023 12:45:15 -0800 (PST) X-Google-Smtp-Source: AK7set8zO1pSYcoy7wH1BBeXB5efVO+qGfdj4GLGmVDR/N5U+wEVuiEjEf1qIhPjX0w7J9C2KEq3 X-Received: by 2002:a05:6214:e42:b0:56b:ec1f:db0d with SMTP id o2-20020a0562140e4200b0056bec1fdb0dmr23697837qvc.34.1677185114943; Thu, 23 Feb 2023 12:45:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677185114; cv=none; d=google.com; s=arc-20160816; b=dzh3hHFNVR56OeYMPjg9hj7UmKjY2j5ixZTSanNIeuA9h4BH01+0RID0370IgBoGCX AvI0tPqqTJvmpnSXpM/zKNTDkTlNPAfzhz3m6zQywrZ7U355Rxob5jlvxkMxzU5h4p8R y7EBRqL2wZsDJcHNvkFNZk7Ia3EPhSI16/pGw11hB+GfL+It1gw7CykyfVjgM8fho/FH 2xnegoeI5Xu4prKIWWkiw9KmLGe+/YqebwPquFB2IJT/UQ4cCArDDNefG0rgyQJ1AqvG A968Y/gVlG0KLBvFZkd56HLEum4wEkjlEP0xKC1+8Uo8tzew4DIgymBp8OXxuwsC4mZT 4JJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=adwGVUESBK0GEWMpzNl1mlsUbwgbVqsJeAYNIU7i/OU=; b=Ym1x14F1Ud9E6FJ58KefR6uqbx4Ah9iLmZ/hZBW0y3+VxpCKgwt/8kcbvbIjzj6Rxx HTkYmMY9IVD+0zXk4DAmi1ltiiwbKwctBz9Aq94OM/JcVVgkDUE7CFBlUqob7izLkp1d O6KO8q7lj8c0Xi/E+b4IfftFh2qAEfn4NHrVLYsPk9ghBBW6OziqEC+QNgD4TOkpm6tE khen7DJNim4IUuhRvuTudygnMTZMqta61U9+rYf3s4z+6vbMpP2zO0U1vI7At8Ub4CMV 6eFiyNR5ND5QofFlXhMq1fMuOuqV3/FHJ2+2gPfwURz7mnu2Y+/4g7qhz2pO/q1p3/rd lQHQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BvWh+Ipm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id e187-20020a6369c4000000b004b1fef0bf16sm5992850pgc.73.2023.02.23.12.43.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Feb 2023 12:43:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 07/13] accel/tcg: Move TLB_WATCHPOINT to TLB_SLOW_FLAGS_MASK Date: Thu, 23 Feb 2023 10:43:36 -1000 Message-Id: <20230223204342.1093632-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230223204342.1093632-1-richard.henderson@linaro.org> References: <20230223204342.1093632-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This frees up one bit of the primary tlb flags without impacting the TLB_NOTDIRTY logic. Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 12 ++++++------ accel/tcg/cputlb.c | 23 ++++++++++++++++------- 2 files changed, 22 insertions(+), 13 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 080cb3112e..f3b2f4229c 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -378,12 +378,10 @@ CPUArchState *cpu_copy(CPUArchState *env); #define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2)) /* Set if TLB entry is an IO callback. */ #define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3)) -/* Set if TLB entry contains a watchpoint. */ -#define TLB_WATCHPOINT (1 << (TARGET_PAGE_BITS_MIN - 4)) +/* Set if TLB entry writes ignored. */ +#define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 4)) /* Set if the slow path must be used; more flags in CPUTLBEntryFull. */ #define TLB_FORCE_SLOW (1 << (TARGET_PAGE_BITS_MIN - 5)) -/* Set if TLB entry writes ignored. */ -#define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 6)) /* * Use this mask to check interception with an alignment mask @@ -391,7 +389,7 @@ CPUArchState *cpu_copy(CPUArchState *env); */ #define TLB_FLAGS_MASK \ (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \ - | TLB_WATCHPOINT | TLB_FORCE_SLOW | TLB_DISCARD_WRITE) + | TLB_FORCE_SLOW | TLB_DISCARD_WRITE) /* * Flags stored in CPUTLBEntryFull.slow_flags[x]. @@ -399,8 +397,10 @@ CPUArchState *cpu_copy(CPUArchState *env); */ /* Set if TLB entry requires byte swap. */ #define TLB_BSWAP (1 << 0) +/* Set if TLB entry contains a watchpoint. */ +#define TLB_WATCHPOINT (1 << 1) -#define TLB_SLOW_FLAGS_MASK TLB_BSWAP +#define TLB_SLOW_FLAGS_MASK (TLB_BSWAP | TLB_WATCHPOINT) /* The two sets of flags must not overlap. */ QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK); diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index e0765c8c10..cc98df9517 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1966,7 +1966,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, */ goto stop_the_world; } - /* Collect TLB_WATCHPOINT for read. */ + /* Collect tlb flags for read. */ tlb_addr |= tlbe->addr_read; } } else /* if (prot & PAGE_READ) */ { @@ -1997,12 +1997,21 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, notdirty_write(env_cpu(env), addr, size, full, retaddr); } - if (unlikely(tlb_addr & TLB_WATCHPOINT)) { - QEMU_BUILD_BUG_ON(PAGE_READ != BP_MEM_READ); - QEMU_BUILD_BUG_ON(PAGE_WRITE != BP_MEM_WRITE); - /* therefore prot == watchpoint bits */ - cpu_check_watchpoint(env_cpu(env), addr, size, - full->attrs, prot, retaddr); + if (unlikely(tlb_addr & TLB_FORCE_SLOW)) { + int wp_flags = 0; + + if ((prot & PAGE_WRITE) && + (full->slow_flags[MMU_DATA_STORE] & TLB_WATCHPOINT)) { + wp_flags |= BP_MEM_WRITE; + } + if ((prot & PAGE_READ) && + (full->slow_flags[MMU_DATA_LOAD] & TLB_WATCHPOINT)) { + wp_flags |= BP_MEM_READ; + } + if (wp_flags) { + cpu_check_watchpoint(env_cpu(env), addr, size, + full->attrs, wp_flags, retaddr); + } } return hostaddr; From patchwork Thu Feb 23 20:43:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 656002 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp539372wrb; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id e187-20020a6369c4000000b004b1fef0bf16sm5992850pgc.73.2023.02.23.12.43.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Feb 2023 12:43:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 08/13] target/arm: Support 32-byte alignment in pow2_align Date: Thu, 23 Feb 2023 10:43:37 -1000 Message-Id: <20230223204342.1093632-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230223204342.1093632-1-richard.henderson@linaro.org> References: <20230223204342.1093632-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Now that we have removed TARGET_PAGE_BITS_MIN-6 from TLB_FLAGS_MASK, we can test for 32-byte alignment. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index c23a3462bf..412fc4aca8 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -940,13 +940,7 @@ static inline void store_reg_from_load(DisasContext *s, int reg, TCGv_i32 var) MemOp pow2_align(unsigned i) { static const MemOp mop_align[] = { - 0, MO_ALIGN_2, MO_ALIGN_4, MO_ALIGN_8, MO_ALIGN_16, - /* - * FIXME: TARGET_PAGE_BITS_MIN affects TLB_FLAGS_MASK such - * that 256-bit alignment (MO_ALIGN_32) cannot be supported: - * see get_alignment_bits(). Enforce only 128-bit alignment for now. - */ - MO_ALIGN_16 + 0, MO_ALIGN_2, MO_ALIGN_4, MO_ALIGN_8, MO_ALIGN_16, MO_ALIGN_32 }; g_assert(i < ARRAY_SIZE(mop_align)); return mop_align[i]; From patchwork Thu Feb 23 20:43:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 656008 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp539913wrb; Thu, 23 Feb 2023 12:47:13 -0800 (PST) X-Google-Smtp-Source: AK7set8/dhmI8/hOwysF//qRGJJlOzxZRiJoKknbruNxAesvtvY9ggv7dEpEOJMKe9sfsPi08Abj X-Received: by 2002:a05:622a:1a24:b0:3bd:7a6:67a2 with SMTP id f36-20020a05622a1a2400b003bd07a667a2mr21264840qtb.27.1677185233111; Thu, 23 Feb 2023 12:47:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677185233; cv=none; d=google.com; s=arc-20160816; b=DBQs1H/FK5IOoSOr+rFo++pRd4PyDCZ2d/HRAyuqPBPVcW4y+pC7VAq2ymfTIcB1hk 9RChfgJHHTt9guiGB7qq6NSuXHSpstDNM1crTul+dNcAgER+c6XC3lcmOg6hG5VueVMo t4/jQBhrGrgogU9EP5Mej51SwRYeUEoo41djSYmrWf+l+xaUmGKzHyZbqpjirEXQUbCM iZQBMAJSp7OETfeBWMcQQ6ak2F+wCs0p0ms6OJwpfC5pGuRUXDxeExp5x/5L6LO7f8bJ BrsHQKVIVjWYh+c+qzTrHhqTtcfoh3SPDqOYC1ZBzwPaIyXjnnwUsHqpOrVz2AJD+a8q OFag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=1DH8GytkPurA9HrZaN37YWqxqd2398SYcw6ExGS87Do=; b=pLUVRLwlRJ3Y8OQs6k/gZWEImXdmFIzZaXQjNYUfQkZFPYyqKUcL7k/6gyPBvYl6Ki 7AKaPRHFemnzr820lwsdhSfh1uzccLfGPJ9TNv4vWu3W9CNR4rzVMYO4Z6yusMw8/NpG 2NkbMua1OqA62aTEWTi5syqbgyekBRq5J0sFWTiecQE+QeP6STbvJOkVJ8fJtcPKOGg0 5vqwGAHh5/MrvGUQjDEM/r4Us8ngoy8EwejBZeFCgg/3nWn5Khsh1dboTjVW65DiV+ZF En3PKKsXcKbQGbpp1LSyPZ0Vo8kWgxKCH3i1jIrbrU4Gf9UR5LalDi/mdrsyhEkH+5GK /zjw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XEAP3hiJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id e187-20020a6369c4000000b004b1fef0bf16sm5992850pgc.73.2023.02.23.12.44.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Feb 2023 12:44:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 09/13] exec/memattrs: Remove target_tlb_bit* Date: Thu, 23 Feb 2023 10:43:38 -1000 Message-Id: <20230223204342.1093632-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230223204342.1093632-1-richard.henderson@linaro.org> References: <20230223204342.1093632-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org These fields are no longer used. Target specific extensions to the page tables should be done with TARGET_PAGE_ENTRY_EXTRA. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- include/exec/memattrs.h | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index 9fb98bc1ef..1bd7b6c5ca 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -47,16 +47,6 @@ typedef struct MemTxAttrs { unsigned int requester_id:16; /* Invert endianness for this page */ unsigned int byte_swap:1; - /* - * The following are target-specific page-table bits. These are not - * related to actual memory transactions at all. However, this structure - * is part of the tlb_fill interface, cached in the cputlb structure, - * and has unused bits. These fields will be read by target-specific - * helpers using env->iotlb[mmu_idx][tlb_index()].attrs.target_tlb_bitN. - */ - unsigned int target_tlb_bit0 : 1; - unsigned int target_tlb_bit1 : 1; - unsigned int target_tlb_bit2 : 1; } MemTxAttrs; /* Bus masters which don't specify any attributes will get this, From patchwork Thu Feb 23 20:43:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 656003 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp539410wrb; Thu, 23 Feb 2023 12:46:09 -0800 (PST) X-Google-Smtp-Source: AK7set8bPei2AhfhzDaN1v5sZs4fLylQm6EwEeoC+terQK40Mv2/2U5ALLvf7zq9CcOB4LQ0Lm+o X-Received: by 2002:a05:622a:174d:b0:3bd:16cf:2f37 with SMTP id l13-20020a05622a174d00b003bd16cf2f37mr23751813qtk.60.1677185169116; Thu, 23 Feb 2023 12:46:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677185169; cv=none; d=google.com; s=arc-20160816; b=Y9/a5caGtHsDfUzXYE7ucEn+lAtgM++22VfiKpWqLUc8L6lV5Hhjr1k7CUUiTw/eH5 jdU9OAU55GjNsAHtV0JDAgy/Isll8tAMt/Sjm+2M9mSwnltY7i/WFcgX8aH/XVC38Qw/ KZUK2MCuMolUIwVNxH778Qv86VPEsPcxVCD/7Zi1wF7pwGi+jAik5XmXkAaQ1ADNDg7q mlVm4Avs02jslQ/kSIKwVO8Y1CSzuTQiwlg4dqjbp3ZwLRQjXMoEdlX5VxOyXR/7KGUy TqqmcZBEYwf1wdAXqrbZy2dux0wTNmlQx+AYwml7gcrwWM86ydhSJIDQt+ueJg8Lm8bi 23aA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=1qnhwX4yflIrdAFP6huqsV3m6ZntpB/Nux3MPFDNhmI=; b=UveJa8JQ/LDWU5TTqwLnwY9ksJYKK7UCjWNlpgJOfnEP6fxFkBPVAyyxi7EvCgxov6 Zrz4s8wmRG08jRq1bBrLbDaOx2wU3z6g0WJmm6ifREnrAYuNaSVQMzwlbmmoKVI5wVJo IjFYXWHFb1l0t1vh2WAju9KLfF4yCQ7H+JjNLEsIKmr9s22RjFaDy/ed6qgsD75jLpGN +6d4otYppQ2mAkESmaJMUzEMPwq+oYoog3OLweZK39qlR11pTTLClHThSzCPjFtAeOmv 2L88b56LdE0uXc+FfkwzvCaXcz/jaa9dtTBicdekS10AN2peUykF1vDQnvYtNel4x3M5 MwTw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="e2+Z/XP3"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id e187-20020a6369c4000000b004b1fef0bf16sm5992850pgc.73.2023.02.23.12.44.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Feb 2023 12:44:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 10/13] accel/tcg: Add tlb_fill_flags to CPUTLBEntryFull Date: Thu, 23 Feb 2023 10:43:39 -1000 Message-Id: <20230223204342.1093632-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230223204342.1093632-1-richard.henderson@linaro.org> References: <20230223204342.1093632-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Allow the target to set tlb flags to apply to all of the comparators. Remove MemTxAttrs.byte_swap, as the bit is not relevant to memory transactions, only the page mapping. Adjust target/sparc to set TLB_BSWAP directly. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- include/exec/cpu-defs.h | 3 +++ include/exec/memattrs.h | 2 -- accel/tcg/cputlb.c | 5 +---- target/sparc/mmu_helper.c | 2 +- 4 files changed, 5 insertions(+), 7 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index ef10c625d4..53743ff3f2 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -170,6 +170,9 @@ typedef struct CPUTLBEntryFull { /* @lg_page_size contains the log2 of the page size. */ uint8_t lg_page_size; + /* Additional tlb flags requested by tlb_fill. */ + uint8_t tlb_fill_flags; + /* * Additional tlb flags for use by the slow path. If non-zero, * the corresponding CPUTLBEntry comparator must have TLB_FORCE_SLOW. diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index 1bd7b6c5ca..5300649c8c 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -45,8 +45,6 @@ typedef struct MemTxAttrs { unsigned int memory:1; /* Requester ID (for MSI for example) */ unsigned int requester_id:16; - /* Invert endianness for this page */ - unsigned int byte_swap:1; } MemTxAttrs; /* Bus masters which don't specify any attributes will get this, diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index cc98df9517..a90688ac30 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1168,14 +1168,11 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, " prot=%x idx=%d\n", vaddr, full->phys_addr, prot, mmu_idx); - read_flags = 0; + read_flags = full->tlb_fill_flags; if (full->lg_page_size < TARGET_PAGE_BITS) { /* Repeat the MMU check and TLB fill on every access. */ read_flags |= TLB_INVALID_MASK; } - if (full->attrs.byte_swap) { - read_flags |= TLB_BSWAP; - } is_ram = memory_region_is_ram(section->mr); is_romd = memory_region_is_romd(section->mr); diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index a98dd0abd4..fa58b4dc03 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -580,7 +580,7 @@ static int get_physical_address_data(CPUSPARCState *env, CPUTLBEntryFull *full, int do_fault = 0; if (TTE_IS_IE(env->dtlb[i].tte)) { - full->attrs.byte_swap = true; + full->tlb_fill_flags |= TLB_BSWAP; } /* access ok? */ From patchwork Thu Feb 23 20:43:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655995 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp538888wrb; Thu, 23 Feb 2023 12:44:42 -0800 (PST) X-Google-Smtp-Source: AK7set//lIU6UiSkunkW/9F1HeC/+Epy7XhSiM9Au/8Du8XoYbZBwqt6fbZ35n+sf9uPw5hdh0wZ X-Received: by 2002:ac8:4cd9:0:b0:3b6:93fe:443c with SMTP id l25-20020ac84cd9000000b003b693fe443cmr7507493qtv.32.1677185082295; Thu, 23 Feb 2023 12:44:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677185082; cv=none; d=google.com; s=arc-20160816; b=XYsxCnS3BoBDVeaYoVFsWS8NJ/bm81pWhNk5t/IfYbfrXOZWhqt8NGIoKx4nX60Q7L +lZsfsCrSrhlEqqj0xLE6UsfaHRaBLNNGMkQxgqkQENSyFDd5E0kIRD3jdf7W219Cfwn QfagiHrRrwcZMkWmvdPm/x1CBZJQPHnYkBIPQY8fhHB5vSuwL4A6vdFCitK+d2eMujDR +iOsK6ps1iYm8v/XDNyiq4WlGJveCK77VbMwScgsTuE83kfmcA9TMcGlDbnGtPdHNUvY ck6fLY/Ay82is5RUup45wDZ+PDYITm9s80Y7CCDl75Xd2q8es4oM0Mg7z6nH1pef7Y7P zJnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=yTc8B4JFMt2BP2s8OFGRKyLxOfXJWkbz6vP1/iv9tl8=; b=NAMZHzGBxZRScMf/IXbDZ+l2LDjed7+0m7mj3nVf6d0A2v5VsTxdRpTuf10Df32ZgG QxbJX7QZcG1/Gyuh39z6Pi6AYiTTjVDbpnIVEGc/zB3AHS3DPfmXygpWBEwrB2XJ1l7e q9DCVaWTLA1OelID2h4Z0wZiwDOozOYnFgLs2iKbzdJdGCc1v0kl5BIo+h4ug70kv9Rw 0YrGJCXjUZZWESR9Jywxm3UVUsoCJs+8guWgeUqlmJF1GGyI4mr+57OjlbDwWIAVQz4Z Ey9EiUik5zfbFH2pa5rL2N6r1yw9RqDj8UFBfCnTMwS4nD0O9bohNN7T/0q0jvwe681L EzUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KtMMPbbn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id e187-20020a6369c4000000b004b1fef0bf16sm5992850pgc.73.2023.02.23.12.44.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Feb 2023 12:44:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 11/13] accel/tcg: Add TLB_CHECK_ALIGNED Date: Thu, 23 Feb 2023 10:43:40 -1000 Message-Id: <20230223204342.1093632-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230223204342.1093632-1-richard.henderson@linaro.org> References: <20230223204342.1093632-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This creates a per-page method for checking of alignment. Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 4 +++- accel/tcg/cputlb.c | 25 ++++++++++++++++++++++++- 2 files changed, 27 insertions(+), 2 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index f3b2f4229c..5bb04782ba 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -399,8 +399,10 @@ CPUArchState *cpu_copy(CPUArchState *env); #define TLB_BSWAP (1 << 0) /* Set if TLB entry contains a watchpoint. */ #define TLB_WATCHPOINT (1 << 1) +/* Set if TLB entry requires aligned accesses. */ +#define TLB_CHECK_ALIGNED (1 << 2) -#define TLB_SLOW_FLAGS_MASK (TLB_BSWAP | TLB_WATCHPOINT) +#define TLB_SLOW_FLAGS_MASK (TLB_BSWAP | TLB_WATCHPOINT | TLB_CHECK_ALIGNED) /* The two sets of flags must not overlap. */ QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK); diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index a90688ac30..c692e71766 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1546,7 +1546,7 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr, flags |= full->slow_flags[access_type]; /* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */ - if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY))) { + if (flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY | TLB_CHECK_ALIGNED)) { *phost = NULL; return TLB_MMIO; } @@ -1885,6 +1885,29 @@ static bool mmu_lookup(CPUArchState *env, target_ulong addr, MemOpIdx oi, tcg_debug_assert((flags & TLB_BSWAP) == 0); } + /* + * This alignment check differs from the one above, in that this is + * based on the atomicity of the operation. The intended use case is + * the ARM memory type field of each PTE, where access to pages with + * Device memory type require alignment. + */ + if (unlikely(flags & TLB_CHECK_ALIGNED)) { + MemOp atmax = l->memop & MO_ATMAX_MASK; + MemOp atom = l->memop & MO_ATOM_MASK; + MemOp size = l->memop & MO_SIZE; + + if (size != MO_8 && atom != MO_ATOM_NONE) { + if (atmax == MO_ATMAX_SIZE) { + a_bits = size; + } else { + a_bits = atmax >> MO_ATMAX_SHIFT; + } + if (addr & ((1 << a_bits) - 1)) { + cpu_unaligned_access(env_cpu(env), addr, type, l->mmu_idx, ra); + } + } + } + return crosspage; } From patchwork Thu Feb 23 20:43:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655997 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp538915wrb; Thu, 23 Feb 2023 12:44:47 -0800 (PST) X-Google-Smtp-Source: AK7set8SGQAqHj+8/OPXgDPA7Sg+zQPQ4N5BnntEvBy8NGWn0JiRXkV7Rricu13TT4vxapHev+yQ X-Received: by 2002:a05:622a:15d2:b0:3b8:2c34:b9f2 with SMTP id d18-20020a05622a15d200b003b82c34b9f2mr23869161qty.63.1677185087226; Thu, 23 Feb 2023 12:44:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677185087; cv=none; d=google.com; s=arc-20160816; b=InmEDId5/wUZRdJXsBWscTwraSBZBS0gozQytbzd8QndC8QfAtr1jvqPLcLbJkoiFv tSu7DtUr1Id3jaJVz/aJCq61vnzsjZSkwCcc6cznmaj8fCfFhc7qWiLrHn8hl6B9hHeO 2x0FaBprDbx+MsQ7o9O2fbI6PlVB+43uYLaaGHQq4KhCdw/2Q7uuOU0Gz20oib/tMIwu WqtNrTE9ClLnkdZLpA5ztKRulvLaMeXzt1kVsnsguxmuasR+l5Ol8A2XqmQfq9h6V59h O79yMfubZONS8nl23Tide8D77SuGoYeiNA9rRoaMmmNihvy7mqR9jKZjbxjJJmnNGIVC 9MhQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=4VpqcMOXVlrjqv2u2QyFnc/vNdrKfYNKBg4oxbaB+0Q=; b=UWi5Q8QbvU3WluBuHHzgo/hrj2ZTJWidNItOcxxrbRpnaXO+UsodE93TAEL8dKMCO4 U5wQpk7ICTG/TS1Q7GwvRRwRrVW6Bh9QGwcx5uSnmYAJMJxgfHM76aCDj1dk9R0mkiOz AIlstCkcrCW8QN1QqW0wvQfPXEVKQ0ZzBykY3MHA12nIQl8V8Bx0Ipe14H51VYTSSFp8 3uuhRgAy6ps7mk97w7GML+HYRi+ApWJgqRUxCSw0p1wjfROJ+eu1u3qjbm2BoPUlz3Uj JYgqprrI7o+MupdbTqyjz0DdR/qc4ukZf2bb+KTQxt/eyIOPGyWdEEb01FhrX7bJQRac GHuQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="AeF+e/q1"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id e187-20020a6369c4000000b004b1fef0bf16sm5992850pgc.73.2023.02.23.12.44.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Feb 2023 12:44:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Idan Horowitz Subject: [PATCH 12/13] target/arm: Do memory type alignment check when translation disabled Date: Thu, 23 Feb 2023 10:43:41 -1000 Message-Id: <20230223204342.1093632-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230223204342.1093632-1-richard.henderson@linaro.org> References: <20230223204342.1093632-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::644; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x644.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org If translation is disabled, the default memory type is Device, which requires alignment checking. This is more optimially done early via the MemOp given to the TCG memory operation. Reported-by: Idan Horowitz Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1204 Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/arm/helper.c | 36 ++++++++++++++++++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 07d4100365..b1b664e0ad 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11867,6 +11867,37 @@ static inline bool fgt_svc(CPUARMState *env, int el) FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL1); } +/* + * Return true if memory alignment should be enforced. + */ +static bool aprofile_require_alignment(CPUARMState *env, int el, uint64_t sctlr) +{ +#ifdef CONFIG_USER_ONLY + return false; +#else + /* Check the alignment enable bit. */ + if (sctlr & SCTLR_A) { + return true; + } + + /* + * If translation is disabled, then the default memory type is + * Device(-nGnRnE) instead of Normal, which requires that alignment + * be enforced. Since this affects all ram, it is most efficient + * to handle this during translation. + */ + if (sctlr & SCTLR_M) { + /* Translation enabled: memory type in PTE via MAIR_ELx. */ + return false; + } + if (el < 2 && (arm_hcr_el2_eff(env) & (HCR_DC | HCR_VM))) { + /* Stage 2 translation enabled: memory type in PTE. */ + return false; + } + return true; +#endif +} + static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx, CPUARMTBFlags flags) @@ -11936,8 +11967,9 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, { CPUARMTBFlags flags = {}; int el = arm_current_el(env); + uint64_t sctlr = arm_sctlr(env, el); - if (arm_sctlr(env, el) & SCTLR_A) { + if (aprofile_require_alignment(env, el, sctlr)) { DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); } @@ -12037,7 +12069,7 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, sctlr = regime_sctlr(env, stage1); - if (sctlr & SCTLR_A) { + if (aprofile_require_alignment(env, el, sctlr)) { DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); } From patchwork Thu Feb 23 20:43:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 656001 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp539324wrb; Thu, 23 Feb 2023 12:45:56 -0800 (PST) X-Google-Smtp-Source: AK7set99wI/8kAzQQ1pjwAN7dFawaGAJUMQ6T8mJ9qruipVLUAWU2CbbdCWULxlNyUoj9D+I1XCa X-Received: by 2002:a05:622a:514:b0:3b9:2c3:675a with SMTP id l20-20020a05622a051400b003b902c3675amr8724389qtx.62.1677185155752; Thu, 23 Feb 2023 12:45:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677185155; cv=none; d=google.com; s=arc-20160816; b=Mi3Sl0BVNONBPudDl+F4l5zhNx0IlgXgpD8ryxFKymSdtoVXyCB+PFsJMix6nxAqAX +qmYM06A3BZvNbe/zrZOtYYFdc4StSkLQADYJVczBOAe2splQKooXbZK+OqYN4pABkDN +CQLjNscNiFTtUEgO7ND/vjI4WHQyu3YXale/30eLClmB9cWnJV0PqckHCRsEnUwQNjW P5MR5y/1h9yhE1E4C8Mqm+jaf/4VkOI6vnAEbfUDD0DGli70WUjzkKsoa3w68tLKyIky 23LmY27olxT86dQgKTg+POXn7KJSyQ/iSUQ9Wch+EHigNzZxgvXu552ZVjL25HLFTwGY opNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=1DYpXgLa7aKwNkf25RMtvRP9iUFACK26xYqqO1SJ46k=; b=mteyLbHxoRnwKujjmjv9padKObd1cc79Ew1S/USpwS2Vc9lZrR7nEJEsso2nRQ8oXp trG7NoMCWFz/s7UoXNxXcdohpRP2ynHydIqlDqrV3gMEbuRq6HZODKFeUI4fxUrXEVMv u/Q7iny8o9gLVBA4rsBITnwxhrpLd2LinxIHLzCPC2TgGIf1Gwj3BMLij+/ecieaEtRD eWTYAN6JwqeaGIKRR1JhZ0JAR9oM4q9YSMxp59J+pgOnb+ncUYAqTrsxLKOMDqlBc7d4 IB2c820GsSWM4fywQwGwaGzDiGPmb+g2ZNV9aJqYpIBWb1ymHReybajgXtCZoy0sgPrO obwg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=J9edVt+D; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id e187-20020a6369c4000000b004b1fef0bf16sm5992850pgc.73.2023.02.23.12.44.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Feb 2023 12:44:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 13/13] target/arm: Do memory type alignment check when translation enabled Date: Thu, 23 Feb 2023 10:43:42 -1000 Message-Id: <20230223204342.1093632-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230223204342.1093632-1-richard.henderson@linaro.org> References: <20230223204342.1093632-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::642; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x642.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org If translation is enabled, and the PTE memory type is Device, enable checking alignment via TLB_CHECK_ALIGNMENT. While the check is done later than it should be per the ARM, it's better than not performing the check at all. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 2b125fff44..19afeb9135 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -194,6 +194,16 @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx, return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0; } +static bool S1_attrs_are_device(uint8_t attrs) +{ + /* + * This slightly under-decodes the MAIR_ELx field: + * 0b0000dd01 is Device with FEAT_XS, otherwise UNPREDICTABLE; + * 0b0000dd1x is UNPREDICTABLE. + */ + return (attrs & 0xf0) == 0; +} + static bool S2_attrs_are_device(uint64_t hcr, uint8_t attrs) { /* @@ -1188,6 +1198,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, bool aarch64 = arm_el_is_aa64(env, el); uint64_t descriptor, new_descriptor; bool nstable; + bool device; /* TODO: This code does not support shareability levels. */ if (aarch64) { @@ -1568,6 +1579,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, if (regime_is_stage2(mmu_idx)) { result->cacheattrs.is_s2_format = true; result->cacheattrs.attrs = extract32(attrs, 2, 4); + device = S2_attrs_are_device(arm_hcr_el2_eff_secstate(env, is_secure), + result->cacheattrs.attrs); } else { /* Index into MAIR registers for cache attributes */ uint8_t attrindx = extract32(attrs, 2, 3); @@ -1575,6 +1588,21 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, assert(attrindx <= 7); result->cacheattrs.is_s2_format = false; result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8); + device = S1_attrs_are_device(result->cacheattrs.attrs); + } + + /* + * Enable alignment checks on Device memory. + * + * Per R_XCHFJ, this check is mis-ordered, in that this alignment check + * should have priority 30, while the permission check should be next at + * priority 31 and stage2 translation faults come after that. + * Due to the way the TCG softmmu TLB operates, we will have implicitly + * done the permission check and the stage2 lookup in finding the TLB + * entry, so the alignment check cannot be done sooner. + */ + if (device) { + result->f.tlb_fill_flags |= TLB_CHECK_ALIGNED; } /*