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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.33.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:33:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 01/25] target/arm: Handle m-profile in arm_is_secure Date: Tue, 21 Feb 2023 16:33:12 -1000 Message-Id: <20230222023336.915045-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 12b1082537..7a2f804aeb 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2426,6 +2426,9 @@ static inline bool arm_is_el3_or_mon(CPUARMState *env) /* Return true if the processor is in secure state */ static inline bool arm_is_secure(CPUARMState *env) { + if (arm_feature(env, ARM_FEATURE_M)) { + return env->v7m.secure; + } if (arm_is_el3_or_mon(env)) { return true; } From patchwork Wed Feb 22 02:33:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655657 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp455800wrb; Tue, 21 Feb 2023 18:34:33 -0800 (PST) X-Google-Smtp-Source: AK7set+t7Zc+bjHMjQQT7ZjJ/CKvtnkAaltyefR7iYDU2p1+YHcDr30bQYk3pF+YEIIg5FGSkW39 X-Received: by 2002:a05:622a:1009:b0:3b9:bc8c:c1ff with SMTP id d9-20020a05622a100900b003b9bc8cc1ffmr11259883qte.10.1677033273729; Tue, 21 Feb 2023 18:34:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677033273; cv=none; d=google.com; s=arc-20160816; b=N1grAQZQEGGh9cxjs8UoFlGiwNoLX1qWp606T/Ai9B/uHecwdwYJ0uM4DtCUdeUija fqf0wu7mwtS6afWiy37eWCdobMTjMASuRM4/hJVLkzXc8Bd/DB0+QTIyEs1mE310Cg3x z0LSDwx3xLehflGwTf0hq6qar2Mss0p0Bza369N4DgPnbzoELuyFjshAvCxblTwZVVUz jmtxPRAlveqjTr6hI7nlSFKY9FctL3/lt2NUkkkT4n4yEuNbJ6373OO9UwhUQ7OLJuwy cagA+xvo4N9wHU+PfDr9zy2j/5roxRA+cMw7YB4pi1G8mmzydv9PnBf7rnpTFMBzsLaM 1cnQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=LyJ1TFoD8DKR6NPPurEInLjBprHxsrJkr+brbjdIpWE=; b=Tnid5PQafcU3nxFU2llRLTHbLSfkqjIxPNjy2yvEY1xbI4vnh0L2Ruw9M62euq2/DN F3GAvIROQyYch92xxSBv86x+uu+X38rh4TQq2pM0Tv6eCHcSF7sZCPoWK2O/Gu2NHjjI 9HbjJG5NFjQWNRP50HL0qgRpuDfFPsgs644mNyarAqGM413+8dMldN9ilp2WCDZ8HrAG P3/cdM3oJ6khOyQpK9m2FWUcSCESU28FtUluu96TuZ2PrFL9amA2hhA24ofaGN4CFVOH qiQwBkZmXzMf60R4ypHmmnMe2N97tyl7ct3mKjU74+R1qjHssps+3HbNH3kHChUqgjvf dWtw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KoYka+m3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.33.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:33:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 02/25] target/arm: Stub arm_hcr_el2_eff for m-profile Date: Tue, 21 Feb 2023 16:33:13 -1000 Message-Id: <20230222023336.915045-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org M-profile doesn't have HCR_EL2. While we could test features before each call, zero is a generally safe return value to disable the code in the caller. This test is required to avoid an assert in arm_is_secure_below_el3. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 07d4100365..37d9267fb4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5788,6 +5788,9 @@ uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure) uint64_t arm_hcr_el2_eff(CPUARMState *env) { + if (arm_feature(env, ARM_FEATURE_M)) { + return 0; + } return arm_hcr_el2_eff_secstate(env, arm_is_secure_below_el3(env)); } From patchwork Wed Feb 22 02:33:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655659 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp455799wrb; Tue, 21 Feb 2023 18:34:33 -0800 (PST) X-Google-Smtp-Source: AK7set/1tbbQhq9QD0B4uely0BE5RjXyFRpFzKfg6z90XRqgw/5FZ+ZShgS1GMNwO2NT0cEchHAT X-Received: by 2002:a05:622a:15d2:b0:3b8:2c34:b9f2 with SMTP id d18-20020a05622a15d200b003b82c34b9f2mr11525940qty.63.1677033273668; Tue, 21 Feb 2023 18:34:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677033273; cv=none; d=google.com; s=arc-20160816; b=RoKnXuFIUZRSBnwK1AI5mXJ14GiAf6X+hsw1oB/C7B/lC5OpNEiMvW5O9te2RnTlaI pxPco8EdgjZATdescxaXcmFkh7h46uY2sd9NAColm7Y1XNykbrhUKq76RLU7C1ea7VmU cTokTYBkia1gvaqYhgIGM3UIyjA8i6WKC5Unczt9TjRlBJ4nK2t77V7S9ToCzpAYLPAl /A4DLsHb4c9qEyjNxDtOv3uupY7z5Qt6d6EJw65g+PrfR6jZQ5g/cFUYBWGyik3u1xto 3J7yTeLyjLHKDfLnlHemDU5KjUfRa8m4BuY9Cu09d50Kr9YNhO8pniACl9OBnuF/05nQ abzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=t0f34z6IL5G95kj5EqfJsxy6GdEQaM54Gjt8GKtIdDA=; b=FRaUdJ/PTLNHemNwodPxUScMBDz+h49xuGjeJv9XAoA40OXM5L8ctPd4ItRKIWxT9Y sh5iA2UFpxNoCm9qJeBs/vSLuojk2cGk862jmPHxxt8F4KqnlM0QLwo/XTDqVhty58yJ lOGaLdMIZuRwAbrzn4UiN7tYRjDXbmN4UIASTsPy8Mie/KLiunQJ3/YjPKKjyEkeVFNQ HQkHst5GTh2Ay7ycxDVto+5XlPivrA95tgfl8FPLg5TlZoGEq+nbTLgRDgNc4soS0XPr Jjr27qowq5wRla7HXzKLIr66qK8+i61mCW7nsJ0rnnvOQzUPDpseX8E+0em1O9nY8bEW V5ZQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AuC22R+l; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.33.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:33:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 03/25] target/arm: Diagnose incorrect usage of arm_is_secure subroutines Date: Tue, 21 Feb 2023 16:33:14 -1000 Message-Id: <20230222023336.915045-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In several places we use arm_is_secure_below_el3 and arm_is_el3_or_mon separately from arm_is_secure. These functions make no sense for m-profile, and would indicate prior incorrect feature testing. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell --- target/arm/cpu.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7a2f804aeb..cb4e405f04 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2389,7 +2389,8 @@ static inline int arm_feature(CPUARMState *env, int feature) void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); #if !defined(CONFIG_USER_ONLY) -/* Return true if exception levels below EL3 are in secure state, +/* + * Return true if exception levels below EL3 are in secure state, * or would be following an exception return to that level. * Unlike arm_is_secure() (which is always a question about the * _current_ state of the CPU) this doesn't care about the current @@ -2397,6 +2398,7 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); */ static inline bool arm_is_secure_below_el3(CPUARMState *env) { + assert(!arm_feature(env, ARM_FEATURE_M)); if (arm_feature(env, ARM_FEATURE_EL3)) { return !(env->cp15.scr_el3 & SCR_NS); } else { @@ -2410,6 +2412,7 @@ static inline bool arm_is_secure_below_el3(CPUARMState *env) /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ static inline bool arm_is_el3_or_mon(CPUARMState *env) { + assert(!arm_feature(env, ARM_FEATURE_M)); if (arm_feature(env, ARM_FEATURE_EL3)) { if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { /* CPU currently in AArch64 state and EL3 */ From patchwork Wed Feb 22 02:33:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655679 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp457143wrb; Tue, 21 Feb 2023 18:38:53 -0800 (PST) X-Google-Smtp-Source: AK7set9wiS176UFfMM4BeCbTdYbTSLdwYXwHvZ4lotUNSp8HIl0nKEFa1yP4w1UFA8SgV0kpDbis X-Received: by 2002:ad4:5aec:0:b0:56e:a791:37c6 with SMTP id c12-20020ad45aec000000b0056ea79137c6mr12270767qvh.16.1677033533020; Tue, 21 Feb 2023 18:38:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677033533; cv=none; d=google.com; s=arc-20160816; b=nwduwXYAezscK3LCx+BT3S6rAUrC5td+7UXa02qwECvLlMdQeY4oSCuKN+y1FEVTp6 uU8lp+YpzwykM7Oy4tH1FgjsAGnfi03k/MAyNKQDqF0Fv3/jN6ZeSly2SgmNmkyBiZgx GG4iBMdeFZRG0k0gzdnicyur4QD+ojkZXZ1walg5CNwBULoCauni+aTL0qlB9f6JX+6l 7FfMknotAodmL0cmRlalp+onqaqhxZgaFavkgkROggxLgeaE8a+GHpkUmNzy4tZPEKXp N1nYZcm0WBVB57/QkU3oOI94uhAFDk6Rwps59bgDAw6YdfkaFVqnMy3Hm0x7czMlLRyP PRiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Hddjs2iU8lgJmQnwAvhIIZw97YOfc6Ski+WodJ2W4+A=; b=yx5ibcdp5lnMMTscNHjwZTU6DqkPmUzWwf9nIbyrIg4LrB04bynWpNO8o32QE0ynuL C/6yVlsyqLBRA36UAD3oQN8H39QwVNHiAtCX+hyXpCo/SgK2psIBruvxoXmR7m1TdA5E McS6R9bV4ctkNCzlpUOnammpv6hEX4K8b09T88H688pAMlJhkwfmP1Qt2e2jv/eJ+GMF UVm1GZyrUhSeU1VZrUn017ED8p3m7zTu6VFmcHV9tXz6NzooWleZ3u5PZ3Aun7qh5TnM fZJ1Ch2Dt6QIFDgocqY2TtUSgUlyqGCqs5HYcIuZ1VlhOpwDuQ4zblXdl28bXS+2+2Tg S//w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SROkWP7x; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.33.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:33:44 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 04/25] target/arm: Rewrite check_s2_mmu_setup Date: Tue, 21 Feb 2023 16:33:15 -1000 Message-Id: <20230222023336.915045-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::643; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x643.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Integrate neighboring code from get_phys_addr_lpae which computed starting level, as it is easier to validate when doing both at the same time. Mirror the checks at the start of AArch{64,32}.S2Walk, especially S2InvalidSL and S2InconsistentSL. This reverts 49ba115bb74, which was incorrect -- there is nothing in the ARM pseudocode that depends on TxSZ, i.e. outputsize; the pseudocode is consistent in referencing PAMax. Fixes: 49ba115bb74 ("target/arm: Pass outputsize down to check_s2_mmu_setup") Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 173 ++++++++++++++++++++++++++--------------------- 1 file changed, 97 insertions(+), 76 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 2b125fff44..6fb72fb086 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1077,70 +1077,119 @@ static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, * check_s2_mmu_setup * @cpu: ARMCPU * @is_aa64: True if the translation regime is in AArch64 state - * @startlevel: Suggested starting level - * @inputsize: Bitsize of IPAs + * @tcr: VTCR_EL2 or VSTCR_EL2 + * @ds: Effective value of TCR.DS. + * @iasize: Bitsize of IPAs * @stride: Page-table stride (See the ARM ARM) * - * Returns true if the suggested S2 translation parameters are OK and - * false otherwise. + * Decode the starting level of the S2 lookup, returning INT_MIN if + * the configuration is invalid. */ -static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, - int inputsize, int stride, int outputsize) +static int check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, uint64_t tcr, + bool ds, int iasize, int stride) { - const int grainsize = stride + 3; - int startsizecheck; - - /* - * Negative levels are usually not allowed... - * Except for FEAT_LPA2, 4k page table, 52-bit address space, which - * begins with level -1. Note that previous feature tests will have - * eliminated this combination if it is not enabled. - */ - if (level < (inputsize == 52 && stride == 9 ? -1 : 0)) { - return false; - } - - startsizecheck = inputsize - ((3 - level) * stride + grainsize); - if (startsizecheck < 1 || startsizecheck > stride + 4) { - return false; - } + int sl0, sl2, startlevel, granulebits, levels; + int s1_min_iasize, s1_max_iasize; + sl0 = extract32(tcr, 6, 2); if (is_aa64) { + /* + * AArch64.S2InvalidTxSZ: While we checked tsz_oob near the top of + * get_phys_addr_lpae, that used aa64_va_parameters which apply + * to aarch64. If Stage1 is aarch32, the min_txsz is larger. + * See AArch64.S2MinTxSZ, where min_tsz is 24, translated to + * inputsize is 64 - 24 = 40. + */ + if (iasize < 40 && !arm_el_is_aa64(&cpu->env, 1)) { + goto fail; + } + + /* + * AArch64.S2InvalidSL: Interpretation of SL depends on the page size, + * so interleave AArch64.S2StartLevel. + */ switch (stride) { - case 13: /* 64KB Pages. */ - if (level == 0 || (level == 1 && outputsize <= 42)) { - return false; + case 9: /* 4KB */ + /* SL2 is RES0 unless DS=1 & 4KB granule. */ + sl2 = extract64(tcr, 33, 1); + if (ds && sl2) { + if (sl0 != 0) { + goto fail; + } + startlevel = -1; + } else { + startlevel = 2 - sl0; + switch (sl0) { + case 2: + if (arm_pamax(cpu) < 44) { + goto fail; + } + break; + case 3: + if (!cpu_isar_feature(aa64_st, cpu)) { + goto fail; + } + startlevel = 3; + break; + } } break; - case 11: /* 16KB Pages. */ - if (level == 0 || (level == 1 && outputsize <= 40)) { - return false; + case 11: /* 16KB */ + switch (sl0) { + case 2: + if (arm_pamax(cpu) < 42) { + goto fail; + } + break; + case 3: + if (!ds) { + goto fail; + } + break; } + startlevel = 3 - sl0; break; - case 9: /* 4KB Pages. */ - if (level == 0 && outputsize <= 42) { - return false; + case 13: /* 64KB */ + switch (sl0) { + case 2: + if (arm_pamax(cpu) < 44) { + goto fail; + } + break; + case 3: + goto fail; } + startlevel = 3 - sl0; break; default: g_assert_not_reached(); } - - /* Inputsize checks. */ - if (inputsize > outputsize && - (arm_el_is_aa64(&cpu->env, 1) || inputsize > 40)) { - /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */ - return false; - } } else { - /* AArch32 only supports 4KB pages. Assert on that. */ + /* + * Things are simpler for AArch32 EL2, with only 4k pages. + * There is no separate S2InvalidSL function, but AArch32.S2Walk + * begins with walkparms.sl0 in {'1x'}. + */ assert(stride == 9); - - if (level == 0) { - return false; + if (sl0 >= 2) { + goto fail; } + startlevel = 2 - sl0; } - return true; + + /* AArch{64,32}.S2InconsistentSL are functionally equivalent. */ + levels = 3 - startlevel; + granulebits = stride + 3; + + s1_min_iasize = levels * stride + granulebits + 1; + s1_max_iasize = s1_min_iasize + (stride - 1) + 4; + + if (iasize >= s1_min_iasize && iasize <= s1_max_iasize) { + return startlevel; + } + + fail: + return INT_MIN; } /** @@ -1296,38 +1345,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, */ level = 4 - (inputsize - 4) / stride; } else { - /* - * For stage 2 translations the starting level is specified by the - * VTCR_EL2.SL0 field (whose interpretation depends on the page size) - */ - uint32_t sl0 = extract32(tcr, 6, 2); - uint32_t sl2 = extract64(tcr, 33, 1); - int32_t startlevel; - bool ok; - - /* SL2 is RES0 unless DS=1 & 4kb granule. */ - if (param.ds && stride == 9 && sl2) { - if (sl0 != 0) { - level = 0; - goto do_translation_fault; - } - startlevel = -1; - } else if (!aarch64 || stride == 9) { - /* AArch32 or 4KB pages */ - startlevel = 2 - sl0; - - if (cpu_isar_feature(aa64_st, cpu)) { - startlevel &= 3; - } - } else { - /* 16KB or 64KB pages */ - startlevel = 3 - sl0; - } - - /* Check that the starting level is valid. */ - ok = check_s2_mmu_setup(cpu, aarch64, startlevel, - inputsize, stride, outputsize); - if (!ok) { + int startlevel = check_s2_mmu_setup(cpu, aarch64, tcr, param.ds, + inputsize, stride); + if (startlevel == INT_MIN) { + level = 0; goto do_translation_fault; } level = startlevel; From patchwork Wed Feb 22 02:33:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655666 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp456230wrb; Tue, 21 Feb 2023 18:35:54 -0800 (PST) X-Google-Smtp-Source: AK7set/G0i03LTrfYdrq3ILZh6rqUbnh1D4mHCJkO7ItkYGxU4+oYfiI+Js2kttQhHRCORAReUhc X-Received: by 2002:a05:6214:1d29:b0:56f:8ef:693 with SMTP id f9-20020a0562141d2900b0056f08ef0693mr12187665qvd.0.1677033353840; Tue, 21 Feb 2023 18:35:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677033353; cv=none; d=google.com; s=arc-20160816; b=n3SgD4vieEcOhR2QGv4Ma30GtjNeTJIYEK/+7XZuNVfu5klgqoK7G5OL3VkhL2679S aSQAGmBn9USTtJTkAqEyHnxCGe4bntW1zU5xkZonGlFnyg2+9Ky71z6ovE9JivScLze5 SnevQplZDRC5xCzJWH44QKQsFq5pQviwtyUjOk1GI4dvU4kc17p47ROB1Sre3+cZn9Id SlUdpra53NHymlPLdSQUpol6XS5Pwd9Z/gGsQEJU87Z94khSgKeNx6x2NLR0lPV2lrJl EdB5pW63uYCzYskt5a0gb6mSIrknO19X8MqpVHZBUhsB53EvW5ebm0eKne9rU5ZMKEbU gpjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=jhdYZZcA+QihWdoYLAkQ3l5owX/qDX7C/pLuLVYgynI=; b=X1yrc3rNFWF3hQdEgtUdlUsSqtrOLgec7XENO7PSsNqvzUw6F2ydxlp0KMTdwcSzQH i0NkGkTezsctAylImAwTRaz0JIL/Mir8/Ip2RJ9v/oUrLYE4E+fFSpy0iHSiA/WQdC2Z D0P0+ci0e304SONCh8drhvZgoI3sU109m/ONEaCIraPnpPVZXGWPWv22SIP7bWaHmmny Kc/S3nP6tCfdpxKO0m664LlGVhtNRzo7FT2Fsz/QWelvOI3yOcwR/eJfAswxjvu5St2V uSOo7K2mgsDYDvQ6FflkiIAy182XypArF29WFq6Qez5Z6ykqKD6xpUAa9DMoyTREWDbn Eraw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sFuMbbqK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.33.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:33:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 05/25] target/arm: Add isar_feature_aa64_rme Date: Tue, 21 Feb 2023 16:33:16 -1000 Message-Id: <20230222023336.915045-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1041; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1041.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add the missing field for ID_AA64PFR0, and the predicate. Disable it if EL3 is forced off by the board or command-line. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/arm/cpu.h | 6 ++++++ target/arm/cpu.c | 4 ++++ 2 files changed, 10 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cb4e405f04..b046f96e4e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2190,6 +2190,7 @@ FIELD(ID_AA64PFR0, SEL2, 36, 4) FIELD(ID_AA64PFR0, MPAM, 40, 4) FIELD(ID_AA64PFR0, AMU, 44, 4) FIELD(ID_AA64PFR0, DIT, 48, 4) +FIELD(ID_AA64PFR0, RME, 52, 4) FIELD(ID_AA64PFR0, CSV2, 56, 4) FIELD(ID_AA64PFR0, CSV3, 60, 4) @@ -3808,6 +3809,11 @@ static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0; } +static inline bool isar_feature_aa64_rme(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RME) != 0; +} + static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 876ab8f3bf..83685ed247 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1947,6 +1947,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0); cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, EL3, 0); + + /* Disable the realm management extension, which requires EL3. */ + cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, + ID_AA64PFR0, RME, 0); } if (!cpu->has_el2) { From patchwork Wed Feb 22 02:33:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655682 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp457308wrb; Tue, 21 Feb 2023 18:39:21 -0800 (PST) X-Google-Smtp-Source: AK7set9n6FgVaf7mZZg/5dhAcf6BR8xTz/g1zAanIwNiGU2LE/7RheLnMUf+9JXqRdHTMlyjWr1+ X-Received: by 2002:ac8:5c0c:0:b0:3b6:2f3f:2713 with SMTP id i12-20020ac85c0c000000b003b62f3f2713mr12596262qti.25.1677033561228; Tue, 21 Feb 2023 18:39:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677033561; cv=none; d=google.com; s=arc-20160816; b=XqSTew5GL1Qbu6pY6jTnPgcwvH1+5F/HVOOZ9BKYG/nPi9zcazPI2vUTTRemz7Lg3W Bua9KJSNga9EYUkJ9w2tEc5zwYEDocY+kgHH9MKq03GhIeCUqg+UdiGp0hmWg/8JgVyK xvNMiw6GKlR5ZIAAUzxE/bIRq9oJ1iuTjtx1fYAPBTr4+r7idYRBJJ2p5ufhByr49bJz PkHCAi9Gw33URqmvrKz0e5aQLkEpsh2dCHMuktfW/G0qAdecdVcDYVae/fZhddto/6PX HYAFQWSiQh9wMXyOKqE22I0AH9P8sgROi1ij0HG0edBYBK98XUxoHVR2OhqqJ4dWW7bO J7Rg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=KKaBXNzHKh4bdHhJlKN/7Fy/mzP8VfMexwZIdNSvfng=; b=iEhR1bSiGjAAwtJirOWMA0Poi1szQCsobvjux1w13dNivBSOxurWatYGDzXqV3Yt8v ZetV7ngm7kKGelR6QXjk1aPFrle7IMTsrP4Xa/vFYWCSl7gJtbCZL45RjVjj9vhAoZfq wXBw/dfmD74cQv6SZTQm8Ik/qx1j6MoFc1Gd8JAupkWv8arpqqNClyG2a0gGX3vLWse4 qUadcFHgmD/8583Rf47Q6OJXMqwjjSynD1QMvqZy9p4YuGFLwV+LEX2Nge7G4irwKmh+ /p2B+nlxnQ9ljVdcAHN+DRE54aBHbsANhFS0Lk92rmbTFe9wYZQagBbgOMQdEyDuFGyJ 9Viw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yncxQCT4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.33.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:33:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 06/25] target/arm: Update SCR and HCR for RME Date: Tue, 21 Feb 2023 16:33:17 -1000 Message-Id: <20230222023336.915045-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Define the missing SCR and HCR bits, allow SCR_NSE and {SCR,HCR}_GPF to be set, and invalidate TLBs when NSE changes. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 +++-- target/arm/helper.c | 10 ++++++++-- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b046f96e4e..230241cf93 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1650,7 +1650,7 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) #define HCR_TERR (1ULL << 36) #define HCR_TEA (1ULL << 37) #define HCR_MIOCNCE (1ULL << 38) -/* RES0 bit 39 */ +#define HCR_TME (1ULL << 39) #define HCR_APK (1ULL << 40) #define HCR_API (1ULL << 41) #define HCR_NV (1ULL << 42) @@ -1659,7 +1659,7 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) #define HCR_NV2 (1ULL << 45) #define HCR_FWB (1ULL << 46) #define HCR_FIEN (1ULL << 47) -/* RES0 bit 48 */ +#define HCR_GPF (1ULL << 48) #define HCR_TID4 (1ULL << 49) #define HCR_TICAB (1ULL << 50) #define HCR_AMVOFFEN (1ULL << 51) @@ -1724,6 +1724,7 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) #define SCR_TRNDR (1ULL << 40) #define SCR_ENTP2 (1ULL << 41) #define SCR_GPF (1ULL << 48) +#define SCR_NSE (1ULL << 62) #define HSTR_TTEE (1 << 16) #define HSTR_TJDBX (1 << 17) diff --git a/target/arm/helper.c b/target/arm/helper.c index 37d9267fb4..3650234c73 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1875,6 +1875,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) if (cpu_isar_feature(aa64_fgt, cpu)) { valid_mask |= SCR_FGTEN; } + if (cpu_isar_feature(aa64_rme, cpu)) { + valid_mask |= SCR_NSE | SCR_GPF; + } } else { valid_mask &= ~(SCR_RW | SCR_ST); if (cpu_isar_feature(aa32_ras, cpu)) { @@ -1904,10 +1907,10 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) env->cp15.scr_el3 = value; /* - * If SCR_EL3.NS changes, i.e. arm_is_secure_below_el3, then + * If SCR_EL3.{NS,NSE} changes, i.e. change of security state, * we must invalidate all TLBs below EL3. */ - if (changed & SCR_NS) { + if (changed & (SCR_NS | SCR_NSE)) { tlb_flush_by_mmuidx(env_cpu(env), (ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_E20_0 | ARMMMUIdxBit_E10_1 | @@ -5655,6 +5658,9 @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) if (cpu_isar_feature(aa64_fwb, cpu)) { valid_mask |= HCR_FWB; } + if (cpu_isar_feature(aa64_rme, cpu)) { + valid_mask |= HCR_GPF; + } } if (cpu_isar_feature(any_evt, cpu)) { From patchwork Wed Feb 22 02:33:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655665 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp456196wrb; Tue, 21 Feb 2023 18:35:48 -0800 (PST) X-Google-Smtp-Source: AK7set8dSBeOU1AI+Iim79xvflARq5xYCN7TMQ9kvRd+xrxP7Cq49MGtntlqrHDPO2bo5Y7X24QX X-Received: by 2002:a05:6214:d89:b0:56c:21d3:3f9c with SMTP id e9-20020a0562140d8900b0056c21d33f9cmr13884831qve.47.1677033347865; Tue, 21 Feb 2023 18:35:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677033347; cv=none; d=google.com; s=arc-20160816; b=xjcZ+cUwbctvmrGGW/XixEczmDGSIYE/UQKilVorZr+i57EaAsR5FLaZw1Kk9Obec6 o0gf752NzYkOHxF7ASRF2jjYo6xw6j4035XSCXiNA5da1iYF9BickIFsIRkdT3nDUFt/ bUSIgaGrvToShVJcY7a44H4OVdiF3ZefiQcnWm6oaRC1Gz7JWsrIbzWWYn5ZXEs+Ly0h RWbT9uLuI1W4XB3D91fhFKkM2taDSOl5B9nYiQejRQNNy6KG6Q/rlgDKWOKBigu2Ke7q bGKFw0MpmrIxpO9cmQLdjtJnIYeuDSh66/1J7+1oC6DraBL/f+r6NyYUvODDCCo3Jord DHBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=eh6Hd17AKGFWk8yBVtARAQj9lZij9aVa5jyFKRWxRtQ=; b=pRePcGolPDuPTUqyZ2djMIfFogGxxzgFVkhpRR4t09qqnGAkUlEys1/kUdOBEC+MbG gqb9ARgRLaRMRdIcmKZZ2BzJHqCxeTWMI9fzZqImrTZmzThcasM45bS0PyrONCd0SoHe sQKfwB/UgsOxOmN50DSKPQfEuLeLC+TnD1w1eaCFdrksOV+zw/2xbom4EeLJAc0WGMGZ XaFUAUmcakQG1PTM/SXa6Zhbm98KXb9s4qenrrUi6iY6IymGbXYVxXSBU3sQdZ7KXwwX UnhFKxVVJ8LsxFs6wmHEfBkkYJE4mKQOvVmdYZ2bOFqnVuNnWgPmM0s0UBr33O0M7cDC KE6g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TfPmPXGZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.33.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:33:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 07/25] target/arm: SCR_EL3.NS may be RES1 Date: Tue, 21 Feb 2023 16:33:18 -1000 Message-Id: <20230222023336.915045-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org With RME, SEL2 must also be present to support secure state. The NS bit is RES1 if SEL2 is not present. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 3650234c73..ae8b3f6a48 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1856,6 +1856,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) } if (cpu_isar_feature(aa64_sel2, cpu)) { valid_mask |= SCR_EEL2; + } else if (cpu_isar_feature(aa64_rme, cpu)) { + /* With RME and without SEL2, NS is RES1 (R_GSWWH, I_DJJQJ). */ + value |= SCR_NS; } if (cpu_isar_feature(aa64_mte, cpu)) { valid_mask |= SCR_ATA; From patchwork Wed Feb 22 02:33:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655664 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp456007wrb; Tue, 21 Feb 2023 18:35:10 -0800 (PST) X-Google-Smtp-Source: AK7set8XEt3SFhCEPRcnFEg4NLHb1728GcH2blBpbniJU4a4RNZOaoTN6+/SHSvpWxgABR0C7CXO X-Received: by 2002:a05:622a:1356:b0:3b8:4951:57b7 with SMTP id w22-20020a05622a135600b003b8495157b7mr12154637qtk.20.1677033310356; Tue, 21 Feb 2023 18:35:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677033310; cv=none; d=google.com; s=arc-20160816; b=aYNlH9Z8IRw/E+OXA+wmSYv40JzT9XG042EWJKAmla0OGH1apxa6C7OW6jRk11ZuMy VUmitWBe0mBNH1/TLIozkQR4yQap78g2sixyiyj43kTlAU6oM4I2WlR0H2Mq0UQZbXD/ 9iBd7SY+OZ2l3PkxQYmSWlLJJBEiqHFei4Q/1f7T6PgZR80sMXq8hrvwoxt2v0GsMzDG I7dd3Uq7ejjgommri7dVYu0+pqIv3iQxSyxZOa2UjAXXJUKFr2sJ6tjJ0X7U62eyWRoJ dOA3Sn3WckPc98Bk7pwr4g38OuGOw+z1rpf9sPnGIiRZwVDgfm8Kc3KlXgJTaV9tJ1a1 fXGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=BxdGjf2oqnzrJHeRZJSywTpPyzmxqXK2LnQoNrr8F7g=; b=ZBEsg4jrAM2Pfco52xYlE3BMQU2r2A2deOjoYLWxXm6EQgLtw86ex//WeZnH2HZY+Z n5HuFJCfvSjCg5AdnMmWB2l15v0RJayF3aTBmGuei9ITrZ3m3CUJgjkOa3sX6GSSC5Kh L/Ha6OzHqx5CKwNQCsv4IqyxeOTJyuz40DAFm11VwovNYo1v3jlfmCQdgycpwuQZWmAQ M4YHaNnUqPNRAa677zmpkWatzA3WQu94SMtFYjz6S2C5f7UY0L84qCFXPRU1JiFhnOg/ 8jtY6CqmDeS+75IBF9ghN6k2a0w7TZ19dXwl88iSDnOFMKFVtftORWPYff+lqf17wzyc 2BiA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hSFH0qMY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.33.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:33:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 08/25] target/arm: Add RME cpregs Date: Tue, 21 Feb 2023 16:33:19 -1000 Message-Id: <20230222023336.915045-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This includes GPCCR, GPTBR, MFAR, the TLB flush insns PAALL, PAALLOS, RPALOS, RPAOS, and the cache flush insns CIPAPA and CIGDPAPA. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 19 +++++++++++ target/arm/helper.c | 83 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 102 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 230241cf93..8d18d98350 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -541,6 +541,11 @@ typedef struct CPUArchState { uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */ uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */ uint64_t fgt_exec[1]; /* HFGITR */ + + /* RME registers */ + uint64_t gpccr_el3; + uint64_t gptbr_el3; + uint64_t mfar_el3; } cp15; struct { @@ -1043,6 +1048,7 @@ struct ArchCPU { uint64_t reset_cbar; uint32_t reset_auxcr; bool reset_hivecs; + uint8_t reset_l0gptsz; /* * Intermediate values used during property parsing. @@ -2336,6 +2342,19 @@ FIELD(MVFR1, SIMDFMAC, 28, 4) FIELD(MVFR2, SIMDMISC, 0, 4) FIELD(MVFR2, FPMISC, 4, 4) +FIELD(GPCCR, PPS, 0, 3) +FIELD(GPCCR, IRGN, 8, 2) +FIELD(GPCCR, ORGN, 10, 2) +FIELD(GPCCR, SH, 12, 2) +FIELD(GPCCR, PGS, 14, 2) +FIELD(GPCCR, GPC, 16, 1) +FIELD(GPCCR, GPCP, 17, 1) +FIELD(GPCCR, L0GPTSZ, 20, 4) + +FIELD(MFAR, FPA, 12, 40) +FIELD(MFAR, NSE, 62, 1) +FIELD(MFAR, NS, 63, 1) + QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); /* If adding a feature bit which corresponds to a Linux ELF diff --git a/target/arm/helper.c b/target/arm/helper.c index ae8b3f6a48..eff109f83c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6935,6 +6935,83 @@ static const ARMCPRegInfo sme_reginfo[] = { .access = PL2_RW, .accessfn = access_esm, .type = ARM_CP_CONST, .resetvalue = 0 }, }; + +static void tlbi_aa64_paall_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *cs = env_cpu(env); + + tlb_flush(cs); +} + +static void gpccr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* L0GPTSZ is RO; other bits not mentioned are RES0. */ + uint64_t rw_mask = R_GPCCR_PPS_MASK | R_GPCCR_IRGN_MASK | + R_GPCCR_ORGN_MASK | R_GPCCR_SH_MASK | R_GPCCR_PGS_MASK | + R_GPCCR_GPC_MASK | R_GPCCR_GPCP_MASK; + + env->cp15.gpccr_el3 = (value & rw_mask) | (env->cp15.gpccr_el3 & ~rw_mask); +} + +static void gpccr_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + env->cp15.gpccr_el3 = FIELD_DP64(0, GPCCR, L0GPTSZ, + env_archcpu(env)->reset_l0gptsz); +} + +static void tlbi_aa64_paallos_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *cs = env_cpu(env); + + tlb_flush_all_cpus_synced(cs); +} + +static const ARMCPRegInfo rme_reginfo[] = { + { .name = "GPCCR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 1, .opc2 = 6, + .access = PL3_RW, .writefn = gpccr_write, .resetfn = gpccr_reset, + .fieldoffset = offsetof(CPUARMState, cp15.gpccr_el3) }, + { .name = "GPTBR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 1, .opc2 = 4, + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.gptbr_el3) }, + { .name = "MFAR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 5, + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mfar_el3) }, + { .name = "TLBI_PAALL", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 4, + .access = PL3_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_paall_write }, + { .name = "TLBI_PAALLOS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 4, + .access = PL3_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_paallos_write }, + /* + * QEMU does not have a way to invalidate by physical address, thus + * invalidating a range of physical addresses is accomplished by + * flushing all tlb entries in the outer sharable domain, + * just like PAALLOS. + */ + { .name = "TLBI_RPALOS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 4, .opc2 = 7, + .access = PL3_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_paallos_write }, + { .name = "TLBI_RPAOS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 4, .opc2 = 3, + .access = PL3_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_paallos_write }, + { .name = "DC_CIPAPA", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 14, .opc2 = 1, + .access = PL3_W, .type = ARM_CP_NOP }, +}; + +static const ARMCPRegInfo rme_mte_reginfo[] = { + { .name = "DC_CIGDPAPA", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 14, .opc2 = 5, + .access = PL3_W, .type = ARM_CP_NOP }, +}; #endif /* TARGET_AARCH64 */ static void define_pmu_regs(ARMCPU *cpu) @@ -9126,6 +9203,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_tlbios, cpu)) { define_arm_cp_regs(cpu, tlbios_reginfo); } + if (cpu_isar_feature(aa64_rme, cpu)) { + define_arm_cp_regs(cpu, rme_reginfo); + if (cpu_isar_feature(aa64_mte, cpu)) { + define_arm_cp_regs(cpu, rme_mte_reginfo); + } + } #ifndef CONFIG_USER_ONLY /* Data Cache clean instructions up to PoP */ if (cpu_isar_feature(aa64_dcpop, cpu)) { From patchwork Wed Feb 22 02:33:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655678 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp457056wrb; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.33.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:33:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 09/25] target/arm: Introduce ARMSecuritySpace Date: Tue, 21 Feb 2023 16:33:20 -1000 Message-Id: <20230222023336.915045-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Introduce both the enumeration and functions to retrieve the current state, and state outside of EL3. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 89 ++++++++++++++++++++++++++++++++++----------- target/arm/helper.c | 60 ++++++++++++++++++++++++++++++ 2 files changed, 127 insertions(+), 22 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8d18d98350..203a3e0046 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2409,25 +2409,53 @@ static inline int arm_feature(CPUARMState *env, int feature) void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); -#if !defined(CONFIG_USER_ONLY) /* + * ARM v9 security states. + * The ordering of the enumeration corresponds to the low 2 bits + * of the GPI value, and (except for Root) the concat of NSE:NS. + */ + +typedef enum ARMSecuritySpace { + ARMSS_Secure = 0, + ARMSS_NonSecure = 1, + ARMSS_Root = 2, + ARMSS_Realm = 3, +} ARMSecuritySpace; + +/* Return true if @space is secure, in the pre-v9 sense. */ +static inline bool arm_space_is_secure(ARMSecuritySpace space) +{ + return space == ARMSS_Secure || space == ARMSS_Root; +} + +/* Return the ARMSecuritySpace for @secure, assuming !RME or EL[0-2]. */ +static inline ARMSecuritySpace arm_secure_to_space(bool secure) +{ + return secure ? ARMSS_Secure : ARMSS_NonSecure; +} + +#if !defined(CONFIG_USER_ONLY) +/** + * arm_security_space_below_el3: + * @env: cpu context + * + * Return the security space of exception levels below EL3, following + * an exception return to those levels. Unlike arm_security_space, + * this doesn't care about the current EL. + */ +ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env); + +/** + * arm_is_secure_below_el3: + * @env: cpu context + * * Return true if exception levels below EL3 are in secure state, - * or would be following an exception return to that level. - * Unlike arm_is_secure() (which is always a question about the - * _current_ state of the CPU) this doesn't care about the current - * EL or mode. + * or would be following an exception return to those levels. */ static inline bool arm_is_secure_below_el3(CPUARMState *env) { - assert(!arm_feature(env, ARM_FEATURE_M)); - if (arm_feature(env, ARM_FEATURE_EL3)) { - return !(env->cp15.scr_el3 & SCR_NS); - } else { - /* If EL3 is not supported then the secure state is implementation - * defined, in which case QEMU defaults to non-secure. - */ - return false; - } + ARMSecuritySpace ss = arm_security_space_below_el3(env); + return ss == ARMSS_Secure; } /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ @@ -2447,16 +2475,23 @@ static inline bool arm_is_el3_or_mon(CPUARMState *env) return false; } -/* Return true if the processor is in secure state */ +/** + * arm_security_space: + * @env: cpu context + * + * Return the current security space of the cpu. + */ +ARMSecuritySpace arm_security_space(CPUARMState *env); + +/** + * arm_is_secure: + * @env: cpu context + * + * Return true if the processor is in secure state. + */ static inline bool arm_is_secure(CPUARMState *env) { - if (arm_feature(env, ARM_FEATURE_M)) { - return env->v7m.secure; - } - if (arm_is_el3_or_mon(env)) { - return true; - } - return arm_is_secure_below_el3(env); + return arm_space_is_secure(arm_security_space(env)); } /* @@ -2475,11 +2510,21 @@ static inline bool arm_is_el2_enabled(CPUARMState *env) } #else +static inline ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env) +{ + return ARMSS_NonSecure; +} + static inline bool arm_is_secure_below_el3(CPUARMState *env) { return false; } +static inline ARMSecuritySpace arm_security_space(CPUARMState *env) +{ + return ARMSS_NonSecure; +} + static inline bool arm_is_secure(CPUARMState *env) { return false; diff --git a/target/arm/helper.c b/target/arm/helper.c index eff109f83c..9e1c1ed6d8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12538,3 +12538,63 @@ void aarch64_sve_change_el(CPUARMState *env, int old_el, } } #endif + +#ifndef CONFIG_USER_ONLY +ARMSecuritySpace arm_security_space(CPUARMState *env) +{ + if (arm_feature(env, ARM_FEATURE_M)) { + return arm_secure_to_space(env->v7m.secure); + } + + /* + * If EL3 is not supported then the secure state is implementation + * defined, in which case QEMU defaults to non-secure. + */ + if (!arm_feature(env, ARM_FEATURE_EL3)) { + return ARMSS_NonSecure; + } + + /* Check for AArch64 EL3 or AArch32 Mon. */ + if (is_a64(env)) { + if (extract32(env->pstate, 2, 2) == 3) { + if (cpu_isar_feature(aa64_rme, env_archcpu(env))) { + return ARMSS_Root; + } else { + return ARMSS_Secure; + } + } + } else { + if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { + return ARMSS_Secure; + } + } + + return arm_security_space_below_el3(env); +} + +ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env) +{ + assert(!arm_feature(env, ARM_FEATURE_M)); + + /* + * If EL3 is not supported then the secure state is implementation + * defined, in which case QEMU defaults to non-secure. + */ + if (!arm_feature(env, ARM_FEATURE_EL3)) { + return ARMSS_NonSecure; + } + + /* + * Note NSE cannot be set without RME, and NSE & !NS is Reserved. + * Ignoring NSE when !NS retains consistency without having to + * modify other predicates. + */ + if (!(env->cp15.scr_el3 & SCR_NS)) { + return ARMSS_Secure; + } else if (env->cp15.scr_el3 & SCR_NSE) { + return ARMSS_Realm; + } else { + return ARMSS_NonSecure; + } +} +#endif /* !CONFIG_USER_ONLY */ From patchwork Wed Feb 22 02:33:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655680 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp457157wrb; Tue, 21 Feb 2023 18:38:55 -0800 (PST) X-Google-Smtp-Source: AK7set+4e5j9tzdA4xtEpH0ARkZGhP+ahvobgA7rQ5L4Xl3Z4uD0TV64uZW3UJV/uhiy9db0A/Kc X-Received: by 2002:a05:622a:40b:b0:3ba:247a:3fbc with SMTP id n11-20020a05622a040b00b003ba247a3fbcmr26648439qtx.39.1677033535138; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.33.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:33:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 10/25] include/exec/memattrs: Add two bits of space to MemTxAttrs Date: Tue, 21 Feb 2023 16:33:21 -1000 Message-Id: <20230222023336.915045-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We will need 2 bits to represent ARMSecurityState. Do not attempt to replace or widen secure, even though it logically overlaps the new field -- there are uses within e.g. hw/block/pflash_cfi01.c, which don't know anything specific about ARM. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/exec/memattrs.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index 9fb98bc1ef..d04170aa27 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -29,10 +29,17 @@ typedef struct MemTxAttrs { * "didn't specify" if necessary. */ unsigned int unspecified:1; - /* ARM/AMBA: TrustZone Secure access + /* + * ARM/AMBA: TrustZone Secure access * x86: System Management Mode access */ unsigned int secure:1; + /* + * ARM: ArmSecuritySpace. This partially overlaps secure, but it is + * easier to have both fields to assist code that does not understand + * ARMv9 RME, or no specific knowledge of ARM at all (e.g. pflash). + */ + unsigned int space:2; /* Memory access is usermode (unprivileged) */ unsigned int user:1; /* From patchwork Wed Feb 22 02:33:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655660 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp455828wrb; Tue, 21 Feb 2023 18:34:38 -0800 (PST) X-Google-Smtp-Source: AK7set8z9bXeBd0SWC9Gj408JOuhKBJlu1/3TGtW2RPX/Ai70EMDtAMgG93MTSFywbOhyuPKOPM7 X-Received: by 2002:a05:6214:29c8:b0:56f:1b7e:d87f with SMTP id gh8-20020a05621429c800b0056f1b7ed87fmr12972467qvb.34.1677033277736; Tue, 21 Feb 2023 18:34:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677033277; cv=none; d=google.com; s=arc-20160816; b=JHYWi7IFd+V3yL8I9KfPB7dk1zia9J0fKgIuDGK515CqEO2elChYfLdqRW/t5pQi79 2OWKwhaO+oJDX4v+DTp98W7fIG/57oROPq97UOf0TWMQ8jnlIx8pM0kAHY4eBUvlBaQB t9j57D0iMUJ2q8D/LrC78kT8UcstlU4s4naL5xYbvTBJUNIq8oH5e+tGd6vYLYItinFL nZJPO8zVDi64/D6drrh0k0n5o887CcFw8CoDCbwOxS32tVtI2xhLUsgChlrw+B+WTBf1 3mjkueHLkf6pG5D2KTjswFE9yoxvY18i7LJYDhr4Bzs4kWq8CHsbRqSVuO+BwC1PQJlA iLWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=EWyoKLNYT7BI4DSP24uw6KDK1ZUmKKpGpsEn941WxC4=; b=O7HXpJhdB9VVCZpacQM1azV/DFS87k1SGwaL+Ok7fQWBbZwpCHO76gDmQ6hA6rRx6g 7NwykZWfKvhY1nIwnNFkuI6SdpNDoHPqmjJUUFB9KaRTXwdn5XdQG5ipaeXCZ4VRkF2s /d/obaYYkuhUc+CaXXAuB2UMbcLHHXaSfJMOgKRWap/aB+VDE7/8+4kDLbw/XPfwH0qy auV2X/+gIqlP4DC4FikPmn6w9KCi9X6RXMfP51YWT55gQfCMN29RYYikyZKQgKxm9Cu2 ODaGmdX0dyyojlITk8MIy9nCRpuhuTmvvRf2UtQERXMpP2aAigKT9JYDO0ZSPWh/pckL OPPw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=trnRBCr4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.33.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:33:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 11/25] target/arm: Adjust the order of Phys and Stage2 ARMMMUIdx Date: Tue, 21 Feb 2023 16:33:22 -1000 Message-Id: <20230222023336.915045-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org It will be helpful to have ARMMMUIdx_Phys_* to be in the same relative order as ARMSecuritySpace enumerators. This requires the adjustment to the nstable check. While there, check for being in secure state rather than rely on clearing the low bit making no change to non-secure state. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 12 ++++++------ target/arm/ptw.c | 12 +++++------- 2 files changed, 11 insertions(+), 13 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 203a3e0046..c5fc475cf8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2855,18 +2855,18 @@ typedef enum ARMMMUIdx { ARMMMUIdx_E2 = 6 | ARM_MMU_IDX_A, ARMMMUIdx_E3 = 7 | ARM_MMU_IDX_A, - /* TLBs with 1-1 mapping to the physical address spaces. */ - ARMMMUIdx_Phys_NS = 8 | ARM_MMU_IDX_A, - ARMMMUIdx_Phys_S = 9 | ARM_MMU_IDX_A, - /* * Used for second stage of an S12 page table walk, or for descriptor * loads during first stage of an S1 page table walk. Note that both * are in use simultaneously for SecureEL2: the security state for * the S2 ptw is selected by the NS bit from the S1 ptw. */ - ARMMMUIdx_Stage2 = 10 | ARM_MMU_IDX_A, - ARMMMUIdx_Stage2_S = 11 | ARM_MMU_IDX_A, + ARMMMUIdx_Stage2_S = 8 | ARM_MMU_IDX_A, + ARMMMUIdx_Stage2 = 9 | ARM_MMU_IDX_A, + + /* TLBs with 1-1 mapping to the physical address spaces. */ + ARMMMUIdx_Phys_S = 10 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_NS = 11 | ARM_MMU_IDX_A, /* * These are not allocated TLBs and are used only for AT system diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 6fb72fb086..5ed5bb5039 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1410,16 +1410,14 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, descaddr |= (address >> (stride * (4 - level))) & indexmask; descaddr &= ~7ULL; nstable = extract32(tableattrs, 4, 1); - if (nstable) { + if (nstable && ptw->in_secure) { /* * Stage2_S -> Stage2 or Phys_S -> Phys_NS - * Assert that the non-secure idx are even, and relative order. + * Assert the relative order of the secure/non-secure indexes. */ - QEMU_BUILD_BUG_ON((ARMMMUIdx_Phys_NS & 1) != 0); - QEMU_BUILD_BUG_ON((ARMMMUIdx_Stage2 & 1) != 0); - QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS + 1 != ARMMMUIdx_Phys_S); - QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2 + 1 != ARMMMUIdx_Stage2_S); - ptw->in_ptw_idx &= ~1; + QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_S + 1 != ARMMMUIdx_Phys_NS); + QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2_S + 1 != ARMMMUIdx_Stage2); + ptw->in_ptw_idx += 1; ptw->in_secure = false; } if (!S1_ptw_translate(env, ptw, descaddr, fi)) { From patchwork Wed Feb 22 02:33:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655675 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp456919wrb; Tue, 21 Feb 2023 18:38:03 -0800 (PST) X-Google-Smtp-Source: AK7set/dUuhoX8fqVot1itvnp6fjApQsEQAYoPY8x4VhvXpX8vBv4yEHyzF63ATbGK5aW1Jh3ljk X-Received: by 2002:ac8:5cd4:0:b0:3bd:d8f:2d7a with SMTP id s20-20020ac85cd4000000b003bd0d8f2d7amr12665619qta.55.1677033483516; Tue, 21 Feb 2023 18:38:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677033483; cv=none; d=google.com; s=arc-20160816; b=OMqdA0hzTnomjFhcIXtUHUByzKUg+CUdyEmizo+l7TYZ/WJWIbgGg8PUuGBycAHIH+ /asvoejaBdzgTHqU5HtcmzQs/gvFUz1/ABj/yNffXFh7H7IaMwumcFstnWAQKqlVz7VN v9c8eVUaC6v/CVaNGEWBuncJMLH9e9PCqZlbxrx2d1C1PINF3El1QpSUiK4Obj8tesaY PAuRbMLjBmjO/Fl+2TX3bFmYX+D6bIy/E5rKroRD+QpPRctSsZrVd0hkfOBtppK4lUdw hrb1q0VM8mPAlO8HlGcderTHU7XyNuy4UaXEpoUHsNyDbynfF1MfLy9nnw3e4dq299fM eWgw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ManreqguuHsU2H8Z3wJmlF43bUQxuUikBGpUaE6IsMg=; b=XIdLFX1dBNHiT4HxAmUGfacxWDn4qVuBFZ4f21qbPOk8UyxJmGwEGLIYqLEVQP5RKW y5MHfoscJuC7DBM8UxaF9PwvZdnF6zdZtRWzyRVAqUOixmYnjbbvEDYiHMDVebC/aHFa 33dTRW5zkAmbAjY1PcWJI4TmUGjwgZgMOU02VOtw5YC/xuz7b9yXY4cF769GKfW/Lqba uKG5wjW3LEmYez5kDZs/Aq6hv2PcafEb4+pLINs1WN1ZUEM+MYbI00T+nwCsooIblLtD +5hoCC3QrT0zZTXpjwd5IZeuC+QXycaRns1PlUf/HhEHYJmlx2EtQ8i+CAyYCqgWDzeU i+Bw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AocALbKh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.33.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:33:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 12/25] target/arm: Introduce ARMMMUIdx_Phys_{Realm,Root} Date: Tue, 21 Feb 2023 16:33:23 -1000 Message-Id: <20230222023336.915045-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org With FEAT_RME, there are four physical address spaces. For now, just define the symbols, and mention them in the same spots as the other Phys indexes in ptw.c. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/arm/cpu-param.h | 2 +- target/arm/cpu.h | 23 +++++++++++++++++++++-- target/arm/ptw.c | 10 ++++++++-- 3 files changed, 30 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 53cac9c89b..8dfd7a0bb6 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -47,6 +47,6 @@ bool guarded; #endif -#define NB_MMU_MODES 12 +#define NB_MMU_MODES 14 #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c5fc475cf8..05fd6e61aa 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2865,8 +2865,10 @@ typedef enum ARMMMUIdx { ARMMMUIdx_Stage2 = 9 | ARM_MMU_IDX_A, /* TLBs with 1-1 mapping to the physical address spaces. */ - ARMMMUIdx_Phys_S = 10 | ARM_MMU_IDX_A, - ARMMMUIdx_Phys_NS = 11 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_S = 10 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_NS = 11 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_Root = 12 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_Realm = 13 | ARM_MMU_IDX_A, /* * These are not allocated TLBs and are used only for AT system @@ -2930,6 +2932,23 @@ typedef enum ARMASIdx { ARMASIdx_TagS = 3, } ARMASIdx; +static inline ARMMMUIdx arm_space_to_phys(ARMSecuritySpace space) +{ + /* Assert the relative order of the physical mmu indexes. */ + QEMU_BUILD_BUG_ON(ARMSS_Secure != 0); + QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS != ARMMMUIdx_Phys_S + ARMSS_NonSecure); + QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Root != ARMMMUIdx_Phys_S + ARMSS_Root); + QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Realm != ARMMMUIdx_Phys_S + ARMSS_Realm); + + return ARMMMUIdx_Phys_S + space; +} + +static inline ARMSecuritySpace arm_phys_to_space(ARMMMUIdx idx) +{ + assert(idx >= ARMMMUIdx_Phys_S && idx <= ARMMMUIdx_Phys_Realm); + return idx - ARMMMUIdx_Phys_S; +} + static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) { /* If all the CLIDR.Ctypem bits are 0 there are no caches, and diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 5ed5bb5039..5a0c5edc88 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -182,8 +182,10 @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx, case ARMMMUIdx_E3: break; - case ARMMMUIdx_Phys_NS: case ARMMMUIdx_Phys_S: + case ARMMMUIdx_Phys_NS: + case ARMMMUIdx_Phys_Root: + case ARMMMUIdx_Phys_Realm: /* No translation for physical address spaces. */ return true; @@ -2632,8 +2634,10 @@ static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address, switch (mmu_idx) { case ARMMMUIdx_Stage2: case ARMMMUIdx_Stage2_S: - case ARMMMUIdx_Phys_NS: case ARMMMUIdx_Phys_S: + case ARMMMUIdx_Phys_NS: + case ARMMMUIdx_Phys_Root: + case ARMMMUIdx_Phys_Realm: break; default: @@ -2830,6 +2834,8 @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, switch (mmu_idx) { case ARMMMUIdx_Phys_S: case ARMMMUIdx_Phys_NS: + case ARMMMUIdx_Phys_Root: + case ARMMMUIdx_Phys_Realm: /* Checking Phys early avoids special casing later vs regime_el. */ return get_phys_addr_disabled(env, address, access_type, mmu_idx, is_secure, result, fi); From patchwork Wed Feb 22 02:33:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655668 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp456513wrb; Tue, 21 Feb 2023 18:36:45 -0800 (PST) X-Google-Smtp-Source: AK7set8HEyp1V0xfgWpdtrxqi5MXMnn63IGRAyzJSWco8a3CrdiyTNY38OAkGUWN4EsLF/IyPsui X-Received: by 2002:a05:6214:e42:b0:56e:fb4c:c1c4 with SMTP id o2-20020a0562140e4200b0056efb4cc1c4mr14697299qvc.14.1677033405656; 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[209.51.188.17]) by mx.google.com with ESMTPS id z18-20020a0c8f12000000b0057109661a1csi6534712qvd.378.2023.02.21.18.36.45 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 21 Feb 2023 18:36:45 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Bw6iPzI4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pUexS-0007fS-NS; Tue, 21 Feb 2023 21:34:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pUexE-0007NO-BK for qemu-devel@nongnu.org; Tue, 21 Feb 2023 21:34:02 -0500 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pUexC-0001cV-Mw for qemu-devel@nongnu.org; Tue, 21 Feb 2023 21:34:00 -0500 Received: by mail-pl1-x634.google.com with SMTP id e5so8271389plg.8 for ; Tue, 21 Feb 2023 18:33:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9iG9/NOmHP3MVj9nzPcx5U3Tkz40AHCYrjm18zTuNT0=; b=Bw6iPzI43P5H9s9qs63KgiGr4M6bWw6o1rWU47REeYdFGsXCUVWYjUs1lNaEgUZqJ+ hmmrla5PtZsYOK3KPDDD4y2wAtz15vBzqKl8I05NGfSy5z3l5VJifbwJCrI8Ph5oTTBf TKHqoesEPjYpA8e4v5b42O1ofO4MUw+mQV1zFi8MYN2qcKiG83HF0uI5ytN+RqftTvfy dnByXPruz9+1op97yz2eIf93RIWLOu5SwfnKU6MBBzokREkcxBuH5E/TgRHMNBzPNFYP AaCGkY2xbZs2I3E1s3ZgHOKEUPQLGC1uWDGGJlLfPWZcY24oRYnqJ5oIxXbGB3hVDa6q 6w7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9iG9/NOmHP3MVj9nzPcx5U3Tkz40AHCYrjm18zTuNT0=; b=CQaUTU3The40z4MjRK0N8QZ746vuzSTGpZ2yvf5Gm3EoMI+ZYnIiCKGxtTG1dpZrr7 DJ3x1Y0eofQnAmoumF2R17D8sX1m76oS4W/S4om6IgmPGqQdK5b18M6EY8h4pi5WeLC3 td0JDqdM3BUt8n4Hew2XZxtSzvzdW1eJw1WNJYrYbB+5VPnh4Tjpygs+qujKphRRlbYp aghNxpk2m9NIPEJ6uYXwLjKDVsyDH6dqzD7u+GHQMID9ikvKpehrDr75JQOZTHh4kQzp pJtupbNZI6fphBNAP+CX2iq8tifZZ475x3rs/XwjykxDZspCbSnSmPbWt86F2VeLIUwX q5Tg== X-Gm-Message-State: AO0yUKVzGgXTFbkRrhrzBKsLmQFED38gTruBOZAG6MlpxyOUDrnocTw2 ZaMHnsvxwHAWpxAZhRqKgbNbO7ypeuW8cB9lmNg= X-Received: by 2002:a17:903:2291:b0:19a:b427:2335 with SMTP id b17-20020a170903229100b0019ab4272335mr9823248plh.56.1677033237914; Tue, 21 Feb 2023 18:33:57 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.33.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:33:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 13/25] target/arm: Remove __attribute__((nonnull)) from ptw.c Date: Tue, 21 Feb 2023 16:33:24 -1000 Message-Id: <20230222023336.915045-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This was added in 7e98e21c098 as part of a reorg in which one of the argument had been legally NULL, and this caught actual instances. Now that the reorg is complete, this serves little purpose. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell --- target/arm/ptw.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 5a0c5edc88..9f608b12b2 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -32,15 +32,13 @@ typedef struct S1Translate { static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, uint64_t address, MMUAccessType access_type, bool s1_is_el0, - GetPhysAddrResult *result, ARMMMUFaultInfo *fi) - __attribute__((nonnull)); + GetPhysAddrResult *result, ARMMMUFaultInfo *fi); static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, target_ulong address, MMUAccessType access_type, GetPhysAddrResult *result, - ARMMMUFaultInfo *fi) - __attribute__((nonnull)); + ARMMMUFaultInfo *fi); /* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */ static const uint8_t pamax_map[] = { From patchwork Wed Feb 22 02:33:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655681 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp457156wrb; Tue, 21 Feb 2023 18:38:55 -0800 (PST) X-Google-Smtp-Source: AK7set8mhX7U++G0E5H+mLmOjYLK7ZhjVmEhuElbxEGXQA4+Um4dM9rfMVrEh0TMvb7HqwG1b+VW X-Received: by 2002:a05:622a:654:b0:3b8:6c10:f52 with SMTP id a20-20020a05622a065400b003b86c100f52mr10381558qtb.46.1677033535055; Tue, 21 Feb 2023 18:38:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677033535; cv=none; d=google.com; s=arc-20160816; b=gfIMbk0k4Z+A/wDEo93jxiLBNz9D0DzXp/mPVtrocm9UkVPSAzNNbOr6HH41midUyv psf3xDN7Efk6bTgtmT4DxFqoc8VCAM5OtT05xdwMYNUJ4OrEG5Ge1w57Y8bNS5zZ47Yd 3Rqgsaj0XYczzjKKq4ONXLuvQe1ISRzd94iYqwaC8pTjzCEQGibvoy1EEOUKO/i0M4ED t9zGNYPLD8lDo8+ilDJTaNmJRKJ1f/qp2OG/LN+rDdbHc0HKywjuqi43jSP0w0tWsw3b CU60JvhAeWtFQAPhOT1JfPuYvt9xoJ/Ame6sp3QgPQ1uOJBw4dee5hFR0JNu964/y2Kt pbmw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=NEdCUdHrW00WmG0Jrfmbg8ARsi/ZJepNVs1RVZlJouA=; b=QhrBjq6roZHqLeT/dH6hb/jLGf//aKHvMBZ7GKlSid2hR89R9oUomBnZUHQEJ7htEe DyZDY1jgOJg/W5/gHVv7O1RYrpOxhbzy6JzxF6/2TLbWdaWSAdsF870+cfAB75OFBbK2 oKxdqBsY6vxqcy3zSKwTHt4aT9dR5Q3lK8ZCNQbyBYxGrfYBiescr1XtB4pRfSTHy5UW b/ZJGZ6YcYwcLaFelYsuu4SFBTvaDld5EYO0v7ciGivoG0kj3CioWBl+03JV1OvwZ3VP 1h7Kd4jr9ZugRlvYMNJIvzfca84lpDlBOTdInwR9XptzKgwHpOeFDP3/JZs4qxCs7J9F DF/w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IdhEnL4H; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.33.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:33:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 14/25] target/arm: Pipe ARMSecuritySpace through ptw.c Date: Tue, 21 Feb 2023 16:33:25 -1000 Message-Id: <20230222023336.915045-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::642; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x642.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add input and output space members to S1Translate. Set and adjust them in S1_ptw_translate, and the various points at which we drop secure state. Initialize the space in get_phys_addr; for now leave get_phys_addr_with_secure considering only secure vs non-secure spaces. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 98 ++++++++++++++++++++++++++++++++++++++---------- 1 file changed, 78 insertions(+), 20 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 9f608b12b2..a77db3dd43 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -19,11 +19,13 @@ typedef struct S1Translate { ARMMMUIdx in_mmu_idx; ARMMMUIdx in_ptw_idx; + ARMSecuritySpace in_space; bool in_secure; bool in_debug; bool out_secure; bool out_rw; bool out_be; + ARMSecuritySpace out_space; hwaddr out_virt; hwaddr out_phys; void *out_host; @@ -216,6 +218,7 @@ static bool S2_attrs_are_device(uint64_t hcr, uint8_t attrs) static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, hwaddr addr, ARMMMUFaultInfo *fi) { + ARMSecuritySpace space = ptw->in_space; bool is_secure = ptw->in_secure; ARMMMUIdx mmu_idx = ptw->in_mmu_idx; ARMMMUIdx s2_mmu_idx = ptw->in_ptw_idx; @@ -232,7 +235,8 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, if (regime_is_stage2(s2_mmu_idx)) { S1Translate s2ptw = { .in_mmu_idx = s2_mmu_idx, - .in_ptw_idx = is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS, + .in_ptw_idx = arm_space_to_phys(space), + .in_space = space, .in_secure = is_secure, .in_debug = true, }; @@ -290,10 +294,17 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, } /* Check if page table walk is to secure or non-secure PA space. */ - ptw->out_secure = (is_secure - && !(pte_secure + if (is_secure) { + bool out_secure = !(pte_secure ? env->cp15.vstcr_el2 & VSTCR_SW - : env->cp15.vtcr_el2 & VTCR_NSW)); + : env->cp15.vtcr_el2 & VTCR_NSW); + if (!out_secure) { + is_secure = false; + space = ARMSS_NonSecure; + } + } + ptw->out_secure = is_secure; + ptw->out_space = space; ptw->out_be = regime_translation_big_endian(env, mmu_idx); return true; @@ -324,7 +335,10 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, S1Translate *ptw, } } else { /* Page tables are in MMIO. */ - MemTxAttrs attrs = { .secure = ptw->out_secure }; + MemTxAttrs attrs = { + .secure = ptw->out_secure, + .space = ptw->out_space, + }; AddressSpace *as = arm_addressspace(cs, attrs); MemTxResult result = MEMTX_OK; @@ -367,7 +381,10 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, S1Translate *ptw, #endif } else { /* Page tables are in MMIO. */ - MemTxAttrs attrs = { .secure = ptw->out_secure }; + MemTxAttrs attrs = { + .secure = ptw->out_secure, + .space = ptw->out_space, + }; AddressSpace *as = arm_addressspace(cs, attrs); MemTxResult result = MEMTX_OK; @@ -873,6 +890,7 @@ static bool get_phys_addr_v6(CPUARMState *env, S1Translate *ptw, * regime, because the attribute will already be non-secure. */ result->f.attrs.secure = false; + result->f.attrs.space = ARMSS_NonSecure; } result->f.phys_addr = phys_addr; return false; @@ -1577,6 +1595,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, * regime, because the attribute will already be non-secure. */ result->f.attrs.secure = false; + result->f.attrs.space = ARMSS_NonSecure; } /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */ @@ -2361,6 +2380,7 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, */ if (sattrs.ns) { result->f.attrs.secure = false; + result->f.attrs.space = ARMSS_NonSecure; } else if (!secure) { /* * NS access to S memory must fault. @@ -2710,6 +2730,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, bool is_secure = ptw->in_secure; bool ret, ipa_secure, s2walk_secure; ARMCacheAttrs cacheattrs1; + ARMSecuritySpace ipa_space, s2walk_space; bool is_el0; uint64_t hcr; @@ -2722,20 +2743,24 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, ipa = result->f.phys_addr; ipa_secure = result->f.attrs.secure; + ipa_space = result->f.attrs.space; if (is_secure) { /* Select TCR based on the NS bit from the S1 walk. */ s2walk_secure = !(ipa_secure ? env->cp15.vstcr_el2 & VSTCR_SW : env->cp15.vtcr_el2 & VTCR_NSW); + s2walk_space = arm_secure_to_space(s2walk_secure); } else { assert(!ipa_secure); s2walk_secure = false; + s2walk_space = ipa_space; } is_el0 = ptw->in_mmu_idx == ARMMMUIdx_Stage1_E0; ptw->in_mmu_idx = s2walk_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; - ptw->in_ptw_idx = s2walk_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS; + ptw->in_ptw_idx = arm_space_to_phys(s2walk_space); ptw->in_secure = s2walk_secure; + ptw->in_space = s2walk_space; /* * S1 is done, now do S2 translation. @@ -2823,11 +2848,12 @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, ARMMMUIdx s1_mmu_idx; /* - * The page table entries may downgrade secure to non-secure, but - * cannot upgrade an non-secure translation regime's attributes - * to secure. + * The page table entries may downgrade Secure to NonSecure, but + * cannot upgrade a NonSecure translation regime's attributes + * to Secure or Realm. */ result->f.attrs.secure = is_secure; + result->f.attrs.space = ptw->in_space; switch (mmu_idx) { case ARMMMUIdx_Phys_S: @@ -2869,7 +2895,7 @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, default: /* Single stage and second stage uses physical for ptw. */ - ptw->in_ptw_idx = is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS; + ptw->in_ptw_idx = arm_space_to_phys(ptw->in_space); break; } @@ -2944,6 +2970,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, S1Translate ptw = { .in_mmu_idx = mmu_idx, .in_secure = is_secure, + .in_space = arm_secure_to_space(is_secure), }; return get_phys_addr_with_struct(env, &ptw, address, access_type, result, fi); @@ -2953,7 +2980,10 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_idx, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { - bool is_secure; + S1Translate ptw = { + .in_mmu_idx = mmu_idx, + }; + ARMSecuritySpace ss; switch (mmu_idx) { case ARMMMUIdx_E10_0: @@ -2966,30 +2996,55 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: case ARMMMUIdx_E2: - is_secure = arm_is_secure_below_el3(env); + ss = arm_security_space_below_el3(env); break; case ARMMMUIdx_Stage2: + /* + * For Secure EL2, we need this index to be NonSecure; + * otherwise this will already be NonSecure or Realm. + */ + ss = arm_security_space_below_el3(env); + if (ss == ARMSS_Secure) { + ss = ARMSS_NonSecure; + } + break; case ARMMMUIdx_Phys_NS: case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: case ARMMMUIdx_MPriv: case ARMMMUIdx_MUser: - is_secure = false; + ss = ARMSS_NonSecure; break; - case ARMMMUIdx_E3: case ARMMMUIdx_Stage2_S: case ARMMMUIdx_Phys_S: case ARMMMUIdx_MSPrivNegPri: case ARMMMUIdx_MSUserNegPri: case ARMMMUIdx_MSPriv: case ARMMMUIdx_MSUser: - is_secure = true; + ss = ARMSS_Secure; + break; + case ARMMMUIdx_E3: + if (arm_feature(env, ARM_FEATURE_AARCH64) && + cpu_isar_feature(aa64_rme, env_archcpu(env))) { + ss = ARMSS_Root; + } else { + ss = ARMSS_Secure; + } + break; + case ARMMMUIdx_Phys_Root: + ss = ARMSS_Root; + break; + case ARMMMUIdx_Phys_Realm: + ss = ARMSS_Realm; break; default: g_assert_not_reached(); } - return get_phys_addr_with_secure(env, address, access_type, mmu_idx, - is_secure, result, fi); + + ptw.in_space = ss; + ptw.in_secure = arm_space_is_secure(ss); + return get_phys_addr_with_struct(env, &ptw, address, access_type, + result, fi); } hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, @@ -2997,9 +3052,12 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; + ARMMMUIdx mmu_idx = arm_mmu_idx(env); + ARMSecuritySpace ss = arm_security_space(env); S1Translate ptw = { - .in_mmu_idx = arm_mmu_idx(env), - .in_secure = arm_is_secure(env), + .in_mmu_idx = mmu_idx, + .in_space = ss, + .in_secure = arm_space_is_secure(ss), .in_debug = true, }; GetPhysAddrResult res = {}; From patchwork Wed Feb 22 02:33:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655670 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp456618wrb; Tue, 21 Feb 2023 18:37:04 -0800 (PST) X-Google-Smtp-Source: AK7set+oEqRiaPCX9Juw/L+HhlRiySgvXh6Tsv+3Io6yasR0b4aspD/bCAQEUEuaqTRz3I/y9034 X-Received: by 2002:a05:6214:2508:b0:56f:8a99:1a7a with SMTP id gf8-20020a056214250800b0056f8a991a7amr11380045qvb.23.1677033423924; Tue, 21 Feb 2023 18:37:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677033423; cv=none; d=google.com; s=arc-20160816; b=L3ld2WeR0/R34pZ8wUHzibKgnsEQuUcdrjfRsmaV9BjJqGo5JfrjJz+MsXeVImGhUc HAUQbOgC/jgWIugC9T7gDImYXuTfGPOJm5/9sdy2gyGQYcr5//dhgaPJNLLqRPKR1VSD fmrHN2ak2dUp7U5Bb2eu0F4KMWubFtfIg+JNrexAIUaHVpfs403VPgb3OcASXH5X3Pnd nez3LWhNnaGYqpMVB0yVcUZinH+/rb3+F3opqfvtNt8VCC5wHAXMCHW8j56rolMYl6S+ yUqKx4n9KrcsmTGDk8lIXR/mUZFWLki3nyvabNjF9dq/ZGkHVOJGiOFicrpKiSybBVBf xucw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=vZ42O5SQoIJotc7B0HupvbG77824SBhRrElE1X3jpLY=; b=Jwoz/k+xMtcadtv06dt4PsYuPIjm+Sn3CqQ64u5rdA2u5z2XcT/rU+3/G11EHK8Ml0 LaJouD0voWp0FRdfJk3ZDbx0sU9PC2qOhSpit3XfdXdMzUs2smzLGRT6wgaBo775cQxp J0Wnmf2JlNyi9ivTt8gUySJ9V6HJj70ga8e6B4i80owiOheSzpan3HKCMB3M4ySda4el z9opi2itMakizdfm0lxxnnElrKQZxdDz9XHCZ5MwSihTtuzGoFjHQeQW8sFNCVLBfooW qlcRfD3D7fmWz726jxN9rPH3WES0vcda7KQjPacj1m1PTXjQ3Ef2xPopZFCbPJBSah45 K51Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="pce8Ec/S"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.33.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:34:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 15/25] target/arm: NSTable is RES0 for the RME EL3 regime Date: Tue, 21 Feb 2023 16:33:26 -1000 Message-Id: <20230222023336.915045-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Test in_space instead of in_secure so that we don't switch out of Root space. Handle the output space change immediately, rather than try and combine the NSTable and NS bits later. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index a77db3dd43..8b3deb0884 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1238,7 +1238,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, { ARMCPU *cpu = env_archcpu(env); ARMMMUIdx mmu_idx = ptw->in_mmu_idx; - bool is_secure = ptw->in_secure; int32_t level; ARMVAParameters param; uint64_t ttbr; @@ -1254,7 +1253,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, uint64_t descaddrmask; bool aarch64 = arm_el_is_aa64(env, el); uint64_t descriptor, new_descriptor; - bool nstable; /* TODO: This code does not support shareability levels. */ if (aarch64) { @@ -1415,20 +1413,19 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, descaddrmask = MAKE_64BIT_MASK(0, 40); } descaddrmask &= ~indexmask_grainsize; - - /* - * Secure accesses start with the page table in secure memory and - * can be downgraded to non-secure at any step. Non-secure accesses - * remain non-secure. We implement this by just ORing in the NSTable/NS - * bits at each step. - */ - tableattrs = is_secure ? 0 : (1 << 4); + tableattrs = 0; next_level: descaddr |= (address >> (stride * (4 - level))) & indexmask; descaddr &= ~7ULL; - nstable = extract32(tableattrs, 4, 1); - if (nstable && ptw->in_secure) { + + /* + * Process the NSTable bit from the previous level. This changes + * the table address space and the output space from Secure to + * NonSecure. With RME, the EL3 translation regime does not change + * from Root to NonSecure. + */ + if (extract32(tableattrs, 4, 1) && ptw->in_space == ARMSS_Secure) { /* * Stage2_S -> Stage2 or Phys_S -> Phys_NS * Assert the relative order of the secure/non-secure indexes. @@ -1437,7 +1434,11 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2_S + 1 != ARMMMUIdx_Stage2); ptw->in_ptw_idx += 1; ptw->in_secure = false; + ptw->in_space = ARMSS_NonSecure; + result->f.attrs.secure = false; + result->f.attrs.space = ARMSS_NonSecure; } + if (!S1_ptw_translate(env, ptw, descaddr, fi)) { goto do_fault; } @@ -1540,7 +1541,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, */ attrs = new_descriptor & (MAKE_64BIT_MASK(2, 10) | MAKE_64BIT_MASK(50, 14)); if (!regime_is_stage2(mmu_idx)) { - attrs |= nstable << 5; /* NS */ + attrs |= !ptw->in_secure << 5; /* NS */ if (!param.hpd) { attrs |= extract64(tableattrs, 0, 2) << 53; /* XN, PXN */ /* From patchwork Wed Feb 22 02:33:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655661 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp455884wrb; Tue, 21 Feb 2023 18:34:49 -0800 (PST) X-Google-Smtp-Source: AK7set9vaTiakjRnh60fqKJNCVmudmkQiK+XhPcnifbZ8ZR7Cm7MGJk6Tb4E/toTyYLGfigl2A/e X-Received: by 2002:a05:6214:d4d:b0:56b:fb30:49c6 with SMTP id 13-20020a0562140d4d00b0056bfb3049c6mr15243571qvr.50.1677033289736; Tue, 21 Feb 2023 18:34:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677033289; cv=none; d=google.com; s=arc-20160816; b=vFhHHekLQ/nPMq7sgD2ZLBEXUcN7RJjKLE3BEhgftBh3Pog4aOOEijZ8MHXV1tgSud eEnnGgJ9YfIz6BlOPncbXeXi5UxuSt6LM3hRpb6AFdz1vIZ5s7RP0VC6P3c5nQAsjoZ3 MwJOOU9lVtotuqxIptA0FQN01enB2ugQyetXzMtFW2GNufypEQucHmqPlL37eJOLdVMH Mgz/ENi49Ur98kZQ7aWYCCR+YciNSJ/LKf8YikNIR9REVZbh0BJm15xE0LkUlGBJPg7G wlIhkSzOvcGjhD0WDpuSvr6S94XErFMdvunsivoolnZC9Sq8LEk3AmyRJTPrfzbqUdja x/sA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Sp5dyg/bRPedb4z1tKWhvvEgmxz3Z+nJXy57x/hLb5A=; b=s17PUM7HHcXS0E4qwcHJpNeskYd13Um1b2XgKoPUfoxwMcHoNkI4Z8K22QozeXsSzB T464Q0OSCrAk1EGfoJuwxJ1tD0IN6XBmvyMl31K9tkU3nRxieMmtBqgJJjSzAEM1E3Ac ya0XWdO/kBYgO+TBdsGfaQRnPCombh/RPpFGXzBk9tsE+FkHaaTvqaFw7ITJJO4yQU6t 0Gn/UzVoPWYvdyGH2ehMRDEOFoLyAgjjIV1hUliq0GbtWcnn3USfDm/CV5R9XiyN2m/G oSzqNvJiXKtxF243zghIIZ7HsHzCs3Rs3TEnp7kCJtuWYKxDdTHx/1+UOIyi5VWBqi9f uPog== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JnFxYy3h; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.34.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:34:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 16/25] target/arm: Handle Block and Page bits for security space Date: Tue, 21 Feb 2023 16:33:27 -1000 Message-Id: <20230222023336.915045-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org With Realm security state, bit 55 of a block or page descriptor during the stage2 walk becomes the NS bit; during the stage1 walk the bit 5 NS bit is RES0. With Root security state, bit 11 of the block or page descriptor during the stage1 walk becomes the NSE bit. Rather than collecting an NS bit and applying it later, compute the output pa space from the input pa space and unconditionally assign. This means that we no longer need to adjust the output space earlier for the NSTable bit. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 91 ++++++++++++++++++++++++++++++++++++++---------- 1 file changed, 73 insertions(+), 18 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 8b3deb0884..61c1227578 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -954,12 +954,14 @@ static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) * @mmu_idx: MMU index indicating required translation regime * @is_aa64: TRUE if AArch64 * @ap: The 2-bit simple AP (AP[2:1]) - * @ns: NS (non-secure) bit * @xn: XN (execute-never) bit * @pxn: PXN (privileged execute-never) bit + * @in_pa: The original input pa space + * @out_pa: The output pa space, modified by NSTable, NS, and NSE */ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, - int ap, int ns, int xn, int pxn) + int ap, int xn, int pxn, + ARMSecuritySpace in_pa, ARMSecuritySpace out_pa) { bool is_user = regime_is_user(env, mmu_idx); int prot_rw, user_rw; @@ -980,7 +982,8 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, } } - if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) { + if (out_pa == ARMSS_NonSecure && in_pa == ARMSS_Secure && + (env->cp15.scr_el3 & SCR_SIF)) { return prot_rw; } @@ -1248,11 +1251,12 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, int32_t stride; int addrsize, inputsize, outputsize; uint64_t tcr = regime_tcr(env, mmu_idx); - int ap, ns, xn, pxn; + int ap, xn, pxn; uint32_t el = regime_el(env, mmu_idx); uint64_t descaddrmask; bool aarch64 = arm_el_is_aa64(env, el); uint64_t descriptor, new_descriptor; + ARMSecuritySpace out_space; /* TODO: This code does not support shareability levels. */ if (aarch64) { @@ -1435,8 +1439,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, ptw->in_ptw_idx += 1; ptw->in_secure = false; ptw->in_space = ARMSS_NonSecure; - result->f.attrs.secure = false; - result->f.attrs.space = ARMSS_NonSecure; } if (!S1_ptw_translate(env, ptw, descaddr, fi)) { @@ -1554,15 +1556,75 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, } ap = extract32(attrs, 6, 2); + out_space = ptw->in_space; if (regime_is_stage2(mmu_idx)) { - ns = mmu_idx == ARMMMUIdx_Stage2; + /* + * R_GYNXY: For stage2 in Realm security state, bit 55 is NS. + * The bit remains ignored for other security states. + */ + if (out_space == ARMSS_Realm && extract64(attrs, 55, 1)) { + out_space = ARMSS_NonSecure; + } xn = extract64(attrs, 53, 2); result->f.prot = get_S2prot(env, ap, xn, s1_is_el0); } else { - ns = extract32(attrs, 5, 1); + int nse, ns = extract32(attrs, 5, 1); + switch (out_space) { + case ARMSS_Root: + /* + * R_GVZML: Bit 11 becomes the NSE field in the EL3 regime. + * R_XTYPW: NSE and NS together select the output pa space. + */ + nse = extract32(attrs, 11, 1); + out_space = (nse << 1) | ns; + if (out_space == ARMSS_Secure && + !cpu_isar_feature(aa64_sel2, cpu)) { + out_space = ARMSS_NonSecure; + } + break; + case ARMSS_Secure: + if (ns) { + out_space = ARMSS_NonSecure; + } + break; + case ARMSS_Realm: + switch (mmu_idx) { + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_Stage1_E1_PAN: + /* I_CZPRF: For Realm EL1&0 stage1, NS bit is RES0. */ + break; + case ARMMMUIdx_E2: + case ARMMMUIdx_E20_0: + case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: + /* + * R_LYKFZ, R_WGRZN: For Realm EL2 and EL2&1, + * NS changes the output to non-secure space. + */ + if (ns) { + out_space = ARMSS_NonSecure; + } + break; + default: + g_assert_not_reached(); + } + break; + case ARMSS_NonSecure: + /* R_QRMFF: For NonSecure state, the NS bit is RES0. */ + break; + default: + g_assert_not_reached(); + } xn = extract64(attrs, 54, 1); pxn = extract64(attrs, 53, 1); - result->f.prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn); + + /* + * Note that we modified ptw->in_space earlier for NSTable, but + * result->f.attrs retains a copy of the original security space. + */ + result->f.prot = get_S1prot(env, mmu_idx, aarch64, ap, xn, pxn, + result->f.attrs.space, out_space); } if (!(result->f.prot & (1 << access_type))) { @@ -1589,15 +1651,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, } } - if (ns) { - /* - * The NS bit will (as required by the architecture) have no effect if - * the CPU doesn't support TZ or this is a non-secure translation - * regime, because the attribute will already be non-secure. - */ - result->f.attrs.secure = false; - result->f.attrs.space = ARMSS_NonSecure; - } + result->f.attrs.space = out_space; + result->f.attrs.secure = arm_space_is_secure(out_space); /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { From patchwork Wed Feb 22 02:33:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655674 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp456893wrb; Tue, 21 Feb 2023 18:37:58 -0800 (PST) X-Google-Smtp-Source: AK7set/qDyEwaykBEEOKgwBmN7sjnZWikWDyqQb4CLFEta9QLVlrzL7DwJWT6zMLCFHvfBJ28P4W X-Received: by 2002:a05:622a:1a84:b0:3b8:2b4e:cbca with SMTP id s4-20020a05622a1a8400b003b82b4ecbcamr23203255qtc.14.1677033478786; Tue, 21 Feb 2023 18:37:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677033478; cv=none; d=google.com; s=arc-20160816; b=a2q5wmPc4+wvu9GiOtEoD2D+SU6lYJ8dEwWTugiNIZPXIgT5H6Wh7AITlPhkSfjB9k d5DhOi5ryL9qDMejhQA1jY+1tzDQqjoP/IrC3j506sY+iFob/0HDnC+cOP7CEbJe2qDC 07Yv4tP/Pzxq5FYatvtttQS0mvEP1mYzJTWhbK0cBYVHdRNJY1Ulc1QHofmoG7ivHn3P usFXa3iR21xqmZgvEsSQ3GgoNIZ8NHVo8/eDmQcQit1d7ZKaaf+chfx5DgUxF1vlZ2lO U4p8dbCtszPQyPTFTFlnPwtvtl4nGtxBDsbxo8sd5k8ADABczFFSTZwQ9Ff8j6OpXa7w SuZA== ARC-Message-Signature: i=1; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.34.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:34:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 17/25] target/arm: Handle no-execute for Realm and Root regimes Date: Tue, 21 Feb 2023 16:33:28 -1000 Message-Id: <20230222023336.915045-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org While Root and Realm may read and write data from other spaces, neither may execute from other pa spaces. This happens for Stage1 EL3, EL2, EL2&0, but stage2 EL1&0. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 52 ++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 46 insertions(+), 6 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 61c1227578..fc4c1ccf54 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -907,7 +907,7 @@ do_fault: * @xn: XN (execute-never) bits * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0 */ -static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) +static int get_S2prot_noexecute(int s2ap) { int prot = 0; @@ -917,6 +917,12 @@ static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) if (s2ap & 2) { prot |= PAGE_WRITE; } + return prot; +} + +static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) +{ + int prot = get_S2prot_noexecute(s2ap); if (cpu_isar_feature(any_tts2uxn, env_archcpu(env))) { switch (xn) { @@ -982,9 +988,39 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, } } - if (out_pa == ARMSS_NonSecure && in_pa == ARMSS_Secure && - (env->cp15.scr_el3 & SCR_SIF)) { - return prot_rw; + if (in_pa != out_pa) { + switch (in_pa) { + case ARMSS_Root: + /* + * R_ZWRVD: permission fault for insn fetched from non-Root, + * I_WWBFB: SIF has no effect in EL3. + */ + return prot_rw; + case ARMSS_Realm: + /* + * R_PKTDS: permission fault for insn fetched from non-Realm, + * for Realm EL2 or EL2&0. The corresponding fault for EL1&0 + * happens during any stage2 translation. + */ + switch (mmu_idx) { + case ARMMMUIdx_E2: + case ARMMMUIdx_E20_0: + case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: + return prot_rw; + default: + break; + } + break; + case ARMSS_Secure: + if (env->cp15.scr_el3 & SCR_SIF) { + return prot_rw; + } + break; + default: + /* Input NonSecure must have output NonSecure. */ + g_assert_not_reached(); + } } /* TODO have_wxn should be replaced with @@ -1561,12 +1597,16 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, /* * R_GYNXY: For stage2 in Realm security state, bit 55 is NS. * The bit remains ignored for other security states. + * R_YMCSL: Executing an insn fetched from non-Realm causes + * a stage2 permission fault. */ if (out_space == ARMSS_Realm && extract64(attrs, 55, 1)) { out_space = ARMSS_NonSecure; + result->f.prot = get_S2prot_noexecute(ap); + } else { + xn = extract64(attrs, 53, 2); + result->f.prot = get_S2prot(env, ap, xn, s1_is_el0); } - xn = extract64(attrs, 53, 2); - result->f.prot = get_S2prot(env, ap, xn, s1_is_el0); } else { int nse, ns = extract32(attrs, 5, 1); switch (out_space) { From patchwork Wed Feb 22 02:33:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655662 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp455890wrb; Tue, 21 Feb 2023 18:34:51 -0800 (PST) X-Google-Smtp-Source: AK7set9xumZAMWPr8CgN7da0uFvepn6/DnK76spC5VvYnQD4cUI3HWyCemwDL89h1mfMsuLWCLfX X-Received: by 2002:a05:6214:768:b0:56c:52e:b169 with SMTP id f8-20020a056214076800b0056c052eb169mr12888381qvz.50.1677033291155; Tue, 21 Feb 2023 18:34:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677033291; cv=none; d=google.com; s=arc-20160816; b=Qhtu9i6tqN40oRnAr2ZIMZhel44rNldLhhNwqeLNbIDjYU3y4SvKDYcOB36OqOOPC9 ZiCkJDpq4jAIpsibtz54kvg1DtBUGlKkvhlcYDFM8Y9fnsvh476h2IV+oMLwP295FCbt SlZpGnSJX2so3nlK+EeEsm42PG/9u0tQPAmYpWoegKrX7Qtr3N3CE/Fv/1rC+ZhqzQz4 QsUklLirJ8gfM04MDzj0LdOL0vqbOA/PeGC4YDiioQmD3AmZHdoC6RZHl1+ZkD8Ubbng XGcd27PKCxJSfDMYhOY/5SotbIyZnVNCpZjtoq32wgsO8hMS2G+kOnPd+rsxWDlvqLJv izyQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Q+0eq15fAwExTOnJJP3OmVXwymVtdfUriRFeQ7/we5Q=; b=OChvbnhriu80xTOrhrcfVWWlOVO2LM82EH9pldCtqZg4AL8vu3TZlIuaBvAoqUz0XD FnoHSJOEjdMVLLTtd1N9qbZHyd6JUKwUBq4OR5nByHXkOAmpti4LIzMfHGPhbjkamOhk ZSfRKuYVRQOQ8eIM7EMAHhO+haNAWYwK/68Vqs4mShYDzOeEiHNnbjV5zoqGxjbooreS sz7gM3r/UaS+A0c+AEeL85sg9AsYZUkl6AgQRuUG0FV4Epi2yMadfMm7cgC/4Diavfya 8t0WABUArRCGb537+1Ee3y676kZrgaav8ehWy2X3VWYfEoqI7mRtUqGpd/PnVQN8tFPZ rX1A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QOrSOeJq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.34.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:34:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 18/25] target/arm: Use get_phys_addr_with_struct in S1_ptw_translate Date: Tue, 21 Feb 2023 16:33:29 -1000 Message-Id: <20230222023336.915045-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Do not provide a fast-path for physical addresses, as those will need to be validated for GPC. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 35 ++++++++++++++--------------------- 1 file changed, 14 insertions(+), 21 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index fc4c1ccf54..8a31af60c9 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -232,29 +232,22 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, * From gdbstub, do not use softmmu so that we don't modify the * state of the cpu at all, including softmmu tlb contents. */ - if (regime_is_stage2(s2_mmu_idx)) { - S1Translate s2ptw = { - .in_mmu_idx = s2_mmu_idx, - .in_ptw_idx = arm_space_to_phys(space), - .in_space = space, - .in_secure = is_secure, - .in_debug = true, - }; - GetPhysAddrResult s2 = { }; + S1Translate s2ptw = { + .in_mmu_idx = s2_mmu_idx, + .in_ptw_idx = arm_space_to_phys(space), + .in_space = space, + .in_secure = is_secure, + .in_debug = true, + }; + GetPhysAddrResult s2 = { }; - if (get_phys_addr_lpae(env, &s2ptw, addr, MMU_DATA_LOAD, - false, &s2, fi)) { - goto fail; - } - ptw->out_phys = s2.f.phys_addr; - pte_attrs = s2.cacheattrs.attrs; - pte_secure = s2.f.attrs.secure; - } else { - /* Regime is physical. */ - ptw->out_phys = addr; - pte_attrs = 0; - pte_secure = is_secure; + if (get_phys_addr_with_struct(env, &s2ptw, addr, + MMU_DATA_LOAD, &s2, fi)) { + goto fail; } + ptw->out_phys = s2.f.phys_addr; + pte_attrs = s2.cacheattrs.attrs; + pte_secure = s2.f.attrs.secure; ptw->out_host = NULL; ptw->out_rw = false; } else { From patchwork Wed Feb 22 02:33:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655667 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp456321wrb; Tue, 21 Feb 2023 18:36:10 -0800 (PST) X-Google-Smtp-Source: AK7set/MGGQRSlyqyvjqy48pdYp3mhslv+aEBfAPxcfl1bYTJJgnbMr1tYlbpt6uyECcbP1ec7l+ X-Received: by 2002:a05:6214:c41:b0:53c:c2d1:e3da with SMTP id r1-20020a0562140c4100b0053cc2d1e3damr10752940qvj.2.1677033370783; Tue, 21 Feb 2023 18:36:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677033370; cv=none; d=google.com; s=arc-20160816; b=QSXMO90RxVfdEW8G1CZn3zJnj8Cm8bu+fe/5XcYeu7OelL5fWAkCzhExmQJ5+9TtLR fNVlIwjx+njtJQxzkhMLv56koSVybvGA8wTMU50yH4YC4lu9v7SDPNDcuYsz5ZiTAuNp LA6x8nPcqubBdQJtAbHFG+keAP2cMuRWEij2aE+610NxzdBVej98gfI7VysgWFeXyYxF jrnfyrnF+/SxywihgeZBzoxp9gKhu8K64DG8BTHWEndYDwwUPBgQT1BPWsOoFDXEikBi 4Oe04gMqWbT7EuNHbeeJsxHKUUvuSy9PJlobgjxq/Ww40CWuKi0ULSmq1iAqpMVVs6Qn +sfA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=AEaPa3mWe3IpmNaEY7zBYHLgHnvDHdVZm/A7K3Apt8Y=; b=DHtcU08FoC4cq5nr8U/q8VBxeu1MSkEFjffaDWz6udF0K0riqCTyQKv2rS1wj4pZNa lnkYRx38MK4BV03/vacKQxzT1fk4fZxhdQGolsap4iMNTSzcJy1VjL2MXpqKR4c2aLGH VZOmBDs5axsVVWbEvfmhkufOCuns5ca7qFuvUoS4W5yRNYGQ3s3Wasfdoafwf19nUeju +9Ra9G6FfaMN9pFh8fyeZZfUqBfJOmzu9lNsIpIQxqcd8DBHoT0Y93VhwH0fZFTCbruC StLVPmYOkHW0sdUbeEOQ6fBzudT43JzFKXvf59RfsGBSNL06UEtrdbB7W1Luhkf9jPSN m5BQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=slrKf1w6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.34.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:34:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 19/25] target/arm: Move s1_is_el0 into S1Translate Date: Tue, 21 Feb 2023 16:33:30 -1000 Message-Id: <20230222023336.915045-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Instead of passing this to get_phys_addr_lpae, stash it in the S1Translate structure. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/arm/ptw.c | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 8a31af60c9..6fa3d33a4e 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -22,6 +22,12 @@ typedef struct S1Translate { ARMSecuritySpace in_space; bool in_secure; bool in_debug; + /* + * If this is stage 2 of a stage 1+2 page table walk, then this must + * be true if stage 1 is an EL0 access; otherwise this is ignored. + * Stage 2 is indicated by in_mmu_idx set to ARMMMUIdx_Stage2{,_S}. + */ + bool in_s1_is_el0; bool out_secure; bool out_rw; bool out_be; @@ -32,8 +38,7 @@ typedef struct S1Translate { } S1Translate; static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, - uint64_t address, - MMUAccessType access_type, bool s1_is_el0, + uint64_t address, MMUAccessType access_type, GetPhysAddrResult *result, ARMMMUFaultInfo *fi); static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, @@ -1255,17 +1260,12 @@ static int check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, uint64_t tcr, * @ptw: Current and next stage parameters for the walk. * @address: virtual address to get physical address for * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH - * @s1_is_el0: if @ptw->in_mmu_idx is ARMMMUIdx_Stage2 - * (so this is a stage 2 page table walk), - * must be true if this is stage 2 of a stage 1+2 - * walk for an EL0 access. If @mmu_idx is anything else, - * @s1_is_el0 is ignored. * @result: set on translation success, * @fi: set to fault info if the translation fails */ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, uint64_t address, - MMUAccessType access_type, bool s1_is_el0, + MMUAccessType access_type, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { ARMCPU *cpu = env_archcpu(env); @@ -1598,7 +1598,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, result->f.prot = get_S2prot_noexecute(ap); } else { xn = extract64(attrs, 53, 2); - result->f.prot = get_S2prot(env, ap, xn, s1_is_el0); + result->f.prot = get_S2prot(env, ap, xn, ptw->in_s1_is_el0); } } else { int nse, ns = extract32(attrs, 5, 1); @@ -2820,7 +2820,6 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, bool ret, ipa_secure, s2walk_secure; ARMCacheAttrs cacheattrs1; ARMSecuritySpace ipa_space, s2walk_space; - bool is_el0; uint64_t hcr; ret = get_phys_addr_with_struct(env, ptw, address, access_type, result, fi); @@ -2845,7 +2844,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, s2walk_space = ipa_space; } - is_el0 = ptw->in_mmu_idx == ARMMMUIdx_Stage1_E0; + ptw->in_s1_is_el0 = ptw->in_mmu_idx == ARMMMUIdx_Stage1_E0; ptw->in_mmu_idx = s2walk_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; ptw->in_ptw_idx = arm_space_to_phys(s2walk_space); ptw->in_secure = s2walk_secure; @@ -2864,8 +2863,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, ret = get_phys_addr_pmsav8(env, ipa, access_type, ptw->in_mmu_idx, is_secure, result, fi); } else { - ret = get_phys_addr_lpae(env, ptw, ipa, access_type, - is_el0, result, fi); + ret = get_phys_addr_lpae(env, ptw, ipa, access_type, result, fi); } fi->s2addr = ipa; @@ -3041,8 +3039,7 @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, } if (regime_using_lpae_format(env, mmu_idx)) { - return get_phys_addr_lpae(env, ptw, address, access_type, false, - result, fi); + return get_phys_addr_lpae(env, ptw, address, access_type, result, fi); } else if (arm_feature(env, ARM_FEATURE_V7) || regime_sctlr(env, mmu_idx) & SCTLR_XP) { return get_phys_addr_v6(env, ptw, address, access_type, result, fi); From patchwork Wed Feb 22 02:33:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655676 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp456921wrb; Tue, 21 Feb 2023 18:38:03 -0800 (PST) X-Google-Smtp-Source: AK7set9PFgZUEwUBry9j8iAaPWCPKpMIPdAgthxAVJacNg/o/zltlnYHHGqRhXwwlEW1GAlvB3Cv X-Received: by 2002:a05:6214:2a86:b0:531:85bf:362a with SMTP id jr6-20020a0562142a8600b0053185bf362amr14881393qvb.23.1677033483633; Tue, 21 Feb 2023 18:38:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677033483; cv=none; d=google.com; s=arc-20160816; b=0TO3UZV89L0moMK8vPlUrLCfvK5SqCoQUhNbqjwcO+5xTG34HiNl79Bif5eEeXGXYk RLO+8rrniIi8H9p1RE1DA4SMfCuVLHs7hrcKcUeTx4fEF2lqN3+mCJV4YRXoLe+Qh+as FXquN3YTwWoEC8drbpWR/3XpGie/x7hi/5ma+QQu99YQWfkE6SenFZ6kAXcuIQbbavI9 O5d/aRk+mB618teKKVBDsl9BNBfV1LUrm4paTZkdCEddpF8L+ObSfFagJLI8xJkKu/2f QJnToMVDL0J0ckHVY9Fzs22pxocBHvBBdwmnsRcH3tNDHW/bPlK0cVjB0a/rk3S/NivG 75Qw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=PhxQ9e9pVV9RyCPmKQ2M0WUBfbr0akWOWFlqn9fFR48=; b=OeihI6QOxD6918CqT1XN5G4jITIhea++j7g+J9vPq+eTDmyy3nZ1JUyRxFchS1WbK+ XSZsJLdD9yLfHFPfljKsG6MbttEIw9SwW7sh9SO/t6qla9ZeUVuYC3m3LWhXfnJscoDS XQYmN7luZQEMmAS32DkNLqYiuOeXQeonNSCcBwZjW2Msg1ei/lEKIK6C5gj7hgxfff9J XkkZ0cFC6l/w5CEkwdcvJ2gTvS6AJr+MaG6mIUNMX4F5TaEqfjV6jDbQxwIli+2wL/Ks WY3OBwJANZuaSrBN49aQ5cISSm6aQcvBoCqbKqcxCugIXZemysOQimjWyZYGhUBHNfhU xNFQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="ElH/lQgU"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.34.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:34:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 20/25] target/arm: Use get_phys_addr_with_struct for stage2 Date: Tue, 21 Feb 2023 16:33:31 -1000 Message-Id: <20230222023336.915045-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This fixes a bug in which we failed to initialize the result attributes properly after the memset. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell --- target/arm/ptw.c | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 6fa3d33a4e..7e1aa34d24 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -37,10 +37,6 @@ typedef struct S1Translate { void *out_host; } S1Translate; -static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, - uint64_t address, MMUAccessType access_type, - GetPhysAddrResult *result, ARMMMUFaultInfo *fi); - static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, target_ulong address, MMUAccessType access_type, @@ -2859,12 +2855,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, cacheattrs1 = result->cacheattrs; memset(result, 0, sizeof(*result)); - if (arm_feature(env, ARM_FEATURE_PMSA)) { - ret = get_phys_addr_pmsav8(env, ipa, access_type, - ptw->in_mmu_idx, is_secure, result, fi); - } else { - ret = get_phys_addr_lpae(env, ptw, ipa, access_type, result, fi); - } + ret = get_phys_addr_with_struct(env, ptw, ipa, access_type, result, fi); fi->s2addr = ipa; /* Combine the S1 and S2 perms. */ From patchwork Wed Feb 22 02:33:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655673 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp456834wrb; Tue, 21 Feb 2023 18:37:44 -0800 (PST) X-Google-Smtp-Source: AK7set8Peo25hwBEdis5RY0ovckYvurmmvPSaYaRTxSrTP5EAp5ZwgONydI9aGth0209VJ+NtSfi X-Received: by 2002:a05:6214:2426:b0:56e:a93e:2300 with SMTP id gy6-20020a056214242600b0056ea93e2300mr14829372qvb.40.1677033464441; Tue, 21 Feb 2023 18:37:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677033464; cv=none; d=google.com; s=arc-20160816; b=s7oqTiDG35MXMzv7CrKJFV3ymHx1vmMFVZqoowz1wAfhOFAnp9dVRXQv1DoRyDAg2v 035y9vRHlIr4dMOEdGhxuF45GSnYeWyXNycyF9TOa5tYFGKOEopeHV1GTq0zWKCXennz tLplJCNr/gkt0hlooD7a8SGNVcVjV4JPcIICXVoS6DobEkNqJPoOfesdet9tXuQLKqL5 oRX/HxesJ1CVOpWC1uGnpUtNbMNTt2vHQRhNgcSjpOI02sWM2XF5Zllb3grFH5fwhKjZ WeboOwCQ6sqPOhyrYrDklS3ObGjUSM9iuiACSChTZTCsrkimnNgFORx0kBt+KiACUyxj hQFg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=BdnIrBC/vjhypfMOEhRm01STyDVGWe2QDHvXiznUOKk=; b=gFKrYz1lV13ej49I4dEQYY8aB/xc32Svdv1XUF3jTvd/Q2v2jv9s+qKNqCjHCkgiKP 6Nsxao0/GfwFpKMoXw34YWL5tw6uqs8oP+edRlh01pwAClncSsUklKopVwjE9ot1lU6l xeAzx9+ajDLUXXouefgXANE6mG6JGXFY4Gc0zlXEALnk6o/tGFdu262kkcNtPwdCzKGe 92R1fgrnTPNvhAVYMt9CTU8m9moNkczQD3lmEOhbKll9sYYxZGdBZm5vwfPeHbxZ+eiV PhXy/WkMexlJQJJrgnt4teNFB//k6P9WI4bNm32kbRM4mORUU6heItHC/+h9NU+jfTGR X9Tw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zso61bsF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.34.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:34:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 21/25] target/arm: Add GPC syndrome Date: Tue, 21 Feb 2023 16:33:32 -1000 Message-Id: <20230222023336.915045-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The function takes the fields as filled in by the Arm ARM pseudocode for TakeGPCException. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/syndrome.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index d27d1bc31f..62254d0e51 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -50,6 +50,7 @@ enum arm_exception_class { EC_SVEACCESSTRAP = 0x19, EC_ERETTRAP = 0x1a, EC_SMETRAP = 0x1d, + EC_GPC = 0x1e, EC_INSNABORT = 0x20, EC_INSNABORT_SAME_EL = 0x21, EC_PCALIGNMENT = 0x22, @@ -247,6 +248,15 @@ static inline uint32_t syn_bxjtrap(int cv, int cond, int rm) (cv << 24) | (cond << 20) | rm; } +static inline uint32_t syn_gpc(int s2ptw, int ind, int gpcsc, + int cm, int s1ptw, int wnr, int fsc) +{ + /* TODO: FEAT_NV2 adds VNCR */ + return (EC_GPC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (s2ptw << 21) + | (ind << 20) | (gpcsc << 14) | (cm << 8) | (s1ptw << 7) + | (wnr << 6) | fsc; +} + static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc) { return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) From patchwork Wed Feb 22 02:33:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655671 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp456640wrb; Tue, 21 Feb 2023 18:37:08 -0800 (PST) X-Google-Smtp-Source: AK7set+koQJ13uOYm673m8FC/HOj32CEAyrkapPF8ITY4MFAiiUfMtnyfDK670YcrxFzZta/KABJ X-Received: by 2002:a05:622a:60e:b0:3b8:6d70:9fe2 with SMTP id z14-20020a05622a060e00b003b86d709fe2mr12401757qta.59.1677033428197; Tue, 21 Feb 2023 18:37:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677033428; cv=none; d=google.com; s=arc-20160816; b=UYGwQqttsP1BUj1XxCR/vZUakFzmDNH01pJLvdFW/Zx9cYlumadqMIA5k8xqhsYh/R Y2osnDGwyAs7PY4nCN2oV/JZhsDgd43R1TWkqA6nPzmIWb8gq/Lampw+XhcDzaJ0Praq MWv5wtI215rt+v8VoOtvFAQXix/aqXGErMHIK4L0E9fRBp34xp29FMkdnfRZk63COzEp SG4pdltg6yaRZ3qtkP2SLCEd5sgo7R7Mnz91PF72L1GLS3FJYKzSlTRoifk9G9EZOykC xQqJym4h+SZo717Z+hccpOetSq2V7OKqfloBn65iFT1ckoiNpSJdVVdXIKhUlbZzwsM2 KvEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=OvOoJ884ZN5PW2Z4ZXukQZSOfuuCRAHBihmEoUNUOLo=; b=KAyTsGeYP4bk2NcbYxvL8oH2FL1XJffgoo7SfD5QlP+RyDS0NWXD/WzX+iInKEy+nW iZXSi7wU7O4+PA29Yat9nTC0gf/xIByr3LueyP6PAUU2Z3LLpNP5d4NIRNqB9+XIvZXn la959SM9ZTdgW5L7yfw5k5uIF6ASZIdGtnLFAtieJTonyeL611QsOFORDn1XgPtuCk4W YfmVYCMqBH8lEb/zzVKMoWDjfua4WpkdxcdhTzQouGhzpGvSJTPZ4qOBazHlNMICXaKR tzqmao7XH3fdb2nKoE/HPQwzWa78i/6oISQ1UAWZlkVE5RzyenTyUGa+3RbnREKWhM9A Frrw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=N6jHqZ4a; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.34.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:34:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 22/25] target/arm: Implement GPC exceptions Date: Tue, 21 Feb 2023 16:33:33 -1000 Message-Id: <20230222023336.915045-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Handle GPC Fault types in arm_deliver_fault, reporting as either a GPC exception at EL3, or falling through to insn or data aborts at various exception levels. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 1 + target/arm/internals.h | 27 ++++++++++++ target/arm/helper.c | 5 +++ target/arm/tlb_helper.c | 96 +++++++++++++++++++++++++++++++++++++++-- 4 files changed, 126 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 05fd6e61aa..b189efadf8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -57,6 +57,7 @@ #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ #define EXCP_VSERR 24 +#define EXCP_GPC 25 /* v9 Granule Protection Check Fault */ /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ #define ARMV7M_EXCP_RESET 1 diff --git a/target/arm/internals.h b/target/arm/internals.h index 759b70c646..5e88649fea 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -352,14 +352,27 @@ typedef enum ARMFaultType { ARMFault_ICacheMaint, ARMFault_QEMU_NSCExec, /* v8M: NS executing in S&NSC memory */ ARMFault_QEMU_SFault, /* v8M: SecureFault INVTRAN, INVEP or AUVIOL */ + ARMFault_GPCFOnWalk, + ARMFault_GPCFOnOutput, } ARMFaultType; +typedef enum ARMGPCF { + GPCF_None, + GPCF_AddressSize, + GPCF_Walk, + GPCF_EABT, + GPCF_Fail, +} ARMGPCF; + /** * ARMMMUFaultInfo: Information describing an ARM MMU Fault * @type: Type of fault + * @gpcf: Subtype of ARMFault_GPCFOn{Walk,Output}. * @level: Table walk level (for translation, access flag and permission faults) * @domain: Domain of the fault address (for non-LPAE CPUs only) * @s2addr: Address that caused a fault at stage 2 + * @paddr: physical address that caused a fault for gpc + * @paddr_space: physical address space that caused a fault for gpc * @stage2: True if we faulted at stage 2 * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk * @s1ns: True if we faulted on a non-secure IPA while in secure state @@ -368,7 +381,10 @@ typedef enum ARMFaultType { typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; struct ARMMMUFaultInfo { ARMFaultType type; + ARMGPCF gpcf; target_ulong s2addr; + target_ulong paddr; + ARMSecuritySpace paddr_space; int level; int domain; bool stage2; @@ -542,6 +558,17 @@ static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo *fi) case ARMFault_Exclusive: fsc = 0x35; break; + case ARMFault_GPCFOnWalk: + assert(fi->level >= -1 && fi->level <= 3); + if (fi->level < 0) { + fsc = 0b100011; + } else { + fsc = 0b100100 | fi->level; + } + break; + case ARMFault_GPCFOnOutput: + fsc = 0b101000; + break; default: /* Other faults can't occur in a context that requires a * long-format status code. diff --git a/target/arm/helper.c b/target/arm/helper.c index 9e1c1ed6d8..dc97dc120b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10238,6 +10238,7 @@ void arm_log_exception(CPUState *cs) [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault", [EXCP_DIVBYZERO] = "v7M DIVBYZERO UsageFault", [EXCP_VSERR] = "Virtual SERR", + [EXCP_GPC] = "Granule Protection Check", }; if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { @@ -10966,6 +10967,10 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) } switch (cs->exception_index) { + case EXCP_GPC: + qemu_log_mask(CPU_LOG_INT, "...with MFAR 0x%" PRIx64 "\n", + env->cp15.mfar_el3); + /* fall through */ case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: /* diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 60abcbebe6..aa03d3f8dc 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -109,17 +109,106 @@ static uint32_t compute_fsr_fsc(CPUARMState *env, ARMMMUFaultInfo *fi, return fsr; } +static bool report_as_gpc_exception(ARMCPU *cpu, int current_el, + ARMMMUFaultInfo *fi) +{ + bool ret; + + switch (fi->gpcf) { + case GPCF_None: + return false; + case GPCF_AddressSize: + case GPCF_Walk: + case GPCF_EABT: + /* R_PYTGX: GPT faults are reported as GPC. */ + ret = true; + break; + case GPCF_Fail: + /* + * R_BLYPM: A GPF at EL3 is reported as insn or data abort. + * R_VBZMW, R_LXHQR: A GPF at EL[0-2] is reported as a GPC + * if SCR_EL3.GPF is set, otherwise an insn or data abort. + */ + ret = (cpu->env.cp15.scr_el3 & SCR_GPF) && current_el != 3; + break; + default: + g_assert_not_reached(); + } + + assert(cpu_isar_feature(aa64_rme, cpu)); + assert(fi->type == ARMFault_GPCFOnWalk || + fi->type == ARMFault_GPCFOnOutput); + if (fi->gpcf == GPCF_AddressSize) { + assert(fi->level == 0); + } else { + assert(fi->level >= 0 && fi->level <= 1); + } + + return ret; +} + +static unsigned encode_gpcsc(ARMMMUFaultInfo *fi) +{ + static uint8_t const gpcsc[] = { + [GPCF_AddressSize] = 0b000000, + [GPCF_Walk] = 0b000100, + [GPCF_Fail] = 0b001100, + [GPCF_EABT] = 0b010100, + }; + + /* Note that we've validated fi->gpcf and fi->level above. */ + return gpcsc[fi->gpcf] | fi->level; +} + static G_NORETURN void arm_deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, ARMMMUFaultInfo *fi) { CPUARMState *env = &cpu->env; - int target_el; + int target_el = exception_target_el(env); + int current_el = arm_current_el(env); bool same_el; uint32_t syn, exc, fsr, fsc; - target_el = exception_target_el(env); + if (report_as_gpc_exception(cpu, current_el, fi)) { + target_el = 3; + + fsr = compute_fsr_fsc(env, fi, target_el, mmu_idx, &fsc); + + syn = syn_gpc(fi->stage2 && fi->type == ARMFault_GPCFOnWalk, + access_type == MMU_INST_FETCH, + encode_gpcsc(fi), 0, fi->s1ptw, + access_type == MMU_DATA_STORE, fsc); + + env->cp15.mfar_el3 = fi->paddr; + switch (fi->paddr_space) { + case ARMSS_Secure: + break; + case ARMSS_NonSecure: + env->cp15.mfar_el3 |= R_MFAR_NS_MASK; + break; + case ARMSS_Root: + env->cp15.mfar_el3 |= R_MFAR_NSE_MASK; + break; + case ARMSS_Realm: + env->cp15.mfar_el3 |= R_MFAR_NSE_MASK | R_MFAR_NS_MASK; + break; + default: + g_assert_not_reached(); + } + + exc = EXCP_GPC; + goto do_raise; + } + + /* If SCR_EL3.GPF is unset, GPF may still be routed to EL2. */ + if (fi->gpcf == GPCF_Fail && target_el < 2) { + if (arm_hcr_el2_eff(env) & HCR_GPF) { + target_el = 2; + } + } + if (fi->stage2) { target_el = 2; env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4; @@ -127,8 +216,8 @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr, env->cp15.hpfar_el2 |= HPFAR_NS; } } - same_el = (arm_current_el(env) == target_el); + same_el = current_el == target_el; fsr = compute_fsr_fsc(env, fi, target_el, mmu_idx, &fsc); if (access_type == MMU_INST_FETCH) { @@ -146,6 +235,7 @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr, exc = EXCP_DATA_ABORT; } + do_raise: env->exception.vaddress = addr; env->exception.fsr = fsr; raise_exception(env, exc, syn, target_el); From patchwork Wed Feb 22 02:33:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655663 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp455915wrb; Tue, 21 Feb 2023 18:34:55 -0800 (PST) X-Google-Smtp-Source: AK7set+Na64nzi94S5kSu1SZoX+panlhtO1Q3tuLEM4XQOnLn4uJhiS29MPeiiMuoxrdoCejgAum X-Received: by 2002:ad4:4ee3:0:b0:537:684b:20c9 with SMTP id dv3-20020ad44ee3000000b00537684b20c9mr13010484qvb.46.1677033295281; Tue, 21 Feb 2023 18:34:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677033295; cv=none; d=google.com; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.34.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:34:11 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 23/25] target/arm: Implement the granule protection check Date: Tue, 21 Feb 2023 16:33:34 -1000 Message-Id: <20230222023336.915045-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::643; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x643.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Place the check at the end of get_phys_addr_with_struct, so that we check all physical results. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 249 +++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 232 insertions(+), 17 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 7e1aa34d24..8fa4849aaa 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -37,11 +37,17 @@ typedef struct S1Translate { void *out_host; } S1Translate; -static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, - target_ulong address, - MMUAccessType access_type, - GetPhysAddrResult *result, - ARMMMUFaultInfo *fi); +static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, + target_ulong address, + MMUAccessType access_type, + GetPhysAddrResult *result, + ARMMMUFaultInfo *fi); + +static bool get_phys_addr_gpc(CPUARMState *env, S1Translate *ptw, + target_ulong address, + MMUAccessType access_type, + GetPhysAddrResult *result, + ARMMMUFaultInfo *fi); /* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */ static const uint8_t pamax_map[] = { @@ -197,6 +203,197 @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx, return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0; } +static bool granule_protection_check(CPUARMState *env, uint64_t paddress, + ARMSecuritySpace pspace, + ARMMMUFaultInfo *fi) +{ + MemTxAttrs attrs = { + .secure = true, + .space = ARMSS_Root, + }; + ARMCPU *cpu = env_archcpu(env); + uint64_t gpccr = env->cp15.gpccr_el3; + unsigned pps, pgs, l0gptsz, level = 0; + uint64_t tableaddr, pps_mask, align, entry, index; + AddressSpace *as; + MemTxResult result; + int gpi; + + if (!FIELD_EX64(gpccr, GPCCR, GPC)) { + return true; + } + + /* + * GPC Priority 1 (R_GMGRR): + * R_JWCSM: If the configuration of GPCCR_EL3 is invalid, + * the access fails as GPT walk fault at level 0. + */ + + /* + * Configuration of PPS to a value exceeding the implemented + * physical address size is invalid. + */ + pps = FIELD_EX64(gpccr, GPCCR, PPS); + if (pps > FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE)) { + goto fault_walk; + } + pps = pamax_map[pps]; + pps_mask = MAKE_64BIT_MASK(0, pps); + + switch (FIELD_EX64(gpccr, GPCCR, SH)) { + case 0b10: /* outer shareable */ + break; + case 0b00: /* non-shareable */ + case 0b11: /* inner shareable */ + /* Inner and Outer non-cacheable requires Outer shareable. */ + if (FIELD_EX64(gpccr, GPCCR, ORGN) == 0 && + FIELD_EX64(gpccr, GPCCR, IRGN) == 0) { + goto fault_walk; + } + break; + default: /* reserved */ + goto fault_walk; + } + + switch (FIELD_EX64(gpccr, GPCCR, PGS)) { + case 0b00: /* 4KB */ + pgs = 12; + break; + case 0b01: /* 64KB */ + pgs = 16; + break; + case 0b10: /* 16KB */ + pgs = 14; + break; + default: /* reserved */ + goto fault_walk; + } + + /* Note this field is read-only and fixed at reset. */ + l0gptsz = 30 + FIELD_EX64(gpccr, GPCCR, L0GPTSZ); + + /* + * GPC Priority 2: Secure, Realm or Root address exceeds PPS. + * R_CPDSB: A NonSecure physical address input exceeding PPS + * does not experience any fault. + */ + if (paddress & ~pps_mask) { + if (pspace == ARMSS_NonSecure) { + return true; + } + goto fault_size; + } + + /* GPC Priority 3: the base address of GPTBR_EL3 exceeds PPS. */ + tableaddr = env->cp15.gptbr_el3 << 12; + if (tableaddr & ~pps_mask) { + goto fault_size; + } + + /* + * BADDR is aligned per a function of PPS and L0GPTSZ. + * These bits of GPTBR_EL3 are RES0, but are not a configuration error, + * unlike the RES0 bits of the GPT entries (R_XNKFZ). + */ + align = MAX(pps - l0gptsz + 3, 12); + align = MAKE_64BIT_MASK(0, align); + tableaddr &= ~align; + + as = arm_addressspace(env_cpu(env), attrs); + + /* Level 0 lookup. */ + index = extract64(paddress, l0gptsz, pps - l0gptsz); + tableaddr += index * 8; + entry = address_space_ldq_le(as, tableaddr, attrs, &result); + if (result != MEMTX_OK) { + goto fault_eabt; + } + + switch (extract32(entry, 0, 4)) { + case 1: /* block descriptor */ + if (entry >> 8) { + goto fault_walk; /* RES0 bits not 0 */ + } + gpi = extract32(entry, 4, 4); + goto found; + case 3: /* table descriptor */ + tableaddr = entry & ~0xf; + align = MAX(l0gptsz - pgs - 1, 12); + align = MAKE_64BIT_MASK(0, align); + if (tableaddr & (~pps_mask | align)) { + goto fault_walk; /* RES0 bits not 0 */ + } + break; + default: /* invalid */ + goto fault_walk; + } + + /* Level 1 lookup */ + level = 1; + index = extract64(paddress, pgs + 4, l0gptsz - pgs - 4); + tableaddr += index * 8; + entry = address_space_ldq_le(as, tableaddr, attrs, &result); + if (result != MEMTX_OK) { + goto fault_eabt; + } + + switch (extract32(entry, 0, 4)) { + case 1: /* contiguous descriptor */ + if (entry >> 10) { + goto fault_walk; /* RES0 bits not 0 */ + } + /* + * Because the softmmu tlb only works on units of TARGET_PAGE_SIZE, + * and because we cannot invalidate by pa, and thus will always + * flush entire tlbs, we don't actually care about the range here + * and can simply extract the GPI as the result. + */ + if (extract32(entry, 8, 2) == 0) { + goto fault_walk; /* reserved contig */ + } + gpi = extract32(entry, 4, 4); + break; + default: + index = extract64(paddress, pgs, 4); + gpi = extract64(entry, index * 4, 4); + break; + } + + found: + switch (gpi) { + case 0b0000: /* no access */ + break; + case 0b1111: /* all access */ + return true; + case 0b1000: + case 0b1001: + case 0b1010: + case 0b1011: + if (pspace == (gpi & 3)) { + return true; + } + break; + default: + goto fault_walk; /* reserved */ + } + + fi->gpcf = GPCF_Fail; + goto fault_common; + fault_eabt: + fi->gpcf = GPCF_EABT; + goto fault_common; + fault_size: + fi->gpcf = GPCF_AddressSize; + goto fault_common; + fault_walk: + fi->gpcf = GPCF_Walk; + fault_common: + fi->level = level; + fi->paddr = paddress; + fi->paddr_space = pspace; + return false; +} + static bool S2_attrs_are_device(uint64_t hcr, uint8_t attrs) { /* @@ -242,10 +439,10 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, }; GetPhysAddrResult s2 = { }; - if (get_phys_addr_with_struct(env, &s2ptw, addr, - MMU_DATA_LOAD, &s2, fi)) { + if (get_phys_addr_gpc(env, &s2ptw, addr, MMU_DATA_LOAD, &s2, fi)) { goto fail; } + ptw->out_phys = s2.f.phys_addr; pte_attrs = s2.cacheattrs.attrs; pte_secure = s2.f.attrs.secure; @@ -304,6 +501,9 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, fail: assert(fi->type != ARMFault_None); + if (fi->type == ARMFault_GPCFOnOutput) { + fi->type = ARMFault_GPCFOnWalk; + } fi->s2addr = addr; fi->stage2 = true; fi->s1ptw = true; @@ -2731,7 +2931,7 @@ static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address, ARMMMUFaultInfo *fi) { uint8_t memattr = 0x00; /* Device nGnRnE */ - uint8_t shareability = 0; /* non-sharable */ + uint8_t shareability = 0; /* non-shareable */ int r_el; switch (mmu_idx) { @@ -2790,7 +2990,7 @@ static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address, } else { memattr = 0x44; /* Normal, NC, No */ } - shareability = 2; /* outer sharable */ + shareability = 2; /* outer shareable */ } result->cacheattrs.is_s2_format = false; break; @@ -2818,7 +3018,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, ARMSecuritySpace ipa_space, s2walk_space; uint64_t hcr; - ret = get_phys_addr_with_struct(env, ptw, address, access_type, result, fi); + ret = get_phys_addr_nogpc(env, ptw, address, access_type, result, fi); /* If S1 fails, return early. */ if (ret) { @@ -2855,7 +3055,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, cacheattrs1 = result->cacheattrs; memset(result, 0, sizeof(*result)); - ret = get_phys_addr_with_struct(env, ptw, ipa, access_type, result, fi); + ret = get_phys_addr_nogpc(env, ptw, ipa, access_type, result, fi); fi->s2addr = ipa; /* Combine the S1 and S2 perms. */ @@ -2915,7 +3115,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, return false; } -static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, +static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, target_ulong address, MMUAccessType access_type, GetPhysAddrResult *result, @@ -3039,6 +3239,23 @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, } } +static bool get_phys_addr_gpc(CPUARMState *env, S1Translate *ptw, + target_ulong address, + MMUAccessType access_type, + GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) +{ + if (get_phys_addr_nogpc(env, ptw, address, access_type, result, fi)) { + return true; + } + if (!granule_protection_check(env, result->f.phys_addr, + result->f.attrs.space, fi)) { + fi->type = ARMFault_GPCFOnOutput; + return true; + } + return false; +} + bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_idx, bool is_secure, GetPhysAddrResult *result, @@ -3049,8 +3266,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, .in_secure = is_secure, .in_space = arm_secure_to_space(is_secure), }; - return get_phys_addr_with_struct(env, &ptw, address, access_type, - result, fi); + return get_phys_addr_gpc(env, &ptw, address, access_type, result, fi); } bool get_phys_addr(CPUARMState *env, target_ulong address, @@ -3120,8 +3336,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, ptw.in_space = ss; ptw.in_secure = arm_space_is_secure(ss); - return get_phys_addr_with_struct(env, &ptw, address, access_type, - result, fi); + return get_phys_addr_gpc(env, &ptw, address, access_type, result, fi); } hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, @@ -3141,7 +3356,7 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, ARMMMUFaultInfo fi = {}; bool ret; - ret = get_phys_addr_with_struct(env, &ptw, addr, MMU_DATA_LOAD, &res, &fi); + ret = get_phys_addr_gpc(env, &ptw, addr, MMU_DATA_LOAD, &res, &fi); *attrs = res.f.attrs; if (ret) { From patchwork Wed Feb 22 02:33:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655677 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp457014wrb; Tue, 21 Feb 2023 18:38:22 -0800 (PST) X-Google-Smtp-Source: AK7set8WY9533Cqb6AbF1+UmuFCbL3/ze7oJ40wNqiBJWjYqqmwMkcbFLSLhEjgQUk5WR9fFuq1w X-Received: by 2002:ad4:5bc5:0:b0:56e:a6f1:8db with SMTP id t5-20020ad45bc5000000b0056ea6f108dbmr10016504qvt.20.1677033501971; Tue, 21 Feb 2023 18:38:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677033501; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.34.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:34:12 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH NOTFORMERGE v3 24/25] target/arm: Enable RME for -cpu max Date: Tue, 21 Feb 2023 16:33:35 -1000 Message-Id: <20230222023336.915045-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1041; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1041.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add a cpu property to set GPCCR_EL3.L0GPTSZ, for testing various possible configurations. Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 4066950da1..70c173ee3d 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -672,6 +672,40 @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) cpu->isar.id_aa64mmfr0 = t; } +static void cpu_max_set_l0gptsz(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + uint32_t value; + + if (!visit_type_uint32(v, name, &value, errp)) { + return; + } + + /* Encode the value for the GPCCR_EL3 field. */ + switch (value) { + case 30: + case 34: + case 36: + case 39: + cpu->reset_l0gptsz = value - 30; + break; + default: + error_setg(errp, "invalid value for l0gptsz"); + error_append_hint(errp, "valid values are 30, 34, 36, 39\n"); + break; + } +} + +static void cpu_max_get_l0gptsz(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + uint32_t value = cpu->reset_l0gptsz + 30; + + visit_type_uint32(v, name, &value, errp); +} + static void aarch64_a57_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); @@ -1200,6 +1234,7 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ + t = FIELD_DP64(t, ID_AA64PFR0, RME, 1); /* FEAT_RME */ t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */ cpu->isar.id_aa64pfr0 = t; @@ -1301,6 +1336,8 @@ static void aarch64_max_initfn(Object *obj) object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq, cpu_max_set_sve_max_vq, NULL, NULL); qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property); + object_property_add(obj, "l0gptsz", "uint32", cpu_max_get_l0gptsz, + cpu_max_set_l0gptsz, NULL, NULL); } static const ARMCPUInfo aarch64_cpus[] = { From patchwork Wed Feb 22 02:33:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655672 Delivered-To: patch@linaro.org Received: by 2002:adf:a3c6:0:0:0:0:0 with SMTP id m6csp456789wrb; Tue, 21 Feb 2023 18:37:36 -0800 (PST) X-Google-Smtp-Source: AK7set+GPFAGoV+IyhwYPfWbXPRVmHWVDJoQg5g49rFMLsmYHqv5aFeYTvp4hbGl3o3I+yqgY7PS X-Received: by 2002:a05:622a:24b:b0:3b9:ca95:da6e with SMTP id c11-20020a05622a024b00b003b9ca95da6emr9639356qtx.44.1677033456370; Tue, 21 Feb 2023 18:37:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677033456; cv=none; d=google.com; s=arc-20160816; b=fXNKXHpnA0NJv/5171m1Ls5l860V5PRT2xucXa2otzYHNKcUP3uDgyG+Q1LM07JBFo wwDNpqsJNMrPjAcefMIS7f1wUkGNU2UTJIDCpBBkszGzTTyK9ANlrMX/MF7sxwVD7A/P BRfbrVMPNBxVerlJw3y0Qqp+r/ALAzhVmYGuBkJZYadrbqr5tqjPA666PrRo4sRo1wUo aACihXM9KxglhAszdo5yFCahlzCSMVK41Em3yb9JQ31+DaAue/KAEZdajz+20eLq0LTz n7JCTXt5RzGq6g8gl8nbLNXj1Sq2+nZ+e8mwjFhBugPdE9uFHHXB3jjGszyA78oKGiHa LunQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=H9Qr7wA8wSIkfPgh/j+3hKBpjrPyoBLV3ksLdpb2kIs=; b=ckTjZHIIgcW/zVsv0n5Sq2C5VtIurVXDhvBazIJbkEh2Gp2Qom46oUp2+Ldl3Jw2eP WpaWiH4wrfpr0UVUYa+ooa0WW09BJ+rEemCQ7nk623qkYzI0gHVe3vg+lWvK0b7SofJZ lczdu6xD2BbWDOHIjy2S5kyFQgXbWtZScQUqssFN4Cfa5F/rEe7cdOA9AAryKpNFjQRp VbpuT8Ig1K5p6xcVCog6A4iKejBagmW7Rfm7n2yD7DzxzRjWxBwTU+FBJ5Ceo+MXGPQp zhQ2PXocAaSXhiiXm07UWD6tkW9CRA6hki7SMPEO4+1cD608MVqtxPfgAq267cmpw3sn 9M4Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dC2VB4qK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.34.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:34:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH NOTFORMERGE v3 25/25] hw/arm/virt: Add some memory for Realm Management Monitor Date: Tue, 21 Feb 2023 16:33:36 -1000 Message-Id: <20230222023336.915045-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This is arbitrary, but used by the Huawei TF-A test code. Signed-off-by: Richard Henderson --- include/hw/arm/virt.h | 2 ++ hw/arm/virt.c | 43 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index e1ddbea96b..5c0c8a67e4 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -86,6 +86,7 @@ enum { VIRT_ACPI_GED, VIRT_NVDIMM_ACPI, VIRT_PVTIME, + VIRT_RMM_MEM, VIRT_LOWMEMMAP_LAST, }; @@ -159,6 +160,7 @@ struct VirtMachineState { bool virt; bool ras; bool mte; + bool rmm; bool dtb_randomness; OnOffAuto acpi; VirtGICType gic_version; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index ac626b3bef..067f16cd77 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -159,6 +159,7 @@ static const MemMapEntry base_memmap[] = { /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, + [VIRT_RMM_MEM] = { 0x0f000000, 0x00100000 }, [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, @@ -1602,6 +1603,25 @@ static void create_secure_ram(VirtMachineState *vms, g_free(nodename); } +static void create_rmm_ram(VirtMachineState *vms, + MemoryRegion *sysmem, + MemoryRegion *tag_sysmem) +{ + MemoryRegion *rmm_ram = g_new(MemoryRegion, 1); + hwaddr base = vms->memmap[VIRT_RMM_MEM].base; + hwaddr size = vms->memmap[VIRT_RMM_MEM].size; + + memory_region_init_ram(rmm_ram, NULL, "virt.rmm-ram", size, + &error_fatal); + memory_region_add_subregion(sysmem, base, rmm_ram); + + /* do not fill in fdt to hide rmm from normal world guest */ + + if (tag_sysmem) { + create_tag_ram(tag_sysmem, base, size, "mach-virt.rmm-tag"); + } +} + static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) { const VirtMachineState *board = container_of(binfo, VirtMachineState, @@ -2283,6 +2303,10 @@ static void machvirt_init(MachineState *machine) machine->ram_size, "mach-virt.tag"); } + if (vms->rmm) { + create_rmm_ram(vms, sysmem, tag_sysmem); + } + vms->highmem_ecam &= (!firmware_loaded || aarch64); create_rtc(vms); @@ -2562,6 +2586,20 @@ static void virt_set_mte(Object *obj, bool value, Error **errp) vms->mte = value; } +static bool virt_get_rmm(Object *obj, Error **errp) +{ + VirtMachineState *vms = VIRT_MACHINE(obj); + + return vms->rmm; +} + +static void virt_set_rmm(Object *obj, bool value, Error **errp) +{ + VirtMachineState *vms = VIRT_MACHINE(obj); + + vms->rmm = value; +} + static char *virt_get_gic_version(Object *obj, Error **errp) { VirtMachineState *vms = VIRT_MACHINE(obj); @@ -3115,6 +3153,11 @@ static void virt_machine_class_init(ObjectClass *oc, void *data) "guest CPU which implements the ARM " "Memory Tagging Extension"); + object_class_property_add_bool(oc, "rmm", virt_get_rmm, virt_set_rmm); + object_class_property_set_description(oc, "rmm", + "Set on/off to enable/disable ram " + "for the Realm Management Monitor"); + object_class_property_add_bool(oc, "its", virt_get_its, virt_set_its); object_class_property_set_description(oc, "its",