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Wysocki" , Viresh Kumar , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH 1/2] dt-bindings: cpufreq: qcom-hw: add a compatible for sa8775p Date: Tue, 21 Feb 2023 16:05:42 +0100 Message-Id: <20230221150543.283487-2-brgl@bgdev.pl> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230221150543.283487-1-brgl@bgdev.pl> References: <20230221150543.283487-1-brgl@bgdev.pl> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Bartosz Golaszewski Add the compatible for the cpufreq engine present on sa8775p platforms. Signed-off-by: Bartosz Golaszewski --- Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml index e4aa8c67d532..92693c33edf9 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -26,6 +26,7 @@ properties: items: - enum: - qcom,qdu1000-cpufreq-epss + - qcom,sa8775p-cpufreq-epss - qcom,sc7280-cpufreq-epss - qcom,sc8280xp-cpufreq-epss - qcom,sm6375-cpufreq-epss From patchwork Tue Feb 21 15:05:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 655625 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79DFBC6FA9D for ; Tue, 21 Feb 2023 15:05:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234675AbjBUPF5 (ORCPT ); Tue, 21 Feb 2023 10:05:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58266 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234653AbjBUPFz (ORCPT ); Tue, 21 Feb 2023 10:05:55 -0500 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D49EE76AC for ; Tue, 21 Feb 2023 07:05:53 -0800 (PST) Received: by mail-wm1-x32e.google.com with SMTP id p16so1273444wmq.5 for ; Tue, 21 Feb 2023 07:05:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=l1i149aTLNTOLkmkyvTEcAaXgMJdiI2YD/KUpWRXaaA=; b=nZImdhglNUEScK1GjzBwIFIncyE6SLWbEYg5kAfxR5dt/o6o3T53UL11KPwyLmN1Bs ebCn35FX8cxCiSk8xT7aSiaL+r2C3tY2si8M+bLoP7Pjrx042y/pFpAMj00Kyzi9dLIr N/V3qjYZTmP7jEO8Jyxb/Zvvsb3Hkz0bM/yGP/tuO3vldxIrUmONOBO5CSZY19CbdzBo zGyZDidXxOmxH2DVSG56Lf4G7bD3oudCYtJtR8yql76sQOWET1YsUIdKzeE4nzIVR56n WLLNElor9meGT8lXFAzeCP/1oWTNeXJ70lmNoU2JzogbX/hZDx/qyUT6MBdMO5H+rqfE eTUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=l1i149aTLNTOLkmkyvTEcAaXgMJdiI2YD/KUpWRXaaA=; b=qrHpD8ksXH5MP4pKrT6TFqMuKtYev/Sztf2udimWSQqXI7a3UGWSvF+Bj0mX7D3+0W UB8ciOIlyYxHNr96zwzSzEutEy8mmMyRl3qzxM5csaFPT28vupdyH3cTk6GjO37vbcLP FJWKl1DZuvKr98u/hpxNCD4uWG/vwTIeilmvlXctOgtkjpU8NZwxa4VoSykH1CmAz1ye AjCrb6GvTWvb6yP8VaB9OZ5QeX6ydjJke5ivs8g1/eQlnYYuK6ESNEhy2EnhwMGkpWhY dXiXYUl8UmXdSLboAxLxA5ZcLmKh15lYOuenzzyRexTc6jN5V6jkV0q3XbP9nFC3UonU VYoQ== X-Gm-Message-State: AO0yUKXlwUb7Nc8mp10RtyJWZFiZR2fHAb37z4azeXZhAw6YD0eS9geT bxE99b2AAB6fKLoeZDLXhNbB1OSLZd5zygP7 X-Google-Smtp-Source: AK7set8Ntvu4HilU/sI4URZx0iaMNEdxXnAvFGiSMkOuQcwlad5ePdFRr1QT6eVqPEY8Zy7uXc4BjQ== X-Received: by 2002:a05:600c:448a:b0:3e1:97d:612e with SMTP id e10-20020a05600c448a00b003e1097d612emr9154458wmo.29.1676991952314; Tue, 21 Feb 2023 07:05:52 -0800 (PST) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:4c24:722f:312a:76c4]) by smtp.gmail.com with ESMTPSA id n30-20020a05600c3b9e00b003e206cc7237sm5331687wms.24.2023.02.21.07.05.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 07:05:51 -0800 (PST) From: Bartosz Golaszewski To: "Rafael J . Wysocki" , Viresh Kumar , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH 2/2] arm64: dts: qcom: sa8775p: add cpufreq node Date: Tue, 21 Feb 2023 16:05:43 +0100 Message-Id: <20230221150543.283487-3-brgl@bgdev.pl> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230221150543.283487-1-brgl@bgdev.pl> References: <20230221150543.283487-1-brgl@bgdev.pl> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Bartosz Golaszewski Add a node for the cpufreq engine and specify the frequency domains for all CPUs. Signed-off-by: Bartosz Golaszewski --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index ce5976e36aee..5e2bc67b3178 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -37,6 +37,7 @@ CPU0: cpu@0 { compatible = "qcom,kryo"; reg = <0x0 0x0>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "cache"; @@ -52,6 +53,7 @@ CPU1: cpu@100 { compatible = "qcom,kryo"; reg = <0x0 0x100>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&L2_1>; L2_1: l2-cache { compatible = "cache"; @@ -64,6 +66,7 @@ CPU2: cpu@200 { compatible = "qcom,kryo"; reg = <0x0 0x200>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&L2_2>; L2_2: l2-cache { compatible = "cache"; @@ -76,6 +79,7 @@ CPU3: cpu@300 { compatible = "qcom,kryo"; reg = <0x0 0x300>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&L2_3>; L2_3: l2-cache { compatible = "cache"; @@ -88,6 +92,7 @@ CPU4: cpu@10000 { compatible = "qcom,kryo"; reg = <0x0 0x10000>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; next-level-cache = <&L2_4>; L2_4: l2-cache { compatible = "cache"; @@ -104,6 +109,7 @@ CPU5: cpu@10100 { compatible = "qcom,kryo"; reg = <0x0 0x10100>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; next-level-cache = <&L2_5>; L2_5: l2-cache { compatible = "cache"; @@ -116,6 +122,7 @@ CPU6: cpu@10200 { compatible = "qcom,kryo"; reg = <0x0 0x10200>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; next-level-cache = <&L2_6>; L2_6: l2-cache { compatible = "cache"; @@ -128,6 +135,7 @@ CPU7: cpu@10300 { compatible = "qcom,kryo"; reg = <0x0 0x10300>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; next-level-cache = <&L2_7>; L2_7: l2-cache { compatible = "cache"; @@ -731,6 +739,19 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells = <1>; }; + cpufreq_hw: cpufreq@18591000 { + compatible = "qcom,sa8775p-cpufreq-epss", + "qcom,cpufreq-epss"; + reg = <0x0 0x18591000 0x0 0x1000>, + <0x0 0x18593000 0x0 0x1000>; + reg-names = "freq-domain0", "freq-domain1"; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + }; + tlmm: pinctrl@f000000 { compatible = "qcom,sa8775p-tlmm"; reg = <0x0 0xf000000 0x0 0x1000000>;