From patchwork Tue Feb 21 19:08:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evan Green X-Patchwork-Id: 655477 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F3C9C64EC7 for ; Tue, 21 Feb 2023 19:10:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229997AbjBUTJ7 (ORCPT ); Tue, 21 Feb 2023 14:09:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32814 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230011AbjBUTJt (ORCPT ); Tue, 21 Feb 2023 14:09:49 -0500 Received: from mail-pl1-x629.google.com (mail-pl1-x629.google.com [IPv6:2607:f8b0:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7BB7F2FCC4 for ; Tue, 21 Feb 2023 11:09:34 -0800 (PST) Received: by mail-pl1-x629.google.com with SMTP id bh1so6166229plb.11 for ; Tue, 21 Feb 2023 11:09:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=h4Uz8oInxrBVxdaNnCcRWzHNxIOpRGtwNCns0Csq24o=; b=5CAoJgBaxdsOsjJt2ARXvUAXbErBCB8xjhCRl/00BIB0m+EhiyRU3XZSidGXeE83LK +FRtmHOsemIRPQ/ytDa3xi5xQubu32PfYgOv1GgPMlj8GBuwVt+RKxxhFTTWQgWjLJbH yVO3GZ6Dl6SpXYXL2PGhBsRPKRHAhmrU/mwngeMnCLv+FnBGjy3WnIrrSyPN0GYSZyeo jlCTpaCtDtXLMs75oLfPUTbR6nm5b9ZUPk1JPx7ptYDFvYWEZy841oLGvuf8Tn0KoTed qy2eDXvLc8W845c/ngN141rjsv76Zdue6P6r4RixeblK422nJLdTcHMc3EqqMVYNZDZP 9Iwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=h4Uz8oInxrBVxdaNnCcRWzHNxIOpRGtwNCns0Csq24o=; b=ry6Bo47Rv7MvEKN15rheKFWlzGgEyZGYhnlrSgpPSB6ztxoY3gWJUBCa3zVUK3iM4G /5OgHom7nAeOtgk5tRfSg4LF3dYcvCZKQm+oDXS83yOLwbjN4rmGJRle5jYavbpQ9nlx X2aXHdNi1pRNXmlGyFpXEXhpJBsCbupqgEpTDNdqMwxcVB48VwiNmAmOsvKiBdt55zts ySb48CXMfQ3RXZxbaOZxJxliZNn7a2Of4/voegFEWy0ooUE+/nlTOezH66AxDPqHA8/t CDkqgzRmGCbzmfuhOxjbFi/sIUqvYGZuWnOHWZRMXk+L+FSxcaBxEpPKIurS/bfwsf+y PniA== X-Gm-Message-State: AO0yUKUyACRA8SaJrbZNCP2bAOlwCp+0QtjxoKCe/80OBScpT13j558i 25LoEVFnzMqldibuPEX/sFAVvg== X-Google-Smtp-Source: AK7set+it96+69j6MVRhBhTTnrkru5X6NVtEvUnH9vgxsurcSiwoU7po5lf6y/VdEVorq3aQjAMmjw== X-Received: by 2002:a17:902:c407:b0:19b:dbf7:f9d1 with SMTP id k7-20020a170902c40700b0019bdbf7f9d1mr6464689plk.37.1677006573615; Tue, 21 Feb 2023 11:09:33 -0800 (PST) Received: from evan.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id b16-20020a170902b61000b0019602b2c00csm1583863pls.175.2023.02.21.11.09.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 11:09:33 -0800 (PST) From: Evan Green To: Palmer Dabbelt Cc: heiko@sntech.de, Conor Dooley , slewis@rivosinc.com, vineetg@rivosinc.com, Evan Green , Albert Ou , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v3 4/7] dt-bindings: Add RISC-V misaligned access performance Date: Tue, 21 Feb 2023 11:08:55 -0800 Message-Id: <20230221190858.3159617-5-evan@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230221190858.3159617-1-evan@rivosinc.com> References: <20230221190858.3159617-1-evan@rivosinc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Palmer Dabbelt This key allows device trees to specify the performance of misaligned accesses to main memory regions from each CPU in the system. Signed-off-by: Palmer Dabbelt Signed-off-by: Evan Green --- Changes in v3: - Added | to description: to make dt-checker happy. Documentation/devicetree/bindings/riscv/cpus.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index c6720764e765..f79e9e5c5ee9 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -85,6 +85,21 @@ properties: $ref: "/schemas/types.yaml#/definitions/string" pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$ + riscv,misaligned-access-performance: + description: | + Identifies the performance of misaligned memory accesses to main memory + regions. There are three flavors of unaligned access performance: "emulated" + means that misaligned accesses are emulated via software and thus + extremely slow, "slow" means that misaligned accesses are supported by + hardware but still slower that aligned accesses sequences, and "fast" + means that misaligned accesses are as fast or faster than the + cooresponding aligned accesses sequences. + $ref: "/schemas/types.yaml#/definitions/string" + enum: + - emulated + - slow + - fast + # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false