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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id jk20-20020a170903331400b0019258bcf3ffsm1911676plb.56.2023.02.20.10.40.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 10:40:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, qemu-s390x@nongnu.org, Ilya Leoshkevich , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v4 01/27] target/s390x: Use tcg_constant_* in local contexts Date: Mon, 20 Feb 2023 08:40:26 -1000 Message-Id: <20230220184052.163465-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230220184052.163465-1-richard.henderson@linaro.org> References: <20230220184052.163465-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Replace tcg_const_* with tcg_constant_* in contexts where the free to remove is nearby. Reviewed-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 410 +++++++++++++---------------------- 1 file changed, 147 insertions(+), 263 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index ac5bd98f04..35e844ef3c 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -171,8 +171,6 @@ static uint64_t inline_branch_miss[CC_OP_MAX]; static void pc_to_link_info(TCGv_i64 out, DisasContext *s, uint64_t pc) { - TCGv_i64 tmp; - if (s->base.tb->flags & FLAG_MASK_32) { if (s->base.tb->flags & FLAG_MASK_64) { tcg_gen_movi_i64(out, pc); @@ -181,9 +179,7 @@ static void pc_to_link_info(TCGv_i64 out, DisasContext *s, uint64_t pc) pc |= 0x80000000; } assert(!(s->base.tb->flags & FLAG_MASK_64)); - tmp = tcg_const_i64(pc); - tcg_gen_deposit_i64(out, out, tmp, 0, 32); - tcg_temp_free_i64(tmp); + tcg_gen_deposit_i64(out, out, tcg_constant_i64(pc), 0, 32); } static TCGv_i64 psw_addr; @@ -360,11 +356,8 @@ static void per_branch(DisasContext *s, bool to_next) tcg_gen_movi_i64(gbea, s->base.pc_next); if (s->base.tb->flags & FLAG_MASK_PER) { - TCGv_i64 next_pc = to_next ? tcg_const_i64(s->pc_tmp) : psw_addr; + TCGv_i64 next_pc = to_next ? tcg_constant_i64(s->pc_tmp) : psw_addr; gen_helper_per_branch(cpu_env, gbea, next_pc); - if (to_next) { - tcg_temp_free_i64(next_pc); - } } #endif } @@ -382,9 +375,8 @@ static void per_branch_cond(DisasContext *s, TCGCond cond, gen_set_label(lab); } else { - TCGv_i64 pc = tcg_const_i64(s->base.pc_next); + TCGv_i64 pc = tcg_constant_i64(s->base.pc_next); tcg_gen_movcond_i64(cond, gbea, arg1, arg2, gbea, pc); - tcg_temp_free_i64(pc); } #endif } @@ -438,23 +430,17 @@ static int get_mem_index(DisasContext *s) static void gen_exception(int excp) { - TCGv_i32 tmp = tcg_const_i32(excp); - gen_helper_exception(cpu_env, tmp); - tcg_temp_free_i32(tmp); + gen_helper_exception(cpu_env, tcg_constant_i32(excp)); } static void gen_program_exception(DisasContext *s, int code) { - TCGv_i32 tmp; + /* Remember what pgm exeption this was. */ + tcg_gen_st_i32(tcg_constant_i32(code), cpu_env, + offsetof(CPUS390XState, int_pgm_code)); - /* Remember what pgm exception this was. */ - tmp = tcg_const_i32(code); - tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_code)); - tcg_temp_free_i32(tmp); - - tmp = tcg_const_i32(s->ilen); - tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_ilen)); - tcg_temp_free_i32(tmp); + tcg_gen_st_i32(tcg_constant_i32(s->ilen), cpu_env, + offsetof(CPUS390XState, int_pgm_ilen)); /* update the psw */ update_psw_addr(s); @@ -473,9 +459,7 @@ static inline void gen_illegal_opcode(DisasContext *s) static inline void gen_data_exception(uint8_t dxc) { - TCGv_i32 tmp = tcg_const_i32(dxc); - gen_helper_data_exception(cpu_env, tmp); - tcg_temp_free_i32(tmp); + gen_helper_data_exception(cpu_env, tcg_constant_i32(dxc)); } static inline void gen_trap(DisasContext *s) @@ -596,13 +580,13 @@ static void gen_op_calc_cc(DisasContext *s) switch (s->cc_op) { default: - dummy = tcg_const_i64(0); + dummy = tcg_constant_i64(0); /* FALLTHRU */ case CC_OP_ADD_64: case CC_OP_SUB_64: case CC_OP_ADD_32: case CC_OP_SUB_32: - local_cc_op = tcg_const_i32(s->cc_op); + local_cc_op = tcg_constant_i32(s->cc_op); break; case CC_OP_CONST0: case CC_OP_CONST1: @@ -675,13 +659,6 @@ static void gen_op_calc_cc(DisasContext *s) tcg_abort(); } - if (local_cc_op) { - tcg_temp_free_i32(local_cc_op); - } - if (dummy) { - tcg_temp_free_i64(dummy); - } - /* We now have cc in cc_op as constant */ set_cc_static(s); } @@ -1300,9 +1277,9 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, Most commonly we're single-stepping or some other condition that disables all use of goto_tb. Just update the PC and exit. */ - TCGv_i64 next = tcg_const_i64(s->pc_tmp); + TCGv_i64 next = tcg_constant_i64(s->pc_tmp); if (is_imm) { - cdest = tcg_const_i64(dest); + cdest = tcg_constant_i64(dest); } if (c->is_64) { @@ -1312,21 +1289,15 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, } else { TCGv_i32 t0 = tcg_temp_new_i32(); TCGv_i64 t1 = tcg_temp_new_i64(); - TCGv_i64 z = tcg_const_i64(0); + TCGv_i64 z = tcg_constant_i64(0); tcg_gen_setcond_i32(c->cond, t0, c->u.s32.a, c->u.s32.b); tcg_gen_extu_i32_i64(t1, t0); tcg_temp_free_i32(t0); tcg_gen_movcond_i64(TCG_COND_NE, psw_addr, t1, z, cdest, next); per_branch_cond(s, TCG_COND_NE, t1, z); tcg_temp_free_i64(t1); - tcg_temp_free_i64(z); } - if (is_imm) { - tcg_temp_free_i64(cdest); - } - tcg_temp_free_i64(next); - ret = DISAS_PC_UPDATED; } @@ -1410,10 +1381,9 @@ static DisasJumpType op_addc64(DisasContext *s, DisasOps *o) { compute_carry(s); - TCGv_i64 zero = tcg_const_i64(0); + TCGv_i64 zero = tcg_constant_i64(0); tcg_gen_add2_i64(o->out, cc_src, o->in1, zero, cc_src, zero); tcg_gen_add2_i64(o->out, cc_src, o->out, cc_src, o->in2, zero); - tcg_temp_free_i64(zero); return DISAS_NEXT; } @@ -2092,9 +2062,8 @@ static DisasJumpType op_clc(DisasContext *s, DisasOps *o) tcg_gen_qemu_ld64(cc_dst, o->in2, get_mem_index(s)); break; default: - vl = tcg_const_i32(l); + vl = tcg_constant_i32(l); gen_helper_clc(cc_op, cpu_env, vl, o->addr1, o->in2); - tcg_temp_free_i32(vl); set_cc_static(s); return DISAS_NEXT; } @@ -2114,11 +2083,9 @@ static DisasJumpType op_clcl(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } - t1 = tcg_const_i32(r1); - t2 = tcg_const_i32(r2); + t1 = tcg_constant_i32(r1); + t2 = tcg_constant_i32(r2); gen_helper_clcl(cc_op, cpu_env, t1, t2); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); set_cc_static(s); return DISAS_NEXT; } @@ -2135,11 +2102,9 @@ static DisasJumpType op_clcle(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } - t1 = tcg_const_i32(r1); - t3 = tcg_const_i32(r3); + t1 = tcg_constant_i32(r1); + t3 = tcg_constant_i32(r3); gen_helper_clcle(cc_op, cpu_env, t1, o->in2, t3); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t3); set_cc_static(s); return DISAS_NEXT; } @@ -2156,24 +2121,22 @@ static DisasJumpType op_clclu(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } - t1 = tcg_const_i32(r1); - t3 = tcg_const_i32(r3); + t1 = tcg_constant_i32(r1); + t3 = tcg_constant_i32(r3); gen_helper_clclu(cc_op, cpu_env, t1, o->in2, t3); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t3); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_clm(DisasContext *s, DisasOps *o) { - TCGv_i32 m3 = tcg_const_i32(get_field(s, m3)); + TCGv_i32 m3 = tcg_constant_i32(get_field(s, m3)); TCGv_i32 t1 = tcg_temp_new_i32(); + tcg_gen_extrl_i64_i32(t1, o->in1); gen_helper_clm(cc_op, cpu_env, t1, m3, o->in2); set_cc_static(s); tcg_temp_free_i32(t1); - tcg_temp_free_i32(m3); return DISAS_NEXT; } @@ -2251,14 +2214,13 @@ static DisasJumpType op_cdsg(DisasContext *s, DisasOps *o) static DisasJumpType op_csst(DisasContext *s, DisasOps *o) { int r3 = get_field(s, r3); - TCGv_i32 t_r3 = tcg_const_i32(r3); + TCGv_i32 t_r3 = tcg_constant_i32(r3); if (tb_cflags(s->base.tb) & CF_PARALLEL) { gen_helper_csst_parallel(cc_op, cpu_env, t_r3, o->addr1, o->in2); } else { gen_helper_csst(cc_op, cpu_env, t_r3, o->addr1, o->in2); } - tcg_temp_free_i32(t_r3); set_cc_static(s); return DISAS_NEXT; @@ -2356,9 +2318,9 @@ static DisasJumpType op_cuXX(DisasContext *s, DisasOps *o) m3 = 0; } - tr1 = tcg_const_i32(r1); - tr2 = tcg_const_i32(r2); - chk = tcg_const_i32(m3); + tr1 = tcg_constant_i32(r1); + tr2 = tcg_constant_i32(r2); + chk = tcg_constant_i32(m3); switch (s->insn->data) { case 12: @@ -2383,9 +2345,6 @@ static DisasJumpType op_cuXX(DisasContext *s, DisasOps *o) g_assert_not_reached(); } - tcg_temp_free_i32(tr1); - tcg_temp_free_i32(tr2); - tcg_temp_free_i32(chk); set_cc_static(s); return DISAS_NEXT; } @@ -2393,15 +2352,11 @@ static DisasJumpType op_cuXX(DisasContext *s, DisasOps *o) #ifndef CONFIG_USER_ONLY static DisasJumpType op_diag(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r3 = tcg_const_i32(get_field(s, r3)); - TCGv_i32 func_code = tcg_const_i32(get_field(s, i2)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3)); + TCGv_i32 func_code = tcg_constant_i32(get_field(s, i2)); gen_helper_diag(cpu_env, r1, r3, func_code); - - tcg_temp_free_i32(func_code); - tcg_temp_free_i32(r3); - tcg_temp_free_i32(r1); return DISAS_NEXT; } #endif @@ -2512,18 +2467,13 @@ static DisasJumpType op_ex(DisasContext *s, DisasOps *o) update_cc_op(s); if (r1 == 0) { - v1 = tcg_const_i64(0); + v1 = tcg_constant_i64(0); } else { v1 = regs[r1]; } - ilen = tcg_const_i32(s->ilen); + ilen = tcg_constant_i32(s->ilen); gen_helper_ex(cpu_env, ilen, v1, o->in2); - tcg_temp_free_i32(ilen); - - if (r1 == 0) { - tcg_temp_free_i64(v1); - } return DISAS_PC_CC_UPDATED; } @@ -2674,12 +2624,11 @@ static DisasJumpType op_idte(DisasContext *s, DisasOps *o) TCGv_i32 m4; if (s390_has_feat(S390_FEAT_LOCAL_TLB_CLEARING)) { - m4 = tcg_const_i32(get_field(s, m4)); + m4 = tcg_constant_i32(get_field(s, m4)); } else { - m4 = tcg_const_i32(0); + m4 = tcg_constant_i32(0); } gen_helper_idte(cpu_env, o->in1, o->in2, m4); - tcg_temp_free_i32(m4); return DISAS_NEXT; } @@ -2688,12 +2637,11 @@ static DisasJumpType op_ipte(DisasContext *s, DisasOps *o) TCGv_i32 m4; if (s390_has_feat(S390_FEAT_LOCAL_TLB_CLEARING)) { - m4 = tcg_const_i32(get_field(s, m4)); + m4 = tcg_constant_i32(get_field(s, m4)); } else { - m4 = tcg_const_i32(0); + m4 = tcg_constant_i32(0); } gen_helper_ipte(cpu_env, o->in1, o->in2, m4); - tcg_temp_free_i32(m4); return DISAS_NEXT; } @@ -2749,16 +2697,12 @@ static DisasJumpType op_msa(DisasContext *s, DisasOps *o) g_assert_not_reached(); }; - t_r1 = tcg_const_i32(r1); - t_r2 = tcg_const_i32(r2); - t_r3 = tcg_const_i32(r3); - type = tcg_const_i32(s->insn->data); + t_r1 = tcg_constant_i32(r1); + t_r2 = tcg_constant_i32(r2); + t_r3 = tcg_constant_i32(r3); + type = tcg_constant_i32(s->insn->data); gen_helper_msa(cc_op, cpu_env, t_r1, t_r2, t_r3, type); set_cc_static(s); - tcg_temp_free_i32(t_r1); - tcg_temp_free_i32(t_r2); - tcg_temp_free_i32(t_r3); - tcg_temp_free_i32(type); return DISAS_NEXT; } @@ -3017,10 +2961,9 @@ static DisasJumpType op_loc(DisasContext *s, DisasOps *o) tcg_gen_extu_i32_i64(t, t32); tcg_temp_free_i32(t32); - z = tcg_const_i64(0); + z = tcg_constant_i64(0); tcg_gen_movcond_i64(TCG_COND_NE, o->out, t, z, o->in2, o->in1); tcg_temp_free_i64(t); - tcg_temp_free_i64(z); } return DISAS_NEXT; @@ -3029,11 +2972,10 @@ static DisasJumpType op_loc(DisasContext *s, DisasOps *o) #ifndef CONFIG_USER_ONLY static DisasJumpType op_lctl(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r3 = tcg_const_i32(get_field(s, r3)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3)); + gen_helper_lctl(cpu_env, r1, o->in2, r3); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r3); /* Exit to main loop to reevaluate s390_cpu_exec_interrupt. */ s->exit_to_mainloop = true; return DISAS_TOO_MANY; @@ -3041,11 +2983,10 @@ static DisasJumpType op_lctl(DisasContext *s, DisasOps *o) static DisasJumpType op_lctlg(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r3 = tcg_const_i32(get_field(s, r3)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3)); + gen_helper_lctlg(cpu_env, r1, o->in2, r3); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r3); /* Exit to main loop to reevaluate s390_cpu_exec_interrupt. */ s->exit_to_mainloop = true; return DISAS_TOO_MANY; @@ -3105,11 +3046,10 @@ static DisasJumpType op_lpswe(DisasContext *s, DisasOps *o) static DisasJumpType op_lam(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r3 = tcg_const_i32(get_field(s, r3)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3)); + gen_helper_lam(cpu_env, r1, o->in2, r3); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r3); return DISAS_NEXT; } @@ -3319,9 +3259,6 @@ static DisasJumpType op_lcbb(DisasContext *s, DisasOps *o) static DisasJumpType op_mc(DisasContext *s, DisasOps *o) { -#if !defined(CONFIG_USER_ONLY) - TCGv_i32 i2; -#endif const uint16_t monitor_class = get_field(s, i2); if (monitor_class & 0xff00) { @@ -3330,9 +3267,8 @@ static DisasJumpType op_mc(DisasContext *s, DisasOps *o) } #if !defined(CONFIG_USER_ONLY) - i2 = tcg_const_i32(monitor_class); - gen_helper_monitor_call(cpu_env, o->addr1, i2); - tcg_temp_free_i32(i2); + gen_helper_monitor_call(cpu_env, o->addr1, + tcg_constant_i32(monitor_class)); #endif /* Defaults to a NOP. */ return DISAS_NEXT; @@ -3396,9 +3332,9 @@ static DisasJumpType op_movx(DisasContext *s, DisasOps *o) static DisasJumpType op_mvc(DisasContext *s, DisasOps *o) { - TCGv_i32 l = tcg_const_i32(get_field(s, l1)); + TCGv_i32 l = tcg_constant_i32(get_field(s, l1)); + gen_helper_mvc(cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); return DISAS_NEXT; } @@ -3410,9 +3346,9 @@ static DisasJumpType op_mvcrl(DisasContext *s, DisasOps *o) static DisasJumpType op_mvcin(DisasContext *s, DisasOps *o) { - TCGv_i32 l = tcg_const_i32(get_field(s, l1)); + TCGv_i32 l = tcg_constant_i32(get_field(s, l1)); + gen_helper_mvcin(cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); return DISAS_NEXT; } @@ -3428,11 +3364,9 @@ static DisasJumpType op_mvcl(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } - t1 = tcg_const_i32(r1); - t2 = tcg_const_i32(r2); + t1 = tcg_constant_i32(r1); + t2 = tcg_constant_i32(r2); gen_helper_mvcl(cc_op, cpu_env, t1, t2); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); set_cc_static(s); return DISAS_NEXT; } @@ -3449,11 +3383,9 @@ static DisasJumpType op_mvcle(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } - t1 = tcg_const_i32(r1); - t3 = tcg_const_i32(r3); + t1 = tcg_constant_i32(r1); + t3 = tcg_constant_i32(r3); gen_helper_mvcle(cc_op, cpu_env, t1, o->in2, t3); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t3); set_cc_static(s); return DISAS_NEXT; } @@ -3470,11 +3402,9 @@ static DisasJumpType op_mvclu(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } - t1 = tcg_const_i32(r1); - t3 = tcg_const_i32(r3); + t1 = tcg_constant_i32(r1); + t3 = tcg_constant_i32(r3); gen_helper_mvclu(cc_op, cpu_env, t1, o->in2, t3); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t3); set_cc_static(s); return DISAS_NEXT; } @@ -3509,49 +3439,45 @@ static DisasJumpType op_mvcs(DisasContext *s, DisasOps *o) static DisasJumpType op_mvn(DisasContext *s, DisasOps *o) { - TCGv_i32 l = tcg_const_i32(get_field(s, l1)); + TCGv_i32 l = tcg_constant_i32(get_field(s, l1)); + gen_helper_mvn(cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); return DISAS_NEXT; } static DisasJumpType op_mvo(DisasContext *s, DisasOps *o) { - TCGv_i32 l = tcg_const_i32(get_field(s, l1)); + TCGv_i32 l = tcg_constant_i32(get_field(s, l1)); + gen_helper_mvo(cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); return DISAS_NEXT; } static DisasJumpType op_mvpg(DisasContext *s, DisasOps *o) { - TCGv_i32 t1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 t2 = tcg_const_i32(get_field(s, r2)); + TCGv_i32 t1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 t2 = tcg_constant_i32(get_field(s, r2)); gen_helper_mvpg(cc_op, cpu_env, regs[0], t1, t2); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_mvst(DisasContext *s, DisasOps *o) { - TCGv_i32 t1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 t2 = tcg_const_i32(get_field(s, r2)); + TCGv_i32 t1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 t2 = tcg_constant_i32(get_field(s, r2)); gen_helper_mvst(cc_op, cpu_env, t1, t2); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_mvz(DisasContext *s, DisasOps *o) { - TCGv_i32 l = tcg_const_i32(get_field(s, l1)); + TCGv_i32 l = tcg_constant_i32(get_field(s, l1)); + gen_helper_mvz(cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); return DISAS_NEXT; } @@ -3637,13 +3563,12 @@ static DisasJumpType op_msdb(DisasContext *s, DisasOps *o) static DisasJumpType op_nabs(DisasContext *s, DisasOps *o) { - TCGv_i64 z, n; - z = tcg_const_i64(0); - n = tcg_temp_new_i64(); + TCGv_i64 z = tcg_constant_i64(0); + TCGv_i64 n = tcg_temp_new_i64(); + tcg_gen_neg_i64(n, o->in2); tcg_gen_movcond_i64(TCG_COND_GE, o->out, o->in2, z, n, o->in2); tcg_temp_free_i64(n); - tcg_temp_free_i64(z); return DISAS_NEXT; } @@ -3668,9 +3593,9 @@ static DisasJumpType op_nabsf128(DisasContext *s, DisasOps *o) static DisasJumpType op_nc(DisasContext *s, DisasOps *o) { - TCGv_i32 l = tcg_const_i32(get_field(s, l1)); + TCGv_i32 l = tcg_constant_i32(get_field(s, l1)); + gen_helper_nc(cc_op, cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); set_cc_static(s); return DISAS_NEXT; } @@ -3702,9 +3627,9 @@ static DisasJumpType op_negf128(DisasContext *s, DisasOps *o) static DisasJumpType op_oc(DisasContext *s, DisasOps *o) { - TCGv_i32 l = tcg_const_i32(get_field(s, l1)); + TCGv_i32 l = tcg_constant_i32(get_field(s, l1)); + gen_helper_oc(cc_op, cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); set_cc_static(s); return DISAS_NEXT; } @@ -3754,9 +3679,9 @@ static DisasJumpType op_oi(DisasContext *s, DisasOps *o) static DisasJumpType op_pack(DisasContext *s, DisasOps *o) { - TCGv_i32 l = tcg_const_i32(get_field(s, l1)); + TCGv_i32 l = tcg_constant_i32(get_field(s, l1)); + gen_helper_pack(cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); return DISAS_NEXT; } @@ -3770,9 +3695,8 @@ static DisasJumpType op_pka(DisasContext *s, DisasOps *o) gen_program_exception(s, PGM_SPECIFICATION); return DISAS_NORETURN; } - l = tcg_const_i32(l2); + l = tcg_constant_i32(l2); gen_helper_pka(cpu_env, o->addr1, o->in2, l); - tcg_temp_free_i32(l); return DISAS_NEXT; } @@ -3786,9 +3710,8 @@ static DisasJumpType op_pku(DisasContext *s, DisasOps *o) gen_program_exception(s, PGM_SPECIFICATION); return DISAS_NORETURN; } - l = tcg_const_i32(l2); + l = tcg_constant_i32(l2); gen_helper_pku(cpu_env, o->addr1, o->in2, l); - tcg_temp_free_i32(l); return DISAS_NEXT; } @@ -4035,9 +3958,8 @@ static DisasJumpType op_sam(DisasContext *s, DisasOps *o) } s->pc_tmp &= mask; - tsam = tcg_const_i64(sam); + tsam = tcg_constant_i64(sam); tcg_gen_deposit_i64(psw_mask, psw_mask, tsam, 31, 2); - tcg_temp_free_i64(tsam); /* Always exit the TB, since we (may have) changed execution mode. */ return DISAS_TOO_MANY; @@ -4096,12 +4018,11 @@ static DisasJumpType op_servc(DisasContext *s, DisasOps *o) static DisasJumpType op_sigp(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r3 = tcg_const_i32(get_field(s, r3)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3)); + gen_helper_sigp(cc_op, cpu_env, o->in2, r1, r3); set_cc_static(s); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r3); return DISAS_NEXT; } #endif @@ -4370,21 +4291,19 @@ static DisasJumpType op_stckc(DisasContext *s, DisasOps *o) static DisasJumpType op_stctg(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r3 = tcg_const_i32(get_field(s, r3)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3)); + gen_helper_stctg(cpu_env, r1, o->in2, r3); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r3); return DISAS_NEXT; } static DisasJumpType op_stctl(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r3 = tcg_const_i32(get_field(s, r3)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3)); + gen_helper_stctl(cpu_env, r1, o->in2, r3); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r3); return DISAS_NEXT; } @@ -4611,11 +4530,10 @@ static DisasJumpType op_st64(DisasContext *s, DisasOps *o) static DisasJumpType op_stam(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r3 = tcg_const_i32(get_field(s, r3)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3)); + gen_helper_stam(cpu_env, r1, o->in2, r3); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r3); return DISAS_NEXT; } @@ -4673,7 +4591,7 @@ static DisasJumpType op_stm(DisasContext *s, DisasOps *o) int r1 = get_field(s, r1); int r3 = get_field(s, r3); int size = s->insn->data; - TCGv_i64 tsize = tcg_const_i64(size); + TCGv_i64 tsize = tcg_constant_i64(size); while (1) { if (size == 8) { @@ -4688,7 +4606,6 @@ static DisasJumpType op_stm(DisasContext *s, DisasOps *o) r1 = (r1 + 1) & 15; } - tcg_temp_free_i64(tsize); return DISAS_NEXT; } @@ -4697,8 +4614,8 @@ static DisasJumpType op_stmh(DisasContext *s, DisasOps *o) int r1 = get_field(s, r1); int r3 = get_field(s, r3); TCGv_i64 t = tcg_temp_new_i64(); - TCGv_i64 t4 = tcg_const_i64(4); - TCGv_i64 t32 = tcg_const_i64(32); + TCGv_i64 t4 = tcg_constant_i64(4); + TCGv_i64 t32 = tcg_constant_i64(32); while (1) { tcg_gen_shl_i64(t, regs[r1], t32); @@ -4711,8 +4628,6 @@ static DisasJumpType op_stmh(DisasContext *s, DisasOps *o) } tcg_temp_free_i64(t); - tcg_temp_free_i64(t4); - tcg_temp_free_i64(t32); return DISAS_NEXT; } @@ -4731,26 +4646,20 @@ static DisasJumpType op_stpq(DisasContext *s, DisasOps *o) static DisasJumpType op_srst(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r2 = tcg_const_i32(get_field(s, r2)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2)); gen_helper_srst(cpu_env, r1, r2); - - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r2); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_srstu(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r2 = tcg_const_i32(get_field(s, r2)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2)); gen_helper_srstu(cpu_env, r1, r2); - - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r2); set_cc_static(s); return DISAS_NEXT; } @@ -4808,10 +4717,9 @@ static DisasJumpType op_subb64(DisasContext *s, DisasOps *o) * Borrow is {0, -1}, so add to subtract; replicate the * borrow input to produce 128-bit -1 for the addition. */ - TCGv_i64 zero = tcg_const_i64(0); + TCGv_i64 zero = tcg_constant_i64(0); tcg_gen_add2_i64(o->out, cc_src, o->in1, zero, cc_src, cc_src); tcg_gen_sub2_i64(o->out, cc_src, o->out, cc_src, o->in2, zero); - tcg_temp_free_i64(zero); return DISAS_NEXT; } @@ -4823,13 +4731,11 @@ static DisasJumpType op_svc(DisasContext *s, DisasOps *o) update_psw_addr(s); update_cc_op(s); - t = tcg_const_i32(get_field(s, i1) & 0xff); + t = tcg_constant_i32(get_field(s, i1) & 0xff); tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_code)); - tcg_temp_free_i32(t); - t = tcg_const_i32(s->ilen); + t = tcg_constant_i32(s->ilen); tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_ilen)); - tcg_temp_free_i32(t); gen_exception(EXCP_SVC); return DISAS_NORETURN; @@ -4886,18 +4792,18 @@ static DisasJumpType op_tprot(DisasContext *s, DisasOps *o) static DisasJumpType op_tp(DisasContext *s, DisasOps *o) { - TCGv_i32 l1 = tcg_const_i32(get_field(s, l1) + 1); + TCGv_i32 l1 = tcg_constant_i32(get_field(s, l1) + 1); + gen_helper_tp(cc_op, cpu_env, o->addr1, l1); - tcg_temp_free_i32(l1); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_tr(DisasContext *s, DisasOps *o) { - TCGv_i32 l = tcg_const_i32(get_field(s, l1)); + TCGv_i32 l = tcg_constant_i32(get_field(s, l1)); + gen_helper_tr(cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); set_cc_static(s); return DISAS_NEXT; } @@ -4915,27 +4821,27 @@ static DisasJumpType op_tre(DisasContext *s, DisasOps *o) static DisasJumpType op_trt(DisasContext *s, DisasOps *o) { - TCGv_i32 l = tcg_const_i32(get_field(s, l1)); + TCGv_i32 l = tcg_constant_i32(get_field(s, l1)); + gen_helper_trt(cc_op, cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_trtr(DisasContext *s, DisasOps *o) { - TCGv_i32 l = tcg_const_i32(get_field(s, l1)); + TCGv_i32 l = tcg_constant_i32(get_field(s, l1)); + gen_helper_trtr(cc_op, cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_trXX(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r2 = tcg_const_i32(get_field(s, r2)); - TCGv_i32 sizes = tcg_const_i32(s->insn->opc & 3); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2)); + TCGv_i32 sizes = tcg_constant_i32(s->insn->opc & 3); TCGv_i32 tst = tcg_temp_new_i32(); int m3 = get_field(s, m3); @@ -4954,9 +4860,6 @@ static DisasJumpType op_trXX(DisasContext *s, DisasOps *o) } gen_helper_trXX(cc_op, cpu_env, r1, r2, tst, sizes); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r2); - tcg_temp_free_i32(sizes); tcg_temp_free_i32(tst); set_cc_static(s); return DISAS_NEXT; @@ -4964,19 +4867,19 @@ static DisasJumpType op_trXX(DisasContext *s, DisasOps *o) static DisasJumpType op_ts(DisasContext *s, DisasOps *o) { - TCGv_i32 t1 = tcg_const_i32(0xff); + TCGv_i32 t1 = tcg_constant_i32(0xff); + tcg_gen_atomic_xchg_i32(t1, o->in2, t1, get_mem_index(s), MO_UB); tcg_gen_extract_i32(cc_op, t1, 7, 1); - tcg_temp_free_i32(t1); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_unpk(DisasContext *s, DisasOps *o) { - TCGv_i32 l = tcg_const_i32(get_field(s, l1)); + TCGv_i32 l = tcg_constant_i32(get_field(s, l1)); + gen_helper_unpk(cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); return DISAS_NEXT; } @@ -4990,9 +4893,8 @@ static DisasJumpType op_unpka(DisasContext *s, DisasOps *o) gen_program_exception(s, PGM_SPECIFICATION); return DISAS_NORETURN; } - l = tcg_const_i32(l1); + l = tcg_constant_i32(l1); gen_helper_unpka(cc_op, cpu_env, o->addr1, l, o->in2); - tcg_temp_free_i32(l); set_cc_static(s); return DISAS_NEXT; } @@ -5007,9 +4909,8 @@ static DisasJumpType op_unpku(DisasContext *s, DisasOps *o) gen_program_exception(s, PGM_SPECIFICATION); return DISAS_NORETURN; } - l = tcg_const_i32(l1); + l = tcg_constant_i32(l1); gen_helper_unpku(cc_op, cpu_env, o->addr1, l, o->in2); - tcg_temp_free_i32(l); set_cc_static(s); return DISAS_NEXT; } @@ -5028,7 +4929,7 @@ static DisasJumpType op_xc(DisasContext *s, DisasOps *o) /* If the addresses are identical, this is a store/memset of zero. */ if (b1 == b2 && d1 == d2 && (l + 1) <= 32) { - o->in2 = tcg_const_i64(0); + o->in2 = tcg_constant_i64(0); l++; while (l >= 8) { @@ -5061,9 +4962,8 @@ static DisasJumpType op_xc(DisasContext *s, DisasOps *o) /* But in general we'll defer to a helper. */ o->in2 = get_address(s, 0, b2, d2); - t32 = tcg_const_i32(l); + t32 = tcg_constant_i32(l); gen_helper_xc(cc_op, cpu_env, t32, o->addr1, o->in2); - tcg_temp_free_i32(t32); set_cc_static(s); return DISAS_NEXT; } @@ -5128,46 +5028,39 @@ static DisasJumpType op_zero2(DisasContext *s, DisasOps *o) #ifndef CONFIG_USER_ONLY static DisasJumpType op_clp(DisasContext *s, DisasOps *o) { - TCGv_i32 r2 = tcg_const_i32(get_field(s, r2)); + TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2)); gen_helper_clp(cpu_env, r2); - tcg_temp_free_i32(r2); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_pcilg(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r2 = tcg_const_i32(get_field(s, r2)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2)); gen_helper_pcilg(cpu_env, r1, r2); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r2); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_pcistg(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r2 = tcg_const_i32(get_field(s, r2)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2)); gen_helper_pcistg(cpu_env, r1, r2); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r2); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_stpcifc(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 ar = tcg_const_i32(get_field(s, b2)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 ar = tcg_constant_i32(get_field(s, b2)); gen_helper_stpcifc(cpu_env, r1, o->addr1, ar); - tcg_temp_free_i32(ar); - tcg_temp_free_i32(r1); set_cc_static(s); return DISAS_NEXT; } @@ -5180,38 +5073,31 @@ static DisasJumpType op_sic(DisasContext *s, DisasOps *o) static DisasJumpType op_rpcit(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r2 = tcg_const_i32(get_field(s, r2)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2)); gen_helper_rpcit(cpu_env, r1, r2); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r2); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_pcistb(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r3 = tcg_const_i32(get_field(s, r3)); - TCGv_i32 ar = tcg_const_i32(get_field(s, b2)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3)); + TCGv_i32 ar = tcg_constant_i32(get_field(s, b2)); gen_helper_pcistb(cpu_env, r1, r3, o->addr1, ar); - tcg_temp_free_i32(ar); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r3); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_mpcifc(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 ar = tcg_const_i32(get_field(s, b2)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 ar = tcg_constant_i32(get_field(s, b2)); gen_helper_mpcifc(cpu_env, r1, o->addr1, ar); - tcg_temp_free_i32(ar); - tcg_temp_free_i32(r1); set_cc_static(s); return DISAS_NEXT; } @@ -6378,16 +6264,15 @@ static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s) if (unlikely(s->ex_value)) { /* Drop the EX data now, so that it's clear on exception paths. */ - TCGv_i64 zero = tcg_const_i64(0); - int i; - tcg_gen_st_i64(zero, cpu_env, offsetof(CPUS390XState, ex_value)); - tcg_temp_free_i64(zero); + tcg_gen_st_i64(tcg_constant_i64(0), cpu_env, + offsetof(CPUS390XState, ex_value)); /* Extract the values saved by EXECUTE. */ insn = s->ex_value & 0xffffffffffff0000ull; ilen = s->ex_value & 0xf; - /* register insn bytes with translator so plugins work */ - for (i = 0; i < ilen; i++) { + + /* Register insn bytes with translator so plugins work. */ + for (int i = 0; i < ilen; i++) { uint8_t byte = extract64(insn, 56 - (i * 8), 8); translator_fake_ldb(byte, pc + i); } @@ -6512,9 +6397,8 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s) #ifndef CONFIG_USER_ONLY if (s->base.tb->flags & FLAG_MASK_PER) { - TCGv_i64 addr = tcg_const_i64(s->base.pc_next); + TCGv_i64 addr = tcg_constant_i64(s->base.pc_next); gen_helper_per_ifetch(cpu_env, addr); - tcg_temp_free_i64(addr); } #endif From patchwork Mon Feb 20 18:40:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655107 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp1551796wrc; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id jk20-20020a170903331400b0019258bcf3ffsm1911676plb.56.2023.02.20.10.40.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 10:41:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Ilya Leoshkevich Subject: [PATCH v4 02/27] target/s390x: Use tcg_constant_* for DisasCompare Date: Mon, 20 Feb 2023 08:40:27 -1000 Message-Id: <20230220184052.163465-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230220184052.163465-1-richard.henderson@linaro.org> References: <20230220184052.163465-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The a and b fields are not modified by the consumer, and while we need not free a constant, tcg will quietly ignore such frees, so free_compare need not be changed. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 44 ++++++++++++++++++------------------ 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 35e844ef3c..a534419073 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -845,7 +845,7 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask) c->is_64 = false; c->u.s32.a = tcg_temp_new_i32(); tcg_gen_extrl_i64_i32(c->u.s32.a, cc_dst); - c->u.s32.b = tcg_const_i32(0); + c->u.s32.b = tcg_constant_i32(0); break; case CC_OP_LTGT_32: case CC_OP_LTUGTU_32: @@ -860,7 +860,7 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask) case CC_OP_NZ: case CC_OP_FLOGR: c->u.s64.a = cc_dst; - c->u.s64.b = tcg_const_i64(0); + c->u.s64.b = tcg_constant_i64(0); c->g1 = true; break; case CC_OP_LTGT_64: @@ -874,14 +874,14 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask) case CC_OP_TM_64: case CC_OP_ICM: c->u.s64.a = tcg_temp_new_i64(); - c->u.s64.b = tcg_const_i64(0); + c->u.s64.b = tcg_constant_i64(0); tcg_gen_and_i64(c->u.s64.a, cc_src, cc_dst); break; case CC_OP_ADDU: case CC_OP_SUBU: c->is_64 = true; - c->u.s64.b = tcg_const_i64(0); + c->u.s64.b = tcg_constant_i64(0); c->g1 = true; switch (mask) { case 8 | 2: @@ -904,65 +904,65 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask) switch (mask) { case 0x8 | 0x4 | 0x2: /* cc != 3 */ cond = TCG_COND_NE; - c->u.s32.b = tcg_const_i32(3); + c->u.s32.b = tcg_constant_i32(3); break; case 0x8 | 0x4 | 0x1: /* cc != 2 */ cond = TCG_COND_NE; - c->u.s32.b = tcg_const_i32(2); + c->u.s32.b = tcg_constant_i32(2); break; case 0x8 | 0x2 | 0x1: /* cc != 1 */ cond = TCG_COND_NE; - c->u.s32.b = tcg_const_i32(1); + c->u.s32.b = tcg_constant_i32(1); break; case 0x8 | 0x2: /* cc == 0 || cc == 2 => (cc & 1) == 0 */ cond = TCG_COND_EQ; c->g1 = false; c->u.s32.a = tcg_temp_new_i32(); - c->u.s32.b = tcg_const_i32(0); + c->u.s32.b = tcg_constant_i32(0); tcg_gen_andi_i32(c->u.s32.a, cc_op, 1); break; case 0x8 | 0x4: /* cc < 2 */ cond = TCG_COND_LTU; - c->u.s32.b = tcg_const_i32(2); + c->u.s32.b = tcg_constant_i32(2); break; case 0x8: /* cc == 0 */ cond = TCG_COND_EQ; - c->u.s32.b = tcg_const_i32(0); + c->u.s32.b = tcg_constant_i32(0); break; case 0x4 | 0x2 | 0x1: /* cc != 0 */ cond = TCG_COND_NE; - c->u.s32.b = tcg_const_i32(0); + c->u.s32.b = tcg_constant_i32(0); break; case 0x4 | 0x1: /* cc == 1 || cc == 3 => (cc & 1) != 0 */ cond = TCG_COND_NE; c->g1 = false; c->u.s32.a = tcg_temp_new_i32(); - c->u.s32.b = tcg_const_i32(0); + c->u.s32.b = tcg_constant_i32(0); tcg_gen_andi_i32(c->u.s32.a, cc_op, 1); break; case 0x4: /* cc == 1 */ cond = TCG_COND_EQ; - c->u.s32.b = tcg_const_i32(1); + c->u.s32.b = tcg_constant_i32(1); break; case 0x2 | 0x1: /* cc > 1 */ cond = TCG_COND_GTU; - c->u.s32.b = tcg_const_i32(1); + c->u.s32.b = tcg_constant_i32(1); break; case 0x2: /* cc == 2 */ cond = TCG_COND_EQ; - c->u.s32.b = tcg_const_i32(2); + c->u.s32.b = tcg_constant_i32(2); break; case 0x1: /* cc == 3 */ cond = TCG_COND_EQ; - c->u.s32.b = tcg_const_i32(3); + c->u.s32.b = tcg_constant_i32(3); break; default: /* CC is masked by something else: (8 >> cc) & mask. */ cond = TCG_COND_NE; c->g1 = false; - c->u.s32.a = tcg_const_i32(8); - c->u.s32.b = tcg_const_i32(0); - tcg_gen_shr_i32(c->u.s32.a, c->u.s32.a, cc_op); + c->u.s32.a = tcg_temp_new_i32(); + c->u.s32.b = tcg_constant_i32(0); + tcg_gen_shr_i32(c->u.s32.a, tcg_constant_i32(8), cc_op); tcg_gen_andi_i32(c->u.s32.a, c->u.s32.a, mask); break; } @@ -1619,7 +1619,7 @@ static DisasJumpType op_bct32(DisasContext *s, DisasOps *o) tcg_gen_subi_i64(t, regs[r1], 1); store_reg32_i64(r1, t); c.u.s32.a = tcg_temp_new_i32(); - c.u.s32.b = tcg_const_i32(0); + c.u.s32.b = tcg_constant_i32(0); tcg_gen_extrl_i64_i32(c.u.s32.a, t); tcg_temp_free_i64(t); @@ -1643,7 +1643,7 @@ static DisasJumpType op_bcth(DisasContext *s, DisasOps *o) tcg_gen_subi_i64(t, t, 1); store_reg32h_i64(r1, t); c.u.s32.a = tcg_temp_new_i32(); - c.u.s32.b = tcg_const_i32(0); + c.u.s32.b = tcg_constant_i32(0); tcg_gen_extrl_i64_i32(c.u.s32.a, t); tcg_temp_free_i64(t); @@ -1664,7 +1664,7 @@ static DisasJumpType op_bct64(DisasContext *s, DisasOps *o) tcg_gen_subi_i64(regs[r1], regs[r1], 1); c.u.s64.a = regs[r1]; - c.u.s64.b = tcg_const_i64(0); + c.u.s64.b = tcg_constant_i64(0); return help_branch(s, &c, is_imm, imm, o->in2); } From patchwork Mon Feb 20 18:40:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655126 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp1553634wrc; Mon, 20 Feb 2023 10:48:55 -0800 (PST) X-Google-Smtp-Source: AK7set/y32nIdowRI/LeS8kmhVQzJuIbEkTlugh2WfPBs7ST/Lpht3uKjMtzqcjLlV5bs/gMj6yl X-Received: by 2002:a05:622a:56:b0:3b6:9c63:5ca1 with SMTP id y22-20020a05622a005600b003b69c635ca1mr20564816qtw.43.1676918934910; Mon, 20 Feb 2023 10:48:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676918934; cv=none; d=google.com; s=arc-20160816; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id jk20-20020a170903331400b0019258bcf3ffsm1911676plb.56.2023.02.20.10.41.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 10:41:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Ilya Leoshkevich Subject: [PATCH v4 03/27] target/s390x: Use tcg_constant_i32 for fpinst_extract_m34 Date: Mon, 20 Feb 2023 08:40:28 -1000 Message-Id: <20230220184052.163465-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230220184052.163465-1-richard.henderson@linaro.org> References: <20230220184052.163465-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Return a constant or NULL, which means the free may be removed from all callers of fpinst_extract_m34. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 26 +------------------------- 1 file changed, 1 insertion(+), 25 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index a534419073..faa6f737ba 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -1790,7 +1790,7 @@ static TCGv_i32 fpinst_extract_m34(DisasContext *s, bool m3_with_fpe, return NULL; } - return tcg_const_i32(deposit32(m3, 4, 4, m4)); + return tcg_constant_i32(deposit32(m3, 4, 4, m4)); } static DisasJumpType op_cfeb(DisasContext *s, DisasOps *o) @@ -1801,7 +1801,6 @@ static DisasJumpType op_cfeb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_cfeb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1814,7 +1813,6 @@ static DisasJumpType op_cfdb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_cfdb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1827,7 +1825,6 @@ static DisasJumpType op_cfxb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_cfxb(o->out, cpu_env, o->in2_128, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1840,7 +1837,6 @@ static DisasJumpType op_cgeb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_cgeb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1853,7 +1849,6 @@ static DisasJumpType op_cgdb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_cgdb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1866,7 +1861,6 @@ static DisasJumpType op_cgxb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_cgxb(o->out, cpu_env, o->in2_128, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1879,7 +1873,6 @@ static DisasJumpType op_clfeb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_clfeb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1892,7 +1885,6 @@ static DisasJumpType op_clfdb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_clfdb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1905,7 +1897,6 @@ static DisasJumpType op_clfxb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_clfxb(o->out, cpu_env, o->in2_128, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1918,7 +1909,6 @@ static DisasJumpType op_clgeb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_clgeb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1931,7 +1921,6 @@ static DisasJumpType op_clgdb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_clgdb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1944,7 +1933,6 @@ static DisasJumpType op_clgxb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_clgxb(o->out, cpu_env, o->in2_128, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1957,7 +1945,6 @@ static DisasJumpType op_cegb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_cegb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -1969,7 +1956,6 @@ static DisasJumpType op_cdgb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_cdgb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -1981,7 +1967,6 @@ static DisasJumpType op_cxgb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_cxgb(o->out_128, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -1993,7 +1978,6 @@ static DisasJumpType op_celgb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_celgb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -2005,7 +1989,6 @@ static DisasJumpType op_cdlgb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_cdlgb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -2017,7 +2000,6 @@ static DisasJumpType op_cxlgb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_cxlgb(o->out_128, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -2486,7 +2468,6 @@ static DisasJumpType op_fieb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_fieb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -2498,7 +2479,6 @@ static DisasJumpType op_fidb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_fidb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -2510,7 +2490,6 @@ static DisasJumpType op_fixb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_fixb(o->out_128, cpu_env, o->in2_128, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -2785,7 +2764,6 @@ static DisasJumpType op_ledb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_ledb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -2797,7 +2775,6 @@ static DisasJumpType op_ldxb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_ldxb(o->out, cpu_env, o->in2_128, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -2809,7 +2786,6 @@ static DisasJumpType op_lexb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_lexb(o->out, cpu_env, o->in2_128, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } From patchwork Mon Feb 20 18:40:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655110 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp1551846wrc; Mon, 20 Feb 2023 10:43:53 -0800 (PST) X-Google-Smtp-Source: AK7set+QYUIctU0mJoBxO1rRNgr/ZKeoBO3wKBS98nfx8zth/9r/n7s52A6k7mG36ozH/nQKGj+T X-Received: by 2002:a05:6214:e42:b0:56f:ab:1502 with SMTP id o2-20020a0562140e4200b0056f00ab1502mr2957967qvc.37.1676918632845; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id jk20-20020a170903331400b0019258bcf3ffsm1911676plb.56.2023.02.20.10.41.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 10:41:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Ilya Leoshkevich Subject: [PATCH v4 04/27] target/s390x: Use tcg_constant_* in translate_vx.c.inc Date: Mon, 20 Feb 2023 08:40:29 -1000 Message-Id: <20230220184052.163465-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230220184052.163465-1-richard.henderson@linaro.org> References: <20230220184052.163465-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In most cases, this is a simple local allocate and free replaced by tcg_constant_*. In three cases, a variable temp was initialized with a constant value -- reorg to localize the constant. In gen_acc, this fixes a leak. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate_vx.c.inc | 45 +++++++++++++---------------- 1 file changed, 20 insertions(+), 25 deletions(-) diff --git a/target/s390x/tcg/translate_vx.c.inc b/target/s390x/tcg/translate_vx.c.inc index d39ee81cd6..3fadc82e5c 100644 --- a/target/s390x/tcg/translate_vx.c.inc +++ b/target/s390x/tcg/translate_vx.c.inc @@ -319,12 +319,10 @@ static void gen_gvec128_4_i64(gen_gvec128_4_i64_fn fn, uint8_t d, uint8_t a, static void gen_addi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah, uint64_t b) { - TCGv_i64 bl = tcg_const_i64(b); - TCGv_i64 bh = tcg_const_i64(0); + TCGv_i64 bl = tcg_constant_i64(b); + TCGv_i64 bh = tcg_constant_i64(0); tcg_gen_add2_i64(dl, dh, al, ah, bl, bh); - tcg_temp_free_i64(bl); - tcg_temp_free_i64(bh); } static DisasJumpType op_vbperm(DisasContext *s, DisasOps *o) @@ -609,9 +607,8 @@ static DisasJumpType op_vlei(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } - tmp = tcg_const_i64((int16_t)get_field(s, i2)); + tmp = tcg_constant_i64((int16_t)get_field(s, i2)); write_vec_element_i64(tmp, get_field(s, v1), enr, es); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } @@ -1107,11 +1104,13 @@ static DisasJumpType op_vseg(DisasContext *s, DisasOps *o) static DisasJumpType op_vst(DisasContext *s, DisasOps *o) { - TCGv_i64 tmp = tcg_const_i64(16); + TCGv_i64 tmp; /* Probe write access before actually modifying memory */ - gen_helper_probe_write_access(cpu_env, o->addr1, tmp); + gen_helper_probe_write_access(cpu_env, o->addr1, + tcg_constant_i64(16)); + tmp = tcg_temp_new_i64(); read_vec_element_i64(tmp, get_field(s, v1), 0, ES_64); tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEUQ); gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); @@ -1270,9 +1269,10 @@ static DisasJumpType op_vstm(DisasContext *s, DisasOps *o) } /* Probe write access before actually modifying memory */ - tmp = tcg_const_i64((v3 - v1 + 1) * 16); - gen_helper_probe_write_access(cpu_env, o->addr1, tmp); + gen_helper_probe_write_access(cpu_env, o->addr1, + tcg_constant_i64((v3 - v1 + 1) * 16)); + tmp = tcg_temp_new_i64(); for (;; v1++) { read_vec_element_i64(tmp, v1, 0, ES_64); tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEUQ); @@ -1359,7 +1359,7 @@ static DisasJumpType op_va(DisasContext *s, DisasOps *o) static void gen_acc(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, uint8_t es) { const uint8_t msb_bit_nr = NUM_VEC_ELEMENT_BITS(es) - 1; - TCGv_i64 msb_mask = tcg_const_i64(dup_const(es, 1ull << msb_bit_nr)); + TCGv_i64 msb_mask = tcg_constant_i64(dup_const(es, 1ull << msb_bit_nr)); TCGv_i64 t1 = tcg_temp_new_i64(); TCGv_i64 t2 = tcg_temp_new_i64(); TCGv_i64 t3 = tcg_temp_new_i64(); @@ -1416,7 +1416,7 @@ static void gen_acc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, { TCGv_i64 th = tcg_temp_new_i64(); TCGv_i64 tl = tcg_temp_new_i64(); - TCGv_i64 zero = tcg_const_i64(0); + TCGv_i64 zero = tcg_constant_i64(0); tcg_gen_add2_i64(tl, th, al, zero, bl, zero); tcg_gen_add2_i64(tl, th, th, zero, ah, zero); @@ -1425,7 +1425,6 @@ static void gen_acc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, tcg_temp_free_i64(th); tcg_temp_free_i64(tl); - tcg_temp_free_i64(zero); } static DisasJumpType op_vacc(DisasContext *s, DisasOps *o) @@ -1455,15 +1454,14 @@ static void gen_ac2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh, TCGv_i64 cl, TCGv_i64 ch) { TCGv_i64 tl = tcg_temp_new_i64(); - TCGv_i64 th = tcg_const_i64(0); + TCGv_i64 zero = tcg_constant_i64(0); /* extract the carry only */ tcg_gen_extract_i64(tl, cl, 0, 1); tcg_gen_add2_i64(dl, dh, al, ah, bl, bh); - tcg_gen_add2_i64(dl, dh, dl, dh, tl, th); + tcg_gen_add2_i64(dl, dh, dl, dh, tl, zero); tcg_temp_free_i64(tl); - tcg_temp_free_i64(th); } static DisasJumpType op_vac(DisasContext *s, DisasOps *o) @@ -1484,7 +1482,7 @@ static void gen_accc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah, { TCGv_i64 tl = tcg_temp_new_i64(); TCGv_i64 th = tcg_temp_new_i64(); - TCGv_i64 zero = tcg_const_i64(0); + TCGv_i64 zero = tcg_constant_i64(0); tcg_gen_andi_i64(tl, cl, 1); tcg_gen_add2_i64(tl, th, tl, zero, al, zero); @@ -1495,7 +1493,6 @@ static void gen_accc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah, tcg_temp_free_i64(tl); tcg_temp_free_i64(th); - tcg_temp_free_i64(zero); } static DisasJumpType op_vaccc(DisasContext *s, DisasOps *o) @@ -1597,14 +1594,13 @@ static void gen_avgl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) static void gen_avgl_i64(TCGv_i64 dl, TCGv_i64 al, TCGv_i64 bl) { TCGv_i64 dh = tcg_temp_new_i64(); - TCGv_i64 zero = tcg_const_i64(0); + TCGv_i64 zero = tcg_constant_i64(0); tcg_gen_add2_i64(dl, dh, al, zero, bl, zero); gen_addi2_i64(dl, dh, dl, dh, 1); tcg_gen_extract2_i64(dl, dl, dh, 1); tcg_temp_free_i64(dh); - tcg_temp_free_i64(zero); } static DisasJumpType op_vavgl(DisasContext *s, DisasOps *o) @@ -2440,7 +2436,7 @@ static void gen_scbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, { TCGv_i64 th = tcg_temp_new_i64(); TCGv_i64 tl = tcg_temp_new_i64(); - TCGv_i64 zero = tcg_const_i64(0); + TCGv_i64 zero = tcg_constant_i64(0); tcg_gen_sub2_i64(tl, th, al, zero, bl, zero); tcg_gen_andi_i64(th, th, 1); @@ -2452,7 +2448,6 @@ static void gen_scbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, tcg_temp_free_i64(th); tcg_temp_free_i64(tl); - tcg_temp_free_i64(zero); } static DisasJumpType op_vscbi(DisasContext *s, DisasOps *o) @@ -2572,11 +2567,12 @@ static DisasJumpType op_vsumq(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } - sumh = tcg_const_i64(0); + sumh = tcg_temp_new_i64(); suml = tcg_temp_new_i64(); - zero = tcg_const_i64(0); + zero = tcg_constant_i64(0); tmpl = tcg_temp_new_i64(); + tcg_gen_mov_i64(sumh, zero); read_vec_element_i64(suml, get_field(s, v3), max_idx, es); for (idx = 0; idx <= max_idx; idx++) { read_vec_element_i64(tmpl, get_field(s, v2), idx, es); @@ -2587,7 +2583,6 @@ static DisasJumpType op_vsumq(DisasContext *s, DisasOps *o) tcg_temp_free_i64(sumh); tcg_temp_free_i64(suml); - tcg_temp_free_i64(zero); tcg_temp_free_i64(tmpl); return DISAS_NEXT; } From patchwork Mon Feb 20 18:40:30 2023 Content-Type: text/plain; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id jk20-20020a170903331400b0019258bcf3ffsm1911676plb.56.2023.02.20.10.41.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 10:41:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, qemu-s390x@nongnu.org, Ilya Leoshkevich Subject: [PATCH v4 05/27] tests/tcg/s390x: Add bal.S Date: Mon, 20 Feb 2023 08:40:30 -1000 Message-Id: <20230220184052.163465-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230220184052.163465-1-richard.henderson@linaro.org> References: <20230220184052.163465-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Ilya Leoshkevich Add a small test to prevent regressions. Signed-off-by: Ilya Leoshkevich Message-Id: <20221103130011.2670186-1-iii@linux.ibm.com> Signed-off-by: Richard Henderson --- tests/tcg/s390x/Makefile.softmmu-target | 1 + tests/tcg/s390x/bal.S | 24 ++++++++++++++++++++++++ 2 files changed, 25 insertions(+) create mode 100644 tests/tcg/s390x/bal.S diff --git a/tests/tcg/s390x/Makefile.softmmu-target b/tests/tcg/s390x/Makefile.softmmu-target index 50c1b88065..bcbe9367ef 100644 --- a/tests/tcg/s390x/Makefile.softmmu-target +++ b/tests/tcg/s390x/Makefile.softmmu-target @@ -7,3 +7,4 @@ QEMU_OPTS=-action panic=exit-failure -kernel -Wl,--build-id=none $< -o $@ TESTS += unaligned-lowcore +TESTS += bal diff --git a/tests/tcg/s390x/bal.S b/tests/tcg/s390x/bal.S new file mode 100644 index 0000000000..e54d8874ff --- /dev/null +++ b/tests/tcg/s390x/bal.S @@ -0,0 +1,24 @@ + .org 0x200 /* lowcore padding */ + .globl _start +_start: + lpswe start24_psw +_start24: + lgrl %r0,initial_r0 + lgrl %r1,expected_r0 + bal %r0,0f +0: + cgrjne %r0,%r1,1f + lpswe success_psw +1: + lpswe failure_psw + .align 8 +start24_psw: + .quad 0x160000000000,_start24 /* 24-bit mode, cc = 1, pm = 6 */ +initial_r0: + .quad 0x1234567887654321 +expected_r0: + .quad 0x1234567896000000 + 0b /* ilc = 2, cc = 1, pm = 6 */ +success_psw: + .quad 0x2000000000000,0xfff /* see is_special_wait_psw() */ +failure_psw: + .quad 0x2000000000000,0 /* disabled wait */ From patchwork Mon Feb 20 18:40:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655108 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp1551808wrc; Mon, 20 Feb 2023 10:43:47 -0800 (PST) X-Google-Smtp-Source: AK7set+K9eHFwEztCrn8CIwxWYHYN/+qgDhPby3SlQ9Y/eRs7P7A0CJ+Mi13PSlNc/1JUbPE8YU+ X-Received: by 2002:a05:622a:13ce:b0:3a9:86dd:3c60 with SMTP id p14-20020a05622a13ce00b003a986dd3c60mr3411265qtk.47.1676918627443; Mon, 20 Feb 2023 10:43:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676918627; cv=none; d=google.com; s=arc-20160816; b=mdD/nvjKzZr/Urh4aKGMHUkNekONhYXEpalgYQoA4JICZ84nZolh72256ofjuGONV4 EaWkG3QzFOTTAGam6a9RD9N9v0gXBYVWL4uqKHm70uVelihGL1uVRMXlt/QuYjLywWSQ 45PJZ9CavOtaYRhCirXDVN9PMTdnhmoF3A7wKQOVo0tieAgmvl5FJy0rThBOdE12cqtY J26T+fiBI5b4mzAXdc/bKFAoiAW5xPthgi50Wj/vdF/p4UN5DeugNgChUKRpNLiOs89z qK+OKCR5gQ5Dn3q5gtQ6tMRh/V8KCdv7uIGEx6PMGElL1FAgu+4g4aTHlGsoeQClI6n0 yDKw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=7m/m4b71FLelzEcXA/0IWs26yxi4/hxYSZhMkqCxBNA=; b=jeiVXnYdFltQK3cPzDqCwEJnVPOhj7a1DJClvY1ejqyQh8RbovQmWXaNHTqEZL4/Xh pkbXsWwmFXdEnFrqhVlHSBnzmfG+MLw9DrNd8p7h+cCPSJheW3Vi7WrNUSH1mMjvqZA0 PmGB3D9/7VLQU2Sng71fhcDcKwZ4OaqWzM2whHm7DFG4NYxFF5DSI/ATeWPs5uVnAHGK /MIDv77eVc+KNhm/CqHEW3QWpRjBESLG698nRv2RHscziF/ZcxxRmFWEFQcKFnU24C0A KssMnHlGAmTrIFvvIcYrZMyJEoNW5VCrRH8bdJZD3xQDAF5ir8sDjVkewUNVpCYt6CKl 2rzQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MBYBM9hY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id jk20-20020a170903331400b0019258bcf3ffsm1911676plb.56.2023.02.20.10.41.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 10:41:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, qemu-s390x@nongnu.org, Ilya Leoshkevich Subject: [PATCH v4 06/27] tests/tcg/s390x: Add sam.S Date: Mon, 20 Feb 2023 08:40:31 -1000 Message-Id: <20230220184052.163465-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230220184052.163465-1-richard.henderson@linaro.org> References: <20230220184052.163465-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Ilya Leoshkevich Add a small test to prevent regressions. Signed-off-by: Ilya Leoshkevich Message-Id: <20221129015328.55439-1-iii@linux.ibm.com> Signed-off-by: Richard Henderson --- tests/tcg/s390x/Makefile.softmmu-target | 1 + tests/tcg/s390x/sam.S | 67 +++++++++++++++++++++++++ 2 files changed, 68 insertions(+) create mode 100644 tests/tcg/s390x/sam.S diff --git a/tests/tcg/s390x/Makefile.softmmu-target b/tests/tcg/s390x/Makefile.softmmu-target index bcbe9367ef..725b6c598d 100644 --- a/tests/tcg/s390x/Makefile.softmmu-target +++ b/tests/tcg/s390x/Makefile.softmmu-target @@ -8,3 +8,4 @@ QEMU_OPTS=-action panic=exit-failure -kernel TESTS += unaligned-lowcore TESTS += bal +TESTS += sam diff --git a/tests/tcg/s390x/sam.S b/tests/tcg/s390x/sam.S new file mode 100644 index 0000000000..4cab2dd200 --- /dev/null +++ b/tests/tcg/s390x/sam.S @@ -0,0 +1,67 @@ +/* DAT on, home-space mode, 64-bit mode */ +#define DAT_PSWM 0x400c00180000000 +#define VIRTUAL_BASE 0x123456789abcd000 + + .org 0x8e +program_interruption_code: + .org 0x150 +program_old_psw: + .org 0x1d0 /* program new PSW */ + .quad 0,pgm_handler + .org 0x200 /* lowcore padding */ + + .globl _start +_start: + lctlg %c13,%c13,hasce + lpswe dat_psw +start_dat: + sam24 +sam24_suppressed: + /* sam24 should fail */ +fail: + basr %r12,%r0 + lpswe failure_psw-.(%r12) +pgm_handler: + chhsi program_interruption_code,6 /* specification exception? */ + jne fail + clc suppressed_psw(16),program_old_psw /* correct location? */ + jne fail + lpswe success_psw + + .align 8 +dat_psw: + .quad DAT_PSWM,VIRTUAL_BASE+start_dat +suppressed_psw: + .quad DAT_PSWM,VIRTUAL_BASE+sam24_suppressed +success_psw: + .quad 0x2000000000000,0xfff /* see is_special_wait_psw() */ +failure_psw: + .quad 0x2000000000000,0 /* disabled wait */ +hasce: + /* DT = 0b11 (region-first-table), TL = 3 (2k entries) */ + .quad region_first_table + (3 << 2) + 3 + .align 0x1000 +region_first_table: + .org region_first_table + ((VIRTUAL_BASE >> 53) & 0x7ff) * 8 + /* TT = 0b11 (region-first-table), TL = 3 (2k entries) */ + .quad region_second_table + (3 << 2) + 3 + .org region_first_table + 0x800 * 8 +region_second_table: + .org region_second_table + ((VIRTUAL_BASE >> 42) & 0x7ff) * 8 + /* TT = 0b10 (region-second-table), TL = 3 (2k entries) */ + .quad region_third_table + (2 << 2) + 3 + .org region_second_table + 0x800 * 8 +region_third_table: + .org region_third_table + ((VIRTUAL_BASE >> 31) & 0x7ff) * 8 + /* TT = 0b01 (region-third-table), TL = 3 (2k entries) */ + .quad segment_table + (1 << 2) + 3 + .org region_third_table + 0x800 * 8 +segment_table: + .org segment_table + ((VIRTUAL_BASE >> 20) & 0x7ff) * 8 + /* TT = 0b00 (segment-table) */ + .quad page_table + .org segment_table + 0x800 * 8 +page_table: + .org page_table + ((VIRTUAL_BASE >> 12) & 0xff) * 8 + .quad 0 + .org page_table + 0x100 * 8 From patchwork Mon Feb 20 18:40:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655105 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp1551683wrc; Mon, 20 Feb 2023 10:43:25 -0800 (PST) X-Google-Smtp-Source: AK7set/1XIM++qKeAwCN43iADClCFn1lDk6kRE9tVIHlnb5RhR9zHTvJ2fBCuu4S6B3M90vUqSlz X-Received: by 2002:a05:622a:346:b0:3bd:140c:91fc with SMTP id r6-20020a05622a034600b003bd140c91fcmr23146218qtw.47.1676918605811; Mon, 20 Feb 2023 10:43:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676918605; cv=none; d=google.com; s=arc-20160816; b=QNU8idci90XgAp9hSvgRitHRWyMyhitpa2z4sfrNufhWqob2G0/3kp7aWnNqLlF5Rk MxVY3M/ByAjp3qojp3CzjKsy5v8SgtfUrSPRvdud2oD4fu0t2VXHFN6OawD7+aqxmysQ i+1264qH8ps5+32hUZRAb3TffK+WBRcHcG/KLFnAO8Y7RXnft8Zy1Rw5QK5Vm7BzhEAM UtibmdKUQUFh5+dHUnXM0HNrkedLGXVP0fSZazxd8we5evB091e3IwHGDB3HwfwVtIpg mv4Qor//SQbvqrwhw/tEoVLzWUU7L/V51xvSnyAZKhJ2WkUfmeDsdwaF8b5HqRVv3duY cM/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=FVcoN5if0V8Us809c/xVyI5a/NDqYw35Cn85wK50aSY=; b=wHdqNu+/B686P/YmO2V7g1h90aIrtFyFDqtzFPXYtoA+y2BWm/WPECdxdkOxgMcUEJ 4yvgcSSXMd+Nt2w1t3yrJtk2nazM7baiB90yRR5LE7HBFVt2/JJ1Q75qQxrWD+3HvvbR mi+CDBxhl9eCife/E0rJ/m98F6f3+Fi+vNp/DLdG/lDrmK+iJEakNJCA/8nAg93tDqR9 2rloOUZp20g9l8XOGBR4bpg609N6ZRtB9NELzsPwIp1M2xX4qrGK1RtJm40LOUD91+NS O9oJOWyehvwK9tuWb7DwxOxGZ2bcK3xEI7n2UJVQ2UdwkZ3Roy2gbZ8pZZpcIUof+uVM 9TnA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Zv9ZHg0E; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id jk20-20020a170903331400b0019258bcf3ffsm1911676plb.56.2023.02.20.10.41.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 10:41:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Ilya Leoshkevich Subject: [PATCH v4 07/27] target/s390x: Change help_goto_direct to work on displacements Date: Mon, 20 Feb 2023 08:40:32 -1000 Message-Id: <20230220184052.163465-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230220184052.163465-1-richard.henderson@linaro.org> References: <20230220184052.163465-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index faa6f737ba..bd7f644f83 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -1161,8 +1161,10 @@ struct DisasInsn { /* ====================================================================== */ /* Miscellaneous helpers, used by several operations. */ -static DisasJumpType help_goto_direct(DisasContext *s, uint64_t dest) +static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp) { + uint64_t dest = s->base.pc_next + disp; + if (dest == s->pc_tmp) { per_branch(s, true); return DISAS_NEXT; @@ -1185,7 +1187,8 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, bool is_imm, int imm, TCGv_i64 cdest) { DisasJumpType ret; - uint64_t dest = s->base.pc_next + (int64_t)imm * 2; + int64_t disp = (int64_t)imm * 2; + uint64_t dest = s->base.pc_next + disp; TCGLabel *lab; /* Take care of the special cases first. */ @@ -1201,7 +1204,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, goto egress; } if (c->cond == TCG_COND_ALWAYS) { - ret = help_goto_direct(s, dest); + ret = help_goto_direct(s, disp); goto egress; } } else { @@ -1573,7 +1576,7 @@ static DisasJumpType op_bal(DisasContext *s, DisasOps *o) static DisasJumpType op_basi(DisasContext *s, DisasOps *o) { pc_to_link_info(o->out, s, s->pc_tmp); - return help_goto_direct(s, s->base.pc_next + (int64_t)get_field(s, i2) * 2); + return help_goto_direct(s, (int64_t)get_field(s, i2) * 2); } static DisasJumpType op_bc(DisasContext *s, DisasOps *o) From patchwork Mon Feb 20 18:40:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655123 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp1552782wrc; Mon, 20 Feb 2023 10:46:31 -0800 (PST) X-Google-Smtp-Source: AK7set/yhgHifRoMY+LHlJcEqjncANug2BtdT0r2Q4ZpGMf5SNYA8Wtn0FpI3ljw02GqBV5kvCaB X-Received: by 2002:a05:622a:188b:b0:3b9:bd75:9415 with SMTP id v11-20020a05622a188b00b003b9bd759415mr20550900qtc.41.1676918791007; Mon, 20 Feb 2023 10:46:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676918790; cv=none; d=google.com; s=arc-20160816; b=vWhKKRwRU5iaDDpf8YVIUjl9QxC+bgSsyiCdFl2u/dFBVTsoRpuBqrQ7kMBqB84z93 Kz9gOPzSFeWg8IjOl45rwmMePt5jafTA1AJdx4aESkXnjLa4LoFFRiTZuBUNPM3ZPoyz P7CFn3ADcGyVegxyUAnbHwBGZ8GBktVoXxAAG6JskqUHtaAG2vJmU3mU0uvAvJCFq9ha 1VtlBRsg9LdflT61uW+tR+R89M583ePQfXqW73E8T5SltIgcmKWJAIzmauTO3cylCB1P 59WOR4VfnZfbcPY3JLWtmYnIaI7Memui0f76BnQNmwIGwYT//DuirRt1I7AmxK+cQnXx 8KSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=zv2ofhoo2yK6y5CvACgkzBidMP/qlNYVsy8kvmdv1TA=; b=JSN67JeYDsOuPgE1DASy4Q7bg/xgxmNHmNMJGlD3ge6lFP9yyHfkEhnq0vH1DzQbZk q31ESuRxAEWcl3URw60xe7PmcdfFYjt6EB/95UC3LoiKPK1lfhBmmVrgUvx+Vn42qgx0 n3WEglneJPuUHHaSixr3h8ObstYQxlD+pDfXllKjl0j13C7L75ugKFzdQcCD55CL748y HWCrkm50+ZMYv4YViXM90ytMrXsD+/kPIA1s8EAsa3KVFJiJf0fF1uSbP6sTBQrwXNNc KBkHK6kjBu6WphZR/0Gu7A22AyRICLWGmRkIMxvZhwsoIFijPhExuI7HCVSCV4WS4hHM s/6w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=u+4tc7st; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id jk20-20020a170903331400b0019258bcf3ffsm1911676plb.56.2023.02.20.10.41.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 10:41:11 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, qemu-s390x@nongnu.org, Ilya Leoshkevich Subject: [PATCH v4 08/27] target/s390x: Introduce gen_psw_addr_disp Date: Mon, 20 Feb 2023 08:40:33 -1000 Message-Id: <20230220184052.163465-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230220184052.163465-1-richard.henderson@linaro.org> References: <20230220184052.163465-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 69 ++++++++++++++++++++++++------------ 1 file changed, 46 insertions(+), 23 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index bd7f644f83..48e558a790 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -169,6 +169,11 @@ static uint64_t inline_branch_hit[CC_OP_MAX]; static uint64_t inline_branch_miss[CC_OP_MAX]; #endif +static void gen_psw_addr_disp(DisasContext *s, TCGv_i64 dest, int64_t disp) +{ + tcg_gen_movi_i64(dest, s->base.pc_next + disp); +} + static void pc_to_link_info(TCGv_i64 out, DisasContext *s, uint64_t pc) { if (s->base.tb->flags & FLAG_MASK_32) { @@ -346,18 +351,24 @@ static void return_low128(TCGv_i64 dest) static void update_psw_addr(DisasContext *s) { - /* psw.addr */ - tcg_gen_movi_i64(psw_addr, s->base.pc_next); + gen_psw_addr_disp(s, psw_addr, 0); } static void per_branch(DisasContext *s, bool to_next) { #ifndef CONFIG_USER_ONLY - tcg_gen_movi_i64(gbea, s->base.pc_next); + gen_psw_addr_disp(s, gbea, 0); if (s->base.tb->flags & FLAG_MASK_PER) { - TCGv_i64 next_pc = to_next ? tcg_constant_i64(s->pc_tmp) : psw_addr; - gen_helper_per_branch(cpu_env, gbea, next_pc); + if (to_next) { + TCGv_i64 next_pc = tcg_temp_new_i64(); + + gen_psw_addr_disp(s, next_pc, s->ilen); + gen_helper_per_branch(cpu_env, gbea, next_pc); + tcg_temp_free_i64(next_pc); + } else { + gen_helper_per_branch(cpu_env, gbea, psw_addr); + } } #endif } @@ -370,20 +381,23 @@ static void per_branch_cond(DisasContext *s, TCGCond cond, TCGLabel *lab = gen_new_label(); tcg_gen_brcond_i64(tcg_invert_cond(cond), arg1, arg2, lab); - tcg_gen_movi_i64(gbea, s->base.pc_next); + gen_psw_addr_disp(s, gbea, 0); gen_helper_per_branch(cpu_env, gbea, psw_addr); gen_set_label(lab); } else { - TCGv_i64 pc = tcg_constant_i64(s->base.pc_next); + TCGv_i64 pc = tcg_temp_new_i64(); + + gen_psw_addr_disp(s, pc, 0); tcg_gen_movcond_i64(cond, gbea, arg1, arg2, gbea, pc); + tcg_temp_free_i64(pc); } #endif } static void per_breaking_event(DisasContext *s) { - tcg_gen_movi_i64(gbea, s->base.pc_next); + gen_psw_addr_disp(s, gbea, 0); } static void update_cc_op(DisasContext *s) @@ -1163,21 +1177,19 @@ struct DisasInsn { static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp) { - uint64_t dest = s->base.pc_next + disp; - - if (dest == s->pc_tmp) { + if (disp == s->ilen) { per_branch(s, true); return DISAS_NEXT; } - if (use_goto_tb(s, dest)) { + if (use_goto_tb(s, s->base.pc_next + disp)) { update_cc_op(s); per_breaking_event(s); tcg_gen_goto_tb(0); - tcg_gen_movi_i64(psw_addr, dest); + gen_psw_addr_disp(s, psw_addr, disp); tcg_gen_exit_tb(s->base.tb, 0); return DISAS_NORETURN; } else { - tcg_gen_movi_i64(psw_addr, dest); + gen_psw_addr_disp(s, psw_addr, disp); per_branch(s, false); return DISAS_PC_UPDATED; } @@ -1235,14 +1247,14 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, /* Branch not taken. */ tcg_gen_goto_tb(0); - tcg_gen_movi_i64(psw_addr, s->pc_tmp); + gen_psw_addr_disp(s, psw_addr, s->ilen); tcg_gen_exit_tb(s->base.tb, 0); /* Branch taken. */ gen_set_label(lab); per_breaking_event(s); tcg_gen_goto_tb(1); - tcg_gen_movi_i64(psw_addr, dest); + gen_psw_addr_disp(s, psw_addr, disp); tcg_gen_exit_tb(s->base.tb, 1); ret = DISAS_NORETURN; @@ -1265,12 +1277,12 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, /* Branch not taken. */ update_cc_op(s); tcg_gen_goto_tb(0); - tcg_gen_movi_i64(psw_addr, s->pc_tmp); + gen_psw_addr_disp(s, psw_addr, s->ilen); tcg_gen_exit_tb(s->base.tb, 0); gen_set_label(lab); if (is_imm) { - tcg_gen_movi_i64(psw_addr, dest); + gen_psw_addr_disp(s, psw_addr, disp); } per_breaking_event(s); ret = DISAS_PC_UPDATED; @@ -1280,9 +1292,12 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, Most commonly we're single-stepping or some other condition that disables all use of goto_tb. Just update the PC and exit. */ - TCGv_i64 next = tcg_constant_i64(s->pc_tmp); + TCGv_i64 next = tcg_temp_new_i64(); + + gen_psw_addr_disp(s, next, s->ilen); if (is_imm) { - cdest = tcg_constant_i64(dest); + cdest = tcg_temp_new_i64(); + gen_psw_addr_disp(s, cdest, disp); } if (c->is_64) { @@ -1301,6 +1316,10 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, tcg_temp_free_i64(t1); } + tcg_temp_free_i64(next); + if (is_imm) { + tcg_temp_free_i64(cdest); + } ret = DISAS_PC_UPDATED; } @@ -5891,7 +5910,8 @@ static void in2_a2(DisasContext *s, DisasOps *o) static void in2_ri2(DisasContext *s, DisasOps *o) { - o->in2 = tcg_const_i64(s->base.pc_next + (int64_t)get_field(s, i2) * 2); + o->in2 = tcg_temp_new_i64(); + gen_psw_addr_disp(s, o->in2, (int64_t)get_field(s, i2) * 2); } #define SPEC_in2_ri2 0 @@ -6376,8 +6396,11 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s) #ifndef CONFIG_USER_ONLY if (s->base.tb->flags & FLAG_MASK_PER) { - TCGv_i64 addr = tcg_constant_i64(s->base.pc_next); + TCGv_i64 addr = tcg_temp_new_i64(); + + gen_psw_addr_disp(s, addr, 0); gen_helper_per_ifetch(cpu_env, addr); + tcg_temp_free_i64(addr); } #endif @@ -6506,7 +6529,7 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s) if (s->base.tb->flags & FLAG_MASK_PER) { /* An exception might be triggered, save PSW if not already done. */ if (ret == DISAS_NEXT || ret == DISAS_TOO_MANY) { - tcg_gen_movi_i64(psw_addr, s->pc_tmp); + gen_psw_addr_disp(s, psw_addr, s->ilen); } /* Call the helper to check for a possible PER exception. */ From patchwork Mon Feb 20 18:40:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655125 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp1553629wrc; Mon, 20 Feb 2023 10:48:54 -0800 (PST) X-Google-Smtp-Source: AK7set/HLpi3oZrrtCKAxtciCjUpoIGrwp54AMuczT4H4/z/jyx8iqv3tzynZ2TuV4yTe0fhRaNY X-Received: by 2002:ad4:5aec:0:b0:56b:fe6a:df87 with SMTP id c12-20020ad45aec000000b0056bfe6adf87mr5165799qvh.52.1676918934518; Mon, 20 Feb 2023 10:48:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676918934; cv=none; d=google.com; s=arc-20160816; b=l9b0UItuF2kD/QU+ZWCyZW7FeY7t+5F7mQMyTApX70tFtDHiBuqlW+02YfrISVmr9t 2Kt0vxAvzSkI+LBUr1LaF8smufJiDlla97dFqx+5E3kMdBnQzUSn5tUywTZBvJQZyl6B 8yWVD10WYq73M7nG4PHtg5s4MyrnseINJRQUb4K0G23wNz0FPo6IxgOU2ZsWhNsBplXn 82qhHPaXxsa2c8LDWWCq0R/NNunTEcYlGNwSOlG8y1+nxQZvZAMdSkQzWq2+4RDIvN8M DwDc45/v3kCMe+Ad8GLbl/1T0kk+xNyf3lk1AcE2jtJ63ITtHJxZinAIy7CI5/ouvxMV oMZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=LOOB3Z1xjodTvhYT+/+rAv7/3kmyBvt7jdZIeAngVJ8=; b=TRwnj6MEI9IvZoDeKbTgbUunq5LRw46eq+9GcIZtL/yQ0LxeQ+d90LeileeeZZeoPU zWtRyt3Sk6nUd6OZMLzVjbo1EAVyXHJ2axr5jt0vozmqnyYQoktnu9QIp3oVE++/mnuD 4ajdAvKitc363M0/KQyAo1QHJRCJrriF/Yd67q1N5R2D3tHruIMrwyTmOgsYJGj88kj6 +4cjtLPed5I905olNYFKlg9VNbM09P810cw+wQA/ERV9ceht37xIY9LpWaAWQGiM/oeK 1PWmGY8xaFTFNjx50jfS6M/wdJZi98PqiaCpkRTQeyy5v55esY6ggGoxsLzqS3zKiMPQ a4EQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=q45uAIVD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id jk20-20020a170903331400b0019258bcf3ffsm1911676plb.56.2023.02.20.10.41.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 10:41:12 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, qemu-s390x@nongnu.org, Ilya Leoshkevich , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v4 09/27] target/s390x: Remove pc argument to pc_to_link_into Date: Mon, 20 Feb 2023 08:40:34 -1000 Message-Id: <20230220184052.163465-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230220184052.163465-1-richard.henderson@linaro.org> References: <20230220184052.163465-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org All callers pass s->pc_tmp. Reviewed-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 48e558a790..3dbbcfd2d3 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -174,8 +174,10 @@ static void gen_psw_addr_disp(DisasContext *s, TCGv_i64 dest, int64_t disp) tcg_gen_movi_i64(dest, s->base.pc_next + disp); } -static void pc_to_link_info(TCGv_i64 out, DisasContext *s, uint64_t pc) +static void pc_to_link_info(TCGv_i64 out, DisasContext *s) { + uint64_t pc = s->pc_tmp; + if (s->base.tb->flags & FLAG_MASK_32) { if (s->base.tb->flags & FLAG_MASK_64) { tcg_gen_movi_i64(out, pc); @@ -1549,7 +1551,7 @@ static DisasJumpType op_ni(DisasContext *s, DisasOps *o) static DisasJumpType op_bas(DisasContext *s, DisasOps *o) { - pc_to_link_info(o->out, s, s->pc_tmp); + pc_to_link_info(o->out, s); if (o->in2) { tcg_gen_mov_i64(psw_addr, o->in2); per_branch(s, false); @@ -1564,7 +1566,7 @@ static void save_link_info(DisasContext *s, DisasOps *o) TCGv_i64 t; if (s->base.tb->flags & (FLAG_MASK_32 | FLAG_MASK_64)) { - pc_to_link_info(o->out, s, s->pc_tmp); + pc_to_link_info(o->out, s); return; } gen_op_calc_cc(s); @@ -1594,7 +1596,7 @@ static DisasJumpType op_bal(DisasContext *s, DisasOps *o) static DisasJumpType op_basi(DisasContext *s, DisasOps *o) { - pc_to_link_info(o->out, s, s->pc_tmp); + pc_to_link_info(o->out, s); return help_goto_direct(s, (int64_t)get_field(s, i2) * 2); } From patchwork Mon Feb 20 18:40:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655119 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp1552503wrc; Mon, 20 Feb 2023 10:45:49 -0800 (PST) X-Google-Smtp-Source: AK7set8UQSAXSpnHyNcWCv5FQv1dePjIdSQiAJT/z9vxOW1dfbCMDdorS+qDEg70JEvVynl1BDga X-Received: by 2002:a05:622a:87:b0:3b9:d1c1:6da6 with SMTP id o7-20020a05622a008700b003b9d1c16da6mr15624848qtw.7.1676918749149; Mon, 20 Feb 2023 10:45:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676918749; cv=none; d=google.com; s=arc-20160816; b=tpGBH2JI+cRAj8uAMGHiHrsE7WvaSAT2Dsdrj2HCN/SOw4aIeMW8dn3LAgVV1NzLYh fkvhUnQeBd2T8gyYeMxHWLsxDKFbFTTxEgqy9FS5o4nrOH0E/BuyWb/x5Q2pbRp7koIo 3Cyk5Mb3kKMZzsPCcrVkQmxOA9JfK9PhUdbbrCgHLJ3/w3dyHrfsKXXpEKTfTivb6AQ1 VCbpQNP/aTz7vwYWuvhEFTq1FqZkon/r0RDhkW2G2BW/9zb6XScJeZx/hmWnt6My4P3P pdnvbVZto2DSKcOPeb7TGpv6X4is2OmbEoSgJ5RxpEf7VbKLVhKKMxcIR7AotCbuQ/ab hl0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=xeg/0EdSZC28AvGMk7qqsjE82NOjaTkrGHHmkOUC36U=; b=sCs6jXZXRbIBN2fgfnIcvkRFHsxIvjdJH5S/Oow4VtgzNRJplPIf310JpUquhtmThT vZH2eZBaN9KKIvM0vrtN0QYZ148QmNfCPzf33JO+Q99flZ+IE+beW5jXrE3st4NL6y/p /cnUNJU75Bn0fW12yRuLf6AWRxt8lAoub8KZSN3QaFkc98VEtGr0L4dwUfkSwulFXxq0 2PMyFmvlD1soTWmdZJlyrtXcPa1qvtQemcIZ2w6JSAN/Y06ml1QfjG4GMdqY3p+e5MeL xbuAjgugoqQjxr/3VHTMPZvvIud3xmN1o2y1DwkFJMJ6XxEOeiMeZ2XI3789eo0Pa6dt 9ejg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mqXC4Pcm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id jk20-20020a170903331400b0019258bcf3ffsm1911676plb.56.2023.02.20.10.41.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 10:41:14 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, qemu-s390x@nongnu.org, Ilya Leoshkevich Subject: [PATCH v4 10/27] target/s390x: Use gen_psw_addr_disp in pc_to_link_info Date: Mon, 20 Feb 2023 08:40:35 -1000 Message-Id: <20230220184052.163465-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230220184052.163465-1-richard.henderson@linaro.org> References: <20230220184052.163465-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This is slightly more complicated than a straight displacement for 31 and 24-bit modes. Dont bother with a cant-happen assert. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 3dbbcfd2d3..027a5b0673 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -176,17 +176,20 @@ static void gen_psw_addr_disp(DisasContext *s, TCGv_i64 dest, int64_t disp) static void pc_to_link_info(TCGv_i64 out, DisasContext *s) { - uint64_t pc = s->pc_tmp; + TCGv_i64 tmp; - if (s->base.tb->flags & FLAG_MASK_32) { - if (s->base.tb->flags & FLAG_MASK_64) { - tcg_gen_movi_i64(out, pc); - return; - } - pc |= 0x80000000; + if (s->base.tb->flags & FLAG_MASK_64) { + gen_psw_addr_disp(s, out, s->ilen); + return; } - assert(!(s->base.tb->flags & FLAG_MASK_64)); - tcg_gen_deposit_i64(out, out, tcg_constant_i64(pc), 0, 32); + + tmp = tcg_temp_new_i64(); + gen_psw_addr_disp(s, tmp, s->ilen); + if (s->base.tb->flags & FLAG_MASK_32) { + tcg_gen_ori_i64(tmp, tmp, 0x80000000); + } + tcg_gen_deposit_i64(out, out, tmp, 0, 32); + tcg_temp_free_i64(tmp); } static TCGv_i64 psw_addr; From patchwork Mon Feb 20 18:40:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655115 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp1552043wrc; Mon, 20 Feb 2023 10:44:25 -0800 (PST) X-Google-Smtp-Source: AK7set8f+hZpb34/D4utWBAElpy2xBc0ybLIehxTSdORFG9rScaNNDh5bk6jg2SAJ14/50tEHott X-Received: by 2002:a05:6214:411a:b0:56c:1b8e:826e with SMTP id kc26-20020a056214411a00b0056c1b8e826emr6452389qvb.15.1676918665617; Mon, 20 Feb 2023 10:44:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676918665; cv=none; d=google.com; s=arc-20160816; b=p3qjbdX2qr/DJXKHegHlXTrypiz+D1GBhGZa1D0GPHoBWDU3pJ6hEOFE0gyxXS6TBK LBS/qltKxMK869lkGfspUmmV8HK+l32xy8CXjiLc0NsKlKDYN+z2htgqv5lxZDFhjKt+ LfTpFlxoBJf6q5Xrb0pzb/NEBrS12KiIrfAfa2c2oXnF4q340H3ohddfru1f5mY8p7TK a0odwCYGA1xvTS5fIeZOzhbwdrFq91nD5irZSqDPOlQ6HeuC2S2NgSN10ZNp81b/STIP nqdvgNaVG1N3GyjGGNrEK91Cq+Mm+rB5XBa4EAjp/GsKJ8FdNpHlmOnYtoLP+rGM8A2q XFzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=xjdX+3lrfnqV9nfR+Pm6BiLQ9pXwmV/7HhcoJgl+TnA=; b=iKWKiFl3Mo0YVqSndu/AT7Bl2x2IW8CM7gc0plr2YbQop/2U0GrvGQQ0XV8Gi+nz5K leeCnz0cRwIJgzLfwriurzehn9sUYYS7HiSTow5mSUKRFmXfMstCf6OQVcR2V+wff/rR aCfXuo3cVjOTW4Flj1NyZiQwiPVKzZVIY96x+fYJDkgtAbPNJ6JQp64zJt99L+fjKOYZ a6qYIgaQBeGTcWLSoE4orUN8K/UjxU4SqAmlesYPVmwuSyyGdP2LeEufxUur45AKu+Xk xJ8IGtA6cZOiKn1uek3TQfjiURN0e2n/IWa2sdwj4j4GTkRVw/WipL22Vi0kymWAdoWK Blqg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YGPV7WPR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id jk20-20020a170903331400b0019258bcf3ffsm1911676plb.56.2023.02.20.10.41.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 10:41:16 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, qemu-s390x@nongnu.org, Ilya Leoshkevich , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v4 11/27] target/s390x: Use gen_psw_addr_disp in save_link_info Date: Mon, 20 Feb 2023 08:40:36 -1000 Message-Id: <20230220184052.163465-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230220184052.163465-1-richard.henderson@linaro.org> References: <20230220184052.163465-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Trivial but non-mechanical conversion away from pc_tmp. Reviewed-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 027a5b0673..9e60abe97d 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -1573,9 +1573,11 @@ static void save_link_info(DisasContext *s, DisasOps *o) return; } gen_op_calc_cc(s); - tcg_gen_andi_i64(o->out, o->out, 0xffffffff00000000ull); - tcg_gen_ori_i64(o->out, o->out, ((s->ilen / 2) << 30) | s->pc_tmp); t = tcg_temp_new_i64(); + tcg_gen_andi_i64(o->out, o->out, 0xffffffff00000000ull); + gen_psw_addr_disp(s, t, s->ilen); + tcg_gen_or_i64(o->out, o->out, t); + tcg_gen_ori_i64(o->out, o->out, (s->ilen / 2) << 30); tcg_gen_shri_i64(t, psw_mask, 16); tcg_gen_andi_i64(t, t, 0x0f000000); tcg_gen_or_i64(o->out, o->out, t); From patchwork Mon Feb 20 18:40:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655104 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp1551516wrc; Mon, 20 Feb 2023 10:42:58 -0800 (PST) X-Google-Smtp-Source: AK7set84R0Ox/qmnVpzm0tjof2DrfQ6dhBqtUqYpxX7RPcXY1rEK0vprrlhLSsKTnKmR7v6gb0TV X-Received: by 2002:ad4:5cae:0:b0:56c:27b0:ed05 with SMTP id q14-20020ad45cae000000b0056c27b0ed05mr5062122qvh.45.1676918578498; Mon, 20 Feb 2023 10:42:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676918578; cv=none; d=google.com; s=arc-20160816; b=0TaJMhRwy5dvE3YIcD2y1q/xJbMHTnpnT/xXi5//G4cZ+m8N4EQgEmkreVIHSPELjx +MqDoJaQpKYNwKFgrEWPcQtYq6gDDE/NM+OFAf1snB8BG7UZBKOKNnpho+SHWQ5x7kIX Mh9acSZzcibxTvrPxnZGh2hEPX2vkKH92tZi8z/VOwC9Dx0HXz98+dVPSfs3BuPkttxt UPpng1FJnP5C3WK3bnSHIY39qC3skBUuFmvdwQv8GWKHVepSpm8c11RSlpIlaUMtNBRg im6tBVPgfAjZWdQ9+3DetbLaIxNCe/MBoWGuw7SqvIsXKU6JgQZLBOT2h8BbcWmlSay5 opdg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=OIXIS3t5z4FrUcuj3cjvlhwZKUVcPBcWn7pb9lpLWrY=; b=wDTdkB9iYnh+nScWLAcYMCWuJVGkbgsEmT9NBWiZHod6v8oMVixsc1T6eCRPxmFpQv NxABz3raCO2H16fkWv6uEzDI0uqRl2kB7z1xOCHZ3/+qHyQKMfFs3qJ+4CaS9WvjJXom VER8Qbd35s8/nOYzX8MVuXsNkghinV6gfR4oPpoZNCMlZaKhj2w3QwLkOehvzDZ2+OgV UbWczdYmFSKmrtupBZzoVVxBziUeMk8+0SqwXsmokIeUVRwCGjC+VSj3o2P7It8iXxLW LDtBdk5V2QW7FImpn/AEN4qvqXaIqGaH/oLrtvdvojE9Wx6MeJkyKCpvsiCDAduJd6UE 7S4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=O2amCHLZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id jk20-20020a170903331400b0019258bcf3ffsm1911676plb.56.2023.02.20.10.41.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 10:41:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, qemu-s390x@nongnu.org, Ilya Leoshkevich Subject: [PATCH v4 12/27] target/s390x: Use gen_psw_addr_disp in op_sam Date: Mon, 20 Feb 2023 08:40:37 -1000 Message-Id: <20230220184052.163465-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230220184052.163465-1-richard.henderson@linaro.org> References: <20230220184052.163465-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Complicated because we may now require a runtime jump. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 40 +++++++++++++++++++++++++----------- 1 file changed, 28 insertions(+), 12 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 9e60abe97d..506bde2c3f 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -3939,7 +3939,7 @@ static DisasJumpType op_sacf(DisasContext *s, DisasOps *o) static DisasJumpType op_sam(DisasContext *s, DisasOps *o) { int sam = s->insn->data; - TCGv_i64 tsam; + TCGLabel *fault = NULL; uint64_t mask; switch (sam) { @@ -3954,20 +3954,36 @@ static DisasJumpType op_sam(DisasContext *s, DisasOps *o) break; } - /* Bizarre but true, we check the address of the current insn for the - specification exception, not the next to be executed. Thus the PoO - documents that Bad Things Happen two bytes before the end. */ - if (s->base.pc_next & ~mask) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - s->pc_tmp &= mask; + /* + * Bizarre but true, we check the address of the current insn for the + * specification exception, not the next to be executed. Thus the PoO + * documents that Bad Things Happen two bytes before the end. + */ + if (mask != -1) { + TCGv_i64 t = tcg_temp_new_i64(); + fault = gen_new_label(); - tsam = tcg_constant_i64(sam); - tcg_gen_deposit_i64(psw_mask, psw_mask, tsam, 31, 2); + gen_psw_addr_disp(s, t, 0); + tcg_gen_andi_i64(t, t, ~mask); + tcg_gen_brcondi_i64(TCG_COND_NE, t, 0, fault); + tcg_temp_free_i64(t); + } + + update_cc_op(s); + + tcg_gen_deposit_i64(psw_mask, psw_mask, tcg_constant_i64(sam), 31, 2); + + gen_psw_addr_disp(s, psw_addr, s->ilen); + tcg_gen_andi_i64(psw_addr, psw_addr, mask); /* Always exit the TB, since we (may have) changed execution mode. */ - return DISAS_TOO_MANY; + tcg_gen_lookup_and_goto_ptr(); + + if (mask != -1) { + gen_set_label(fault); + gen_program_exception(s, PGM_SPECIFICATION); + } + return DISAS_NORETURN; } static DisasJumpType op_sar(DisasContext *s, DisasOps *o) From patchwork Mon Feb 20 18:40:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655118 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp1552421wrc; Mon, 20 Feb 2023 10:45:36 -0800 (PST) X-Google-Smtp-Source: AK7set8v+5dhZQde0OQvtwZniAwD/dU4G6C6t2Nro7nJI0fmSjajhhZ5GLgbRUnsSjUg24l57Jla X-Received: by 2002:a05:6214:e8d:b0:56e:a07b:f4d4 with SMTP id hf13-20020a0562140e8d00b0056ea07bf4d4mr5497232qvb.3.1676918736033; Mon, 20 Feb 2023 10:45:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676918736; cv=none; d=google.com; s=arc-20160816; b=NMkh/UezsiHkT+L2b6qqZHmT0d5pl/U0uKAdFlAaCLq1oOjEsBfofVokJazqq/ITko IEy32H3inIVt3a1D0RFIqB901+gudQunJjD6+4uCGThmHEHaTxtrZ1rQ7NMhldWzUluj XZiK4GQx4+LqjkwnE88qWWgCPStfglhqh4OFTUbGFA/qp4KbTq55OP4MikJ26OuJ3Auk OWmjqd095ppv+zV96KpE+fApVnfvJBfwh1CPCxqdM3yeo0sH/U8Wtbhs+gwYPd5rpyDG jFRAXrg2nesEynrUoChGOxzvR2QmeFgZ/WQqAHkL1+9fQQSdf/xA+5l1caD5bW1N+Ebz CveQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=bfaFG09oDD2o28vcTR7j+acmldxB7/SXD7I4ujzpsng=; b=NR2Hhr+UaOCidJvo/OFsHH15nEno1yBEGtsSWcptV1jvcbTaYuCZQB3FWl9AjEjN0Z tF/Hg2Oo2K9RZ3hKn3wkoV0YV7prIPk2jqlwAqtIxsC9z4f1klOcTq374CXYJsSvFtpr VOKvdCJRk3WLvicYAPlwy6CB620mdUo14LM7R4WJbWhw3ZJtPdY3ZzgvQ1Gs1aMkkw5X P8iSmIb8kWTSLgerNZQFoPVUOTWiAiNJ7gvoXn8ZtSLCft4I4MFIwVexMi3PlgviTJCU hIvsNepeXpfLGuRCgTk3gUfIRc+IDzQ+ZyjtCodvrbBlToypj66Aj9ZUN8M3D5oQXW89 9iwA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uyxjU2PE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id jk20-20020a170903331400b0019258bcf3ffsm1911676plb.56.2023.02.20.10.41.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 10:41:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Ilya Leoshkevich Subject: [PATCH v4 13/27] target/s390x: Use ilen instead in branches Date: Mon, 20 Feb 2023 08:40:38 -1000 Message-Id: <20230220184052.163465-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230220184052.163465-1-richard.henderson@linaro.org> References: <20230220184052.163465-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Remove the remaining uses of pc_tmp, and remove the variable. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 506bde2c3f..3a61491222 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -141,12 +141,6 @@ struct DisasContext { TCGOp *insn_start; DisasFields fields; uint64_t ex_value; - /* - * During translate_one(), pc_tmp is used to determine the instruction - * to be executed after base.pc_next - e.g. next sequential instruction - * or a branch target. - */ - uint64_t pc_tmp; uint32_t ilen; enum cc_op cc_op; bool exit_to_mainloop; @@ -1214,7 +1208,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, goto egress; } if (is_imm) { - if (dest == s->pc_tmp) { + if (disp == s->ilen) { /* Branch to next. */ per_branch(s, true); ret = DISAS_NEXT; @@ -1238,7 +1232,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, } } - if (use_goto_tb(s, s->pc_tmp)) { + if (use_goto_tb(s, s->base.pc_next + s->ilen)) { if (is_imm && use_goto_tb(s, dest)) { /* Both exits can use goto_tb. */ update_cc_op(s); @@ -6317,7 +6311,6 @@ static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s) g_assert_not_reached(); } } - s->pc_tmp = s->base.pc_next + ilen; s->ilen = ilen; /* We can't actually determine the insn format until we've looked up @@ -6562,7 +6555,7 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s) out: /* Advance to the next instruction. */ - s->base.pc_next = s->pc_tmp; + s->base.pc_next += s->ilen; return ret; } From patchwork Mon Feb 20 18:40:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655121 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp1552583wrc; Mon, 20 Feb 2023 10:46:05 -0800 (PST) X-Google-Smtp-Source: AK7set/qFWNXaLrBLFF0Fng/6UaBx6AJphPKnpH9H6pqd/gRrPYzkFkVwjABt8wl34PU+D49plix X-Received: by 2002:a05:622a:87:b0:3b9:d1c1:6da6 with SMTP id o7-20020a05622a008700b003b9d1c16da6mr15626094qtw.7.1676918765263; Mon, 20 Feb 2023 10:46:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676918765; cv=none; d=google.com; s=arc-20160816; b=CyxUFsIfOa+ebvg7aiiNaGZz1Ewsr6FObrk7x9pJQwg2eEhhOTzpSgRcbb+TGYSXJR nWc42p0WUY3mHeV18/OkPyo4W1l/a8+mL2F6vBtIDvAUXd9+cGqOGTXP15IL+k0J7o9C JUmF7a/mt9hozP7rn6EJWMBR7W+yoo1oVLYCdEOFmGoL3krD42SiNfUQ/bxTve8xVw8l S92b6BLMbIcHHgu5gDuhV4ALgq52dlv6JpAfHDW0l8Kj+JCZ6F2fik1bJhxm2Yw6ysCl j35ANOA0F/16lCX5jULr6RxfoWkdWomqN7//mI0ybhNNJCKuTzSPzKlLtoAdLzDqT83L qSWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=x6mVVLeAKLfZ1QsaICACHihb7zGLUdrCmrZOJHSfaPM=; b=EZAeQ1aYe+FoPV3YdT59lGkKR1HgzRCEHuv7Lfkrjb00Xr9WTUk3gTk+8YeZWmt7aS NjC/Vx86J18jJCreXuWrOTNZnGUh2sSiuCH3Fm7kbLQC8ttlMvx0Fjlg8EN2Zw5zxnYm 8rbhtRCbjCQ+lP69/bKqmEpDUEfD0QFqH3cIkyQsxvgTawGqx7S6yjAZ+Pz3h3561z8E eIsaOP4cKwmuKZsnBz9HH8eQ7/pzxahVCaS56WN7EMC6SElkgPiCUgslnXEgWFRiO04u UxBvDSCUZZyXunQcBkFeFY2hwRghFLsHi0EqgO/5NRL/WcNxs2RuEtW0LYOj+j+3iFo5 tUfw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Pa/2FLLd"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id jk20-20020a170903331400b0019258bcf3ffsm1911676plb.56.2023.02.20.10.41.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 10:41:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, qemu-s390x@nongnu.org, Ilya Leoshkevich Subject: [PATCH v4 14/27] target/s390x: Assert masking of psw.addr in cpu_get_tb_cpu_state Date: Mon, 20 Feb 2023 08:40:39 -1000 Message-Id: <20230220184052.163465-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230220184052.163465-1-richard.henderson@linaro.org> References: <20230220184052.163465-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When changing modes via SAM, we raise a specification exception if the new PC is out of range. The masking in s390x_tr_init_disas_context was too late to be correct, but may be removed. Add a debugging assert in cpu_get_tb_cpu_state. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/cpu.h | 20 ++++++++++++++------ target/s390x/tcg/translate.c | 6 +----- 2 files changed, 15 insertions(+), 11 deletions(-) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 7d6d01325b..c7eeebfc53 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -379,17 +379,25 @@ static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch) } static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc, - target_ulong *cs_base, uint32_t *flags) + target_ulong *cs_base, uint32_t *pflags) { - *pc = env->psw.addr; - *cs_base = env->ex_value; - *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; + int flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; if (env->cregs[0] & CR0_AFP) { - *flags |= FLAG_MASK_AFP; + flags |= FLAG_MASK_AFP; } if (env->cregs[0] & CR0_VECTOR) { - *flags |= FLAG_MASK_VECTOR; + flags |= FLAG_MASK_VECTOR; } + *pflags = flags; + *cs_base = env->ex_value; + *pc = env->psw.addr; +#ifdef CONFIG_DEBUG_TCG + if (!(flags & FLAG_MASK_32)) { + assert(*pc <= 0xffffff); + } else if (!(flags & FLAG_MASK_64)) { + assert(*pc <= 0x7fffffff); + } +#endif } /* PER bits from control register 9 */ diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 3a61491222..d21b6d7f72 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -6563,11 +6563,7 @@ static void s390x_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc = container_of(dcbase, DisasContext, base); - /* 31-bit mode */ - if (!(dc->base.tb->flags & FLAG_MASK_64)) { - dc->base.pc_first &= 0x7fffffff; - dc->base.pc_next = dc->base.pc_first; - } + /* Note cpu_get_tb_cpu_state asserts PC is masked for the mode. */ dc->cc_op = CC_OP_DYNAMIC; dc->ex_value = dc->base.tb->cs_base; From patchwork Mon Feb 20 18:40:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655111 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp1551901wrc; Mon, 20 Feb 2023 10:44:01 -0800 (PST) X-Google-Smtp-Source: AK7set8inDWPdkRKI8eIWjvQGjb6W++wRy/0lun4D4u3/YEFMQlmYcdmET6OvrxhCqsmw7ZegpY3 X-Received: by 2002:a05:622a:1343:b0:3ba:19e5:3e47 with SMTP id w3-20020a05622a134300b003ba19e53e47mr2426111qtk.65.1676918641809; Mon, 20 Feb 2023 10:44:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676918641; cv=none; d=google.com; s=arc-20160816; b=EZp2D+EdaCp6VqtAhH9ME5rCcLGSXOWbwN0siiYuZ2qGGaxOtaHOd45HF3ZbRYbGpw R6U0h2aHZwMGOP/L8PyVETtziNo/BQDJtmfso64n/VeL7J3PKhU7+af7o4X6wkcamwpQ wieN12lHDkU5IfIBBFmyvmXCHpyRC1vgndrFAx69ASDglxYM+W9CEbkgO18eD7nsNw6+ cAAmaE2809bGIi8qNoRIbdydIYlQYaEU0e2a8HDYOmIgA69xw5jX1wnBkK06ptyxyn1r wBQmhgyWu6pbdb0vncrH6WTxmSUwOTJSVe+9jWZHWyn5Gp4ml6C9uPvmuvsbuGRkv7lv 1LSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=R32w+gpJSW/QF+uQd1ste0+qotsnEJ4jVU8optw/M+8=; b=tLXZlftxpvCYzTDYoXEIfEyR/uucJewwTC30peFOE4ACfhcTXcd4O575Ltn321eHez 6c8eCQmlwThSxhvQEr1MspzOAYm6Mq9KfONfy/7+8lVQvgoWJGuzQ02Zb3sO+58HA9E9 LmsAu9HUqfzns3WTCwek8m0MA6nzWSBYpaeceV+M83Xs+ZiIz2m7eIgRyXkx2G1K5jGv BGmP6zGZ3wPRFDVX4DlxfCcYPjWsG7TiLRs2CkOoxvn/YMckbNTbpFCIYYMfd9GCRGvD W4c2YzA9ZZQLFMa1X1TbJSw5b3qPRWrzrW0RH+l2gpCJJ45RZPaXcLl/9M2erK/9fZdh OThA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qPo54lyC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id jk20-20020a170903331400b0019258bcf3ffsm1911676plb.56.2023.02.20.10.41.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 10:41:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Ilya Leoshkevich Subject: [PATCH v4 15/27] target/s390x: Add disp argument to update_psw_addr Date: Mon, 20 Feb 2023 08:40:40 -1000 Message-Id: <20230220184052.163465-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230220184052.163465-1-richard.henderson@linaro.org> References: <20230220184052.163465-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Rename to update_psw_addr_disp at the same time. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index d21b6d7f72..160c5eef59 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -348,9 +348,9 @@ static void return_low128(TCGv_i64 dest) tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUS390XState, retxl)); } -static void update_psw_addr(DisasContext *s) +static void update_psw_addr_disp(DisasContext *s, int64_t disp) { - gen_psw_addr_disp(s, psw_addr, 0); + gen_psw_addr_disp(s, psw_addr, disp); } static void per_branch(DisasContext *s, bool to_next) @@ -456,7 +456,7 @@ static void gen_program_exception(DisasContext *s, int code) offsetof(CPUS390XState, int_pgm_ilen)); /* update the psw */ - update_psw_addr(s); + update_psw_addr_disp(s, 0); /* Save off cc. */ update_cc_op(s); @@ -1184,11 +1184,11 @@ static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp) update_cc_op(s); per_breaking_event(s); tcg_gen_goto_tb(0); - gen_psw_addr_disp(s, psw_addr, disp); + update_psw_addr_disp(s, disp); tcg_gen_exit_tb(s->base.tb, 0); return DISAS_NORETURN; } else { - gen_psw_addr_disp(s, psw_addr, disp); + update_psw_addr_disp(s, disp); per_branch(s, false); return DISAS_PC_UPDATED; } @@ -2468,7 +2468,7 @@ static DisasJumpType op_ex(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } - update_psw_addr(s); + update_psw_addr_disp(s, 0); update_cc_op(s); if (r1 == 0) { @@ -3192,7 +3192,7 @@ static DisasJumpType op_lpd(DisasContext *s, DisasOps *o) /* In a parallel context, stop the world and single step. */ if (tb_cflags(s->base.tb) & CF_PARALLEL) { - update_psw_addr(s); + update_psw_addr_disp(s, 0); update_cc_op(s); gen_exception(EXCP_ATOMIC); return DISAS_NORETURN; @@ -4505,7 +4505,7 @@ static DisasJumpType op_stura(DisasContext *s, DisasOps *o) tcg_gen_qemu_st_tl(o->in1, o->in2, MMU_REAL_IDX, s->insn->data); if (s->base.tb->flags & FLAG_MASK_PER) { - update_psw_addr(s); + update_psw_addr_disp(s, 0); gen_helper_per_store_real(cpu_env); } return DISAS_NEXT; @@ -4743,7 +4743,7 @@ static DisasJumpType op_svc(DisasContext *s, DisasOps *o) { TCGv_i32 t; - update_psw_addr(s); + update_psw_addr_disp(s, 0); update_cc_op(s); t = tcg_constant_i32(get_field(s, i1) & 0xff); @@ -6545,7 +6545,7 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s) if (s->base.tb->flags & FLAG_MASK_PER) { /* An exception might be triggered, save PSW if not already done. */ if (ret == DISAS_NEXT || ret == DISAS_TOO_MANY) { - gen_psw_addr_disp(s, psw_addr, s->ilen); + update_psw_addr_disp(s, s->ilen); } /* Call the helper to check for a possible PER exception. */ @@ -6614,7 +6614,7 @@ static void s390x_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) case DISAS_NORETURN: break; case DISAS_TOO_MANY: - update_psw_addr(dc); + update_psw_addr_disp(dc, 0); /* FALLTHRU */ case DISAS_PC_UPDATED: /* Next TB starts off with CC_OP_DYNAMIC, so make sure the From patchwork Mon Feb 20 18:40:41 2023 Content-Type: text/plain; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id jk20-20020a170903331400b0019258bcf3ffsm1911676plb.56.2023.02.20.10.41.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 10:41:24 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, qemu-s390x@nongnu.org, Ilya Leoshkevich Subject: [PATCH v4 16/27] target/s390x: Don't set gbea for user-only Date: Mon, 20 Feb 2023 08:40:41 -1000 Message-Id: <20230220184052.163465-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230220184052.163465-1-richard.henderson@linaro.org> References: <20230220184052.163465-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The rest of the per_* functions have this ifdef; this one seemed to be missing. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 160c5eef59..d8dad71814 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -396,7 +396,9 @@ static void per_branch_cond(DisasContext *s, TCGCond cond, static void per_breaking_event(DisasContext *s) { +#ifndef CONFIG_USER_ONLY gen_psw_addr_disp(s, gbea, 0); +#endif } static void update_cc_op(DisasContext *s) From patchwork Mon Feb 20 18:40:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655109 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp1551815wrc; Mon, 20 Feb 2023 10:43:48 -0800 (PST) X-Google-Smtp-Source: AK7set8C0xco8K1ogRQioTmCM9alWfJajy35qGZGyP0QM6KP6DmM/hhQbmVtIy8096SEVkhxl41U X-Received: by 2002:a05:6214:248c:b0:56e:b1d2:9c2a with SMTP id gi12-20020a056214248c00b0056eb1d29c2amr6228544qvb.28.1676918628701; Mon, 20 Feb 2023 10:43:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676918628; cv=none; d=google.com; s=arc-20160816; b=Ql0GKqQzzjpIgi/ttwVYMkiFPPE3xMqRuQrpgzRCSnc94TCTxhEjwrWjeCAKeA04HF lW3YMgKCNf35JqIGLcVcPyapB4G+0NlOi+7zJWHwEAxLU3IKnpm5Ns6JwoksC7i4xuR5 0mKFGGzBOuH8afGuZ9G5RLh1lJVmC2qMrWUQecg32sN35sqJmmQj40Q5p09HTriR9mOI fLleVYZEnJqyGiMA/Zags+yYOtkw8wEp5wdpCZTC+Bvivsvz1KT0hkQHij6xPcTm599Z 1pVfMZEVHEMg0Dxh6EIJqJ1NNVd51ZUk04loar4NdOb0iqTdLCJ4JEkBs1iddtO2+M8+ 8bkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=hVAOE5bYdVyLdxBG7UtWUVaMQMKRna4hS5x0eRllW54=; b=TmhN9UMdTAvza/izTOvtrL2eonz6M/MWxBTEe8pcRk9uJOsy9HvEIkbN6ymGbM2OSO J5AQJIFYiWcBbfk19WgUXRmX66tfzsTwrR5BZ2sDlEtMZcfTwdYx/c8+aJnvaCFrrDmI wSM9WKrMx9wpqCxNSqoD0swexdXGgQl8oaejudtXej8WCxxjRc4R9ySUOnepZjBIgDUn 72gJr2sUh8eRqttRhfJ96f8Cd9snz2wxvuLTyBy/yodMDZ61wZAHe/y+FMwRYyhigD4d weQJv8nEyP7jzp6OA4NeGPFKigTuJxwJhI2Xab6XMikphdnC1dWssq7PwYsl+wiU4S0y XsKA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GnAhD7GX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id jk20-20020a170903331400b0019258bcf3ffsm1911676plb.56.2023.02.20.10.41.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 10:41:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, qemu-s390x@nongnu.org, Ilya Leoshkevich Subject: [PATCH v4 17/27] target/s390x: Introduce per_enabled Date: Mon, 20 Feb 2023 08:40:42 -1000 Message-Id: <20230220184052.163465-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230220184052.163465-1-richard.henderson@linaro.org> References: <20230220184052.163465-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Hoist the test of FLAG_MASK_PER to a helper. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index d8dad71814..433703b4c9 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -353,12 +353,21 @@ static void update_psw_addr_disp(DisasContext *s, int64_t disp) gen_psw_addr_disp(s, psw_addr, disp); } +static inline bool per_enabled(DisasContext *s) +{ +#ifdef CONFIG_USER_ONLY + return false; +#else + return unlikely(s->base.tb->flags & FLAG_MASK_PER); +#endif +} + static void per_branch(DisasContext *s, bool to_next) { #ifndef CONFIG_USER_ONLY gen_psw_addr_disp(s, gbea, 0); - if (s->base.tb->flags & FLAG_MASK_PER) { + if (per_enabled(s)) { if (to_next) { TCGv_i64 next_pc = tcg_temp_new_i64(); @@ -376,7 +385,7 @@ static void per_branch_cond(DisasContext *s, TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2) { #ifndef CONFIG_USER_ONLY - if (s->base.tb->flags & FLAG_MASK_PER) { + if (per_enabled(s)) { TCGLabel *lab = gen_new_label(); tcg_gen_brcond_i64(tcg_invert_cond(cond), arg1, arg2, lab); @@ -680,7 +689,7 @@ static void gen_op_calc_cc(DisasContext *s) static bool use_goto_tb(DisasContext *s, uint64_t dest) { - if (unlikely(s->base.tb->flags & FLAG_MASK_PER)) { + if (per_enabled(s)) { return false; } return translator_use_goto_tb(&s->base, dest); @@ -4506,7 +4515,7 @@ static DisasJumpType op_stura(DisasContext *s, DisasOps *o) { tcg_gen_qemu_st_tl(o->in1, o->in2, MMU_REAL_IDX, s->insn->data); - if (s->base.tb->flags & FLAG_MASK_PER) { + if (per_enabled(s)) { update_psw_addr_disp(s, 0); gen_helper_per_store_real(cpu_env); } @@ -6413,7 +6422,7 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s) } #ifndef CONFIG_USER_ONLY - if (s->base.tb->flags & FLAG_MASK_PER) { + if (per_enabled(s)) { TCGv_i64 addr = tcg_temp_new_i64(); gen_psw_addr_disp(s, addr, 0); @@ -6544,7 +6553,7 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s) } #ifndef CONFIG_USER_ONLY - if (s->base.tb->flags & FLAG_MASK_PER) { + if (per_enabled(s)) { /* An exception might be triggered, save PSW if not already done. */ if (ret == DISAS_NEXT || ret == DISAS_TOO_MANY) { update_psw_addr_disp(s, s->ilen); @@ -6569,7 +6578,7 @@ static void s390x_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) dc->cc_op = CC_OP_DYNAMIC; dc->ex_value = dc->base.tb->cs_base; - dc->exit_to_mainloop = (dc->base.tb->flags & FLAG_MASK_PER) || dc->ex_value; + dc->exit_to_mainloop = per_enabled(dc) || dc->ex_value; } static void s390x_tr_tb_start(DisasContextBase *db, CPUState *cs) From patchwork Mon Feb 20 18:40:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655128 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp1553784wrc; Mon, 20 Feb 2023 10:49:23 -0800 (PST) X-Google-Smtp-Source: AK7set/2/36ldoR6JoZyhoVazNA48i9azAhs02lIZXUzRkmUltNpYlDaXl8QeJtpx2/J/t5vqJhI X-Received: by 2002:ad4:5942:0:b0:56e:aeb3:52be with SMTP id eo2-20020ad45942000000b0056eaeb352bemr4485164qvb.8.1676918963394; Mon, 20 Feb 2023 10:49:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676918963; cv=none; d=google.com; s=arc-20160816; b=DACkidJ0NmI8m51dmsSHyTOH6uAiJXcMWXvb7i5iyg7viQM8XjVhy+8FW3uTQr1Grv uc+KZPT2TAH5/2qXbAL4d9QuuwKHJ+3LNaStLvFBEkzJvnaJxV/eUpcWZg9J1yaCz1bk EvUS2Gtz0aBChj1rm7iTC+9deABJHyHbsgMvwad6FDctvWtRBVL0gyi4u6dHQpec12Yv 45J9zQ7mMYvnpXryagnFX+cDZcK8UNSyfoAX/ltjO8ED41gbNPwWOFsITk8xo7JSEZxn r7SFRPCBJtls+JFjmAzwGdoKXs/khW1Ryfz1cSvgmu1toHkXFf6oFBzRH5GRwdFV+aEW 36MA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=WCjjPlh2Wg57tPbIo2qksXSfr4SotDLh83V8udd4S54=; b=sSyzm36Sn2d0alw4z6uuREYL5O7iPPDuDxCCsjzvBPQU/YHjLjAEEstLhWlM9QLc27 rgXJ/5HWc8qV3UjPICvOCDH6xtqwlYmkcJvTHVitDfgGdmy+b89jCEYB55MOENWQ1JR6 qO17YY5i/NUB8dxH/plgOegifC8hNL/PA1KCu/dd7v5wR+J8lzfqCh4aFBliKN59o9nY 0XsZ0AVlswnfpOBEAX2LTsiL1j7cOMoacReRDdc/AM7Dgu165T8LF39hDieynBREYnyy K46BjiE3y8+CBYNzsoDzyB8yaXKtZH/v0OCKHlM4ogfyFnBO8prbx1EtFk55CXubq8bu OGlA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jI7oWeaJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id jk20-20020a170903331400b0019258bcf3ffsm1911676plb.56.2023.02.20.10.41.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 10:41:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, qemu-s390x@nongnu.org, Ilya Leoshkevich Subject: [PATCH v4 18/27] target/s390x: Disable conditional branch-to-next for PER Date: Mon, 20 Feb 2023 08:40:43 -1000 Message-Id: <20230220184052.163465-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230220184052.163465-1-richard.henderson@linaro.org> References: <20230220184052.163465-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org For PER, we require a conditional call to helper_per_branch for the conditional branch. Fold the remaining optimization into a call to helper_goto_direct, which will take care of the remaining gbea adjustment. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 433703b4c9..6757a0f44f 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -1219,13 +1219,12 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, goto egress; } if (is_imm) { - if (disp == s->ilen) { - /* Branch to next. */ - per_branch(s, true); - ret = DISAS_NEXT; - goto egress; - } - if (c->cond == TCG_COND_ALWAYS) { + /* + * Do not optimize a conditional branch if PER enabled, because we + * still need a conditional call to helper_per_branch. + */ + if (c->cond == TCG_COND_ALWAYS + || (disp == s->ilen && !per_enabled(s))) { ret = help_goto_direct(s, disp); goto egress; } From patchwork Mon Feb 20 18:40:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655114 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp1552021wrc; Mon, 20 Feb 2023 10:44:22 -0800 (PST) X-Google-Smtp-Source: AK7set+6ykfQ4PhuhZdrJVceBbbCYftbAhZ83IsZOXCz/wCB3pv4ATHobgpY4TbxpfPewzW8sawi X-Received: by 2002:ac8:7d89:0:b0:3b2:365c:9a9e with SMTP id c9-20020ac87d89000000b003b2365c9a9emr2831875qtd.61.1676918661916; Mon, 20 Feb 2023 10:44:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676918661; cv=none; d=google.com; s=arc-20160816; b=f2O9tuTaJpN8OKuxWs7P8qBBYNu7GavOFtRY4tAHJl+Vnhjov1wXpaaCBOrotxhPlO jyTVJAenCXcv7jpXfAsQG42Ub24ZGpyT5Z7zEVW4DBh66v2NdiGIcbRE9DdGR/CVy6EI 1aTJwONR/EZMw/6mLZzKEUyg71Mr6dop3qSYCqV/GWXLEqBwXWXqrymC4cy+miYjuT34 0vvQmNbbYaRQlJIJAaIq4rXG75kSQ83KV5uECSYYru4i8fvPtV0CN1fxPK9A5re3I6wf nCknWbIzxpiYmCtqh2/gPcP/yHEI6IE0Ztj7IndqWGJNTLgK19UbxX3ExsEPVDJQZfg3 MFjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=+Gcs847vjJc3xC2UOWHkazgkIaAtl/2Q94u6UiZ63QI=; b=BwvezOEnnUG618dYTJ+kwJSLrlAI6I/TQLKAtCo1CQyx4tS9iEPpvWabnQcF1wRE6T xZ3/1DgSNyNCC5laxlyR3kqjHSDlU+UMYVc63zfefPpcaWTCj0OT2//VIvFwRVao1/9y 4H90lpTXYqeRQGgbKQwcvLZE+EEAA8085i46Itggf7FzgJmeOyFaCkM1LzrKWo7mJYAU 1vnSVUPVFFA4ALe8UyQWUPY9ngoIC4z9c422EV+mctofFaoex4QPuYp2fWUL9IgTYFSu p+X+V63kvw9CdI2+n4IYrMgraDH8i1XASLsNEL1tg2EbIWFg1q//tbGvpIPMfqkgF3J1 VZBg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qXoF6sn6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id jk20-20020a170903331400b0019258bcf3ffsm1911676plb.56.2023.02.20.10.41.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 10:41:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Ilya Leoshkevich Subject: [PATCH v4 19/27] target/s390x: Introduce help_goto_indirect Date: Mon, 20 Feb 2023 08:40:44 -1000 Message-Id: <20230220184052.163465-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230220184052.163465-1-richard.henderson@linaro.org> References: <20230220184052.163465-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add a small helper to handle unconditional indirect jumps. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 6757a0f44f..afa5f56fc4 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -1205,6 +1205,13 @@ static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp) } } +static DisasJumpType help_goto_indirect(DisasContext *s, TCGv_i64 dest) +{ + tcg_gen_mov_i64(psw_addr, dest); + per_branch(s, false); + return DISAS_PC_UPDATED; +} + static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, bool is_imm, int imm, TCGv_i64 cdest) { @@ -1235,9 +1242,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, goto egress; } if (c->cond == TCG_COND_ALWAYS) { - tcg_gen_mov_i64(psw_addr, cdest); - per_branch(s, false); - ret = DISAS_PC_UPDATED; + ret = help_goto_indirect(s, cdest); goto egress; } } @@ -1560,9 +1565,7 @@ static DisasJumpType op_bas(DisasContext *s, DisasOps *o) { pc_to_link_info(o->out, s); if (o->in2) { - tcg_gen_mov_i64(psw_addr, o->in2); - per_branch(s, false); - return DISAS_PC_UPDATED; + return help_goto_indirect(s, o->in2); } else { return DISAS_NEXT; } @@ -1595,9 +1598,7 @@ static DisasJumpType op_bal(DisasContext *s, DisasOps *o) { save_link_info(s, o); if (o->in2) { - tcg_gen_mov_i64(psw_addr, o->in2); - per_branch(s, false); - return DISAS_PC_UPDATED; + return help_goto_indirect(s, o->in2); } else { return DISAS_NEXT; } From patchwork Mon Feb 20 18:40:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655103 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp1551519wrc; Mon, 20 Feb 2023 10:42:58 -0800 (PST) X-Google-Smtp-Source: AK7set+Wa4oDjQPvR7qWm9Ci/LaZ3auH2DMd+/X9lhP+YoibnoCkisnvz+JzK5D/8AuY0WihKYaP X-Received: by 2002:ac8:5c86:0:b0:3b9:bc8c:c214 with SMTP id r6-20020ac85c86000000b003b9bc8cc214mr1795674qta.31.1676918578682; Mon, 20 Feb 2023 10:42:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676918578; cv=none; d=google.com; s=arc-20160816; b=D9i1rp3nkhT9dxUYJhkrETdY/2f3C1BpdgLOfm30PQzRp+iUSQzpHIarEuBt/rOD4D 29pyXRgky9So6tDhZvtshE92SGEOcuN8SlKD0F4HY9howpI5W+wyp/l9Dg3VSBapW5Zx d7ivNeqBsXohXe5CM/kDq633XrJkBR7n0oHBkqkIbM2PutF7CuHyMqllyhc2Rtk12Jw+ h3Y02lZT2DRj8u2S242kiZgx9dbj+SV/I5rvvh2ZIMSV4z4netuECPHWnMdfQNaKEGLf GlzqRROLFN01nUYOWzucP+qqIpsaNmmrr3Wpk1vBjNR1VNOX3QOsFiPz/+sJASlQEfQd Qpxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=EmEW4Ui+jZHyPbqDarHaGkbuRfLpWlEHhDk+zbdrYtU=; b=mL+RtRr4ulNwbxk/Cn7tKsmCthCLqUHE3eOcoEQ81h8PgA3yN91Cu5LV14pD97ePNJ ofruhqP6x7oYK76kexvc4BHbMS4ecHJwqqeqScqQ25L+1ifbTyPuFAVKFWEz+3NQjp+d ix9ibOxy/mvlDxVNNBwtdJOm2viRP54J2CmhS3g+B3W8cazCuUO6UKPV7iQgoLLAiRRO lUjSVg/p9teeRnZWLj0i4uYcwEHdg1AkEKOa2KQDMrKvB4gc8k1WaA3Iydz9qAKbYYkz GVs54f/R8guSlaWB2GiB8u5K6sKYP386dlStqB/ovCRfq6wmHXlQvnNwoTllSaq8sugJ j3rw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KE5M8POD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id jk20-20020a170903331400b0019258bcf3ffsm1911676plb.56.2023.02.20.10.41.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 10:41:31 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, qemu-s390x@nongnu.org, Ilya Leoshkevich Subject: [PATCH v4 20/27] target/s390x: Split per_branch Date: Mon, 20 Feb 2023 08:40:45 -1000 Message-Id: <20230220184052.163465-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230220184052.163465-1-richard.henderson@linaro.org> References: <20230220184052.163465-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Split into per_branch_dest and per_branch_disp, which can be used for direct and indirect. In preperation for TARGET_TB_PCREL, call per_branch_* before indirect branches. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index afa5f56fc4..878b220bf6 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -362,21 +362,25 @@ static inline bool per_enabled(DisasContext *s) #endif } -static void per_branch(DisasContext *s, bool to_next) +static void per_branch_dest(DisasContext *s, TCGv_i64 dest) { #ifndef CONFIG_USER_ONLY gen_psw_addr_disp(s, gbea, 0); - if (per_enabled(s)) { - if (to_next) { - TCGv_i64 next_pc = tcg_temp_new_i64(); + gen_helper_per_branch(cpu_env, gbea, dest); + } +#endif +} - gen_psw_addr_disp(s, next_pc, s->ilen); - gen_helper_per_branch(cpu_env, gbea, next_pc); - tcg_temp_free_i64(next_pc); - } else { - gen_helper_per_branch(cpu_env, gbea, psw_addr); - } +static void per_branch_disp(DisasContext *s, int64_t disp) +{ +#ifndef CONFIG_USER_ONLY + gen_psw_addr_disp(s, gbea, 0); + if (per_enabled(s)) { + TCGv_i64 dest = tcg_temp_new_i64(); + gen_psw_addr_disp(s, dest, disp); + gen_helper_per_branch(cpu_env, gbea, dest); + tcg_temp_free_i64(dest); } #endif } @@ -1188,7 +1192,7 @@ struct DisasInsn { static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp) { if (disp == s->ilen) { - per_branch(s, true); + per_branch_disp(s, disp); return DISAS_NEXT; } if (use_goto_tb(s, s->base.pc_next + disp)) { @@ -1200,7 +1204,7 @@ static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp) return DISAS_NORETURN; } else { update_psw_addr_disp(s, disp); - per_branch(s, false); + per_branch_dest(s, psw_addr); return DISAS_PC_UPDATED; } } @@ -1208,7 +1212,7 @@ static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp) static DisasJumpType help_goto_indirect(DisasContext *s, TCGv_i64 dest) { tcg_gen_mov_i64(psw_addr, dest); - per_branch(s, false); + per_branch_dest(s, psw_addr); return DISAS_PC_UPDATED; } From patchwork Mon Feb 20 18:40:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655116 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp1552233wrc; Mon, 20 Feb 2023 10:45:03 -0800 (PST) X-Google-Smtp-Source: AK7set8XA5pNVry54ixXINqQJFZ58lHrgIIAtJteX+wEL/xH7kqjRMTIWyA9kCwZXZy62dGNdv5w X-Received: by 2002:a05:6214:ac6:b0:570:ccb9:a4d0 with SMTP id g6-20020a0562140ac600b00570ccb9a4d0mr2581684qvi.16.1676918703438; Mon, 20 Feb 2023 10:45:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676918703; cv=none; d=google.com; s=arc-20160816; b=P/kaSk4NrAj/dcsDG4ye8iAuQE6/madXoMu86R5nf49bfeaFptb3sbAvyFx3m8UkUp o/R0qb1dNCmD2k6xb86CHiZft1sCRH7hthnpbdTNtg7VU9Fok6FO84UM2xgnT0k9lMHj KmfNBUYmtjhgspDGchitZBWSeGqVEWd0XdLkYkILhDOWWf10Ib6sZjuvrmHeJqwN5ntf jKFlID+u1WEgWw0vhuCpUi27GO0KMdJCDTjTRJVTg3WcbXtubqRB9657DKMYzpD0FHY4 zJI/Q63yItWkwG9L7xovbeT/0lu+EQlrKxAejKaczx7RumD3JOWibnvuI+uNppbpET10 pmVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=KFZlwHO4prWAnCAMSFhTLLBR8p62EDJKLKSzIIGOyMU=; b=XqLI+n/XEXYGMXIPftj9gcwKIb3Q9mj36ezD9WFIvj11WRBdf7c9LyCBsqY3M480gQ XaWdkJ+jZFVyYc7UodRYCBDtxHtAeDz4At8JcDWg+Z/GkmgndvVN7C0IWH6YbvTVnivZ RH/UvODBGZ68Jh26aJjkAz3BBhX32c/ePJ4XGA0yL7AlbzWrXoL8Mqj3Bv1UXZEtMOCw leImLi6tW+VkXbhaCkW+H+vwej/Ai8xSMkH7wQZHRPwbsJZdfGRciOgkpLHxkxlQrg+R lLuawKHbGN0OucoDNOFxvoAe+cbfmgjMyeqGvwjdw2D1K9NDS+EitgAZ2DR96cO5n1Bm xqFg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cQVpIT2K; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id jk20-20020a170903331400b0019258bcf3ffsm1911676plb.56.2023.02.20.10.41.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 10:41:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, qemu-s390x@nongnu.org, Ilya Leoshkevich Subject: [PATCH v4 21/27] target/s390x: Simplify help_branch Date: Mon, 20 Feb 2023 08:40:46 -1000 Message-Id: <20230220184052.163465-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230220184052.163465-1-richard.henderson@linaro.org> References: <20230220184052.163465-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Always use a tcg branch, instead of movcond. The movcond was not a bad idea before PER was added, but since then we have either 2 or 3 actions to perform on each leg of the branch, and multiple movcond is inefficient. Reorder the taken branch to be fallthrough of the tcg branch. This will be helpful later with TARGET_TB_PCREL. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 154 ++++++++++------------------------- 1 file changed, 44 insertions(+), 110 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 878b220bf6..4e39cf1646 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -385,28 +385,6 @@ static void per_branch_disp(DisasContext *s, int64_t disp) #endif } -static void per_branch_cond(DisasContext *s, TCGCond cond, - TCGv_i64 arg1, TCGv_i64 arg2) -{ -#ifndef CONFIG_USER_ONLY - if (per_enabled(s)) { - TCGLabel *lab = gen_new_label(); - tcg_gen_brcond_i64(tcg_invert_cond(cond), arg1, arg2, lab); - - gen_psw_addr_disp(s, gbea, 0); - gen_helper_per_branch(cpu_env, gbea, psw_addr); - - gen_set_label(lab); - } else { - TCGv_i64 pc = tcg_temp_new_i64(); - - gen_psw_addr_disp(s, pc, 0); - tcg_gen_movcond_i64(cond, gbea, arg1, arg2, gbea, pc); - tcg_temp_free_i64(pc); - } -#endif -} - static void per_breaking_event(DisasContext *s) { #ifndef CONFIG_USER_ONLY @@ -1221,7 +1199,6 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, { DisasJumpType ret; int64_t disp = (int64_t)imm * 2; - uint64_t dest = s->base.pc_next + disp; TCGLabel *lab; /* Take care of the special cases first. */ @@ -1251,96 +1228,53 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, } } - if (use_goto_tb(s, s->base.pc_next + s->ilen)) { - if (is_imm && use_goto_tb(s, dest)) { - /* Both exits can use goto_tb. */ - update_cc_op(s); + update_cc_op(s); - lab = gen_new_label(); - if (c->is_64) { - tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab); - } else { - tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab); - } - - /* Branch not taken. */ - tcg_gen_goto_tb(0); - gen_psw_addr_disp(s, psw_addr, s->ilen); - tcg_gen_exit_tb(s->base.tb, 0); - - /* Branch taken. */ - gen_set_label(lab); - per_breaking_event(s); - tcg_gen_goto_tb(1); - gen_psw_addr_disp(s, psw_addr, disp); - tcg_gen_exit_tb(s->base.tb, 1); - - ret = DISAS_NORETURN; - } else { - /* Fallthru can use goto_tb, but taken branch cannot. */ - /* Store taken branch destination before the brcond. This - avoids having to allocate a new local temp to hold it. - We'll overwrite this in the not taken case anyway. */ - if (!is_imm) { - tcg_gen_mov_i64(psw_addr, cdest); - } - - lab = gen_new_label(); - if (c->is_64) { - tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab); - } else { - tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab); - } - - /* Branch not taken. */ - update_cc_op(s); - tcg_gen_goto_tb(0); - gen_psw_addr_disp(s, psw_addr, s->ilen); - tcg_gen_exit_tb(s->base.tb, 0); - - gen_set_label(lab); - if (is_imm) { - gen_psw_addr_disp(s, psw_addr, disp); - } - per_breaking_event(s); - ret = DISAS_PC_UPDATED; - } - } else { - /* Fallthru cannot use goto_tb. This by itself is vanishingly rare. - Most commonly we're single-stepping or some other condition that - disables all use of goto_tb. Just update the PC and exit. */ - - TCGv_i64 next = tcg_temp_new_i64(); - - gen_psw_addr_disp(s, next, s->ilen); - if (is_imm) { - cdest = tcg_temp_new_i64(); - gen_psw_addr_disp(s, cdest, disp); - } - - if (c->is_64) { - tcg_gen_movcond_i64(c->cond, psw_addr, c->u.s64.a, c->u.s64.b, - cdest, next); - per_branch_cond(s, c->cond, c->u.s64.a, c->u.s64.b); - } else { - TCGv_i32 t0 = tcg_temp_new_i32(); - TCGv_i64 t1 = tcg_temp_new_i64(); - TCGv_i64 z = tcg_constant_i64(0); - tcg_gen_setcond_i32(c->cond, t0, c->u.s32.a, c->u.s32.b); - tcg_gen_extu_i32_i64(t1, t0); - tcg_temp_free_i32(t0); - tcg_gen_movcond_i64(TCG_COND_NE, psw_addr, t1, z, cdest, next); - per_branch_cond(s, TCG_COND_NE, t1, z); - tcg_temp_free_i64(t1); - } - - tcg_temp_free_i64(next); - if (is_imm) { - tcg_temp_free_i64(cdest); - } - ret = DISAS_PC_UPDATED; + /* + * Store taken branch destination before the brcond. This + * avoids having to allocate a new local temp to hold it. + * We'll overwrite this in the not taken case anyway. + */ + if (!is_imm) { + tcg_gen_mov_i64(psw_addr, cdest); } + lab = gen_new_label(); + if (c->is_64) { + tcg_gen_brcond_i64(tcg_invert_cond(c->cond), + c->u.s64.a, c->u.s64.b, lab); + } else { + tcg_gen_brcond_i32(tcg_invert_cond(c->cond), + c->u.s32.a, c->u.s32.b, lab); + } + + /* Branch taken. */ + if (is_imm) { + gen_psw_addr_disp(s, psw_addr, disp); + } + per_branch_dest(s, psw_addr); + + if (is_imm && use_goto_tb(s, s->base.pc_next + disp)) { + tcg_gen_goto_tb(0); + tcg_gen_exit_tb(s->base.tb, 0); + } else { + tcg_gen_lookup_and_goto_ptr(); + } + + gen_set_label(lab); + + /* Branch not taken. */ + if (use_goto_tb(s, s->base.pc_next + s->ilen)) { + tcg_gen_goto_tb(1); + gen_psw_addr_disp(s, psw_addr, s->ilen); + tcg_gen_exit_tb(s->base.tb, 1); + } else { + gen_psw_addr_disp(s, psw_addr, s->ilen); + tcg_gen_lookup_and_goto_ptr(); + } + + ret = DISAS_NORETURN; + egress: free_compare(c); return ret; From patchwork Mon Feb 20 18:40:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655124 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp1553238wrc; Mon, 20 Feb 2023 10:47:48 -0800 (PST) X-Google-Smtp-Source: AK7set9l0ZtOX4BK14TbKN8ZLdiU4NMVl2BbVT4H0hjeii+j10xu0upBaEcxN9k00sy+iQNb62WR X-Received: by 2002:ad4:5d65:0:b0:537:4b09:670f with SMTP id fn5-20020ad45d65000000b005374b09670fmr5229065qvb.25.1676918867657; Mon, 20 Feb 2023 10:47:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676918867; cv=none; d=google.com; s=arc-20160816; b=T2CT6Q3Q9b+eQnUVVuCEVAv1j8QlvD6bPXXFw1hmS8JU28mvAdJ3QdFjH1CacGyvJS rCLuVHQNDoyyycqVKivKITpKWNrA8QUyh8UIHDW+AGbKsfzqHe70co8rzWv61M2Vlvhc VjtGL4uI1sZqJib5tKpLeS38yTuBK6qSW8DpZOKMqjOiEKK5wfKgm0VJyeZf3RxTNYl7 hj0ZE+iOin26S4QgP1TOYcg62tcEG2jZZoG8hf32FcyqVkvRgcF7L/oIqKAXYRk7s79o SzOn5C1EoYpFlgZ6acbrJrmGSOxlGFg6PyYgBxJHH+QdwC+z9JtFFtZqIPiwFiZ0tm0E tWjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=yGToGuwwYtvWTL4/oWkEUIL2elnwxjyqoTAnw+xRj6w=; b=SMoXPB0Hw4W+V24WqnUxF1bnB3rAqLVzPsy5ZuJ1OUqqjeB8FCN8nOoD2xHywDTyw1 5BEwD4VYzlK5N7j9tV4nE7ITudsVoZ1nGuPl/PaxrAwQQuQg134OGVvvVWreXKvOyM5X 97eIbHzMljirLAkevVTHjWSoq8QdzZ3quBQnTeKtS5AFhuW4w2kk+pPpyQiasWBgpFQo eys9+syAnztFNLGRftlHawjq6klUMtuvcc3xAJZAZ3dwkfK5IVQL+nANoG50QroKxdMs asQLBm7rMrb9MMbMoA0YyD0ZeqgYjDuPaCHHCXTdLdOAHvCcr6YUfQaVpD41B2bl6Vmx vy7g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="EIu/snbx"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id jk20-20020a170903331400b0019258bcf3ffsm1911676plb.56.2023.02.20.10.41.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 10:41:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, qemu-s390x@nongnu.org, Ilya Leoshkevich Subject: [PATCH v4 22/27] target/s390x: Split per_breaking_event from per_branch_* Date: Mon, 20 Feb 2023 08:40:47 -1000 Message-Id: <20230220184052.163465-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230220184052.163465-1-richard.henderson@linaro.org> References: <20230220184052.163465-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This allows us to update gbea before other updates to psw_addr, which will be important for TARGET_TB_PCREL. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 4e39cf1646..8fbbbf8bbd 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -365,7 +365,6 @@ static inline bool per_enabled(DisasContext *s) static void per_branch_dest(DisasContext *s, TCGv_i64 dest) { #ifndef CONFIG_USER_ONLY - gen_psw_addr_disp(s, gbea, 0); if (per_enabled(s)) { gen_helper_per_branch(cpu_env, gbea, dest); } @@ -375,7 +374,6 @@ static void per_branch_dest(DisasContext *s, TCGv_i64 dest) static void per_branch_disp(DisasContext *s, int64_t disp) { #ifndef CONFIG_USER_ONLY - gen_psw_addr_disp(s, gbea, 0); if (per_enabled(s)) { TCGv_i64 dest = tcg_temp_new_i64(); gen_psw_addr_disp(s, dest, disp); @@ -1169,13 +1167,14 @@ struct DisasInsn { static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp) { + per_breaking_event(s); + if (disp == s->ilen) { per_branch_disp(s, disp); return DISAS_NEXT; } if (use_goto_tb(s, s->base.pc_next + disp)) { update_cc_op(s); - per_breaking_event(s); tcg_gen_goto_tb(0); update_psw_addr_disp(s, disp); tcg_gen_exit_tb(s->base.tb, 0); @@ -1189,6 +1188,7 @@ static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp) static DisasJumpType help_goto_indirect(DisasContext *s, TCGv_i64 dest) { + per_breaking_event(s); tcg_gen_mov_i64(psw_addr, dest); per_branch_dest(s, psw_addr); return DISAS_PC_UPDATED; @@ -1249,6 +1249,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, } /* Branch taken. */ + per_breaking_event(s); if (is_imm) { gen_psw_addr_disp(s, psw_addr, disp); } From patchwork Mon Feb 20 18:40:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655117 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp1552420wrc; Mon, 20 Feb 2023 10:45:36 -0800 (PST) X-Google-Smtp-Source: AK7set+WcFbxR58ywbfklLuUL5xqEBTTCMiwzfoyvydHz5oT/WCC6qi+mOgv0mKHAUGzDQz4eU8o X-Received: by 2002:a05:6214:c8e:b0:56e:ba7e:35e0 with SMTP id r14-20020a0562140c8e00b0056eba7e35e0mr3679659qvr.48.1676918735967; Mon, 20 Feb 2023 10:45:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676918735; cv=none; d=google.com; s=arc-20160816; b=Ns9+s7Blsv72/KlovD/w/pJupy870dJFvTRMeF+1Ej1KHJC8XYeghT/s+RtKSAGRuv 2tkFvDTAc7NrqZcwW+pWfCPegO3ek4tzX20GXeBF/fzVhvglhDvU2WSmmkk8KPCOb2ot 3mYaowg0mSQsCXIJtZWQXNGNqBilRAeD+AKfaWcvxjnbguInC9l3PKC5jh1OvDAHU658 qcthdAgbYhRZC5YWvQOX0J1w3hkhmIB3ARlKqHrPB7TrneRPKJOpDWAC+mTW3Rpq+PKJ nOgWO9Kz+xmBjNboUTFfMEjoNKB5qtq8YsN/ok+fZmZsi1ZmEWVvU/adtOgINPt4ATzw J3Dw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=cyCAXVLuk59H/kOzKITUKZ8TOliuBbhdnYn70YklQIk=; b=CfFjpOoEnYF539xQ61mK5uJjqXBL2Eymy6GN79Z5UbjoEASzLxadgA6opww66sVXDz 6QhXOK3hIMc9FG/3pASEpgv6jvFRdSH4RAbbU4L/J/g3Wchjb5LJfpgVDs2gFpTkgp9N pHX6H1N05zk/6SjRr7Nyqm4JXEo6yc3xgGZakkb/FenSY/MyeM3sl5xc2rDo3cgwxATI wy+LONyqucwMVBjSvP2Nk3EBUohZIj74MsTA8jPIdWH/f8zTAzV2XcHoULWwCBrUyM/P AlzXCEGA851Vrh/aK1Pb+yeXc8CCP2R6jDn2yGmNKZ252/xr5K5ved9IbG/29K2vd+0U pguA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yeypxRVO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id jk20-20020a170903331400b0019258bcf3ffsm1911676plb.56.2023.02.20.10.41.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 10:41:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, qemu-s390x@nongnu.org, Ilya Leoshkevich Subject: [PATCH v4 23/27] target/s390x: Remove PER check from use_goto_tb Date: Mon, 20 Feb 2023 08:40:48 -1000 Message-Id: <20230220184052.163465-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230220184052.163465-1-richard.henderson@linaro.org> References: <20230220184052.163465-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org While it is common for the PC update to happen in the shadow of a goto_tb, it is not required to be there. By moving it before the goto_tb, we can also place the call to helper_per_branch there, and then afterward chain to the next tb. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 8fbbbf8bbd..24d8d84727 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -669,9 +669,6 @@ static void gen_op_calc_cc(DisasContext *s) static bool use_goto_tb(DisasContext *s, uint64_t dest) { - if (per_enabled(s)) { - return false; - } return translator_use_goto_tb(&s->base, dest); } @@ -1173,15 +1170,16 @@ static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp) per_branch_disp(s, disp); return DISAS_NEXT; } + + update_psw_addr_disp(s, disp); + per_branch_dest(s, psw_addr); + if (use_goto_tb(s, s->base.pc_next + disp)) { update_cc_op(s); tcg_gen_goto_tb(0); - update_psw_addr_disp(s, disp); tcg_gen_exit_tb(s->base.tb, 0); return DISAS_NORETURN; } else { - update_psw_addr_disp(s, disp); - per_branch_dest(s, psw_addr); return DISAS_PC_UPDATED; } } From patchwork Mon Feb 20 18:40:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655127 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp1553707wrc; Mon, 20 Feb 2023 10:49:09 -0800 (PST) X-Google-Smtp-Source: AK7set+ZFqU1/4aLNHk9BUbtdxTL1lAlalre/ZkWG5m1kF/RhESGhz7mJG+jmSjNR0hTj6283ioW X-Received: by 2002:a05:6214:3017:b0:56e:bc57:d646 with SMTP id ke23-20020a056214301700b0056ebc57d646mr6163761qvb.43.1676918949635; Mon, 20 Feb 2023 10:49:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676918949; cv=none; d=google.com; s=arc-20160816; b=yVgQwD8Hc3SP/Yy8HH3y52G45KqW6ruc2DUxFO6xkas8q14yWiqAaIGC9v5oFTHrVB 5anoKri+c/zlcVTb3/L2z1+1ptR+G0VDx6juvhUMxku0QYhQ9c1r88TpMItyt3CryzZO N14ILVWWiCI51+NbGoMUBo6EDjThAItajqRdGKt/+KedfmtDTEsV4eyTjMnPyaCAedYF hOn2VAqC0Zs4HqhRDtmvrZah5svA0cls6/Zxd7VRWNj2QkYhQSXYT91LTQIR3yMCo84P ftHi/xRHx8rH8qc5XwDpNlZfgyZ2e5m3EyFVUBHYBgrVI9hhP4QyKbv8+Es3/+rWzt62 z+sQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=qoDF/rY8HtyNlykYqkZFXY86Nrt61o0/K7nWThd7Dr8=; b=N9Q2x+DZbVUDZBYRwhREtdvCB+5xMfYBcFfsKwKL4697YBKoiEfgMPrPrrHKlr+I5a xmySnm8XI8awheLjoQxUYdQZ8b/wu1wXVFVAmDMCnAKaHYfu9zX3oGfxty+Gu1/osXLk SJ1I3vwLdQJLJaxyJ6J3JEgDrlS0PfVOWeGGz2wpHG4Ez5qiuGsZ2sGbu87MzkMTqmS2 u06szG+g0uCRvkvQsU+2P/RT14UFKm5LST5uJOhlMN3YKNhPtn4QKM+NKObpf0q4RAaF wbgyaDULWte6zGR4vdlTFU0sgD9aX2oEqVo8zOTEwi+BH2LcLpm1gXXkt6g1XCindprY JaNw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hvKZ9EHh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id jk20-20020a170903331400b0019258bcf3ffsm1911676plb.56.2023.02.20.10.41.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 10:41:39 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, qemu-s390x@nongnu.org, Ilya Leoshkevich Subject: [PATCH v4 24/27] target/s390x: Fix successful-branch PER events Date: Mon, 20 Feb 2023 08:40:49 -1000 Message-Id: <20230220184052.163465-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230220184052.163465-1-richard.henderson@linaro.org> References: <20230220184052.163465-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Ilya Leoshkevich The branching code sets per_perc_atmid, but afterwards it does goto_tb/exit_tb, so per_check_exception() added by translate_one() is not reached. Fix by raising PER exception in per_branch(). Signed-off-by: Ilya Leoshkevich Message-Id: <20221130174610.434590-1-iii@linux.ibm.com> Signed-off-by: Richard Henderson --- target/s390x/tcg/misc_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/s390x/tcg/misc_helper.c b/target/s390x/tcg/misc_helper.c index 576157b1f3..e5015daf07 100644 --- a/target/s390x/tcg/misc_helper.c +++ b/target/s390x/tcg/misc_helper.c @@ -618,6 +618,7 @@ void HELPER(per_branch)(CPUS390XState *env, uint64_t from, uint64_t to) || get_per_in_range(env, to)) { env->per_address = from; env->per_perc_atmid = PER_CODE_EVENT_BRANCH | get_per_atmid(env); + tcg_s390_program_interrupt(env, PGM_PER, GETPC()); } } } From patchwork Mon Feb 20 18:40:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655112 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp1551910wrc; Mon, 20 Feb 2023 10:44:02 -0800 (PST) X-Google-Smtp-Source: AK7set8ZwDzMYrbghO+wN+mj6qx5708681xyOm88vkG1HMxFBnAs5DJez5ShCPKDZXgotZ7+dJdq X-Received: by 2002:a05:622a:409:b0:3a9:818f:db3d with SMTP id n9-20020a05622a040900b003a9818fdb3dmr20001985qtx.53.1676918642634; Mon, 20 Feb 2023 10:44:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676918642; cv=none; d=google.com; s=arc-20160816; b=kDGgFSrcKFSS/ir4NJEuVXqbVb2kj10RwxP38MQNkxZKYnoNUsWddlTP6SC09QqPuJ Xo5Lbt37FTLX097mVIjpMpMBExi45u7cmZYwvaLApoU5pKZvWlOlUlC430gspSIkoOP0 ybmjVbOh9rNXzXQaKZGybME8uqLiLxwcMSyqby5PNkh2qSdQiW2kKKrSKmxUPtygzwwY 9Crl/M1twKdsV2XFk11HAvzivhC4EdyKcuzpBTf+/GsknjceMggGlZ8GjC6EnuCEXqpK /bQJ6qM1+Vgms7xF2Ne1LQ0COm4Bc20ib4ahCZcErp4aZQXHBjCFxO0sVLYuoF53xkhm cgBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ZWlppU2XNhFXTdVt0C0CpRj3rW11FE4bGKcS7c5hawE=; b=nW1OzRdOAu8D8/ELDyDvP9yqdTdAFTIByxLa4XBjYwjK5K2AmejRuJMWcqFKJCFE0U xYJ0tXPQ+AtJ5HBUhUrHurGyiqjdzIDb8//SU3GpmNCHsMqDHiZZSXqdWtGHv+hcrseo zgifSKLUW7coJZH9u3yHG0ioyld2LGERlfe1dj3HD1wq2VHQoFpgvy+WSMZc/ABF/ynA dydRMC8e+fH23ghudTpcCq+iGITC0T7enctPYbuiPMm9iH1hSjhpH3kE2MpGR4DNUtn8 +DPnlVCPUsGmTYidd9TcvmZnrdO8T65IaDWaxUwJAkrs8rdU8aPyKITqeotK1zZSQWn4 FecQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YkXS++rA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id jk20-20020a170903331400b0019258bcf3ffsm1911676plb.56.2023.02.20.10.41.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 10:41:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, qemu-s390x@nongnu.org, Ilya Leoshkevich Subject: [PATCH v4 25/27] tests/tcg/s390x: Add per.S Date: Mon, 20 Feb 2023 08:40:50 -1000 Message-Id: <20230220184052.163465-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230220184052.163465-1-richard.henderson@linaro.org> References: <20230220184052.163465-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Ilya Leoshkevich Add a small test to avoid regressions. Signed-off-by: Ilya Leoshkevich Message-Id: <20221130174610.434590-2-iii@linux.ibm.com> Signed-off-by: Richard Henderson --- tests/tcg/s390x/Makefile.softmmu-target | 1 + tests/tcg/s390x/per.S | 55 +++++++++++++++++++++++++ 2 files changed, 56 insertions(+) create mode 100644 tests/tcg/s390x/per.S diff --git a/tests/tcg/s390x/Makefile.softmmu-target b/tests/tcg/s390x/Makefile.softmmu-target index 725b6c598d..c286d22a9f 100644 --- a/tests/tcg/s390x/Makefile.softmmu-target +++ b/tests/tcg/s390x/Makefile.softmmu-target @@ -9,3 +9,4 @@ QEMU_OPTS=-action panic=exit-failure -kernel TESTS += unaligned-lowcore TESTS += bal TESTS += sam +TESTS += per diff --git a/tests/tcg/s390x/per.S b/tests/tcg/s390x/per.S new file mode 100644 index 0000000000..02f8422c44 --- /dev/null +++ b/tests/tcg/s390x/per.S @@ -0,0 +1,55 @@ +#define N_ITERATIONS 10 + + .org 0x8d +ilc: + .org 0x8e +program_interruption_code: + .org 0x96 +per_code: + .org 0x150 +program_old_psw: + .org 0x1d0 /* program new PSW */ + .quad 0,pgm_handler + .org 0x200 /* lowcore padding */ + + .globl _start +_start: + lpswe per_on_psw +start_per: + lghi %r0,N_ITERATIONS + xgr %r1,%r1 + lctlg %c9,%c11,per_on_regs +loop: + brct %r0,loop + lctlg %c9,%c11,per_off_regs + cgijne %r1,N_ITERATIONS-1,fail /* expected number of events? */ + lpswe success_psw +fail: + lpswe failure_psw + +pgm_handler: + chhsi program_interruption_code,0x80 /* PER event? */ + jne fail + cli per_code,0x80 /* successful-branching event? */ + jne fail + la %r1,1(%r1) /* increment event counter */ + mvc return_psw(8),program_old_psw + lg %r3,program_old_psw+8 + llgc %r2,ilc + sgr %r3,%r2 /* rewind PSW */ + stg %r3,return_psw+8 + lpswe return_psw + + .align 8 +per_on_psw: + .quad 0x4000000000000000,start_per +per_on_regs: + .quad 0x80000000,0,-1 /* successful-branching everywhere */ +per_off_regs: + .quad 0,0,0 +return_psw: + .quad 0,0 +success_psw: + .quad 0x2000000000000,0xfff /* see is_special_wait_psw() */ +failure_psw: + .quad 0x2000000000000,0 /* disabled wait */ From patchwork Mon Feb 20 18:40:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655129 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp1554012wrc; Mon, 20 Feb 2023 10:50:06 -0800 (PST) X-Google-Smtp-Source: AK7set9vjMJVEjpD/1a2HdEIAQNdqyc8rZkCmGfM5WMeW3+ql6KzO2zE0kcPL+jeLfBosxVShtRo X-Received: by 2002:ac8:5b06:0:b0:3bd:6c0:9c8e with SMTP id m6-20020ac85b06000000b003bd06c09c8emr1800215qtw.2.1676919006366; Mon, 20 Feb 2023 10:50:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676919006; cv=none; d=google.com; s=arc-20160816; b=cMh+/Hbd4FA3+KecL2p1++6k6E1H5XjAsLK5q06DEfJyPn1UOLpl3UKCdVVouuGwWk Fo5UaG2UWxMm3Gonw1hAAKPeAaOzFxR6q69vRQFR9Vk4SGlyQ27aRj/s6VVJX1X8zRcG qGhjSLJikLUFFEGc3Qs0LZvhNb9eOsA0+/p/qYlPg59AvFFBPfqG6yjo8rB9kr07Im2W bTn/Tt40J8Spr4X59+yMzD4SswFi66x6gKFrUN1jMzk0vEgHDvuoughm3ZNjB1vQZN0e YL8xSUmCdg9rKFmgp55t7MjrldtoW1MrXH/HGQbL9NTjjMIICWU+DVRkIxI3A9kBtPAY RM7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=zXucR7EhGSIkydzJkgAPzsrJnH+F7Rth0vxWHmdJQnQ=; b=Kr5Lg2RoEDIqM0BoRs+SeHuwt+G0L82UC4uXQQvaytdDHeRbzEtYDBYPTLtw6JwM9p 6H7EbP0Fs6ddGOJtAP6VM1MpTDAv0j3xVEeirdS9LHuJjFhNWNE0MaPo2TklnOBPlAbH p0lMZNwbij4fxXgrgWi+HIW0y3tXTot6gZV7VILhMRfiSpYXn9bnO+VEjHHJFtK7DtOS msbNu0jQjFfY/JnEYVQpwWNw0xz5l5E1dsRXvaihVki/QuIPhKr5Kavt9BvqIKci+EIv +bnwwb9zRCtyTyEG4tceUpUEY+n8w+zuJ77RvKGyDAYervkQPNfchz6WgcR7yV0prJPG HmGQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bDSr6QIz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id jk20-20020a170903331400b0019258bcf3ffsm1911676plb.56.2023.02.20.10.41.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 10:41:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, qemu-s390x@nongnu.org, Ilya Leoshkevich Subject: [PATCH v4 26/27] target/s390x: Pass original r2 register to BCR Date: Mon, 20 Feb 2023 08:40:51 -1000 Message-Id: <20230220184052.163465-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230220184052.163465-1-richard.henderson@linaro.org> References: <20230220184052.163465-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We do not modify any general-purpose registers in BCR, which means that we may be able to avoid saving the value across a branch. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/insn-data.h.inc | 2 +- target/s390x/tcg/translate.c | 10 ++++++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.h.inc index 9d2d35f084..bdfc09db3e 100644 --- a/target/s390x/tcg/insn-data.h.inc +++ b/target/s390x/tcg/insn-data.h.inc @@ -121,7 +121,7 @@ /* BRANCH INDIRECT ON CONDITION */ C(0xe347, BIC, RXY_b, MIE2,0, m2_64w, 0, 0, bc, 0) /* BRANCH ON CONDITION */ - C(0x0700, BCR, RR_b, Z, 0, r2_nz, 0, 0, bc, 0) + C(0x0700, BCR, RR_b, Z, 0, r2_o_nz, 0, 0, bc, 0) C(0x4700, BC, RX_b, Z, 0, a2, 0, 0, bc, 0) /* BRANCH RELATIVE ON CONDITION */ C(0xa704, BRC, RI_c, Z, 0, 0, 0, 0, bc, 0) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 24d8d84727..e4db5f1c02 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -5754,6 +5754,16 @@ static void in2_r2_nz(DisasContext *s, DisasOps *o) } #define SPEC_in2_r2_nz 0 +static void in2_r2_o_nz(DisasContext *s, DisasOps *o) +{ + int r2 = get_field(s, r2); + if (r2 != 0) { + o->in2 = regs[r2]; + o->g_in2 = true; + } +} +#define SPEC_in2_r2_o_nz 0 + static void in2_r2_8s(DisasContext *s, DisasOps *o) { o->in2 = tcg_temp_new_i64(); From patchwork Mon Feb 20 18:40:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655113 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp1551921wrc; Mon, 20 Feb 2023 10:44:04 -0800 (PST) X-Google-Smtp-Source: AK7set8LBpjXiTZjJ8y5HEU7XdhajrUL0t8NSP78SHZN0WR8ICcXe9Xl0OieGpCg3Ci6AmdNqWtl X-Received: by 2002:a05:622a:34f:b0:3b8:2602:9a35 with SMTP id r15-20020a05622a034f00b003b826029a35mr15997108qtw.52.1676918643970; Mon, 20 Feb 2023 10:44:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676918643; cv=none; d=google.com; s=arc-20160816; b=l3MHkGGNg+51KnbpOt4q1YpEwy7wYEJ106GEAM85RXdI48xXJtjMCww0Ufyz1mXFO/ IEpTCKwdrMtFw2Gxgn6JBG8YxrZPS8SNQEu3QqAlsCUU75xctqlW1NTtKOIeUjq6VMxl 2gPY7MsTI9qxMXqRmZyfuOhm281iqK8cFLRoApB4aHciDdXB4WeL0MuC5sPlXYirmBlv A2xy9hZ35k0tiYkPuVRXATuHslU5sTpo5HP5euMBitwtS9rirKduf5H+rwP28W6MvU4Y hrqyFZJfHJNflxLR43328fHMIY9Aw+WLWc2inpRRcjdkI9LNZDnQN8PgHYwD00WP8xta /8kQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=nhcflml4JRvY7oryEDQJR+jOvLdQs2W3Z2C+LbDJ1BM=; b=1D0nTKYiDYuxmmVhpT0S6FacX03sPotN/d4i87N+xEdPDrpoy0LKS3SWK4RIpwiGDG gpT8LB11luYE28L7W3NGAVp8w5ck+VbN2o/DwbTfkHSozOE2EOTBrAxsDzAmBJk1Kryi sAZmgkEmb5IyhI0YnvKZrZlw/keEixiqmJ/9R3gJtmV44Q3IhNvlzIvAoWeP3vjI91Y0 EC3jrznxdwxj3lenweUhcGHnQPCS3xRSWDBhgIV250YqrcgvQUP2s1LrQBsEOIuNJQuH BlEMxCwwMURGeSuwguW2qVpoomIn79woJkamas6WpLaf/OXkDk4SyCcM9LUUhcB3s38B ld5Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IEIzH0rI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id jk20-20020a170903331400b0019258bcf3ffsm1911676plb.56.2023.02.20.10.41.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 10:41:44 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, qemu-s390x@nongnu.org, Ilya Leoshkevich Subject: [PATCH v4 27/27] target/s390x: Enable TARGET_TB_PCREL Date: Mon, 20 Feb 2023 08:40:52 -1000 Message-Id: <20230220184052.163465-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230220184052.163465-1-richard.henderson@linaro.org> References: <20230220184052.163465-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/cpu-param.h | 4 ++ target/s390x/cpu.c | 12 +++++ target/s390x/tcg/translate.c | 86 +++++++++++++++++++++++------------- 3 files changed, 71 insertions(+), 31 deletions(-) diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h index bf951a002e..52bb95de57 100644 --- a/target/s390x/cpu-param.h +++ b/target/s390x/cpu-param.h @@ -14,4 +14,8 @@ #define TARGET_VIRT_ADDR_SPACE_BITS 64 #define NB_MMU_MODES 4 +#ifndef CONFIG_USER_ONLY +# define TARGET_TB_PCREL 1 +#endif + #endif diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index b10a8541ff..933ff06395 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -37,6 +37,7 @@ #ifndef CONFIG_USER_ONLY #include "sysemu/reset.h" #endif +#include "exec/exec-all.h" #define CR0_RESET 0xE0UL #define CR14_RESET 0xC2000000UL; @@ -83,6 +84,16 @@ uint64_t s390_cpu_get_psw_mask(CPUS390XState *env) return r; } +static void s390_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) +{ + /* The program counter is always up to date with TARGET_TB_PCREL. */ + if (!TARGET_TB_PCREL) { + S390CPU *cpu = S390_CPU(cs); + cpu->env.psw.addr = tb_pc(tb); + } +} + static void s390_cpu_set_pc(CPUState *cs, vaddr value) { S390CPU *cpu = S390_CPU(cs); @@ -274,6 +285,7 @@ static void s390_cpu_reset_full(DeviceState *dev) static const struct TCGCPUOps s390_tcg_ops = { .initialize = s390x_translate_init, + .synchronize_from_tb = s390_cpu_synchronize_from_tb, .restore_state_to_opc = s390x_restore_state_to_opc, #ifdef CONFIG_USER_ONLY diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index e4db5f1c02..a016d23d53 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -139,6 +139,7 @@ struct DisasContext { DisasContextBase base; const DisasInsn *insn; TCGOp *insn_start; + target_ulong pc_save; DisasFields fields; uint64_t ex_value; uint32_t ilen; @@ -163,29 +164,6 @@ static uint64_t inline_branch_hit[CC_OP_MAX]; static uint64_t inline_branch_miss[CC_OP_MAX]; #endif -static void gen_psw_addr_disp(DisasContext *s, TCGv_i64 dest, int64_t disp) -{ - tcg_gen_movi_i64(dest, s->base.pc_next + disp); -} - -static void pc_to_link_info(TCGv_i64 out, DisasContext *s) -{ - TCGv_i64 tmp; - - if (s->base.tb->flags & FLAG_MASK_64) { - gen_psw_addr_disp(s, out, s->ilen); - return; - } - - tmp = tcg_temp_new_i64(); - gen_psw_addr_disp(s, tmp, s->ilen); - if (s->base.tb->flags & FLAG_MASK_32) { - tcg_gen_ori_i64(tmp, tmp, 0x80000000); - } - tcg_gen_deposit_i64(out, out, tmp, 0, 32); - tcg_temp_free_i64(tmp); -} - static TCGv_i64 psw_addr; static TCGv_i64 psw_mask; static TCGv_i64 gbea; @@ -348,9 +326,39 @@ static void return_low128(TCGv_i64 dest) tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUS390XState, retxl)); } +static void gen_psw_addr_disp(DisasContext *s, TCGv_i64 dest, int64_t disp) +{ + assert(s->pc_save != -1); + if (TARGET_TB_PCREL) { + disp += s->base.pc_next - s->pc_save; + tcg_gen_addi_i64(dest, psw_addr, disp); + } else { + tcg_gen_movi_i64(dest, s->base.pc_next + disp); + } +} + +static void pc_to_link_info(TCGv_i64 out, DisasContext *s) +{ + TCGv_i64 tmp; + + if (s->base.tb->flags & FLAG_MASK_64) { + gen_psw_addr_disp(s, out, s->ilen); + return; + } + + tmp = tcg_temp_new_i64(); + gen_psw_addr_disp(s, tmp, s->ilen); + if (s->base.tb->flags & FLAG_MASK_32) { + tcg_gen_ori_i64(tmp, tmp, 0x80000000); + } + tcg_gen_deposit_i64(out, out, tmp, 0, 32); + tcg_temp_free_i64(tmp); +} + static void update_psw_addr_disp(DisasContext *s, int64_t disp) { gen_psw_addr_disp(s, psw_addr, disp); + s->pc_save = s->base.pc_next + disp; } static inline bool per_enabled(DisasContext *s) @@ -1188,6 +1196,7 @@ static DisasJumpType help_goto_indirect(DisasContext *s, TCGv_i64 dest) { per_breaking_event(s); tcg_gen_mov_i64(psw_addr, dest); + s->pc_save = -1; per_branch_dest(s, psw_addr); return DISAS_PC_UPDATED; } @@ -1197,6 +1206,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, { DisasJumpType ret; int64_t disp = (int64_t)imm * 2; + TCGv_i64 cdest_save = NULL; TCGLabel *lab; /* Take care of the special cases first. */ @@ -1229,12 +1239,12 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, update_cc_op(s); /* - * Store taken branch destination before the brcond. This - * avoids having to allocate a new local temp to hold it. - * We'll overwrite this in the not taken case anyway. + * Save taken branch destination across the brcond if required. */ if (!is_imm) { - tcg_gen_mov_i64(psw_addr, cdest); + cdest_save = tcg_temp_local_new_i64(); + tcg_gen_mov_i64(cdest_save, cdest); + cdest = cdest_save; } lab = gen_new_label(); @@ -1250,6 +1260,11 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, per_breaking_event(s); if (is_imm) { gen_psw_addr_disp(s, psw_addr, disp); + } else { + tcg_gen_mov_i64(psw_addr, cdest); + } + if (cdest_save) { + tcg_temp_free_i64(cdest_save); } per_branch_dest(s, psw_addr); @@ -1263,15 +1278,15 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, gen_set_label(lab); /* Branch not taken. */ + gen_psw_addr_disp(s, psw_addr, s->ilen); if (use_goto_tb(s, s->base.pc_next + s->ilen)) { tcg_gen_goto_tb(1); - gen_psw_addr_disp(s, psw_addr, s->ilen); tcg_gen_exit_tb(s->base.tb, 1); } else { - gen_psw_addr_disp(s, psw_addr, s->ilen); tcg_gen_lookup_and_goto_ptr(); } + s->pc_save = -1; ret = DISAS_NORETURN; egress: @@ -6523,6 +6538,7 @@ static void s390x_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) /* Note cpu_get_tb_cpu_state asserts PC is masked for the mode. */ + dc->pc_save = dc->base.pc_first; dc->cc_op = CC_OP_DYNAMIC; dc->ex_value = dc->base.tb->cs_base; dc->exit_to_mainloop = per_enabled(dc) || dc->ex_value; @@ -6535,9 +6551,13 @@ static void s390x_tr_tb_start(DisasContextBase *db, CPUState *cs) static void s390x_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc = container_of(dcbase, DisasContext, base); + target_ulong pc_arg = dc->base.pc_next; + if (TARGET_TB_PCREL) { + pc_arg &= ~TARGET_PAGE_MASK; + } /* Delay the set of ilen until we've read the insn. */ - tcg_gen_insn_start(dc->base.pc_next, dc->cc_op, 0); + tcg_gen_insn_start(pc_arg, dc->cc_op, 0); dc->insn_start = tcg_last_op(); } @@ -6631,7 +6651,11 @@ void s390x_restore_state_to_opc(CPUState *cs, CPUS390XState *env = &cpu->env; int cc_op = data[1]; - env->psw.addr = data[0]; + if (TARGET_TB_PCREL) { + env->psw.addr = (env->psw.addr & TARGET_PAGE_MASK) | data[0]; + } else { + env->psw.addr = data[0]; + } /* Update the CC opcode if it is not already up-to-date. */ if ((cc_op != CC_OP_DYNAMIC) && (cc_op != CC_OP_STATIC)) {