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[83.9.1.117]) by smtp.gmail.com with ESMTPSA id m11-20020a19520b000000b004cb34b81150sm249903lfb.282.2023.02.16.02.51.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 02:51:43 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , "Rafael J. Wysocki" , Viresh Kumar , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2] cpufreq: qcom-hw: Simplify counting frequency domains Date: Thu, 16 Feb 2023 11:51:40 +0100 Message-Id: <20230216105140.3938749-1-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org For quite some time, this driver has been performing some quite low-level DT operations. Simplify that using platform_get_resource. Signed-off-by: Konrad Dybcio Reviewed-by: Bjorn Andersson --- v1 -> v2: - remove stray newline near probe return - s/doing performing/performing/ v1: https://lore.kernel.org/linux-arm-msm/20230216102956.3933639-1-konrad.dybcio@linaro.org/T/#u drivers/cpufreq/qcom-cpufreq-hw.c | 29 ++++++----------------------- 1 file changed, 6 insertions(+), 23 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c index 2f581d2d617d..575a4461c25a 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -29,6 +29,8 @@ #define GT_IRQ_STATUS BIT(2) +#define MAX_FREQ_DOMAINS 3 + struct qcom_cpufreq_soc_data { u32 reg_enable; u32 reg_domain_state; @@ -651,10 +653,9 @@ static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev) { struct clk_hw_onecell_data *clk_data; struct device *dev = &pdev->dev; - struct device_node *soc_node; struct device *cpu_dev; struct clk *clk; - int ret, i, num_domains, reg_sz; + int ret, i, num_domains; clk = clk_get(dev, "xo"); if (IS_ERR(clk)) @@ -681,24 +682,9 @@ static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev) if (ret) return ret; - /* Allocate qcom_cpufreq_data based on the available frequency domains in DT */ - soc_node = of_get_parent(dev->of_node); - if (!soc_node) - return -EINVAL; - - ret = of_property_read_u32(soc_node, "#address-cells", ®_sz); - if (ret) - goto of_exit; - - ret = of_property_read_u32(soc_node, "#size-cells", &i); - if (ret) - goto of_exit; - - reg_sz += i; - - num_domains = of_property_count_elems_of_size(dev->of_node, "reg", sizeof(u32) * reg_sz); - if (num_domains <= 0) - return num_domains; + for (num_domains = 0; num_domains < MAX_FREQ_DOMAINS; num_domains++) + if (!platform_get_resource(pdev, IORESOURCE_MEM, num_domains)) + break; qcom_cpufreq.data = devm_kzalloc(dev, sizeof(struct qcom_cpufreq_data) * num_domains, GFP_KERNEL); @@ -762,9 +748,6 @@ static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev) else dev_dbg(dev, "QCOM CPUFreq HW driver initialized\n"); -of_exit: - of_node_put(soc_node); - return ret; }