From patchwork Fri Feb 17 14:20:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Devi Priya X-Patchwork-Id: 654523 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4FAE5C6379F for ; Fri, 17 Feb 2023 14:21:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229516AbjBQOVS (ORCPT ); Fri, 17 Feb 2023 09:21:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49292 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229539AbjBQOVR (ORCPT ); Fri, 17 Feb 2023 09:21:17 -0500 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 13F573B3E5; Fri, 17 Feb 2023 06:21:09 -0800 (PST) Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 31HAA6LU024385; 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Fri, 17 Feb 2023 14:21:00 GMT Received: from devipriy-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Fri, 17 Feb 2023 06:20:55 -0800 From: Devi Priya To: , , , , , , , , , CC: , , , , , , Subject: [PATCH V2 2/6] regulator: qcom_smd: Add s1 sub-node to mp5496 regulator Date: Fri, 17 Feb 2023 19:50:26 +0530 Message-ID: <20230217142030.16012-3-quic_devipriy@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230217142030.16012-1-quic_devipriy@quicinc.com> References: <20230217142030.16012-1-quic_devipriy@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: vYCq1PYbDiCPUIbdcbZ3avD1WKBNGcgR X-Proofpoint-ORIG-GUID: vYCq1PYbDiCPUIbdcbZ3avD1WKBNGcgR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.170.22 definitions=2023-02-17_08,2023-02-17_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 adultscore=0 spamscore=0 bulkscore=0 mlxscore=0 malwarescore=0 mlxlogscore=974 suspectscore=0 clxscore=1015 phishscore=0 impostorscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2302170130 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Adding s1 sub-node entry to mp5496 regulator node Signed-off-by: Devi Priya --- Changes in V2: - Dropped ipq9574 compatible as the existing MP5496 support is extended for S1 regulator .../devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml b/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml index 8c45f53212b1..a8ca8e0b27f8 100644 --- a/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml @@ -22,7 +22,7 @@ description: Each sub-node is identified using the node's name, with valid values listed for each of the pmics below. - For mp5496, s2 + For mp5496, s1, s2 For pm2250, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19, l20, l21, l22 From patchwork Fri Feb 17 14:20:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Devi Priya X-Patchwork-Id: 654522 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC15BC6379F for ; Fri, 17 Feb 2023 14:21:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229553AbjBQOVg (ORCPT ); Fri, 17 Feb 2023 09:21:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49538 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229649AbjBQOVf (ORCPT ); Fri, 17 Feb 2023 09:21:35 -0500 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6FA3B6D78F; Fri, 17 Feb 2023 06:21:16 -0800 (PST) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 31HCh5IT007130; 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Fri, 17 Feb 2023 14:21:12 GMT Received: from devipriy-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Fri, 17 Feb 2023 06:21:06 -0800 From: Devi Priya To: , , , , , , , , , CC: , , , , , , Subject: [PATCH V2 4/6] regulator: qcom_smd: Add support to define the bootup voltage Date: Fri, 17 Feb 2023 19:50:28 +0530 Message-ID: <20230217142030.16012-5-quic_devipriy@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230217142030.16012-1-quic_devipriy@quicinc.com> References: <20230217142030.16012-1-quic_devipriy@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: YEMFytLkcXna97A2s7soBw90a_vnxzlX X-Proofpoint-ORIG-GUID: YEMFytLkcXna97A2s7soBw90a_vnxzlX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.170.22 definitions=2023-02-17_09,2023-02-17_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 phishscore=0 malwarescore=0 adultscore=0 mlxlogscore=926 priorityscore=1501 impostorscore=0 lowpriorityscore=0 mlxscore=0 suspectscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2302170130 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Kernel does not know the initial voltage set by the bootloaders. During regulator registration, the voltage variable is just declared and it is zero. Based on that, the regulator framework considers current the voltage as zero and tries to bring up each regulator to minimum the supported voltage. This introduces a dip in the voltage during kernel boot and gets stabilized once the voltage scaling comes into picture. To avoid the voltage dip, adding support to define the bootup voltage set by the boodloaders and based on it, regulator framework understands that proper voltage is already set Co-developed-by: Praveenkumar I Signed-off-by: Praveenkumar I Signed-off-by: Devi Priya --- Changes in V2: - Added the bootup voltages to s2 and l2 regulators drivers/regulator/qcom_smd-regulator.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/regulator/qcom_smd-regulator.c b/drivers/regulator/qcom_smd-regulator.c index a40e66cea7e7..5f9fe6b9d368 100644 --- a/drivers/regulator/qcom_smd-regulator.c +++ b/drivers/regulator/qcom_smd-regulator.c @@ -800,12 +800,13 @@ struct rpm_regulator_data { u32 id; const struct regulator_desc *desc; const char *supply; + int boot_uV; /* To store the bootup voltage set by bootloaders */ }; static const struct rpm_regulator_data rpm_mp5496_regulators[] = { - { "s1", QCOM_SMD_RPM_SMPA, 1, &mp5496_smpa1, "s1" }, - { "s2", QCOM_SMD_RPM_SMPA, 2, &mp5496_smpa2, "s2" }, - { "l2", QCOM_SMD_RPM_LDOA, 2, &mp5496_ldoa2, "l2" }, + { "s1", QCOM_SMD_RPM_SMPA, 1, &mp5496_smpa1, "s1", 875000 }, + { "s2", QCOM_SMD_RPM_SMPA, 2, &mp5496_smpa2, "s2", 875000 }, + { "l2", QCOM_SMD_RPM_LDOA, 2, &mp5496_ldoa2, "l2", 2950000 }, {} }; @@ -1388,6 +1389,9 @@ static int rpm_regulator_init_vreg(struct qcom_rpm_reg *vreg, struct device *dev vreg->type = rpm_data->type; vreg->id = rpm_data->id; + if (rpm_data->boot_uV) + vreg->uV = rpm_data->boot_uV; + memcpy(&vreg->desc, rpm_data->desc, sizeof(vreg->desc)); vreg->desc.name = rpm_data->name; vreg->desc.supply_name = rpm_data->supply; From patchwork Fri Feb 17 14:20:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Devi Priya X-Patchwork-Id: 654521 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62ABBC6379F for ; Fri, 17 Feb 2023 14:21:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229575AbjBQOVq (ORCPT ); Fri, 17 Feb 2023 09:21:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50122 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229867AbjBQOVo (ORCPT ); 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Fri, 17 Feb 2023 14:21:24 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 31HELO4m025162 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 17 Feb 2023 14:21:24 GMT Received: from devipriy-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Fri, 17 Feb 2023 06:21:18 -0800 From: Devi Priya To: , , , , , , , , , CC: , , , , , , Subject: [PATCH V2 6/6] arm64: dts: qcom: ipq9574: Add cpufreq support Date: Fri, 17 Feb 2023 19:50:30 +0530 Message-ID: <20230217142030.16012-7-quic_devipriy@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230217142030.16012-1-quic_devipriy@quicinc.com> References: <20230217142030.16012-1-quic_devipriy@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: _1oZblUYjUfXvl7ArZfyPYNgaUgvgJVv X-Proofpoint-ORIG-GUID: _1oZblUYjUfXvl7ArZfyPYNgaUgvgJVv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.170.22 definitions=2023-02-17_09,2023-02-17_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 mlxlogscore=780 mlxscore=0 adultscore=0 malwarescore=0 clxscore=1015 phishscore=0 spamscore=0 impostorscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2302170130 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add cpu freq nodes in the device tree to bump cpu frequency above 800MHz Co-developed-by: Praveenkumar I Signed-off-by: Praveenkumar I Signed-off-by: Devi Priya --- Changes in V2: - Created a separate patch for CPU freq related nodes - Updated cpu0-supply to cpu-supply in CPU@0 node - Moved the opp-table-cpu node after memory to have it sorted alphabetically - Added a new line between the subnodes in opp-table-cpu arch/arm64/boot/dts/qcom/ipq9574.dtsi | 58 +++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 2f300cbab93e..2bb4053641da 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -6,6 +6,7 @@ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ +#include #include #include #include @@ -73,6 +74,10 @@ reg = <0x0>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq9574_s1>; }; CPU1: cpu@1 { @@ -81,6 +86,10 @@ reg = <0x1>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq9574_s1>; }; CPU2: cpu@2 { @@ -89,6 +98,10 @@ reg = <0x2>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq9574_s1>; }; CPU3: cpu@3 { @@ -97,6 +110,10 @@ reg = <0x3>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq9574_s1>; }; L2_0: l2-cache { @@ -111,6 +128,47 @@ reg = <0x0 0x40000000 0x0 0x0>; }; + cpu_opp_table: opp-table-cpu { + compatible = "operating-points-v2"; + opp-shared; + + opp-936000000 { + opp-hz = /bits/ 64 <936000000>; + opp-microvolt = <725000>; + clock-latency-ns = <200000>; + }; + + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <787500>; + clock-latency-ns = <200000>; + }; + + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <862500>; + clock-latency-ns = <200000>; + }; + + opp-1488000000 { + opp-hz = /bits/ 64 <1488000000>; + opp-microvolt = <925000>; + clock-latency-ns = <200000>; + }; + + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <987500>; + clock-latency-ns = <200000>; + }; + + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-microvolt = <1062500>; + clock-latency-ns = <200000>; + }; + }; + firmware { scm { compatible = "qcom,scm-ipq9574", "qcom,scm";