From patchwork Thu Feb 16 13:23:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raag Jadav X-Patchwork-Id: 654270 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0158C64ED6 for ; Thu, 16 Feb 2023 13:25:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230180AbjBPNZS (ORCPT ); Thu, 16 Feb 2023 08:25:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38056 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230176AbjBPNZQ (ORCPT ); Thu, 16 Feb 2023 08:25:16 -0500 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 50A625456B; Thu, 16 Feb 2023 05:25:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676553914; x=1708089914; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=exkUBYfDlKiFbWEf4ZXH6U0C9Ft4nl3TOo39Vx5rZDk=; b=Xpb0LVm/9SOhnwLOxiMRnu/5qMQM7Fv7hBvdDXiQKP/Qzkd+iHBq7CMm Tt4Aepynihwv9SAjplzzUyAGD6cfJ2l9fAVw8OCl+dkBoYiIFWvwqgZup ZORUD6vixI5s10T5Ql2mM0ZNOoAvtqBmDh8Z0s7Fxv6X4fF4/BZ6SJaKo pQnYyYcP6EDVMBHmzsd03JcFamMyEciVzS79wSX3nuE+cqOVaFLvhla2R +TGNsSTh2a+6yCVHjvqXWSCsBj+A9OQPtNTUSRH7KFUhYb7LEOoo/jDGW N+N8/qPpFoFaGm1KllN1TKq0mdOnUM1IIOxoqJxYhCkDh3tRJFLmoPIF1 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10623"; a="331711615" X-IronPort-AV: E=Sophos;i="5.97,302,1669104000"; d="scan'208";a="331711615" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Feb 2023 05:25:11 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10623"; a="999033090" X-IronPort-AV: E=Sophos;i="5.97,302,1669104000"; d="scan'208";a="999033090" Received: from inesxmail01.iind.intel.com ([10.223.154.20]) by fmsmga005.fm.intel.com with ESMTP; 16 Feb 2023 05:25:08 -0800 Received: from inlubt0316.iind.intel.com (inlubt0316.iind.intel.com [10.191.20.213]) by inesxmail01.iind.intel.com (Postfix) with ESMTP id 044E915B6C; Thu, 16 Feb 2023 18:55:08 +0530 (IST) Received: by inlubt0316.iind.intel.com (Postfix, from userid 12101951) id F1E48189; Thu, 16 Feb 2023 18:55:07 +0530 (IST) From: Raag Jadav To: linus.walleij@linaro.org, brgl@bgdev.pl, andriy.shevchenko@linux.intel.com Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, mallikarjunappa.sangannavar@intel.com, pandith.n@intel.com, Raag Jadav Subject: [PATCH v1 1/3] gpio: tangier: Introduce tangier gpio driver Date: Thu, 16 Feb 2023 18:53:54 +0530 Message-Id: <20230216132356.29922-2-raag.jadav@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230216132356.29922-1-raag.jadav@intel.com> References: <20230216132356.29922-1-raag.jadav@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Pandith N Intel Elkhart Lake and Merrifield platforms have same GPIO IP. Intel Tangier implements the common GPIO functionalities for both Elkhart Lake and Merrifield platforms. Signed-off-by: Pandith N Co-developed-by: Raag Jadav Signed-off-by: Raag Jadav --- MAINTAINERS | 1 + drivers/gpio/Kconfig | 8 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-tangier.c | 505 ++++++++++++++++++++++++++++++++++++ drivers/gpio/gpio-tangier.h | 110 ++++++++ 5 files changed, 625 insertions(+) create mode 100644 drivers/gpio/gpio-tangier.c create mode 100644 drivers/gpio/gpio-tangier.h diff --git a/MAINTAINERS b/MAINTAINERS index 7f86d02cb427..3e9d42b2747d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10395,6 +10395,7 @@ F: drivers/gpio/gpio-ml-ioh.c F: drivers/gpio/gpio-pch.c F: drivers/gpio/gpio-sch.c F: drivers/gpio/gpio-sodaville.c +F: drivers/gpio/gpio-tangier.c INTEL GVT-g DRIVERS (Intel GPU Virtualization) M: Zhenyu Wang diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index ec7cfd4f52b1..952afd4e28b6 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -626,6 +626,14 @@ config GPIO_SYSCON help Say yes here to support GPIO functionality though SYSCON driver. +config GPIO_TANGIER + tristate + select GPIOLIB_IRQCHIP + help + GPIO support for Intel Tangier and compatible platforms. + + If built as a module its name will be gpio-tangier. + config GPIO_TB10X bool select GPIO_GENERIC diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 010587025fc8..a6cea9d2c973 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -146,6 +146,7 @@ obj-$(CONFIG_GPIO_SPRD) += gpio-sprd.o obj-$(CONFIG_GPIO_STMPE) += gpio-stmpe.o obj-$(CONFIG_GPIO_STP_XWAY) += gpio-stp-xway.o obj-$(CONFIG_GPIO_SYSCON) += gpio-syscon.o +obj-$(CONFIG_GPIO_TANGIER) += gpio-tangier.o obj-$(CONFIG_GPIO_TB10X) += gpio-tb10x.o obj-$(CONFIG_GPIO_TC3589X) += gpio-tc3589x.o obj-$(CONFIG_GPIO_TEGRA186) += gpio-tegra186.o diff --git a/drivers/gpio/gpio-tangier.c b/drivers/gpio/gpio-tangier.c new file mode 100644 index 000000000000..a3d91a0ca7be --- /dev/null +++ b/drivers/gpio/gpio-tangier.c @@ -0,0 +1,505 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Intel Tangier GPIO driver + * + * Copyright (c) 2016, 2021, 2023 Intel Corporation. + * + * Authors: Andy Shevchenko + * Pandith N + * Raag Jadav + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "gpio-tangier.h" + +#define GCCR 0x000 /* Controller configuration */ +#define GPLR 0x004 /* Pin level r/o */ +#define GPDR 0x01c /* Pin direction */ +#define GPSR 0x034 /* Pin set w/o */ +#define GPCR 0x04c /* Pin clear w/o */ +#define GRER 0x064 /* Rising edge detect */ +#define GFER 0x07c /* Falling edge detect */ +#define GFBR 0x094 /* Glitch filter bypass */ +#define GIMR 0x0ac /* Interrupt mask */ +#define GISR 0x0c4 /* Interrupt source */ +#define GITR 0x300 /* Input type */ +#define GLPR 0x318 /* Level input polarity */ + +static inline u32 tng_gpio_readl(void __iomem *base, u32 offset) +{ + return readl(base + offset); +} + +static inline void tng_gpio_writel(void __iomem *base, u32 offset, u32 value) +{ + writel(value, base + offset); +} + +static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned int offset, + unsigned int reg) +{ + struct tng_gpio *priv = gpiochip_get_data(chip); + u8 reg_offset = offset / 32; + + return priv->reg_base + reg + reg_offset * 4; +} + +static void __iomem *gpio_reg_and_bit(struct gpio_chip *chip, unsigned int offset, + unsigned int reg, u8 *bit) +{ + struct tng_gpio *priv = gpiochip_get_data(chip); + u8 reg_offset = offset / 32; + u8 shift = offset % 32; + + *bit = shift; + return priv->reg_base + reg + reg_offset * 4; +} + +static int tng_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + void __iomem *gplr; + u8 shift; + + gplr = gpio_reg_and_bit(chip, offset, GPLR, &shift); + + return !!(readl(gplr) & BIT(shift)); +} + +static void tng_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) +{ + struct tng_gpio *priv = gpiochip_get_data(chip); + u32 reg = value ? GPSR : GPCR; + unsigned long flags; + + raw_spin_lock_irqsave(&priv->lock, flags); + + tng_gpio_writel(priv->reg_base, reg, BIT(offset)); + + raw_spin_unlock_irqrestore(&priv->lock, flags); +} + +static int tng_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) +{ + struct tng_gpio *priv = gpiochip_get_data(chip); + unsigned long flags; + void __iomem *gpdr; + u32 value; + u8 shift; + + gpdr = gpio_reg_and_bit(chip, offset, GPDR, &shift); + + raw_spin_lock_irqsave(&priv->lock, flags); + + value = readl(gpdr); + value &= ~BIT(shift); + writel(value, gpdr); + + raw_spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static int tng_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, + int value) +{ + struct tng_gpio *priv = gpiochip_get_data(chip); + unsigned long flags; + void __iomem *gpdr; + u8 shift; + + gpdr = gpio_reg_and_bit(chip, offset, GPDR, &shift); + tng_gpio_set(chip, offset, value); + + raw_spin_lock_irqsave(&priv->lock, flags); + + value = readl(gpdr); + value |= BIT(shift); + writel(value, gpdr); + + raw_spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static int tng_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) +{ + struct tng_gpio *priv = gpiochip_get_data(chip); + + if (tng_gpio_readl(priv->reg_base, GPDR) & BIT(offset)) + return GPIO_LINE_DIRECTION_OUT; + + return GPIO_LINE_DIRECTION_IN; +} + +static int tng_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset, + unsigned int debounce) +{ + struct tng_gpio *priv = gpiochip_get_data(chip); + unsigned long flags; + void __iomem *gfbr; + u32 value; + u8 shift; + + gfbr = gpio_reg_and_bit(chip, offset, GFBR, &shift); + + raw_spin_lock_irqsave(&priv->lock, flags); + + value = readl(gfbr); + if (debounce) + value &= ~BIT(shift); + else + value |= BIT(shift); + writel(value, gfbr); + + raw_spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static int tng_gpio_set_config(struct gpio_chip *chip, unsigned int offset, + unsigned long config) +{ + u32 debounce; + + switch (pinconf_to_config_param(config)) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + return gpiochip_generic_config(chip, offset, config); + case PIN_CONFIG_INPUT_DEBOUNCE: + debounce = pinconf_to_config_argument(config); + return tng_gpio_set_debounce(chip, offset, debounce); + default: + return -ENOTSUPP; + } +} + +static void tng_irq_ack(struct irq_data *d) +{ + struct tng_gpio *priv = irq_data_get_irq_chip_data(d); + irq_hw_number_t gpio = irqd_to_hwirq(d); + unsigned long flags; + void __iomem *gisr; + u8 shift; + + gisr = gpio_reg_and_bit(&priv->chip, gpio, GISR, &shift); + + raw_spin_lock_irqsave(&priv->lock, flags); + writel(BIT(shift), gisr); + raw_spin_unlock_irqrestore(&priv->lock, flags); +} + +static void tng_irq_unmask_mask(struct tng_gpio *priv, u32 gpio, bool unmask) +{ + unsigned long flags; + void __iomem *gimr; + u32 value; + u8 shift; + + gimr = gpio_reg_and_bit(&priv->chip, gpio, GIMR, &shift); + + raw_spin_lock_irqsave(&priv->lock, flags); + + value = readl(gimr); + if (unmask) + value |= BIT(shift); + else + value &= ~BIT(shift); + writel(value, gimr); + + raw_spin_unlock_irqrestore(&priv->lock, flags); +} + +static void tng_irq_mask(struct irq_data *d) +{ + struct tng_gpio *priv = irq_data_get_irq_chip_data(d); + irq_hw_number_t gpio = irqd_to_hwirq(d); + + tng_irq_unmask_mask(priv, gpio, false); + gpiochip_disable_irq(&priv->chip, gpio); +} + +static void tng_irq_unmask(struct irq_data *d) +{ + struct tng_gpio *priv = irq_data_get_irq_chip_data(d); + irq_hw_number_t gpio = irqd_to_hwirq(d); + + gpiochip_enable_irq(&priv->chip, gpio); + tng_irq_unmask_mask(priv, gpio, true); +} + +static int tng_irq_set_type(struct irq_data *d, unsigned int type) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct tng_gpio *priv = gpiochip_get_data(gc); + irq_hw_number_t gpio = irqd_to_hwirq(d); + void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER); + void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER); + void __iomem *gitr = gpio_reg(&priv->chip, gpio, GITR); + void __iomem *glpr = gpio_reg(&priv->chip, gpio, GLPR); + u8 shift = gpio % 32; + unsigned long flags; + u32 value; + + raw_spin_lock_irqsave(&priv->lock, flags); + + value = readl(grer); + if (type & IRQ_TYPE_EDGE_RISING) + value |= BIT(shift); + else + value &= ~BIT(shift); + writel(value, grer); + + value = readl(gfer); + if (type & IRQ_TYPE_EDGE_FALLING) + value |= BIT(shift); + else + value &= ~BIT(shift); + writel(value, gfer); + + /* + * To prevent glitches from triggering an unintended level interrupt, + * configure GLPR register first and then configure GITR. + */ + value = readl(glpr); + if (type & IRQ_TYPE_LEVEL_LOW) + value |= BIT(shift); + else + value &= ~BIT(shift); + writel(value, glpr); + + if (type & IRQ_TYPE_LEVEL_MASK) { + value = readl(gitr); + value |= BIT(shift); + writel(value, gitr); + + irq_set_handler_locked(d, handle_level_irq); + } else if (type & IRQ_TYPE_EDGE_BOTH) { + value = readl(gitr); + value &= ~BIT(shift); + writel(value, gitr); + + irq_set_handler_locked(d, handle_edge_irq); + } + + raw_spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static int tng_irq_set_wake(struct irq_data *d, unsigned int on) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct tng_gpio *priv = gpiochip_get_data(gc); + irq_hw_number_t gpio = irqd_to_hwirq(d); + void __iomem *gwmr = gpio_reg(&priv->chip, gpio, priv->reg.gwmr); + void __iomem *gwsr = gpio_reg(&priv->chip, gpio, priv->reg.gwsr); + u8 shift = gpio % 32; + unsigned long flags; + u32 value; + + raw_spin_lock_irqsave(&priv->lock, flags); + + /* Clear the existing wake status */ + writel(BIT(shift), gwsr); + + value = readl(gwmr); + if (on) + value |= BIT(shift); + else + value &= ~BIT(shift); + writel(value, gwmr); + + raw_spin_unlock_irqrestore(&priv->lock, flags); + + dev_dbg(priv->dev, "%s wake for gpio %lu\n", str_enable_disable(on), gpio); + return 0; +} + +static const struct irq_chip tng_irqchip = { + .name = "gpio-tangier", + .irq_ack = tng_irq_ack, + .irq_mask = tng_irq_mask, + .irq_unmask = tng_irq_unmask, + .irq_set_type = tng_irq_set_type, + .irq_set_wake = tng_irq_set_wake, + .flags = IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + +static void tng_irq_handler(struct irq_desc *desc) +{ + struct gpio_chip *gc = irq_desc_get_handler_data(desc); + struct tng_gpio *priv = gpiochip_get_data(gc); + struct irq_chip *irqchip = irq_desc_get_chip(desc); + unsigned long base, gpio; + + chained_irq_enter(irqchip, desc); + + /* Check GPIO controller to check which pin triggered the interrupt */ + for (base = 0; base < priv->chip.ngpio; base += 32) { + void __iomem *gisr = gpio_reg(&priv->chip, base, GISR); + void __iomem *gimr = gpio_reg(&priv->chip, base, GIMR); + unsigned long pending, enabled; + + pending = readl(gisr); + enabled = readl(gimr); + + /* Only interrupts that are enabled */ + pending &= enabled; + + for_each_set_bit(gpio, &pending, 32) + generic_handle_domain_irq(gc->irq.domain, base + gpio); + } + + chained_irq_exit(irqchip, desc); +} + +static int tng_irq_init_hw(struct gpio_chip *chip) +{ + struct tng_gpio *priv = gpiochip_get_data(chip); + void __iomem *reg; + unsigned int base; + + for (base = 0; base < priv->chip.ngpio; base += 32) { + /* Clear the rising-edge detect register */ + reg = gpio_reg(&priv->chip, base, GRER); + writel(0, reg); + + /* Clear the falling-edge detect register */ + reg = gpio_reg(&priv->chip, base, GFER); + writel(0, reg); + } + + return 0; +} + +static int tng_gpio_add_pin_ranges(struct gpio_chip *chip) +{ + struct tng_gpio *priv = gpiochip_get_data(chip); + const struct tng_gpio_pinrange *range; + unsigned int i; + int ret; + + for (i = 0; i < priv->pin_info.nranges; i++) { + range = &priv->pin_info.pin_ranges[i]; + ret = gpiochip_add_pin_range(&priv->chip, + priv->pin_info.name, + range->gpio_base, + range->pin_base, + range->npins); + if (ret) { + dev_err(priv->dev, "failed to add GPIO pin range\n"); + return ret; + } + } + + return 0; +} + +int tng_gpio_probe(struct tng_gpio *gpio) +{ + struct device *dev = gpio->dev; + struct gpio_irq_chip *girq; + int ret; + + gpio->chip.label = dev_name(dev); + gpio->chip.parent = dev; + gpio->chip.request = gpiochip_generic_request; + gpio->chip.free = gpiochip_generic_free; + gpio->chip.direction_input = tng_gpio_direction_input; + gpio->chip.direction_output = tng_gpio_direction_output; + gpio->chip.get = tng_gpio_get; + gpio->chip.set = tng_gpio_set; + gpio->chip.get_direction = tng_gpio_get_direction; + gpio->chip.set_config = tng_gpio_set_config; + gpio->chip.add_pin_ranges = tng_gpio_add_pin_ranges; + + raw_spin_lock_init(&gpio->lock); + + girq = &gpio->chip.irq; + gpio_irq_chip_set_chip(girq, &tng_irqchip); + girq->init_hw = tng_irq_init_hw; + girq->parent_handler = tng_irq_handler; + girq->num_parents = 1; + girq->parents = devm_kcalloc(dev, girq->num_parents, + sizeof(*girq->parents), GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; + + girq->parents[0] = gpio->irq; + girq->first = gpio->irq_base; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_bad_irq; + + ret = devm_gpiochip_add_data(dev, &gpio->chip, gpio); + if (ret) + return dev_err_probe(dev, ret, "gpiochip_add error %d\n", ret); + + return 0; +} +EXPORT_SYMBOL_NS_GPL(tng_gpio_probe, GPIO_TANGIER); + +int tng_gpio_suspend(struct device *dev) +{ + struct tng_gpio *priv = dev_get_drvdata(dev); + struct tng_gpio_context *ctx = priv->ctx; + unsigned long flags; + + raw_spin_lock_irqsave(&priv->lock, flags); + + ctx->gplr = tng_gpio_readl(priv->reg_base, GPLR); + ctx->gpdr = tng_gpio_readl(priv->reg_base, GPDR); + ctx->grer = tng_gpio_readl(priv->reg_base, GRER); + ctx->gfer = tng_gpio_readl(priv->reg_base, GFER); + ctx->gimr = tng_gpio_readl(priv->reg_base, GIMR); + ctx->gwmr = tng_gpio_readl(priv->reg_base, priv->reg.gwmr); + + raw_spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} +EXPORT_SYMBOL_NS_GPL(tng_gpio_suspend, GPIO_TANGIER); + +int tng_gpio_resume(struct device *dev) +{ + struct tng_gpio *priv = dev_get_drvdata(dev); + struct tng_gpio_context *ctx = priv->ctx; + unsigned long flags; + + raw_spin_lock_irqsave(&priv->lock, flags); + + /* GPLR is RO, values read will restore using GPSR */ + tng_gpio_writel(priv->reg_base, GPSR, ctx->gplr); + tng_gpio_writel(priv->reg_base, GPDR, ctx->gpdr); + tng_gpio_writel(priv->reg_base, GRER, ctx->grer); + tng_gpio_writel(priv->reg_base, GFER, ctx->gfer); + tng_gpio_writel(priv->reg_base, GIMR, ctx->gimr); + tng_gpio_writel(priv->reg_base, priv->reg.gwmr, ctx->gwmr); + + raw_spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} +EXPORT_SYMBOL_NS_GPL(tng_gpio_resume, GPIO_TANGIER); + +MODULE_AUTHOR("Andy Shevchenko "); +MODULE_AUTHOR("Pandith N "); +MODULE_AUTHOR("Raag Jadav "); +MODULE_DESCRIPTION("Intel Tangier GPIO driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/gpio/gpio-tangier.h b/drivers/gpio/gpio-tangier.h new file mode 100644 index 000000000000..4850af012f17 --- /dev/null +++ b/drivers/gpio/gpio-tangier.h @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Intel Tangier GPIO functions + * + * Copyright (c) 2016, 2021, 2023 Intel Corporation. + * + * Authors: Andy Shevchenko + * Pandith N + * Raag Jadav + */ + +#ifndef _GPIO_TANGIER_H_ +#define _GPIO_TANGIER_H_ + +#include +#include +#include + +struct device; + +#define GPIO_PINRANGE(gstart, gend, pstart) \ + { \ + .gpio_base = (gstart), \ + .pin_base = (pstart), \ + .npins = (gend) - (gstart) + 1, \ + } + +/** + * struct tng_gpio_context - Context to be saved during suspend-resume + * @gplr: Pin level + * @gpdr: Pin direction + * @grer: Rising edge detect enable + * @gfer: Falling edge detect enable + * @gimr: Interrupt mask + * @gwmr: Wake mask + */ +struct tng_gpio_context { + u32 gplr; + u32 gpdr; + u32 grer; + u32 gfer; + u32 gimr; + u32 gwmr; +}; + +/** + * struct tng_wake_regs - Platform specific wake registers + * @gwmr: Wake mask + * @gwsr: Wake source + * @gsir: Secure input + */ +struct tng_wake_regs { + u32 gwmr; + u32 gwsr; + u32 gsir; +}; + +/** + * struct tng_gpio_pinrange - Map pin numbers to gpio numbers + * @gpio_base: Starting gpio number of this range + * @pin_base: Starting pin number of this range + * @npins: Number of pins in this range + */ +struct tng_gpio_pinrange { + unsigned int gpio_base; + unsigned int pin_base; + unsigned int npins; +}; + +/** + * struct tng_gpio_pin_info - Platform specific pinout information + * @pin_ranges: Pin to gpio mapping + * @nranges: Number of pin ranges + * @name: Respective pinctrl device name + */ +struct tng_gpio_pin_info { + const struct tng_gpio_pinrange *pin_ranges; + unsigned int nranges; + const char *name; +}; + +/** + * struct tng_gpio - Platform specific private data + * @chip: Instance of the gpio_chip + * @reg_base: Base address of MMIO registers + * @lock: Synchronization lock to prevent I/O race conditions + * @dev: The gpio device + * @ctx: Context to be saved during suspend-resum + * @reg: Platform specific wake registers + * @pin_info: Platform specific pinout information + * @irq: Interrupt for the gpio device + * @irq_base: Base of irq number for interrupt + */ +struct tng_gpio { + struct gpio_chip chip; + void __iomem *reg_base; + raw_spinlock_t lock; + struct device *dev; + struct tng_gpio_context *ctx; + struct tng_wake_regs reg; + struct tng_gpio_pin_info pin_info; + int irq; + int irq_base; +}; + +int tng_gpio_probe(struct tng_gpio *gpio); +int tng_gpio_suspend(struct device *dev); +int tng_gpio_resume(struct device *dev); + +#endif /* _GPIO_TANGIER_H_ */ From patchwork Thu Feb 16 13:23:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raag Jadav X-Patchwork-Id: 654658 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E55CEC636D6 for ; Thu, 16 Feb 2023 13:25:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230192AbjBPNZR (ORCPT ); Thu, 16 Feb 2023 08:25:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38016 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230126AbjBPNZP (ORCPT ); Thu, 16 Feb 2023 08:25:15 -0500 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4DC6755284; Thu, 16 Feb 2023 05:25:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676553913; x=1708089913; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=oYHBvE6Orl3dJohMcJFTy8m770BvU0foqf1oKHZFBaI=; b=A23ZW6VRdsaYGtihKdDIRvYM7Mvr5gSpqGDXr90WwV9DefpUKnQass94 nVTifl9pbziK9VkxSkR7OOviQHg9HGPaHqCZPCpqThAkhy8vvUCy2nphz wRPXcLpYKKCefd+DnUAxQgkuiGOheb0dNyykog2NKV++yKlGrccM1SfAp M5yjW+sxOR5mxj9PhCzZ5RhlYPSflRMEjSLDlI4hTIu/7TxRiKggfEsJY 4a6dZI3bYneMhBtB9TLuood/8FVeweqpxY+FAwjpWj3WLBLbzVVvVf4wL CY88gAH0GT8u0cH6zuUKz7sH/HsaFD2++GyaXCduoUj9qC64cQiYIdteE A==; X-IronPort-AV: E=McAfee;i="6500,9779,10623"; a="331711612" X-IronPort-AV: E=Sophos;i="5.97,302,1669104000"; d="scan'208";a="331711612" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Feb 2023 05:25:11 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10623"; a="999033085" X-IronPort-AV: E=Sophos;i="5.97,302,1669104000"; d="scan'208";a="999033085" Received: from inesxmail01.iind.intel.com ([10.223.154.20]) by fmsmga005.fm.intel.com with ESMTP; 16 Feb 2023 05:25:08 -0800 Received: from inlubt0316.iind.intel.com (inlubt0316.iind.intel.com [10.191.20.213]) by inesxmail01.iind.intel.com (Postfix) with ESMTP id 04EB71A9F3; Thu, 16 Feb 2023 18:55:08 +0530 (IST) Received: by inlubt0316.iind.intel.com (Postfix, from userid 12101951) id 01CDF18C; Thu, 16 Feb 2023 18:55:08 +0530 (IST) From: Raag Jadav To: linus.walleij@linaro.org, brgl@bgdev.pl, andriy.shevchenko@linux.intel.com Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, mallikarjunappa.sangannavar@intel.com, pandith.n@intel.com, Raag Jadav Subject: [PATCH v1 2/3] gpio: merrifield: Adapt to tangier driver Date: Thu, 16 Feb 2023 18:53:55 +0530 Message-Id: <20230216132356.29922-3-raag.jadav@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230216132356.29922-1-raag.jadav@intel.com> References: <20230216132356.29922-1-raag.jadav@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Pandith N Make use of Intel Tangier as a library driver for Merrifield. Signed-off-by: Pandith N Co-developed-by: Raag Jadav Signed-off-by: Raag Jadav --- drivers/gpio/Kconfig | 4 +- drivers/gpio/gpio-merrifield.c | 444 +++------------------------------ drivers/gpio/gpio-tangier.h | 5 + 3 files changed, 38 insertions(+), 415 deletions(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 952afd4e28b6..7fc7a2768705 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -631,6 +631,8 @@ config GPIO_TANGIER select GPIOLIB_IRQCHIP help GPIO support for Intel Tangier and compatible platforms. + Currently supported: + - Merrifield If built as a module its name will be gpio-tangier. @@ -1524,7 +1526,7 @@ config GPIO_BT8XX config GPIO_MERRIFIELD tristate "Intel Merrifield GPIO support" depends on X86_INTEL_MID - select GPIOLIB_IRQCHIP + select GPIO_TANGIER help Say Y here to support Intel Merrifield GPIO. diff --git a/drivers/gpio/gpio-merrifield.c b/drivers/gpio/gpio-merrifield.c index 92ea8411050d..e91749ddb38a 100644 --- a/drivers/gpio/gpio-merrifield.c +++ b/drivers/gpio/gpio-merrifield.c @@ -1,61 +1,26 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* * Intel Merrifield SoC GPIO driver * - * Copyright (c) 2016 Intel Corporation. + * Copyright (c) 2016, 2023 Intel Corporation. * Author: Andy Shevchenko */ #include #include -#include -#include +#include +#include #include #include #include -#include -#include +#include -#define GCCR 0x000 /* controller configuration */ -#define GPLR 0x004 /* pin level r/o */ -#define GPDR 0x01c /* pin direction */ -#define GPSR 0x034 /* pin set w/o */ -#define GPCR 0x04c /* pin clear w/o */ -#define GRER 0x064 /* rising edge detect */ -#define GFER 0x07c /* falling edge detect */ -#define GFBR 0x094 /* glitch filter bypass */ -#define GIMR 0x0ac /* interrupt mask */ -#define GISR 0x0c4 /* interrupt source */ -#define GITR 0x300 /* input type */ -#define GLPR 0x318 /* level input polarity */ -#define GWMR 0x400 /* wake mask */ -#define GWSR 0x418 /* wake source */ -#define GSIR 0xc00 /* secure input */ +#include "gpio-tangier.h" /* Intel Merrifield has 192 GPIO pins */ #define MRFLD_NGPIO 192 -struct mrfld_gpio_pinrange { - unsigned int gpio_base; - unsigned int pin_base; - unsigned int npins; -}; - -#define GPIO_PINRANGE(gstart, gend, pstart) \ - { \ - .gpio_base = (gstart), \ - .pin_base = (pstart), \ - .npins = (gend) - (gstart) + 1, \ - } - -struct mrfld_gpio { - struct gpio_chip chip; - void __iomem *reg_base; - raw_spinlock_t lock; - struct device *dev; -}; - -static const struct mrfld_gpio_pinrange mrfld_gpio_ranges[] = { +static const struct tng_gpio_pinrange mrfld_gpio_ranges[] = { GPIO_PINRANGE(0, 11, 146), GPIO_PINRANGE(12, 13, 144), GPIO_PINRANGE(14, 15, 35), @@ -84,316 +49,7 @@ static const struct mrfld_gpio_pinrange mrfld_gpio_ranges[] = { GPIO_PINRANGE(190, 191, 178), }; -static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned int offset, - unsigned int reg_type_offset) -{ - struct mrfld_gpio *priv = gpiochip_get_data(chip); - u8 reg = offset / 32; - - return priv->reg_base + reg_type_offset + reg * 4; -} - -static int mrfld_gpio_get(struct gpio_chip *chip, unsigned int offset) -{ - void __iomem *gplr = gpio_reg(chip, offset, GPLR); - - return !!(readl(gplr) & BIT(offset % 32)); -} - -static void mrfld_gpio_set(struct gpio_chip *chip, unsigned int offset, - int value) -{ - struct mrfld_gpio *priv = gpiochip_get_data(chip); - void __iomem *gpsr, *gpcr; - unsigned long flags; - - raw_spin_lock_irqsave(&priv->lock, flags); - - if (value) { - gpsr = gpio_reg(chip, offset, GPSR); - writel(BIT(offset % 32), gpsr); - } else { - gpcr = gpio_reg(chip, offset, GPCR); - writel(BIT(offset % 32), gpcr); - } - - raw_spin_unlock_irqrestore(&priv->lock, flags); -} - -static int mrfld_gpio_direction_input(struct gpio_chip *chip, - unsigned int offset) -{ - struct mrfld_gpio *priv = gpiochip_get_data(chip); - void __iomem *gpdr = gpio_reg(chip, offset, GPDR); - unsigned long flags; - u32 value; - - raw_spin_lock_irqsave(&priv->lock, flags); - - value = readl(gpdr); - value &= ~BIT(offset % 32); - writel(value, gpdr); - - raw_spin_unlock_irqrestore(&priv->lock, flags); - - return 0; -} - -static int mrfld_gpio_direction_output(struct gpio_chip *chip, - unsigned int offset, int value) -{ - struct mrfld_gpio *priv = gpiochip_get_data(chip); - void __iomem *gpdr = gpio_reg(chip, offset, GPDR); - unsigned long flags; - - mrfld_gpio_set(chip, offset, value); - - raw_spin_lock_irqsave(&priv->lock, flags); - - value = readl(gpdr); - value |= BIT(offset % 32); - writel(value, gpdr); - - raw_spin_unlock_irqrestore(&priv->lock, flags); - - return 0; -} - -static int mrfld_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) -{ - void __iomem *gpdr = gpio_reg(chip, offset, GPDR); - - if (readl(gpdr) & BIT(offset % 32)) - return GPIO_LINE_DIRECTION_OUT; - - return GPIO_LINE_DIRECTION_IN; -} - -static int mrfld_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset, - unsigned int debounce) -{ - struct mrfld_gpio *priv = gpiochip_get_data(chip); - void __iomem *gfbr = gpio_reg(chip, offset, GFBR); - unsigned long flags; - u32 value; - - raw_spin_lock_irqsave(&priv->lock, flags); - - if (debounce) - value = readl(gfbr) & ~BIT(offset % 32); - else - value = readl(gfbr) | BIT(offset % 32); - writel(value, gfbr); - - raw_spin_unlock_irqrestore(&priv->lock, flags); - - return 0; -} - -static int mrfld_gpio_set_config(struct gpio_chip *chip, unsigned int offset, - unsigned long config) -{ - u32 debounce; - - if ((pinconf_to_config_param(config) == PIN_CONFIG_BIAS_DISABLE) || - (pinconf_to_config_param(config) == PIN_CONFIG_BIAS_PULL_UP) || - (pinconf_to_config_param(config) == PIN_CONFIG_BIAS_PULL_DOWN)) - return gpiochip_generic_config(chip, offset, config); - - if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) - return -ENOTSUPP; - - debounce = pinconf_to_config_argument(config); - return mrfld_gpio_set_debounce(chip, offset, debounce); -} - -static void mrfld_irq_ack(struct irq_data *d) -{ - struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d); - u32 gpio = irqd_to_hwirq(d); - void __iomem *gisr = gpio_reg(&priv->chip, gpio, GISR); - unsigned long flags; - - raw_spin_lock_irqsave(&priv->lock, flags); - - writel(BIT(gpio % 32), gisr); - - raw_spin_unlock_irqrestore(&priv->lock, flags); -} - -static void mrfld_irq_unmask_mask(struct mrfld_gpio *priv, u32 gpio, bool unmask) -{ - void __iomem *gimr = gpio_reg(&priv->chip, gpio, GIMR); - unsigned long flags; - u32 value; - - raw_spin_lock_irqsave(&priv->lock, flags); - - if (unmask) - value = readl(gimr) | BIT(gpio % 32); - else - value = readl(gimr) & ~BIT(gpio % 32); - writel(value, gimr); - - raw_spin_unlock_irqrestore(&priv->lock, flags); -} - -static void mrfld_irq_mask(struct irq_data *d) -{ - struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d); - u32 gpio = irqd_to_hwirq(d); - - mrfld_irq_unmask_mask(priv, gpio, false); - gpiochip_disable_irq(&priv->chip, gpio); -} - -static void mrfld_irq_unmask(struct irq_data *d) -{ - struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d); - u32 gpio = irqd_to_hwirq(d); - - gpiochip_enable_irq(&priv->chip, gpio); - mrfld_irq_unmask_mask(priv, gpio, true); -} - -static int mrfld_irq_set_type(struct irq_data *d, unsigned int type) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct mrfld_gpio *priv = gpiochip_get_data(gc); - u32 gpio = irqd_to_hwirq(d); - void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER); - void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER); - void __iomem *gitr = gpio_reg(&priv->chip, gpio, GITR); - void __iomem *glpr = gpio_reg(&priv->chip, gpio, GLPR); - unsigned long flags; - u32 value; - - raw_spin_lock_irqsave(&priv->lock, flags); - - if (type & IRQ_TYPE_EDGE_RISING) - value = readl(grer) | BIT(gpio % 32); - else - value = readl(grer) & ~BIT(gpio % 32); - writel(value, grer); - - if (type & IRQ_TYPE_EDGE_FALLING) - value = readl(gfer) | BIT(gpio % 32); - else - value = readl(gfer) & ~BIT(gpio % 32); - writel(value, gfer); - - /* - * To prevent glitches from triggering an unintended level interrupt, - * configure GLPR register first and then configure GITR. - */ - if (type & IRQ_TYPE_LEVEL_LOW) - value = readl(glpr) | BIT(gpio % 32); - else - value = readl(glpr) & ~BIT(gpio % 32); - writel(value, glpr); - - if (type & IRQ_TYPE_LEVEL_MASK) { - value = readl(gitr) | BIT(gpio % 32); - writel(value, gitr); - - irq_set_handler_locked(d, handle_level_irq); - } else if (type & IRQ_TYPE_EDGE_BOTH) { - value = readl(gitr) & ~BIT(gpio % 32); - writel(value, gitr); - - irq_set_handler_locked(d, handle_edge_irq); - } - - raw_spin_unlock_irqrestore(&priv->lock, flags); - - return 0; -} - -static int mrfld_irq_set_wake(struct irq_data *d, unsigned int on) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct mrfld_gpio *priv = gpiochip_get_data(gc); - u32 gpio = irqd_to_hwirq(d); - void __iomem *gwmr = gpio_reg(&priv->chip, gpio, GWMR); - void __iomem *gwsr = gpio_reg(&priv->chip, gpio, GWSR); - unsigned long flags; - u32 value; - - raw_spin_lock_irqsave(&priv->lock, flags); - - /* Clear the existing wake status */ - writel(BIT(gpio % 32), gwsr); - - if (on) - value = readl(gwmr) | BIT(gpio % 32); - else - value = readl(gwmr) & ~BIT(gpio % 32); - writel(value, gwmr); - - raw_spin_unlock_irqrestore(&priv->lock, flags); - - dev_dbg(priv->dev, "%s wake for gpio %u\n", str_enable_disable(on), gpio); - return 0; -} - -static const struct irq_chip mrfld_irqchip = { - .name = "gpio-merrifield", - .irq_ack = mrfld_irq_ack, - .irq_mask = mrfld_irq_mask, - .irq_unmask = mrfld_irq_unmask, - .irq_set_type = mrfld_irq_set_type, - .irq_set_wake = mrfld_irq_set_wake, - .flags = IRQCHIP_IMMUTABLE, - GPIOCHIP_IRQ_RESOURCE_HELPERS, -}; - -static void mrfld_irq_handler(struct irq_desc *desc) -{ - struct gpio_chip *gc = irq_desc_get_handler_data(desc); - struct mrfld_gpio *priv = gpiochip_get_data(gc); - struct irq_chip *irqchip = irq_desc_get_chip(desc); - unsigned long base, gpio; - - chained_irq_enter(irqchip, desc); - - /* Check GPIO controller to check which pin triggered the interrupt */ - for (base = 0; base < priv->chip.ngpio; base += 32) { - void __iomem *gisr = gpio_reg(&priv->chip, base, GISR); - void __iomem *gimr = gpio_reg(&priv->chip, base, GIMR); - unsigned long pending, enabled; - - pending = readl(gisr); - enabled = readl(gimr); - - /* Only interrupts that are enabled */ - pending &= enabled; - - for_each_set_bit(gpio, &pending, 32) - generic_handle_domain_irq(gc->irq.domain, base + gpio); - } - - chained_irq_exit(irqchip, desc); -} - -static int mrfld_irq_init_hw(struct gpio_chip *chip) -{ - struct mrfld_gpio *priv = gpiochip_get_data(chip); - void __iomem *reg; - unsigned int base; - - for (base = 0; base < priv->chip.ngpio; base += 32) { - /* Clear the rising-edge detect register */ - reg = gpio_reg(&priv->chip, base, GRER); - writel(0, reg); - /* Clear the falling-edge detect register */ - reg = gpio_reg(&priv->chip, base, GFER); - writel(0, reg); - } - - return 0; -} - -static const char *mrfld_gpio_get_pinctrl_dev_name(struct mrfld_gpio *priv) +static const char *mrfld_gpio_get_pinctrl_dev_name(struct tng_gpio *priv) { struct acpi_device *adev; const char *name; @@ -409,37 +65,9 @@ static const char *mrfld_gpio_get_pinctrl_dev_name(struct mrfld_gpio *priv) return name; } -static int mrfld_gpio_add_pin_ranges(struct gpio_chip *chip) -{ - struct mrfld_gpio *priv = gpiochip_get_data(chip); - const struct mrfld_gpio_pinrange *range; - const char *pinctrl_dev_name; - unsigned int i; - int retval; - - pinctrl_dev_name = mrfld_gpio_get_pinctrl_dev_name(priv); - if (!pinctrl_dev_name) - return -ENOMEM; - - for (i = 0; i < ARRAY_SIZE(mrfld_gpio_ranges); i++) { - range = &mrfld_gpio_ranges[i]; - retval = gpiochip_add_pin_range(&priv->chip, pinctrl_dev_name, - range->gpio_base, - range->pin_base, - range->npins); - if (retval) { - dev_err(priv->dev, "failed to add GPIO pin range\n"); - return retval; - } - } - - return 0; -} - static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id) { - struct gpio_irq_chip *girq; - struct mrfld_gpio *priv; + struct tng_gpio *priv; u32 gpio_base, irq_base; void __iomem *base; int retval; @@ -466,49 +94,37 @@ static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id if (!priv) return -ENOMEM; + priv->ctx = devm_kzalloc(&pdev->dev, sizeof(*priv->ctx), GFP_KERNEL); + if (!priv->ctx) + return -ENOMEM; + priv->dev = &pdev->dev; priv->reg_base = pcim_iomap_table(pdev)[0]; - - priv->chip.label = dev_name(&pdev->dev); - priv->chip.parent = &pdev->dev; - priv->chip.request = gpiochip_generic_request; - priv->chip.free = gpiochip_generic_free; - priv->chip.direction_input = mrfld_gpio_direction_input; - priv->chip.direction_output = mrfld_gpio_direction_output; - priv->chip.get = mrfld_gpio_get; - priv->chip.set = mrfld_gpio_set; - priv->chip.get_direction = mrfld_gpio_get_direction; - priv->chip.set_config = mrfld_gpio_set_config; priv->chip.base = gpio_base; priv->chip.ngpio = MRFLD_NGPIO; + priv->pin_info.pin_ranges = mrfld_gpio_ranges; + priv->pin_info.nranges = ARRAY_SIZE(mrfld_gpio_ranges); priv->chip.can_sleep = false; - priv->chip.add_pin_ranges = mrfld_gpio_add_pin_ranges; - raw_spin_lock_init(&priv->lock); + priv->pin_info.name = mrfld_gpio_get_pinctrl_dev_name(priv); + if (!priv->pin_info.name) + return -ENOMEM; retval = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); if (retval < 0) return retval; - girq = &priv->chip.irq; - gpio_irq_chip_set_chip(girq, &mrfld_irqchip); - girq->init_hw = mrfld_irq_init_hw; - girq->parent_handler = mrfld_irq_handler; - girq->num_parents = 1; - girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents, - sizeof(*girq->parents), GFP_KERNEL); - if (!girq->parents) - return -ENOMEM; - girq->parents[0] = pci_irq_vector(pdev, 0); - girq->first = irq_base; - girq->default_type = IRQ_TYPE_NONE; - girq->handler = handle_bad_irq; + priv->irq = pci_irq_vector(pdev, 0); + priv->irq_base = irq_base; - retval = devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv); - if (retval) { - dev_err(&pdev->dev, "gpiochip_add error %d\n", retval); - return retval; - } + priv->reg.gwmr = GWMR_MRFLD; + priv->reg.gwsr = GWSR_MRFLD; + priv->reg.gsir = GSIR_MRFLD; + + retval = tng_gpio_probe(priv); + if (retval) + return dev_err_probe(&pdev->dev, retval, + "tng_gpio_probe error %d\n", retval); pci_set_drvdata(pdev, priv); return 0; @@ -525,9 +141,9 @@ static struct pci_driver mrfld_gpio_driver = { .id_table = mrfld_gpio_ids, .probe = mrfld_gpio_probe, }; - module_pci_driver(mrfld_gpio_driver); MODULE_AUTHOR("Andy Shevchenko "); MODULE_DESCRIPTION("Intel Merrifield SoC GPIO driver"); -MODULE_LICENSE("GPL v2"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS(GPIO_TANGIER); diff --git a/drivers/gpio/gpio-tangier.h b/drivers/gpio/gpio-tangier.h index 4850af012f17..414530c60c5a 100644 --- a/drivers/gpio/gpio-tangier.h +++ b/drivers/gpio/gpio-tangier.h @@ -18,6 +18,11 @@ struct device; +/* Merrifield specific wake registers */ +#define GWMR_MRFLD 0x400 /* Wake mask */ +#define GWSR_MRFLD 0x418 /* Wake source */ +#define GSIR_MRFLD 0xc00 /* Secure input */ + #define GPIO_PINRANGE(gstart, gend, pstart) \ { \ .gpio_base = (gstart), \ From patchwork Thu Feb 16 13:23:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raag Jadav X-Patchwork-Id: 654271 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C45BDC636CC for ; Thu, 16 Feb 2023 13:25:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230171AbjBPNZQ (ORCPT ); Thu, 16 Feb 2023 08:25:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38008 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229506AbjBPNZO (ORCPT ); Thu, 16 Feb 2023 08:25:14 -0500 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 34E8D54561; Thu, 16 Feb 2023 05:25:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676553913; x=1708089913; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=2H++iGRfR09wbs4iqdkBPck8cSAllR7ohEnhgO/4WCI=; b=lpIrJscX4Fac4jxOk4Mb8rNmUvC0xRlwTP0t/s4jqwhz87KS6hfy1hTS qIDdjNv3oyEH+iBfN6Bj+yf+KQ1GSW5n2o4Ifm3NqbY8opGSMLIzmWIYH HEk2Z9HXch39oqcMaX9L5M6/+3+y6AUmynwnAxIbsL1L8+8Ft5P+45hfd HWP7oQ+UU+cZoy/S8rYHd2VFCNBQNS7OhIl8jYE61WwqKpMBP14Wh6ev9 Af2gBFhny7YpwLo2KYVkdvkI665hGHGZImld3eQQgD1uZith97S4Vab1O DH3bVxMYTyGbOqPvtgdIZ0MUIgwQhsYHT+UnXuVPwKB0/eE049e9gjatm Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10623"; a="331711609" X-IronPort-AV: E=Sophos;i="5.97,302,1669104000"; d="scan'208";a="331711609" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Feb 2023 05:25:11 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10623"; a="999033087" X-IronPort-AV: E=Sophos;i="5.97,302,1669104000"; d="scan'208";a="999033087" Received: from inesxmail01.iind.intel.com ([10.223.154.20]) by fmsmga005.fm.intel.com with ESMTP; 16 Feb 2023 05:25:08 -0800 Received: from inlubt0316.iind.intel.com (inlubt0316.iind.intel.com [10.191.20.213]) by inesxmail01.iind.intel.com (Postfix) with ESMTP id 095DE1A9F6; Thu, 16 Feb 2023 18:55:08 +0530 (IST) Received: by inlubt0316.iind.intel.com (Postfix, from userid 12101951) id 061B9162; Thu, 16 Feb 2023 18:55:08 +0530 (IST) From: Raag Jadav To: linus.walleij@linaro.org, brgl@bgdev.pl, andriy.shevchenko@linux.intel.com Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, mallikarjunappa.sangannavar@intel.com, pandith.n@intel.com, Raag Jadav Subject: [PATCH v1 3/3] gpio: elkhartlake: Introduce Elkhart Lake PSE GPIO Date: Thu, 16 Feb 2023 18:53:56 +0530 Message-Id: <20230216132356.29922-4-raag.jadav@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230216132356.29922-1-raag.jadav@intel.com> References: <20230216132356.29922-1-raag.jadav@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Pandith N This driver adds support for Elkhart Lake PSE GPIO controller, using Intel Tangier as a library driver. Signed-off-by: Pandith N Co-developed-by: Raag Jadav Signed-off-by: Raag Jadav --- MAINTAINERS | 1 + drivers/gpio/Kconfig | 12 +++++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-elkhartlake.c | 94 +++++++++++++++++++++++++++++++++ drivers/gpio/gpio-tangier.h | 5 ++ 5 files changed, 113 insertions(+) create mode 100644 drivers/gpio/gpio-elkhartlake.c diff --git a/MAINTAINERS b/MAINTAINERS index 3e9d42b2747d..aec1a2040f32 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10389,6 +10389,7 @@ M: Andy Shevchenko L: linux-gpio@vger.kernel.org S: Supported T: git git://git.kernel.org/pub/scm/linux/kernel/git/andy/linux-gpio-intel.git +F: drivers/gpio/gpio-elkhartlake.c F: drivers/gpio/gpio-ich.c F: drivers/gpio/gpio-merrifield.c F: drivers/gpio/gpio-ml-ioh.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 7fc7a2768705..c60066d4cd72 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -242,6 +242,17 @@ config GPIO_DWAPB Say Y or M here to build support for the Synopsys DesignWare APB GPIO block. +config GPIO_ELKHARTLAKE + tristate "Intel Elkhart Lake PSE GPIO support" + depends on (X86 && ACPI) || COMPILE_TEST + select GPIO_TANGIER + help + Select this option to enable GPIO support for Intel Elkhart Lake + PSE GPIO IP. + + To compile this driver as a module, choose M here: the module will + be called gpio-elkhartlake. + config GPIO_EIC_SPRD tristate "Spreadtrum EIC support" depends on ARCH_SPRD || COMPILE_TEST @@ -632,6 +643,7 @@ config GPIO_TANGIER help GPIO support for Intel Tangier and compatible platforms. Currently supported: + - Elkhart Lake - Merrifield If built as a module its name will be gpio-tangier. diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index a6cea9d2c973..8c34d5e39eb8 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -54,6 +54,7 @@ obj-$(CONFIG_GPIO_DAVINCI) += gpio-davinci.o obj-$(CONFIG_GPIO_DLN2) += gpio-dln2.o obj-$(CONFIG_GPIO_DWAPB) += gpio-dwapb.o obj-$(CONFIG_GPIO_EIC_SPRD) += gpio-eic-sprd.o +obj-$(CONFIG_GPIO_ELKHARTLAKE) += gpio-elkhartlake.o obj-$(CONFIG_GPIO_EM) += gpio-em.o obj-$(CONFIG_GPIO_EN7523) += gpio-en7523.o obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o diff --git a/drivers/gpio/gpio-elkhartlake.c b/drivers/gpio/gpio-elkhartlake.c new file mode 100644 index 000000000000..cf728ff35857 --- /dev/null +++ b/drivers/gpio/gpio-elkhartlake.c @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Intel Elkhart Lake PSE GPIO driver + * + * Copyright (c) 2023 Intel Corporation. + * + * Authors: Pandith N + * Raag Jadav + */ + +#include +#include +#include +#include +#include + +#include "gpio-tangier.h" + +/* Each Intel EHL PSE GPIO Controller has 30 GPIO pins */ +#define EHL_PSE_NGPIO 30 + +static int ehl_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct tng_gpio *priv; + int irq, ret; + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->ctx = devm_kzalloc(dev, sizeof(*priv->ctx), GFP_KERNEL); + if (!priv->ctx) + return -ENOMEM; + + priv->reg_base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->reg_base)) + return PTR_ERR(priv->reg_base); + + priv->dev = dev; + priv->chip.base = -1; + priv->chip.ngpio = EHL_PSE_NGPIO; + priv->chip.can_sleep = false; + priv->irq = irq; + + priv->reg.gwmr = GWMR_EHL; + priv->reg.gwsr = GWSR_EHL; + priv->reg.gsir = GSIR_EHL; + + ret = tng_gpio_probe(priv); + if (ret) + return dev_err_probe(dev, ret, "tng_gpio_probe error %d\n", ret); + + platform_set_drvdata(pdev, priv); + return 0; +} + +static int ehl_gpio_suspend(struct device *dev) +{ + return tng_gpio_suspend(dev); +} + +static int ehl_gpio_resume(struct device *dev) +{ + return tng_gpio_resume(dev); +} + +static DEFINE_SIMPLE_DEV_PM_OPS(ehl_gpio_pm_ops, ehl_gpio_suspend, ehl_gpio_resume); + +static const struct platform_device_id ehl_gpio_ids[] = { + { "gpio-elkhartlake" }, + { } +}; +MODULE_DEVICE_TABLE(platform, ehl_gpio_ids); + +static struct platform_driver ehl_gpio_driver = { + .driver = { + .name = "gpio-elkhartlake", + .pm = pm_sleep_ptr(&ehl_gpio_pm_ops), + }, + .probe = ehl_gpio_probe, + .id_table = ehl_gpio_ids, +}; +module_platform_driver(ehl_gpio_driver); + +MODULE_AUTHOR("Pandith N "); +MODULE_AUTHOR("Raag Jadav "); +MODULE_DESCRIPTION("Intel Elkhart Lake PSE GPIO driver"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS(GPIO_TANGIER); diff --git a/drivers/gpio/gpio-tangier.h b/drivers/gpio/gpio-tangier.h index 414530c60c5a..6390a14ed9de 100644 --- a/drivers/gpio/gpio-tangier.h +++ b/drivers/gpio/gpio-tangier.h @@ -18,6 +18,11 @@ struct device; +/* Elkhart Lake specific wake registers */ +#define GWMR_EHL 0x100 /* Wake mask */ +#define GWSR_EHL 0x118 /* Wake source */ +#define GSIR_EHL 0x130 /* Secure input */ + /* Merrifield specific wake registers */ #define GWMR_MRFLD 0x400 /* Wake mask */ #define GWSR_MRFLD 0x418 /* Wake source */