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[209.51.188.17]) by mx.google.com with ESMTPS id 10-20020ac8574a000000b003b62c88b4ebsi1688635qtx.81.2023.02.16.06.26.00 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 16 Feb 2023 06:26:01 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tiUpkAAc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pSfAu-0005cm-F2; Thu, 16 Feb 2023 09:23:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pSfAt-0005c3-2c for qemu-devel@nongnu.org; Thu, 16 Feb 2023 09:23:51 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pSfAp-00079u-Uz for qemu-devel@nongnu.org; Thu, 16 Feb 2023 09:23:50 -0500 Received: by mail-wm1-x336.google.com with SMTP id he5so1685699wmb.3 for ; Thu, 16 Feb 2023 06:23:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JNh8xTJOWod+s7ucBgmNWDci6dZ45Cp+WXSSHvSLoZ8=; b=tiUpkAAcnadyQJ+dVkubzde61bStnA0Kbi3UuyGWDQtEL6yLFqrBOH0YNEIXCeG2/M Y0ImUy3irOA9xnWN7wtRCpZ9wvqkgEm0ktfjlLCPHuXbNuuM03m9noxAnscZp7byCftz /vR0ZVULZUZbxg4dVuJP1WA4lJ04y4gUMi6fmzg4dCoa++Ir2Itb6A4Z06NG3iORGtCh 24xIw7Hih7PmTbInUMPTtmACsstE5YJ2d8lhm6J54YzCr0gg0lxImnFJ193b3I9YRal7 07/NOPhzbMMaFH9DORST7s/FRijumX0Ze217GCFHSxg12cxUcDCnKZ7n51Y15njjuil2 RwUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JNh8xTJOWod+s7ucBgmNWDci6dZ45Cp+WXSSHvSLoZ8=; b=JoW4DFE4ultKkx3mGU2FjCGGsipRWTVhU90LWem4CtcZftjr5xbDZLxr/KaC/2Sj8Q diiXCJyznZTEfIlEI4sfJOcaIUn4BW2BD3axTGCp8Ufw42kFvUHzCsbaB1SsV5LyMQML 4WK3JaOSDo7maZE/tXsDTO+Km1SJw4LOUq/K/XNuPmF/5AsoqNzbk5lRpEKcWOGrhv3C puxUcdZByFjs2mlsteOJA/uutMIW2pDUy0qxjT6MMT9VI8WkULpCgMda1ex0Mi5bEbqS Vtv3ZzbSjBfVu6rEaT3DdBbWF5odwhbVLlV3Ja3M9GgQabg0SUce8WD6l0xVIqsvzJNe 8JQQ== X-Gm-Message-State: AO0yUKUiOVDM5oVtqL5Mkse0Rx3m0MpM8DKmGijyoQeKFZdFgC0C3jR+ cQofrgJByEHc/PRXVdLmPdo3P2nvaoUsyjgh X-Received: by 2002:a05:600c:91d:b0:3e2:668:3ed7 with SMTP id m29-20020a05600c091d00b003e206683ed7mr3871662wmp.1.1676557426291; Thu, 16 Feb 2023 06:23:46 -0800 (PST) Received: from localhost.localdomain ([81.0.6.76]) by smtp.gmail.com with ESMTPSA id p15-20020a7bcdef000000b003e21356bddcsm1966221wmj.33.2023.02.16.06.23.44 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 16 Feb 2023 06:23:45 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Dapeng Mi , Sean Christopherson , Bin Meng , Zhuocheng Ding , =?utf-8?q?Alex_Benn=C3=A9e?= , Zhenyu Wang , qemu-riscv@nongnu.org, Alistair Francis , Zhao Liu , "Edgar E. Iglesias" , Paolo Bonzini , Marcel Apfelbaum , Robert Hoo , Yanan Wang , qemu-arm@nongnu.org, Peter Maydell , =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= , Palmer Dabbelt , Like Xu , Alistair Francis , Zhao Liu , Eduardo Habkost Subject: [PATCH 1/5] hw/cpu: Extend CPUState::cluster_index documentation Date: Thu, 16 Feb 2023 15:23:34 +0100 Message-Id: <20230216142338.82982-2-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230216142338.82982-1-philmd@linaro.org> References: <20230216142338.82982-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Copy part of the description of commit f7b78602fd ("accel/tcg: Add cluster number to TCG TB hash") in tcg_cpu_init_cflags(), improving a bit CPUState::cluster_index documentation. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell --- accel/tcg/tcg-accel-ops.c | 13 ++++++++++++- include/hw/core/cpu.h | 2 ++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 19cbf1db3a..654aeec04c 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -44,7 +44,18 @@ void tcg_cpu_init_cflags(CPUState *cpu, bool parallel) { - uint32_t cflags = cpu->cluster_index << CF_CLUSTER_SHIFT; + uint32_t cflags; + + /* + * Include the cluster number in the hash we use to look up TBs. + * This is important because a TB that is valid for one cluster at + * a given physical address and set of CPU flags is not necessarily + * valid for another: + * the two clusters may have different views of physical memory, or + * may have different CPU features (eg FPU present or absent). + */ + cflags = cpu->cluster_index << CF_CLUSTER_SHIFT; + cflags |= parallel ? CF_PARALLEL : 0; cflags |= icount_enabled() ? CF_USE_ICOUNT : 0; cpu->tcg_cflags = cflags; diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 2417597236..d427db0bc7 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -272,6 +272,8 @@ struct qemu_work_item; * to a cluster this will be UNASSIGNED_CLUSTER_INDEX; otherwise it will * be the same as the cluster-id property of the CPU object's TYPE_CPU_CLUSTER * QOM parent. + * Under TCG this value is propagated to @tcg_cflags. + * See TranslationBlock::TCG CF_CLUSTER_MASK. * @tcg_cflags: Pre-computed cflags for this cpu. * @nr_cores: Number of cores within this CPU package. * @nr_threads: Number of threads within this CPU. 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Iglesias" , Paolo Bonzini , Marcel Apfelbaum , Robert Hoo , Yanan Wang , qemu-arm@nongnu.org, Peter Maydell , =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= , Palmer Dabbelt , Like Xu , Alistair Francis , Zhao Liu , Eduardo Habkost Subject: [PATCH 2/5] hw/cpu/cluster: Only add CPU objects to CPU cluster Date: Thu, 16 Feb 2023 15:23:35 +0100 Message-Id: <20230216142338.82982-3-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230216142338.82982-1-philmd@linaro.org> References: <20230216142338.82982-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Do not recursively add CPU and all their children objects. Simply iterate on the cluster direct children, which must be of TYPE_CPU. Otherwise raise an error. Signed-off-by: Philippe Mathieu-Daudé --- hw/cpu/cluster.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/hw/cpu/cluster.c b/hw/cpu/cluster.c index bf3e27e945..b0cdf7d931 100644 --- a/hw/cpu/cluster.c +++ b/hw/cpu/cluster.c @@ -39,12 +39,19 @@ typedef struct CallbackData { static bool add_cpu_to_cluster(Object *obj, void *opaque, Error **errp) { CallbackData *cbdata = opaque; - CPUState *cpu = (CPUState *)object_dynamic_cast(obj, TYPE_CPU); + CPUState *cpu; - if (cpu) { - cpu->cluster_index = cbdata->cluster->cluster_id; - cbdata->cpu_count++; + cpu = (CPUState *)object_dynamic_cast(obj, TYPE_CPU); + if (!cpu) { + error_setg(errp, "cluster %s can only accept CPU types (got %s)", + object_get_canonical_path(OBJECT(cbdata->cluster)), + object_get_typename(obj)); + return false; } + + cpu->cluster_index = cbdata->cluster->cluster_id; + cbdata->cpu_count++; + return true; } @@ -63,8 +70,9 @@ static void cpu_cluster_realize(DeviceState *dev, Error **errp) return; } - object_child_foreach_recursive(cluster_obj, add_cpu_to_cluster, - &cbdata, NULL); + if (!object_child_foreach(cluster_obj, add_cpu_to_cluster, &cbdata, errp)) { + return; + } /* * A cluster with no CPUs is a bug in the board/SoC code that created it; From patchwork Thu Feb 16 14:23:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 654038 Delivered-To: patch@linaro.org Received: by 2002:adf:f90f:0:0:0:0:0 with SMTP id b15csp381603wrr; Thu, 16 Feb 2023 06:25:49 -0800 (PST) X-Google-Smtp-Source: AK7set/iCPikbf4HIqcvpFLkwZyaBB88+p3anPlTACTnNyj2owvvPTfyoTTB0fnBPXxVJ61s9l8e X-Received: by 2002:ac8:7f4d:0:b0:3ba:18e2:7de8 with SMTP id g13-20020ac87f4d000000b003ba18e27de8mr10174555qtk.38.1676557549063; Thu, 16 Feb 2023 06:25:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676557549; cv=none; d=google.com; s=arc-20160816; b=Qrn/Toyb+a6r29u41Ge81owFO5Vt97JlpAE0XnC2GC/T5J/7pyk/ZgIjth1Vn7zptz 2HgcteTObItZatUcjw25GGAseNJqHu7guFqcD9/65Zhc/BDs1w229ZF+tRCa/3hqdQcM hrSpam/yUQmiQ+8ZLaQk295b96eoN4o4EUQGdtNYZY9P269n5V4Rz8X8paAAoKcnTWDD HJqxt72zwKhGauIiHGvKHg5y31mF1CAuuQPn5KUMMA3PfZ0q2VX5YjaNntjH207TKWDV iWE8rsR2zCR+z9ZjpyN1taKSxKiSmYID+WLrOFEcIu3Q6qoAsPUr6G8iofr/3a5ErpQ2 4p2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=TZ4uzPiIvaikQ5NFFcOsPUHe0pcwccK15cuAkxemPTA=; b=d5bC/i6rY/1hytt/QR5Vpcn8X/SDRXz/ipdYqQnHU7lhNAukt71Acn/IdY1ZsF7zE4 qbTLrYDR8YQb3F3i1d3WneXcvMpypPV94Woj3h7u9Fq5is/1vw2zqotazF6iuMfUUAi7 nW0ACpHV/DIaJG4NE33jUPxDlKbYYMfsylX93p2zCN6MbdH00HCb1wc4o/y79rKrtATt eSi1SMLtvQO+RuNxiTDmN9a/fARUDJOzCvBXFbNFZSkWmmNVJS8F9PfW5W7AYh1qQkbM B6BJqY9ODnWUGrHML8TpjUBMmgjebPopZxFR6QYlQmyxk8MycvD21onXzMfF7v5M/ArX ioxA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JArp8dD4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , Paolo Bonzini , Marcel Apfelbaum , Robert Hoo , Yanan Wang , qemu-arm@nongnu.org, Peter Maydell , =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= , Palmer Dabbelt , Like Xu , Alistair Francis , Zhao Liu , Eduardo Habkost Subject: [PATCH 3/5] hw/cpu/cluster: Restrict CPU cluster to a particular CPU type Date: Thu, 16 Feb 2023 15:23:36 +0100 Message-Id: <20230216142338.82982-4-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230216142338.82982-1-philmd@linaro.org> References: <20230216142338.82982-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org CPU cluster id is used by TCG accelerator to "group" CPUs sharing the same ISA features, so TranslationBlock can be shared between the cluster (see commit f7b78602fd "accel/tcg: Add cluster number to TCG TB hash"). This mean we shouldn't mix different kind of CPUs into the same cluster. Enforce that by adding a 'cpu-type' property. The cluster's realize() method will check all children are of that 'cpu-type' class. If the property is not set, the first CPU added to a cluster sets its CPU type, and only that type fo CPU can be added. Example of error: qemu-system-aarch64: cluster /machine/soc/rpu-cluster can only accept cortex-r5f-arm-cpu CPUs (got cortex-a9-arm-cpu) Signed-off-by: Philippe Mathieu-Daudé --- hw/cpu/cluster.c | 19 ++++++++++++++++--- include/hw/cpu/cluster.h | 1 + 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/hw/cpu/cluster.c b/hw/cpu/cluster.c index b0cdf7d931..0d06944824 100644 --- a/hw/cpu/cluster.c +++ b/hw/cpu/cluster.c @@ -28,6 +28,7 @@ static Property cpu_cluster_properties[] = { DEFINE_PROP_UINT32("cluster-id", CPUClusterState, cluster_id, 0), + DEFINE_PROP_STRING("cpu-type", CPUClusterState, cpu_type), DEFINE_PROP_END_OF_LIST() }; @@ -41,11 +42,17 @@ static bool add_cpu_to_cluster(Object *obj, void *opaque, Error **errp) CallbackData *cbdata = opaque; CPUState *cpu; - cpu = (CPUState *)object_dynamic_cast(obj, TYPE_CPU); + if (cbdata->cluster->cpu_type == NULL) { + /* If no 'cpu-type' property set, enforce it with the first CPU added */ + assert(object_dynamic_cast(obj, TYPE_CPU) != NULL); + cbdata->cluster->cpu_type = g_strdup(object_get_typename(obj)); + } + + cpu = (CPUState *)object_dynamic_cast(obj, cbdata->cluster->cpu_type); if (!cpu) { - error_setg(errp, "cluster %s can only accept CPU types (got %s)", + error_setg(errp, "cluster %s can only accept %s CPUs (got %s)", object_get_canonical_path(OBJECT(cbdata->cluster)), - object_get_typename(obj)); + cbdata->cluster->cpu_type, object_get_typename(obj)); return false; } @@ -69,6 +76,12 @@ static void cpu_cluster_realize(DeviceState *dev, Error **errp) error_setg(errp, "cluster-id must be less than %d", MAX_CLUSTERS); return; } + if (cluster->cpu_type) { + if (object_class_is_abstract(object_class_by_name(cluster->cpu_type))) { + error_setg(errp, "cpu-type must be a concrete class"); + return; + } + } if (!object_child_foreach(cluster_obj, add_cpu_to_cluster, &cbdata, errp)) { return; diff --git a/include/hw/cpu/cluster.h b/include/hw/cpu/cluster.h index 53fbf36af5..c9792d6f05 100644 --- a/include/hw/cpu/cluster.h +++ b/include/hw/cpu/cluster.h @@ -76,6 +76,7 @@ struct CPUClusterState { /*< public >*/ uint32_t cluster_id; + char *cpu_type; }; #endif From patchwork Thu Feb 16 14:23:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 654039 Delivered-To: patch@linaro.org Received: by 2002:adf:f90f:0:0:0:0:0 with SMTP id b15csp381646wrr; Thu, 16 Feb 2023 06:25:52 -0800 (PST) X-Google-Smtp-Source: AK7set+zljSw0iBtQ7eD+0MeNQALTI+kmSBUXC7XsohVu8xM1i4OKs1VzBCxp45cZzhUHCiTLs3p X-Received: by 2002:ac8:5c54:0:b0:3bb:8dfd:c867 with SMTP id j20-20020ac85c54000000b003bb8dfdc867mr10232193qtj.24.1676557552297; Thu, 16 Feb 2023 06:25:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676557552; cv=none; d=google.com; s=arc-20160816; b=kT2GFpNYaixeCiZb+BYFYMoQKQef8r8SFZoYZn0PjUXEwqLokiiPTdGKMaJnfS2dtp SfqVR/nJdTpNOBkYDdU8BERq1s71KBvsD8A0nVrdnnT2zadjsga4Pz6PcwbTC3Kpa3Lw ktjch75vBkd4kEDPv7gqxYsInsbl9Tp0bFx6icX+vuAAQmTOIiBkRhzZCGqg7Tmt7SZy 12/hLd366dLG9Udfuq/9cW7KU07jSsTuE72dbMURfea5P9Ct2VPN1thToGZOsE1E/zKo +FuTKielfxHx3hwscDrxbkdPICkaJdL5n6XVP/I/E3DhAysonVrnN+cv0trgRSxr6GYK Woew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=pkUuoVsPO7rj7crjxhqsXkiJdIbOheCDQODQm6zJmAM=; b=W5rhaT+ui44PqAtz9HHPljqPino0wFow68GkD6ztc5a9AaYVOCNVrKHYeTvl2CWJSo t7CDIa5vF/QMy/sgMbnHQCmuxdJJd7nfnG2acU8scg2sjqz6Yy+OCNr0wlEY6A6gORVg uSmm1crIoj2nCu+xtolKZDnruPk+/6FCUP+db38Z7diuV7sBSerlBb/saVeZkqvdWYf5 WbE2VjGeQDTI64ldvr8TJ43mEIL7/RMCPMYBzJpsVro3uuVJqv353pW79b9CEXfTq2Bu noGiX2MZ+eCspZ+i+gbM6aR8m/o+eYd32LAvha2KYHMboKdmE6CCXUg7Iwd/JYTb+mLR XGqQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZqFCD2Vt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , Paolo Bonzini , Marcel Apfelbaum , Robert Hoo , Yanan Wang , qemu-arm@nongnu.org, Peter Maydell , =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= , Palmer Dabbelt , Like Xu , Alistair Francis , Zhao Liu , Eduardo Habkost Subject: [PATCH 4/5] hw/arm: Restrict CPU clusters to the expected type Date: Thu, 16 Feb 2023 15:23:37 +0100 Message-Id: <20230216142338.82982-5-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230216142338.82982-1-philmd@linaro.org> References: <20230216142338.82982-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org ARM SSE expects v7-M cores; the ZynqMP SoC expects Cortex-A53/R5F. Do not allow any other CPU type by setting the cluster 'cpu-type' property. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/armsse.c | 1 + hw/arm/xlnx-zynqmp.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 0202bad787..1132fdcbe2 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -715,6 +715,7 @@ static void armsse_init(Object *obj) name = g_strdup_printf("cluster%d", i); object_initialize_child(obj, name, &s->cluster[i], TYPE_CPU_CLUSTER); qdev_prop_set_uint32(DEVICE(&s->cluster[i]), "cluster-id", i); + qdev_prop_set_string(DEVICE(&s->cluster[i]), "cpu-type", TYPE_ARMV7M); g_free(name); name = g_strdup_printf("armv7m%d", i); diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 335cfc417d..e45cf88625 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -224,6 +224,8 @@ static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s, object_initialize_child(OBJECT(s), "rpu-cluster", &s->rpu_cluster, TYPE_CPU_CLUSTER); qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1); + qdev_prop_set_string(DEVICE(&s->rpu_cluster), "cpu-type", + ARM_CPU_TYPE_NAME("cortex-r5f")); for (i = 0; i < num_rpus; i++) { const char *name; @@ -381,6 +383,8 @@ static void xlnx_zynqmp_init(Object *obj) object_initialize_child(obj, "apu-cluster", &s->apu_cluster, TYPE_CPU_CLUSTER); qdev_prop_set_uint32(DEVICE(&s->apu_cluster), "cluster-id", 0); + qdev_prop_set_string(DEVICE(&s->apu_cluster), "cpu-type", + ARM_CPU_TYPE_NAME("cortex-a53")); for (i = 0; i < num_apus; i++) { object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]", From patchwork Thu Feb 16 14:23:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 654040 Delivered-To: patch@linaro.org Received: by 2002:adf:f90f:0:0:0:0:0 with SMTP id b15csp381711wrr; Thu, 16 Feb 2023 06:25:59 -0800 (PST) X-Google-Smtp-Source: AK7set+W5jpFHbtqdI44OQ84oa1R0ZJWhhtUoyyDuHmCCUCvIBbCh8u1k3Lez2wIfjZw9zFMIRGh X-Received: by 2002:a05:6214:c8b:b0:56e:a07b:f4db with SMTP id r11-20020a0562140c8b00b0056ea07bf4dbmr11044904qvr.24.1676557558870; Thu, 16 Feb 2023 06:25:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676557558; cv=none; d=google.com; s=arc-20160816; b=XzWG9BlpGFvJvPZODmNn4kETKSTMMXqZQl0/1nlf4wGNwScLmakQRoWNBv3lbwOyUA BYVB5DUye4UR/Ad+Q5Xk0/LqHzPDCHsPhizzBfoPRwZhMU52NaqzAw1OjBR7TUKNpha0 XOECJ9DdwOjbn816nJheFzJDp7+TXA8fxmnDEtmjoYqhJdeBPWwMt7IWQkamQ/AttTpw Vi9UoYcqVpxlOrTMGNIR+jB8moG8dRnDEXXh8weF1xHCbUFRl5QY/k/mHRJgXK6Qjwwh p48DZavd/WuJiSiW3UGE5v2kKTtc1Uux735JF54WrJKf4MRlKoi1gQqf/tZbkEtMSroH 8ucA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=AgNv7jvYIv3Rzz9yuX+hevsRvmOvV3oj8SZGxY0IVW0=; b=nB0B6KYwQwCa2ubb53Ty/1zMqVS2MeXzjD1LRL9lDfmO8pCVc8f8fi1xqz2E3ep2HP fyldMvTjFnvhpLYEwcZd6fBkZUCKxo24eOkPgyYG7Lkuh9UA6FgjxykmEuZWa3++PmtW 0Nb6WXW06co0dyIixG5dFLwsKmRHOHYEO/++FcVc99bIutc+iqWARusV7WNTn/VE5d9u lZulwVpAgOzqrzywWldRKU6TtZJBoHdc/txb3fSqdpFIEgIziXhUnrvaUedmwiLmVma2 dcnW0CL/zKsWz0WDYt39KPhorSIacSvDm8FYADYeIs3pUxRt1hNR1SyKNoJY5hffdMlZ 35hA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=l+8FD4H3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , Paolo Bonzini , Marcel Apfelbaum , Robert Hoo , Yanan Wang , qemu-arm@nongnu.org, Peter Maydell , =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= , Palmer Dabbelt , Like Xu , Alistair Francis , Zhao Liu , Eduardo Habkost Subject: [PATCH 5/5] hw/riscv: Restrict CPU clusters to the expected type Date: Thu, 16 Feb 2023 15:23:38 +0100 Message-Id: <20230216142338.82982-6-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230216142338.82982-1-philmd@linaro.org> References: <20230216142338.82982-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Microchip PolarFire SoC expects U51/U54 cores, the SiFive Freedom board: the E31/E51 and U34/U54. Do not allow any other CPU type by setting the cluster 'cpu-type' property. Signed-off-by: Philippe Mathieu-Daudé --- hw/riscv/microchip_pfsoc.c | 4 ++++ hw/riscv/sifive_u.c | 2 ++ 2 files changed, 6 insertions(+) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 2b91e49561..658307fdfb 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -150,6 +150,8 @@ static void microchip_pfsoc_soc_instance_init(Object *obj) object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER); qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); + qdev_prop_set_string(DEVICE(&s->e_cluster), "cpu-type", + TYPE_RISCV_CPU_SIFIVE_E51); object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, TYPE_RISCV_HART_ARRAY); @@ -161,6 +163,8 @@ static void microchip_pfsoc_soc_instance_init(Object *obj) object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER); qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); + qdev_prop_set_string(DEVICE(&s->e_cluster), "cpu-type", + TYPE_RISCV_CPU_SIFIVE_U54); object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, TYPE_RISCV_HART_ARRAY); diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index d3ab7a9cda..d0535746ca 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -763,6 +763,7 @@ static void sifive_u_soc_instance_init(Object *obj) object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER); qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); + qdev_prop_set_string(DEVICE(&s->e_cluster), "cpu-type", SIFIVE_E_CPU); object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, TYPE_RISCV_HART_ARRAY); @@ -813,6 +814,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp) * CPU must exist and have been parented into the cluster before the * cluster is realized. */ + qdev_prop_set_string(DEVICE(&s->u_cluster), "cpu-type", s->cpu_type); qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort);