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[5.69.146.176]) by smtp.gmail.com with ESMTPSA id p24-20020a05600c1d9800b003dd1bd0b915sm20636570wms.22.2023.02.14.09.21.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 09:21:06 -0800 (PST) From: Jean-Philippe Brucker To: eric.auger@redhat.com Cc: peter.maydell@linaro.org, richard.henderson@linaro.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org, ola.hugosson@arm.com, Jean-Philippe Brucker Subject: [PATCH v2 1/2] hw/arm/smmu-common: Support 64-bit addresses Date: Tue, 14 Feb 2023 17:19:21 +0000 Message-Id: <20230214171921.1917916-2-jean-philippe@linaro.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230214171921.1917916-1-jean-philippe@linaro.org> References: <20230214171921.1917916-1-jean-philippe@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=jean-philippe@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Addresses targeting the second translation table (TTB1) in the SMMU have all upper bits set. Ensure the IOMMU region covers all 64 bits. Reviewed-by: Richard Henderson Signed-off-by: Jean-Philippe Brucker Reviewed-by: Eric Auger --- include/hw/arm/smmu-common.h | 2 -- hw/arm/smmu-common.c | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index c5683af07d..9fcff26357 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -27,8 +27,6 @@ #define SMMU_PCI_DEVFN_MAX 256 #define SMMU_PCI_DEVFN(sid) (sid & 0xFF) -#define SMMU_MAX_VA_BITS 48 - /* * Page table walk error types */ diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 733c964778..2b8c67b9a1 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -439,7 +439,7 @@ static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn) memory_region_init_iommu(&sdev->iommu, sizeof(sdev->iommu), s->mrtypename, - OBJECT(s), name, 1ULL << SMMU_MAX_VA_BITS); + OBJECT(s), name, UINT64_MAX); address_space_init(&sdev->as, MEMORY_REGION(&sdev->iommu), name); trace_smmu_add_mr(name); From patchwork Tue Feb 14 17:19:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Philippe Brucker X-Patchwork-Id: 653482 Delivered-To: patch@linaro.org Received: by 2002:adf:f90f:0:0:0:0:0 with SMTP id b15csp3178891wrr; Tue, 14 Feb 2023 09:21:49 -0800 (PST) X-Google-Smtp-Source: AK7set94qbbqesPJDYCSfRjWjwdbdHarO/Ril2t0H3mAfGKUTYnXxnf+7bdUse18amNE2qacoICc X-Received: by 2002:ac8:5895:0:b0:3b5:87db:f99e with SMTP id t21-20020ac85895000000b003b587dbf99emr4465385qta.39.1676395308831; Tue, 14 Feb 2023 09:21:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676395308; cv=none; d=google.com; s=arc-20160816; b=IRTHRRPzYFwutAhXkz41VD4ef4KpFM7lAOnOPI5tFYUaVwkr76oAmcitObGNqie9I8 RkpXksdRxfuVwzhwQXM80IAoiU4ozWt54pn7RoU1WdkbsmNJav+A3f5RsibSET3lwK9t UojyohXsq07JwLbp1lb5yNx/+1bqO4YqkPMLzfe2M7TtsqmD6+/HdWPdIn8+BU8qskgi Jh6INrDiiKakccfycG/cXAu8L22ndrATeheBYd++ofD3f3aZ+0VV4cW94MIAkdpToj9W 0kPSfFJglPkUHN7Nm+xvkGIcHWZXNPCNra6sWF3U3Rd7hwKDSWGfoBacG3nBhIn0Bcvl +z+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=R1o7dkQJ+2Jq4AnP/hQ+CdLt1UTgBQpw0WHFXcyfQhY=; b=afzk16uUm0vxiCNs0hcB+THFnVFw6gw56B4Bds3+1i8h/cPvx/mGbZgJBZ2v5JwH4y isK4rkvx8+dS5g4TED+b8QvFBKRYb25zCOPVByHV0W4v+ehf/4raSQND6dD6MjBhtJP6 CjodZ2tdkV6JajFZ4UcnLhfAS1rFzLzsaRQtawb2TT0p8dCNJWc3lVjmKp71hzhTm9yg xITpmsiYs8kgsrUcUvea/lP28eZrfVTWK1Wl9140CI6YRscFbC3oehyxB3og3uHYgqNA 0ETF0KzSwIZ8+1RuWwKSqi+7ivXwRLIDf+V4Gr18RTolSf1jFfdcaiPjODqchN6rnQJf bfdw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nSgUDlDR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[5.69.146.176]) by smtp.gmail.com with ESMTPSA id p24-20020a05600c1d9800b003dd1bd0b915sm20636570wms.22.2023.02.14.09.21.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 09:21:07 -0800 (PST) From: Jean-Philippe Brucker To: eric.auger@redhat.com Cc: peter.maydell@linaro.org, richard.henderson@linaro.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org, ola.hugosson@arm.com, Jean-Philippe Brucker Subject: [PATCH v2 2/2] hw/arm/smmu-common: Fix TTB1 handling Date: Tue, 14 Feb 2023 17:19:22 +0000 Message-Id: <20230214171921.1917916-3-jean-philippe@linaro.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230214171921.1917916-1-jean-philippe@linaro.org> References: <20230214171921.1917916-1-jean-philippe@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=jean-philippe@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Addresses targeting the second translation table (TTB1) in the SMMU have all upper bits set (except for the top byte when TBI is enabled). Fix the TTB1 check. Reported-by: Ola Hugosson Reviewed-by: Eric Auger Reviewed-by: Richard Henderson Signed-off-by: Jean-Philippe Brucker --- hw/arm/smmu-common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 2b8c67b9a1..0a5a60ca1e 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -249,7 +249,7 @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova) /* there is a ttbr0 region and we are in it (high bits all zero) */ return &cfg->tt[0]; } else if (cfg->tt[1].tsz && - !extract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte)) { + sextract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte) == -1) { /* there is a ttbr1 region and we are in it (high bits all one) */ return &cfg->tt[1]; } else if (!cfg->tt[0].tsz) {