From patchwork Wed May 1 04:37:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 163173 Delivered-To: patch@linaro.org Received: by 2002:a92:7e86:0:0:0:0:0 with SMTP id q6csp4099978ill; Tue, 30 Apr 2019 21:37:46 -0700 (PDT) X-Google-Smtp-Source: APXvYqxYFj6Xax7F1LhcF9wFlieFymeFF8Ny+b2gBlFBFJmHwQjEGXdp3eOq7MjhmpW1JofBXW0P X-Received: by 2002:a63:1055:: with SMTP id 21mr52482356pgq.200.1556685466145; Tue, 30 Apr 2019 21:37:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556685466; cv=none; d=google.com; s=arc-20160816; b=NBuk2/+tkFKLU7Se6ZSgRkYDrwCQRzjMIfwEXlZqQ+vi7sYLPxf+WYNh1/hbm88GhH ZgeaVtJ92nJ7vepjmCgOZ5RoLg2t9DvWCfp5cxQy3V/tiWHmNvqupy50yg8HBqGJuoz/ aLl9TsYrF3nFCbBoeO8Ghx5zSst2QC7kHEzEvu9XuIMPscjIM0N2cXOzxBtnTl13iFXX VBs5Ye7uXe8wTP7h6PnVmlsuE2Q28TMKYHKVgRPXOXgzESz+r9UDj4yP2WRCu73J38dg 79+4GsITr8gUEmU7NtivWHwrNcSNjR6uoDl7kwOHH+kFrvauLyFLoAntqxMa2H2B84nP eQ0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=CtH/Vn4WPiwe6wcK50aezzc3xrR7S8mKnOtvGN8/o3U=; b=jUXIofvyBmcbjNlsEL8x7Ysjo1sfOfTd2URAtzWaWxgP+2LoopJ5OPfQghCeGlUgZK XBzJBg+9yEXHhPClKYh3SBhxjRzpxefte6DKOj/0KzxPHsD8ShtVVYUrXIwNEZCCZYEN /VqGMqDF+tFdIb8wnJd7zGii0VOIK+KD8D4bHqwWa0/c6lnTb+xzwrh2BpsTruxp/gt/ vShpQaN3i/wOHRlH6XEJsMrSCqdjOpWGgR81iWwgdnRzJ/aEAvIDEerZEYJiy8WNNbIA FKSGPATmGAXoLeMp6H4PTU5dME1VU4bGLCUZq/tQQ8MQYHcA9G037jTWWrsB2pQybPVR Ky3w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=y713F90O; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id q128sm55912865pga.60.2019.04.30.21.37.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 30 Apr 2019 21:37:38 -0700 (PDT) From: Bjorn Andersson To: Andy Gross , David Brown , Rob Herring , Mark Rutland Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 1/4] dt-bindings: soc: qcom: Add AOSS QMP binding Date: Tue, 30 Apr 2019 21:37:31 -0700 Message-Id: <20190501043734.26706-2-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190501043734.26706-1-bjorn.andersson@linaro.org> References: <20190501043734.26706-1-bjorn.andersson@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add binding for the QMP based side-channel communication mechanism to the AOSS, which is used to control resources not exposed through the RPMh interface. Signed-off-by: Bjorn Andersson --- Changes since v6: - Added #clock-cells .../bindings/soc/qcom/qcom,aoss-qmp.txt | 81 +++++++++++++++++++ include/dt-bindings/power/qcom-aoss-qmp.h | 14 ++++ 2 files changed, 95 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt create mode 100644 include/dt-bindings/power/qcom-aoss-qmp.h -- 2.18.0 Reviewed-by: Vinod Koul diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt new file mode 100644 index 000000000000..14a45b3dc059 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt @@ -0,0 +1,81 @@ +Qualcomm Always-On Subsystem side channel binding + +This binding describes the hardware component responsible for side channel +requests to the always-on subsystem (AOSS), used for certain power management +requests that is not handled by the standard RPMh interface. Each client in the +SoC has it's own block of message RAM and IRQ for communication with the AOSS. +The protocol used to communicate in the message RAM is known as Qualcomm +Messagin Protocol (QMP) + +The AOSS side channel exposes control over a set of resources, used to control +a set of debug related clocks and to affect the low power state of resources +related to the secondary subsystems. These resources are exposed as a set of +power-domains. + +- compatible: + Usage: required + Value type: + Definition: must be "qcom,sdm845-aoss-qmp" + +- reg: + Usage: required + Value type: + Definition: the base address and size of the message RAM for this + client's communication with the AOSS + +- interrupts: + Usage: required + Value type: + Definition: should specify the AOSS message IRQ for this client + +- mboxes: + Usage: required + Value type: + Definition: reference to the mailbox representing the outgoing doorbell + in APCS for this client, as described in mailbox/mailbox.txt + +- #clock-cells: + Usage: optional + Value type: + Definition: must be 0 + The single clock represents the QDSS clock. + +- #power-domain-cells: + Usage: optional + Value type: + Definition: must be 1 + The provided power-domains are: + CDSP state (0), LPASS state (1), modem state (2), SLPI + state (3), SPSS state (4) and Venus state (5). + += SUBNODES +The AOSS side channel also provides the controls for three cooling devices, +these are expressed as subnodes of the QMP node. The name of the node is used +to identify the resource and must therefor be "cx", "mx" or "ebi". + +- #cooling-cells: + Usage: optional + Value type: + Definition: must be 2 + += EXAMPLE + +The following example represents the AOSS side-channel message RAM and the +mechanism exposing the power-domains, as found in SDM845. + + aoss_qmp: qmp@c300000 { + compatible = "qcom,sdm845-aoss-qmp"; + reg = <0x0c300000 0x100000>; + interrupts = ; + mboxes = <&apss_shared 0>; + + #power-domain-cells = <1>; + + cx_cdev: cx { + #cooling-cells = <2>; + }; + + mx_cdev: mx { + #cooling-cells = <2>; + }; + }; diff --git a/include/dt-bindings/power/qcom-aoss-qmp.h b/include/dt-bindings/power/qcom-aoss-qmp.h new file mode 100644 index 000000000000..ec336d31dee4 --- /dev/null +++ b/include/dt-bindings/power/qcom-aoss-qmp.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018, Linaro Ltd. */ + +#ifndef __DT_BINDINGS_POWER_QCOM_AOSS_QMP_H +#define __DT_BINDINGS_POWER_QCOM_AOSS_QMP_H + +#define AOSS_QMP_LS_CDSP 0 +#define AOSS_QMP_LS_LPASS 1 +#define AOSS_QMP_LS_MODEM 2 +#define AOSS_QMP_LS_SLPI 3 +#define AOSS_QMP_LS_SPSS 4 +#define AOSS_QMP_LS_VENUS 5 + +#endif From patchwork Wed May 1 04:37:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 163176 Delivered-To: patch@linaro.org Received: by 2002:a92:7e86:0:0:0:0:0 with SMTP id q6csp4100026ill; Tue, 30 Apr 2019 21:37:52 -0700 (PDT) X-Google-Smtp-Source: APXvYqyFCgxLCjRx3y8214eH9z77sQOpQgwvvIzh94A+SLXUs3xj8Lt7cOxk7Al8FoDW2v9x3LIb X-Received: by 2002:a17:902:f24:: with SMTP id 33mr67910524ply.44.1556685472319; Tue, 30 Apr 2019 21:37:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556685472; cv=none; d=google.com; s=arc-20160816; b=gZkyruS3JOR/lpBfHC5E/gYWdbgEoJTWTEObqlWu0waHYRiYV2/82RsX4dEsNZe5/s px9kNo56WMoypAeCxWf5IPyAXOs6pW5df6TzqPEmmT9s2obmUs/4zbBJO9q9bOT5uY2e tArMyRVOohcnrmCjSA/Tn8kxxCVth6Y7+mAoB5PEb3Mx1YS13tBnueGZ7S2BLt+oF8cH mcZlTlM2hgGooEMPyCZ5k5gcH1KGjQPAH1qVhOf7urKSC5Q7mMbeCcWKjSQLxLAhwlGl THkkgmd6uxOdPQ4fBAvhMnth1BQJD/S8QEqAe8GdSCgMmnKR7e7awtcutoO+RQWVqw/q I/wg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=a10hGuK3vdCOEjNUJMZxmg7vPboJuN/bkuHq4KflRrI=; b=V69ccalJrzUGEvzwZgxE/T1CzpIflm/rSfDH4gR7XIS2uJ8cY9nk8hv9wt2zbzsAYT CylriT+5baTVuwL//bpYNH2vuuGVi3dY+Wp9DkGTyj3uMm8y+YUiGbl97YdZ9plcexmQ M5MiYvucGeuSI/5MiZOXnsGUboM+HVhhpdvJllhESyPO7w8kSfTzFK03lPRWTwVO3D3t 5QyDgZ2YV3xW9QAlccIPew7aHH8TMQvbrkIO+bLqFaC5n/Boo4qPMoqUpD7J7aNjo58m is8mBtv6V+UqjasUP9IS1og9+kdkStNahDhMv6gi18IWEEzbjpE1bYguUlMWRVlNU5Fi yZ1Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pDVa8e7j; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id q128sm55912865pga.60.2019.04.30.21.37.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 30 Apr 2019 21:37:43 -0700 (PDT) From: Bjorn Andersson To: Andy Gross , David Brown Cc: Rob Herring , Mark Rutland , Stephen Boyd , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 4/4] arm64: dts: qcom: sdm845: Add Q6V5 MSS node Date: Tue, 30 Apr 2019 21:37:34 -0700 Message-Id: <20190501043734.26706-5-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190501043734.26706-1-bjorn.andersson@linaro.org> References: <20190501043734.26706-1-bjorn.andersson@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Sibi Sankar This patch adds Q6V5 MSS remoteproc node for SDM845 SoCs. Reviewed-by: Douglas Anderson Signed-off-by: Sibi Sankar Signed-off-by: Bjorn Andersson --- Changes since v6: - None arch/arm64/boot/dts/qcom/sdm845.dtsi | 58 ++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) -- 2.18.0 diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 666bc88d3e81..2f3ab6acda3d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1672,6 +1672,64 @@ }; }; + mss_pil: remoteproc@4080000 { + compatible = "qcom,sdm845-mss-pil"; + reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; + reg-names = "qdsp6", "rmb"; + + interrupts-extended = + <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack", + "shutdown-ack"; + + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, + <&gcc GCC_BOOT_ROM_AHB_CLK>, + <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, + <&gcc GCC_MSS_SNOC_AXI_CLK>, + <&gcc GCC_MSS_MFAB_AXIS_CLK>, + <&gcc GCC_PRNG_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "bus", "mem", "gpll0_mss", + "snoc_axi", "mnoc_axi", "prng", "xo"; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + resets = <&aoss_reset AOSS_CC_MSS_RESTART>, + <&pdc_reset PDC_MODEM_SYNC_RESET>; + reset-names = "mss_restart", "pdc_reset"; + + qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; + + power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>, + <&rpmhpd SDM845_CX>, + <&rpmhpd SDM845_MX>, + <&rpmhpd SDM845_MSS>; + power-domain-names = "load_state", "cx", "mx", "mss"; + + mba { + memory-region = <&mba_region>; + }; + + mpss { + memory-region = <&mpss_region>; + }; + + glink-edge { + interrupts = ; + label = "modem"; + qcom,remote-pid = <1>; + mboxes = <&apss_shared 12>; + }; + }; + gpucc: clock-controller@5090000 { compatible = "qcom,sdm845-gpucc"; reg = <0 0x05090000 0 0x9000>;