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(localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 8C6CE1FF8C; Tue, 30 Apr 2019 17:52:34 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Tue, 30 Apr 2019 17:52:20 +0100 Message-Id: <20190430165234.32272-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190430165234.32272-1-alex.bennee@linaro.org> References: <20190430165234.32272-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH v5 01/15] tests/tcg/multiarch: add support for multiarch system tests X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, mark.cave-ayland@ilande.co.uk, cota@braap.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We can certainly support some common tests for system emulation that make use of our minimal defined boot.S support. It will still be up to individual architectures to ensure they build so we provide a MULTIARCH_TESTS variable that they can tack onto TESTS themselves. Signed-off-by: Alex Bennée --- tests/tcg/Makefile | 1 + tests/tcg/multiarch/system/Makefile.softmmu-target | 14 ++++++++++++++ 2 files changed, 15 insertions(+) create mode 100644 tests/tcg/multiarch/system/Makefile.softmmu-target -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/tests/tcg/Makefile b/tests/tcg/Makefile index 1cdd628e96..6fa63cc8d5 100644 --- a/tests/tcg/Makefile +++ b/tests/tcg/Makefile @@ -96,6 +96,7 @@ else # build options for bare programs are usually pretty different. They # are expected to provide their own build recipes. -include $(SRC_PATH)/tests/tcg/minilib/Makefile.target +-include $(SRC_PATH)/tests/tcg/multiarch/system/Makefile.softmmu-target -include $(SRC_PATH)/tests/tcg/$(TARGET_BASE_ARCH)/Makefile.softmmu-target ifneq ($(TARGET_BASE_ARCH),$(TARGET_NAME)) -include $(SRC_PATH)/tests/tcg/$(TARGET_NAME)/Makefile.softmmu-target diff --git a/tests/tcg/multiarch/system/Makefile.softmmu-target b/tests/tcg/multiarch/system/Makefile.softmmu-target new file mode 100644 index 0000000000..db4bbeda44 --- /dev/null +++ b/tests/tcg/multiarch/system/Makefile.softmmu-target @@ -0,0 +1,14 @@ +# -*- Mode: makefile -*- +# +# Multiarch system tests +# +# We just collect the tests together here and rely on the actual guest +# architecture to add to the test dependancies and deal with the +# complications of building. +# + +MULTIARCH_SYSTEM_SRC=$(SRC_PATH)/tests/tcg/multiarch/system +VPATH+=$(MULTIARCH_SYSTEM_SRC) + +MULTIARCH_TEST_SRCS=$(wildcard $(MULTIARCH_SYSTEM_SRC)/*.c) +MULTIARCH_TESTS = $(patsubst $(MULTIARCH_SYSTEM_SRC)/%.c, %, $(MULTIARCH_TEST_SRCS)) From patchwork Tue Apr 30 16:52:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 163149 Delivered-To: patch@linaro.org Received: by 2002:a92:7e86:0:0:0:0:0 with SMTP id q6csp3497008ill; Tue, 30 Apr 2019 10:13:33 -0700 (PDT) X-Google-Smtp-Source: APXvYqz6+1RA7d9HBCOnmsRFBIrVINyrzxxl0Qx++oPh383rpXaswBA/9JpyBRTsg4A7yb7BR4B7 X-Received: by 2002:adf:c6c3:: with SMTP id c3mr3936467wrh.267.1556644413757; Tue, 30 Apr 2019 10:13:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556644413; cv=none; d=google.com; s=arc-20160816; b=JLLlKSnYuk3tMutllmQnCPDEDoM/b8rkZ9gjNSxkTQ2BycnEmAJXGARV24b+D89LT0 BVNSbHOpVl/z3hAIPAGCDc+RXkzUS78BBvPga7+SxGaOMhDHma07p19STusbYlNDlzv3 zEv0FS+bPJAhOLUGfvREEoaxLMCTFWO/oKM5dwRO154kVcUTQFeKtvADMPcGG4WygGFF s48nZoCxulVCAQH4J9qnf1Ysw7j3kmX/DDkLeEaDc6LlEyiLp/2fMXFHTRUd1bxgkTW0 4m5ZsZGFN66mBIM+73vU6JHpnZhUFAaWKEXrrxOdilhKslcR31Z3ObEd7qXcdixzarw0 VrOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=ggkcaTzzuYDH/ZORZV/VDUHUFe6Rd9N+H9lpwdVyMAg=; b=RzEzNn1Qt/U9mn1seYYdeIsJpBEbSoH7yoYwtnaP5LcWYIicBoWWqFMmOd+oDpvi8W 59Ck2XKNJ4OGv0Z+dmiwo7zbXSy9mdmAhT8cWlZBESUHOw37/uNrjXG8gGlwMgy5GuVm 9j3RLgB8FpSANbm+3t+Mz+dgTH1oZVdQVgQiyDTsJuGuTwAakOiS66RYr5MQ3MbfhNge kBEd2GkZsEUaey1wYExSpC1uEEiS0Pl45Ab1/xVF+5502Ny8g3Bfp3jC2uRL2mou2owi zosuCSmmvMq0vx7QWcTeGb8tp4omqywhMbcCHr3M3UEbsGERAaBHmFZJTDy6GCgpolzH hTqw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=PnRP5CJP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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(localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 981791FF8F; Tue, 30 Apr 2019 17:52:34 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Tue, 30 Apr 2019 17:52:21 +0100 Message-Id: <20190430165234.32272-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190430165234.32272-1-alex.bennee@linaro.org> References: <20190430165234.32272-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH v5 02/15] tests/tcg/multiarch: add hello world system test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, mark.cave-ayland@ilande.co.uk, cota@braap.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is not really i386 only, we can have the same test for all architectures supporting system tests. Signed-off-by: Alex Bennée --- tests/tcg/i386/Makefile.softmmu-target | 2 +- tests/tcg/{i386 => multiarch}/system/hello.c | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename tests/tcg/{i386 => multiarch}/system/hello.c (100%) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/tests/tcg/i386/Makefile.softmmu-target b/tests/tcg/i386/Makefile.softmmu-target index 53c9c5ece0..c31bbbf39a 100644 --- a/tests/tcg/i386/Makefile.softmmu-target +++ b/tests/tcg/i386/Makefile.softmmu-target @@ -27,7 +27,7 @@ CFLAGS+=-m32 LINK_SCRIPT=$(I386_SYSTEM_SRC)/kernel.ld LDFLAGS=-Wl,-T$(LINK_SCRIPT) -Wl,-melf_i386 # FIXME: move to common once x86_64 is bootstrapped -TESTS+=$(X86_TESTS) +TESTS+=$(X86_TESTS) $(MULTIARCH_TESTS) endif CFLAGS+=-nostdlib -ggdb -O0 $(MINILIB_INC) LDFLAGS+=-static -nostdlib $(CRT_OBJS) $(MINILIB_OBJS) -lgcc diff --git a/tests/tcg/i386/system/hello.c b/tests/tcg/multiarch/system/hello.c similarity index 100% rename from tests/tcg/i386/system/hello.c rename to tests/tcg/multiarch/system/hello.c From patchwork Tue Apr 30 16:52:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 163134 Delivered-To: patch@linaro.org Received: by 2002:a92:7e86:0:0:0:0:0 with SMTP id q6csp3484635ill; Tue, 30 Apr 2019 10:03:40 -0700 (PDT) X-Google-Smtp-Source: APXvYqxNxcYFaeB9SWtvDAXnn26v9m/fyTD656HXVMxE65BlUh/aJ3YtNRIecPMuO4b8gmoAXvdi X-Received: by 2002:adf:e9cb:: with SMTP id l11mr27535253wrn.114.1556643820497; Tue, 30 Apr 2019 10:03:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556643820; cv=none; d=google.com; s=arc-20160816; b=UEI4Hv3AVUU/4/ck98gM0P/YMdiwNa/L4BWarX8jBcMNYu7Vz5LoBL93GVZWq/+hcK DTPlPnhaD6dj6sYYan+jQHElSE/8Xi3FV6Evy1nHtJ/0bGneD9kro+Hjb2swtLRAOqzx Z2bLsskhRCyU4T9bu1UXwYAXVp+m+lxOaDnz/pYvQqGy68Y1Xu/L7tRWIRHE33VlVk6a QbmMWoLzJNupVUH6fbPhuX6ZfHaZXs3X9SNr7KPLYHm34OBHOYBNxK/1ULkSUcrRfAbv yhDmvkR+pnc5b5KbtOKRcdXEsrk9CXBWXZMPH0llj8gE5X2sn7vUGg27QWnGfdabC9DX SKiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=+yEjKlsJwKF3hEXc9nK8fe/qlKiVoemDI5/tX+ia1Pc=; b=h9iesI8rXecQvzLwzaLNQO4i9JzZ4EGypw5SzA7r/6IYAbiFYdUsSbEvm4Hc5lPDyg WldeCZhjIP2SkQ3+KZtbb7xu3be5ZV88ml3i/FSBTW8CBPDSqGoCpbiy7dB89e0A/+0J p1m4U5D2B02tek2CAczl5jxVh/jQxsWlJeAQMiuoChsYBDFmpnEqYpKignj+RqMsZ9uV ikkMGUmm2UMO+uSXCfMRYhrU/3qd+LKYNhWt0+7XbbhOq1QtM52SunDn5F1nlopjjsZD 0x7KmRUWVPHr3061kKekEnFktmL5+iIi36+E9GTYmv+CfIxo1pNIQWrkTuJGC4YQwgJF /jBQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=KNkDXDry; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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(localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id A3EA91FF90; Tue, 30 Apr 2019 17:52:34 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Tue, 30 Apr 2019 17:52:22 +0100 Message-Id: <20190430165234.32272-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190430165234.32272-1-alex.bennee@linaro.org> References: <20190430165234.32272-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH v5 03/15] tests/tcg/aarch64: add system boot.S X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, mark.cave-ayland@ilande.co.uk, cota@braap.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This provides the bootstrap and low level helper functions for an aarch64 kernel. We use semihosting to handle test output and exiting the emulation. semihosting's parameter passing is a little funky so we end up using the stack and pointing to that as the parameter block. Signed-off-by: Alex Bennée --- tests/tcg/aarch64/Makefile.softmmu-target | 32 ++++ tests/tcg/aarch64/system/boot.S | 200 ++++++++++++++++++++++ tests/tcg/aarch64/system/kernel.ld | 22 +++ 3 files changed, 254 insertions(+) create mode 100644 tests/tcg/aarch64/Makefile.softmmu-target create mode 100644 tests/tcg/aarch64/system/boot.S create mode 100644 tests/tcg/aarch64/system/kernel.ld -- 2.20.1 diff --git a/tests/tcg/aarch64/Makefile.softmmu-target b/tests/tcg/aarch64/Makefile.softmmu-target new file mode 100644 index 0000000000..e6aee856c8 --- /dev/null +++ b/tests/tcg/aarch64/Makefile.softmmu-target @@ -0,0 +1,32 @@ +# +# Aarch64 system tests +# + +AARCH64_SYSTEM_SRC=$(SRC_PATH)/tests/tcg/aarch64/system +VPATH+=$(AARCH64_SYSTEM_SRC) + +# These objects provide the basic boot code and helper functions for all tests +CRT_OBJS=boot.o + +AARCH64_TEST_SRCS=$(wildcard $(AARCH64_SYSTEM_SRC)/*.c) +AARCH64_TESTS = $(patsubst $(AARCH64_SYSTEM_SRC)/%.c, %, $(AARCH64_TEST_SRCS)) + +CRT_PATH=$(AARCH64_SYSTEM_SRC) +LINK_SCRIPT=$(AARCH64_SYSTEM_SRC)/kernel.ld +LDFLAGS=-Wl,-T$(LINK_SCRIPT) +TESTS+=$(AARCH64_TESTS) $(MULTIARCH_TESTS) +CFLAGS+=-nostdlib -ggdb -O0 $(MINILIB_INC) +LDFLAGS+=-static -nostdlib $(CRT_OBJS) $(MINILIB_OBJS) -lgcc + +# building head blobs +.PRECIOUS: $(CRT_OBJS) + +%.o: $(CRT_PATH)/%.S + $(CC) $(CFLAGS) -x assembler-with-cpp -c $< -o $@ + +# Build and link the tests +%: %.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS) + $(CC) $(CFLAGS) $< -o $@ $(LDFLAGS) + +# Running +QEMU_OPTS+=-M virt -cpu max -display none -semihosting -kernel diff --git a/tests/tcg/aarch64/system/boot.S b/tests/tcg/aarch64/system/boot.S new file mode 100644 index 0000000000..03d319e07f --- /dev/null +++ b/tests/tcg/aarch64/system/boot.S @@ -0,0 +1,200 @@ +/* + * Minimal AArch64 system boot code. + * + * Copyright Linaro Ltd 2019 + * + * Loosely based on the newlib/libgloss setup stubs. Using semihosting + * for serial output and exit functions. + */ + +/* + * Semihosting interface on ARM AArch64 + * See "Semihosting for AArch32 and AArch64 Relase 2.0" by ARM + * w0 - semihosting call number + * x1 - semihosting parameter + */ +#define semihosting_call hlt 0xf000 +#define SYS_WRITEC 0x03 /* character to debug channel */ +#define SYS_WRITE0 0x04 /* string to debug channel */ +#define SYS_EXIT 0x18 + + .align 12 + + .macro ventry label + .align 7 + b \label + .endm + +vector_table: + /* Current EL with SP0. */ + ventry curr_sp0_sync /* Synchronous */ + ventry curr_sp0_irq /* Irq/vIRQ */ + ventry curr_sp0_fiq /* Fiq/vFIQ */ + ventry curr_sp0_serror /* SError/VSError */ + + /* Current EL with SPx. */ + ventry curr_spx_sync /* Synchronous */ + ventry curr_spx_irq /* IRQ/vIRQ */ + ventry curr_spx_fiq /* FIQ/vFIQ */ + ventry curr_spx_serror /* SError/VSError */ + + /* Lower EL using AArch64. */ + ventry lower_a64_sync /* Synchronous */ + ventry lower_a64_irq /* IRQ/vIRQ */ + ventry lower_a64_fiq /* FIQ/vFIQ */ + ventry lower_a64_serror /* SError/VSError */ + + /* Lower EL using AArch32. */ + ventry lower_a32_sync /* Synchronous */ + ventry lower_a32_irq /* IRQ/vIRQ */ + ventry lower_a32_fiq /* FIQ/vFIQ */ + ventry lower_a32_serror /* SError/VSError */ + + .text + .align 4 + + /* Common vector handling for now */ +curr_sp0_sync: +curr_sp0_irq: +curr_sp0_fiq: +curr_sp0_serror: +curr_spx_sync: +curr_spx_irq: +curr_spx_fiq: +curr_spx_serror: +lower_a64_sync: +lower_a64_irq: +lower_a64_fiq: +lower_a64_serror: +lower_a32_sync: +lower_a32_irq: +lower_a32_fiq: +lower_a32_serror: + mov x0, SYS_WRITE0 + adr x1, .error + semihosting_call + mov x0, SYS_EXIT + mov x1, 1 + semihosting_call + /* never returns */ + +.error: + .string "Terminated by exception.\n" + + .align 4 + .global __start +__start: + /* Installs a table of exception vectors to catch and handle all + exceptions by terminating the process with a diagnostic. */ + adr x0, vector_table + msr vbar_el1, x0 + + /* Page table setup (identity mapping). */ + adrp x0, ttb + add x0, x0, :lo12:ttb + msr ttbr0_el1, x0 + + /* Create some (big) pages */ + adr x1, . /* phys address */ + bic x1, x1, #(1 << 30) - 1 /* 1GB block alignment */ + + add x2, x0, x1, lsr #(30 - 3) /* page offset in l1 page table */ + + mov x3, #0x401 /* page table attributes (AF, block) */ + orr x1, x1, x3 + + str x1, [x2], #8 /* 1st GB */ + + mov x3, #(1 << 30) /* 1GB block */ + add x1, x1, x3 + + str x1, [x2] /* 2nd GB */ + + /* Setup/enable the MMU. */ + + /* + * TCR_EL1 - Translation Control Registers + * + * IPS[34:32] = 40-bit PA, 1TB + * ORGN0[11:10] = Outer: Normal, Outer Write-Back Read-Allocate No Write-Allocate Cacheable + * IRGN0[9:8] = Inner: Normal, Inner Write-Back Read-Allocate No Write-Allocate Cacheable. + * T0SZ[5:0] = 2^(64 - 25) + */ + ldr x0, = (2 << 32) | 25 | (3 << 10) | (3 << 8) + msr tcr_el1, x0 + + mov x0, #0xee /* Inner/outer cacheable WB */ + msr mair_el1, x0 + isb + + /* + * SCTLR_EL1 - System Control Register + * + * WXN[19] = 0 = no effect, Write does not imply XN (execute never) + * I[12] = Instruction cachability control + * SA[3] = SP alignment check + * C[2] = Data cachability control + * M[0] = 1, enable stage 1 address translation for EL0/1 + */ + mrs x0, sctlr_el1 + ldr x1, =0x100d /* bits I(12) SA(3) C(2) M(0) */ + bic x0, x0, #(1 << 1) /* clear bit A(1) */ + bic x0, x0, #(1 << 19) /* clear WXN */ + orr x0, x0, x1 /* set bits */ + + dsb sy + msr sctlr_el1, x0 + isb + + /* + * Enable FP registers. The standard C pre-amble will be + * saving these and A-profile compilers will use AdvSIMD + * registers unless we tell it not to. + */ + mrs x0, cpacr_el1 + orr x0, x0, #(3 << 20) + msr cpacr_el1, x0 + + /* Setup some stack space and enter the test code. + * Assume everthing except the return value is garbage when we + * return, we won't need it. + */ + adrp x0, stack + add x0, x0, :lo12:stack + + mov sp, x0 + bl main + + /* pass return value to sys exit */ + mov x1, x0 + ldr x0, =0x20026 /* ADP_Stopped_ApplicationExit */ + stp x0, x1, [sp, #-16]! + mov x1, sp + mov x0, SYS_EXIT + semihosting_call + /* never returns */ + + /* + * Helper Functions + */ + + /* Output a single character to serial port */ + .global __sys_outc +__sys_outc: + stp x0, x1, [sp, #-16]! + /* pass address of c on stack */ + mov x1, sp + mov x0, SYS_WRITEC + semihosting_call + ldp x0, x1, [sp], #16 + ret + + .data + .align 12 +ttb: + .space 4096, 0 + + .align 12 +stack: + .space 65536, 0 +stack_end: diff --git a/tests/tcg/aarch64/system/kernel.ld b/tests/tcg/aarch64/system/kernel.ld new file mode 100644 index 0000000000..73d75cae64 --- /dev/null +++ b/tests/tcg/aarch64/system/kernel.ld @@ -0,0 +1,22 @@ +ENTRY(__start) + +SECTIONS +{ + /* virt machine, RAM starts at 1gb */ + . = (1 << 30); + .text : { + *(.text) + } + .data : { + *(.data) + } + .rodata : { + *(.rodata) + } + .bss : { + *(.bss) + } + /DISCARD/ : { + *(.ARM.attributes) + } +} From patchwork Tue Apr 30 16:52:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 163146 Delivered-To: patch@linaro.org Received: by 2002:a92:7e86:0:0:0:0:0 with SMTP id q6csp3490797ill; Tue, 30 Apr 2019 10:08:30 -0700 (PDT) X-Google-Smtp-Source: APXvYqyBPtSAp89NNcagkLB2mOz0cNSuba+aJQx/Ko93df2mTI7Pas8enI5n77rrxg/3T/nWcjIY X-Received: by 2002:a5d:65ce:: with SMTP id e14mr25131049wrw.270.1556644109921; Tue, 30 Apr 2019 10:08:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556644109; cv=none; d=google.com; s=arc-20160816; b=NSI25uIrrpUgm02Hj3C/Y9qV5FavFl2paUNlE15NTzzbRHWKldCmxtNbd+ffQ5epoo pjQ78/kahndYIuxykLHDdnP/v10BcC55D4O8fiDahC5YtOJeWRwBfSQW8UsEN1Vl4+sY exxad67DV91/6vrOrI5wXcCvZdu38rWAiqOdDjhJCEkaGseEvc4aQ6sFo0Hq6HTditrH zbVkPq9njuZRzDwMGdkUZ+dND8iDOZjrzZZfyk5ptnD4Z17YohRvs6tMzGxxjjXq2PLm XWWAAkXMYy2Vl8DAGalcQhuXSFynEheXzSIiQjbsovIaTIq0kec0+CO4evgCp6WT2fSR g+9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=mJ7CZS0sQcbUsk/Tw/L7H0J0hSgoFo0m9c7Q9J4OMKs=; b=q1rlx+dDfaui3c0m6oPBv8bD/cwOi7qYnOQqNelNFpP7TVXLFUgq5KEAdYf9+GTS2+ iJ7ZHofdSaavfW3bFiWlm699CogQisbDZypYQn1A9YqE/DatnQMIIDo4+jENDNxE1DIy C+eaEAnGQpj9208IykleKs/gQYIC7YXDS7HngyHAVsKKAaT6jhH/sFQSMvXvfcBYc+3i 0+/8EomhaLHEo+tND5zdD6CbNe63ukcFLm9slheNezCjRFjpDPd04k/mH632Fy2j/V10 MMIvJRSSbMw2GVZeNUuWqWgS//y8Q6Fk0aVNqErk3bswH45hf83cFZpDoViYO0T0mrGq qPBg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NKkCAJse; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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(localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id AFE0E1FF91; Tue, 30 Apr 2019 17:52:34 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Tue, 30 Apr 2019 17:52:23 +0100 Message-Id: <20190430165234.32272-5-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190430165234.32272-1-alex.bennee@linaro.org> References: <20190430165234.32272-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH v5 04/15] tests/tcg/multiarch: move the system memory test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, mark.cave-ayland@ilande.co.uk, cota@braap.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There is nothing inherently architecture specific about the memory test although we may have to manage different restrictions of unaligned access across architectures. Signed-off-by: Alex Bennée --- tests/tcg/{i386 => multiarch}/system/memory.c | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename tests/tcg/{i386 => multiarch}/system/memory.c (100%) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/tests/tcg/i386/system/memory.c b/tests/tcg/multiarch/system/memory.c similarity index 100% rename from tests/tcg/i386/system/memory.c rename to tests/tcg/multiarch/system/memory.c From patchwork Tue Apr 30 16:52:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 163147 Delivered-To: patch@linaro.org Received: by 2002:a92:7e86:0:0:0:0:0 with SMTP id q6csp3492334ill; Tue, 30 Apr 2019 10:09:42 -0700 (PDT) X-Google-Smtp-Source: APXvYqxIx4A42yfFB+oBSoq66EZe40r6xCF7WtIS3hBPbrFdKZ08Cg3HbBDAXuOgEhwbgU3Y5z3L X-Received: by 2002:adf:ee42:: with SMTP id w2mr43935881wro.161.1556644181988; Tue, 30 Apr 2019 10:09:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556644181; cv=none; d=google.com; s=arc-20160816; b=zUGuaVRgJ/k/jHQFGPRUBMiXQi0D/TqI7tc+yr9QKjL47WtYQ8McubbyYrDkXssXVo MhCV1Vh5wmFFgNYC5ivQCKSTzo6Bqnf+q9kGcRVh6OCryHWtbNiCo5m0fHJUoL8LalFy GYMXDEEoaL3Sf0FTpwZLmVejBYNaKMzbAihxDHL1aFs7bsi9tDTMDDOYnrfCXNS5uqwJ NsvcHzdoJTCKlq8GYByiaVGSMIKeyfFU+ElP7y12ivxNkDY1jiVceicZOQCzvR8P9bZR 5I+KAi4NAdJwCp3ifunddJ1QIq4kLheC5b5EKq0FfKxYjL5bNb9P0IpmAwqPrAcT9Do8 pJ4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=6vVqCrsSMAq2VmXMxaXptAXGJhe00/TSZtSzKlH1E7Y=; b=J3DLA4p9eD56Zl6xPC7Bqhlk95/AL5EJPmu1b0yCMQ2TnrzOR0ea4//mXGhHt7LfFo U4ao1AxqYEK8Xw1AkZOt9g71ytm+lfnzvVtSjUI021tF9Y8y/JJzRUVodLGPKEa7rrFs r68sjafGXXHN1C9ssqncI8TYEsBsShPp+hu5i4FEV4eY6sK5OqSZy8HAkpULibMuLBKA +QDUQPbVWlUga6P6pXOC3kqvO2NwDO8zYlY1TsXMgmrCXMNricKh+BHpRI6rGcQPfNfY 1Z7lH626GnpHAUH0YDIy/BSSbB1dGlEgy4fYJNechDTxbBY0Jp1lor1ysyjQApUnrNAv IkzQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=N+TEAR2q; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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(localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id BCC911FF92; Tue, 30 Apr 2019 17:52:34 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Tue, 30 Apr 2019 17:52:24 +0100 Message-Id: <20190430165234.32272-6-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190430165234.32272-1-alex.bennee@linaro.org> References: <20190430165234.32272-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH v5 05/15] tests/tcg/minilib: support %c format char X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, mark.cave-ayland@ilande.co.uk, cota@braap.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée --- tests/tcg/minilib/printf.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/tests/tcg/minilib/printf.c b/tests/tcg/minilib/printf.c index 121620cb16..d530b32be5 100644 --- a/tests/tcg/minilib/printf.c +++ b/tests/tcg/minilib/printf.c @@ -47,7 +47,7 @@ static void print_num(unsigned long long value, int base) void ml_printf(const char *fmt, ...) { va_list ap; - char *str; + char *str, c; int base; int has_long; int alt_form; @@ -119,6 +119,10 @@ void ml_printf(const char *fmt, ...) str = va_arg(ap, char*); print_str(str); break; + case 'c': + c = (char) va_arg(ap, int); + __sys_outc(c); + break; case '%': __sys_outc(*fmt); break; From patchwork Tue Apr 30 16:52:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 163136 Delivered-To: patch@linaro.org Received: by 2002:a92:7e86:0:0:0:0:0 with SMTP id q6csp3486770ill; Tue, 30 Apr 2019 10:05:17 -0700 (PDT) X-Google-Smtp-Source: APXvYqym8ndX3X/GkzX8p4BycSeUDkJE2kE1O3rHRZBJCkH7fLVW1VpXYpPyFMUWCF70FZtrOrea X-Received: by 2002:adf:f384:: with SMTP id m4mr1062271wro.68.1556643917763; Tue, 30 Apr 2019 10:05:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556643917; cv=none; d=google.com; s=arc-20160816; b=gcL53oEP5mdxNu8aR+QDvs07BBaZwX0Vcxy2P79cfr5DOcubsWCcj+7aNfWcuAMB+C 0k7NvmYkRuEJM5RsaVS5ia+1U6f8qMYLGNEiS8PPH5xWUMDUhB7V2S/1ED7DaCliQg0z mNyr0IbaR8UPedfJmlXXmxpBIWavW3lMunf4Q1WalGklB+47a2U9kzCnJZmSp7uTzhML tY1p4rlHN95bpRA36CR5BUmzTtXHon7lgLCmiR4VzDtA37A6pEmqUndbKUp9QJFQAwBE kdIPQvuhrQ0nD/EdN+XaIJf6MnJWjmufWyfjJ4lyjg+0Mz0CqDHzh4xpcK7KjUTfWeWq reYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=EdGFZbKcoEBKfDx7OK4/edboZqTBfkUrZ7ki4QLE8eA=; b=XluLzMd8eWtfCo2/gYUfnJk4iCnv3+cr+fyb7YG2783gF+6nFbNtpiQjM/Dhe5hcev 3T7JN9pgQRf+ls8PwKiYy+QXHxPsLclsG2d0H+mTZa/oraFTWVe2jWiESppzogOhuHMr erD2NoWZc5izPR8pMB54p+oy+vEb4mobIutJ9ESV89wcw5352p4uXTLB+zLgWrNUV/fv LRwVJwRDK4XTx+u1Pnv12fg8zqkxu/9zp2LA2DKk8rwx3QWZTBzZ4HEPpWsV4nkzkudS wmUQmnTgecBD7espHBWCm6neGAoY+3b9Z6L5MPhue5fzQCYniQa25dVkTJFVNgKMkvMA k44w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Vnh4GMUK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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(localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id C971F1FF93; Tue, 30 Apr 2019 17:52:34 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Tue, 30 Apr 2019 17:52:25 +0100 Message-Id: <20190430165234.32272-7-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190430165234.32272-1-alex.bennee@linaro.org> References: <20190430165234.32272-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH v5 06/15] tests/tcg/multiarch: expand system memory test to cover more X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, mark.cave-ayland@ilande.co.uk, cota@braap.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Expand the memory test to cover move of the softmmu code. Specifically we: - improve commentary - add some helpers (for later BE support) - reduce boiler plate into helpers - add signed reads at various sizes/offsets Signed-off-by: Alex Bennée --- tests/tcg/multiarch/system/memory.c | 254 ++++++++++++++++++++++++---- 1 file changed, 219 insertions(+), 35 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/tests/tcg/multiarch/system/memory.c b/tests/tcg/multiarch/system/memory.c index a7a0a8e978..5befbb36bb 100644 --- a/tests/tcg/multiarch/system/memory.c +++ b/tests/tcg/multiarch/system/memory.c @@ -5,16 +5,21 @@ * behave across normal and unaligned accesses across several pages. * We are not replicating memory tests for stuck bits and other * hardware level failures but looking for issues with different size - * accesses when: - + * accesses when access is: * + * - unaligned at various sizes + * - spanning a (softmmu) page + * - sign extension when loading */ #include +#include #include -#define TEST_SIZE (4096 * 4) /* 4 pages */ +#define PAGE_SIZE 4096 /* nominal 4k "pages" */ +#define TEST_SIZE (PAGE_SIZE * 4) /* 4 pages */ +__attribute__((aligned(PAGE_SIZE))) static uint8_t test_data[TEST_SIZE]; static void pdot(int count) @@ -24,11 +29,19 @@ static void pdot(int count) } } +/* + * Helper macros for shift/extract so we can keep our endian handling + * in one place. + */ +#define BYTE_SHIFT(b, pos) ((uint64_t)b << (pos * 8)) +#define BYTE_EXTRACT(b, pos) ((b >> (pos * 8)) & 0xff) /* - * Fill the data with ascending value bytes. As x86 is a LE machine we - * write in ascending order and then read and high byte should either - * be zero or higher than the lower bytes. + * Fill the data with ascending value bytes. + * + * Currently we only support Little Endian machines so write in + * ascending address order. When we read higher address bytes should + * either be zero or higher than the lower bytes. */ static void init_test_data_u8(void) @@ -44,60 +57,109 @@ static void init_test_data_u8(void) ml_printf("done\n"); } +/* + * Full the data with alternating positive and negative bytes. This + * should mean for reads larger than a byte all subsequent reads will + * stay either negative or positive. We never write 0. + */ + +static inline uint8_t get_byte(int index, bool neg) +{ + return neg ? ( 0xff << (index % 7)) : ( 0xff >> ((index % 6) + 1)); +} + +static void init_test_data_s8(bool neg_first) +{ + uint8_t top, bottom, *ptr = &test_data[0]; + int i; + + ml_printf("Filling test area with s8 pairs (%s):", neg_first ? "neg first":"pos first"); + for (i = 0; i < TEST_SIZE / 2; i++) { + *ptr++ = get_byte(i, neg_first); + *ptr++ = get_byte(i, !neg_first); + pdot(i); + } + ml_printf("done\n"); +} + +/* + * Zero the first few bytes of the test data in preparation for + * new offset values. + */ +static void reset_start_data(int offset) +{ + uint32_t *ptr = (uint32_t *) &test_data[0]; + int i; + for (i = 0; i < offset; i++) { + *ptr++ = 0; + } +} + static void init_test_data_u16(int offset) { uint8_t count = 0; - uint16_t word, *ptr = (uint16_t *) &test_data[0]; + uint16_t word, *ptr = (uint16_t *) &test_data[offset]; const int max = (TEST_SIZE - offset) / sizeof(word); int i; - ml_printf("Filling test area with u16 (offset %d):", offset); + ml_printf("Filling test area with u16 (offset %d, %p):", offset, ptr); - /* Leading zeros */ - for (i = 0; i < offset; i++) { - *ptr = 0; - } + reset_start_data(offset); - ptr = (uint16_t *) &test_data[offset]; for (i = 0; i < max; i++) { - uint8_t high, low; - low = count++; - high = count++; - word = (high << 8) | low; + uint8_t low = count++, high = count++; + word = BYTE_SHIFT(high, 1) | BYTE_SHIFT(low, 0); *ptr++ = word; pdot(i); } - ml_printf("done\n"); + ml_printf("done @ %p\n", ptr); } static void init_test_data_u32(int offset) { uint8_t count = 0; - uint32_t word, *ptr = (uint32_t *) &test_data[0]; + uint32_t word, *ptr = (uint32_t *) &test_data[offset]; const int max = (TEST_SIZE - offset) / sizeof(word); int i; - ml_printf("Filling test area with u32 (offset %d):", offset); + ml_printf("Filling test area with u32 (offset %d, %p):", offset, ptr); - /* Leading zeros */ - for (i = 0; i < offset; i++) { - *ptr = 0; - } + reset_start_data(offset); - ptr = (uint32_t *) &test_data[offset]; for (i = 0; i < max; i++) { - uint8_t b1, b2, b3, b4; - b4 = count++; - b3 = count++; - b2 = count++; - b1 = count++; - word = (b1 << 24) | (b2 << 16) | (b3 << 8) | b4; + uint8_t b4 = count++, b3 = count++; + uint8_t b2 = count++, b1 = count++; + word = BYTE_SHIFT(b1, 3) | BYTE_SHIFT(b2, 2) | BYTE_SHIFT(b3, 1) | b4; *ptr++ = word; pdot(i); } - ml_printf("done\n"); + ml_printf("done @ %p\n", ptr); } +static void init_test_data_u64(int offset) +{ + uint8_t count = 0; + uint64_t word, *ptr = (uint64_t *) &test_data[offset]; + const int max = (TEST_SIZE - offset) / sizeof(word); + int i; + + ml_printf("Filling test area with u64 (offset %d, %p):", offset, ptr); + + reset_start_data(offset); + + for (i = 0; i < max; i++) { + uint8_t b8 = count++, b7 = count++; + uint8_t b6 = count++, b5 = count++; + uint8_t b4 = count++, b3 = count++; + uint8_t b2 = count++, b1 = count++; + word = BYTE_SHIFT(b1, 7) | BYTE_SHIFT(b2, 6) | BYTE_SHIFT(b3, 5) | + BYTE_SHIFT(b4, 4) | BYTE_SHIFT(b5, 3) | BYTE_SHIFT(b6, 2) | + BYTE_SHIFT(b7, 1) | b8; + *ptr++ = word; + pdot(i); + } + ml_printf("done @ %p\n", ptr); +} static int read_test_data_u16(int offset) { @@ -120,7 +182,7 @@ static int read_test_data_u16(int offset) } } - ml_printf("done\n"); + ml_printf("done @ %p\n", ptr); return 0; } @@ -150,7 +212,7 @@ static int read_test_data_u32(int offset) pdot(i); } } - ml_printf("done\n"); + ml_printf("done @ %p\n", ptr); return 0; } @@ -189,7 +251,7 @@ static int read_test_data_u64(int offset) pdot(i); } } - ml_printf("done\n"); + ml_printf("done @ %p\n", ptr); return 0; } @@ -209,6 +271,110 @@ int do_reads(void) return r; } +/* + * We need to ensure signed data is read into a larger data type to + * ensure that sign extension is working properly. + */ + +static int read_test_data_s8(int offset, bool neg_first) +{ + int8_t *ptr = (int8_t *)&test_data[offset]; + int i; + const int max = (TEST_SIZE - offset) / 2; + + ml_printf("Reading s8 pairs from %#lx (offset %d):", ptr, offset); + + for (i = 0; i < max; i++) { + int16_t first, second; + bool ok; + first = *ptr++; + second = *ptr++; + + if (neg_first && first < 0 && second > 0) { + pdot(i); + } else if (!neg_first && first > 0 && second < 0) { + pdot(i); + } else { + ml_printf("Error %d %c %d\n", first, neg_first ? '<' : '>', second); + return 1; + } + } + ml_printf("done @ %p\n", ptr); + return 0; +} + +static int read_test_data_s16(int offset, bool neg_first) +{ + int16_t *ptr = (int16_t *)&test_data[offset]; + int i; + const int max = (TEST_SIZE - offset) / (sizeof(*ptr)); + + ml_printf("Reading s16 from %#lx (offset %d, %s):", + ptr, offset, neg_first ? "neg":"pos"); + + for (i = 0; i < max; i++) { + int32_t data = *ptr++; + + if (neg_first && data < 0) { + pdot(i); + } else if (data > 0) { + pdot(i); + } else { + ml_printf("Error %d %c 0\n", data, neg_first ? '<' : '>'); + return 1; + } + } + ml_printf("done @ %p\n", ptr); + return 0; +} + +static int read_test_data_s32(int offset, bool neg_first) +{ + int32_t *ptr = (int32_t *)&test_data[offset]; + int i; + const int max = (TEST_SIZE - offset) / (sizeof(int32_t)); + + ml_printf("Reading s32 from %#lx (offset %d, %s):", + ptr, offset, neg_first ? "neg":"pos"); + + for (i = 0; i < max; i++) { + int64_t data = *ptr++; + + if (neg_first && data < 0) { + pdot(i); + } else if (data > 0) { + pdot(i); + } else { + ml_printf("Error %d %c 0\n", data, neg_first ? '<' : '>'); + return 1; + } + } + ml_printf("done @ %p\n", ptr); + return 0; +} + +/* + * Read the test data and verify at various offsets + * + * For everything except bytes all our reads should be either positive + * or negative depending on what offset we are reading from. Currently + * we only handle LE systems. + */ +int do_signed_reads(bool neg_first) +{ + int r = 0; + int off = 0; + + while (r == 0 && off < 8) { + r = read_test_data_s8(off, neg_first ^ (off & 1)); + r |= read_test_data_s16(off, !(neg_first ^ (off & 1))); + r |= read_test_data_s32(off, !(neg_first ^ (off & 1))); + off++; + } + + return r; +} + int main(void) { int i, r = 0; @@ -238,6 +404,24 @@ int main(void) } } + for (i = 0; i < 8; i++) { + init_test_data_u64(i); + + r = do_reads(); + if (r) { + return r; + } + } + + init_test_data_s8(false); + r = do_signed_reads(false); + if (r) { + return r; + } + + init_test_data_s8(true); + r = do_signed_reads(true); + ml_printf("Test complete: %s\n", r == 0 ? "PASSED" : "FAILED"); return r; } From patchwork Tue Apr 30 16:52:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 163143 Delivered-To: patch@linaro.org Received: by 2002:a92:7e86:0:0:0:0:0 with SMTP id q6csp3488056ill; Tue, 30 Apr 2019 10:06:19 -0700 (PDT) X-Google-Smtp-Source: APXvYqzKTE8tk/BRgPwfH6qzYJRgBgnCo9pzlRSmXleC/rWeWSn6lBV/jQliac/5l77lTMafXGyz X-Received: by 2002:a1c:2348:: with SMTP id j69mr3878051wmj.35.1556643979115; Tue, 30 Apr 2019 10:06:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556643979; cv=none; d=google.com; s=arc-20160816; b=pph/nMhEibCMbzS/EqqrmorFxYys6TUyYCgzIAi3W7cyXZA0EpZWsrO1WIblsk0fZz 6hArvrKkpcR1Rr1MJo5RcDB7MEuNo4odGQYWM+kXDizVnBwCyH0Ok3nVmXFV6ZAyY2R6 izPj0M7M84iSS0EnHAWVGQzoMef/v5H65LIaZhNfyCb3QK+dmpNTjtnLr1dQOqDv4iZC t7BMrXEid+tddiSI72NjO3NvB424NOkwX22VqjRosyql8Nsmo5G9rBF4UTaprAdoIgKi G/zlM1Z56h6AMxY2mTh2ODGW1UmAVUWgXv+f+VrV4aotwwGWRtpmFdvSZ1vIxfRGB2nr +dfA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=ejP6pDni6QnG+BscnVUAk98KJ5gB2/yQBCsR3BIh/q8=; b=p+xgW5Le0hjdZPeoFQQlSsEKB4lVpu3tA5aYlHNijT5jNRpGvo8Q9GNouxnOvScENL CEaR3MFKPHV0QDdK9D2N7T5NePABbq6u4kbgH5+J5NsD3RJwjv22t5h3wslBzRyI6I5C G8p/Wp81oHVk7nhlNhdqM7fEjVlgBKz2gQ9ZiRsDx9fhdjEbzlTpCHjPEjj0lfqQE7Qc JisPdb4BaRjsUpG+Tln8wVAVzauXZx++EPn3Tjk+ZyPIW4XU6lNF6PshezkOda1b+AWO 1pIgLhvl0GtmEYpgvr+n/qm6l/ek+4j8vdEBoSiAccHcvpAhpSbLantlrhJqbnzUabT9 pnJQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=rSsNIvY2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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(localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id D4C581FF96; Tue, 30 Apr 2019 17:52:34 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Tue, 30 Apr 2019 17:52:26 +0100 Message-Id: <20190430165234.32272-8-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190430165234.32272-1-alex.bennee@linaro.org> References: <20190430165234.32272-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH v5 07/15] accel/tcg: demacro cputlb X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, mark.cave-ayland@ilande.co.uk, cota@braap.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Instead of expanding a series of macros to generate the load/store helpers we move stuff into common functions and rely on the compiler to eliminate the dead code for each variant. Signed-off-by: Alex Bennée --- v5 - merged rth's fixes: - cast to uint64_t instead of tcg_target_ulong - make haddr void * instead of uintptr_t (reduce casting) - common & size_mask --- accel/tcg/cputlb.c | 478 ++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 452 insertions(+), 26 deletions(-) -- 2.20.1 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index f2f618217d..12f21865ee 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1168,26 +1168,421 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, } #ifdef TARGET_WORDS_BIGENDIAN -# define TGT_BE(X) (X) -# define TGT_LE(X) BSWAP(X) +#define NEED_BE_BSWAP 0 +#define NEED_LE_BSWAP 1 #else -# define TGT_BE(X) BSWAP(X) -# define TGT_LE(X) (X) +#define NEED_BE_BSWAP 1 +#define NEED_LE_BSWAP 0 #endif -#define MMUSUFFIX _mmu +/* + * Byte Swap Helper + * + * This should all dead code away depending on the build host and + * access type. + */ -#define DATA_SIZE 1 -#include "softmmu_template.h" +static inline uint64_t handle_bswap(uint64_t val, int size, bool big_endian) +{ + if ((big_endian && NEED_BE_BSWAP) || (!big_endian && NEED_LE_BSWAP)) { + switch (size) { + case 1: return val; + case 2: return bswap16(val); + case 4: return bswap32(val); + case 8: return bswap64(val); + default: + g_assert_not_reached(); + } + } else { + return val; + } +} -#define DATA_SIZE 2 -#include "softmmu_template.h" +/* + * Load Helpers + * + * We support two different access types. SOFTMMU_CODE_ACCESS is + * specifically for reading instructions from system memory. It is + * called by the translation loop and in some helpers where the code + * is disassembled. It shouldn't be called directly by guest code. + */ -#define DATA_SIZE 4 -#include "softmmu_template.h" +static uint64_t load_helper(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr, + size_t size, bool big_endian, + bool code_read) +{ + uintptr_t mmu_idx = get_mmuidx(oi); + uintptr_t index = tlb_index(env, mmu_idx, addr); + CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr); + target_ulong tlb_addr = code_read ? entry->addr_code : entry->addr_read; + const size_t tlb_off = code_read ? + offsetof(CPUTLBEntry, addr_code) : offsetof(CPUTLBEntry, addr_read); + unsigned a_bits = get_alignment_bits(get_memop(oi)); + void *haddr; + uint64_t res; + + /* Handle CPU specific unaligned behaviour */ + if (addr & ((1 << a_bits) - 1)) { + cpu_unaligned_access(ENV_GET_CPU(env), addr, + code_read ? MMU_INST_FETCH : MMU_DATA_LOAD, + mmu_idx, retaddr); + } -#define DATA_SIZE 8 -#include "softmmu_template.h" + /* If the TLB entry is for a different page, reload and try again. */ + if (!tlb_hit(tlb_addr, addr)) { + if (!victim_tlb_hit(env, mmu_idx, index, tlb_off, + addr & TARGET_PAGE_MASK)) { + tlb_fill(ENV_GET_CPU(env), addr, size, + code_read ? MMU_INST_FETCH : MMU_DATA_LOAD, + mmu_idx, retaddr); + index = tlb_index(env, mmu_idx, addr); + entry = tlb_entry(env, mmu_idx, addr); + } + tlb_addr = code_read ? entry->addr_code : entry->addr_read; + } + + /* Handle an IO access. */ + if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { + CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index]; + uint64_t tmp; + + if ((addr & (size - 1)) != 0) { + goto do_unaligned_access; + } + + tmp = io_readx(env, iotlbentry, mmu_idx, addr, retaddr, + tlb_addr & TLB_RECHECK, + code_read ? MMU_INST_FETCH : MMU_DATA_LOAD, size); + return handle_bswap(tmp, size, big_endian); + } + + /* Handle slow unaligned access (it spans two pages or IO). */ + if (size > 1 + && unlikely((addr & ~TARGET_PAGE_MASK) + size - 1 + >= TARGET_PAGE_SIZE)) { + target_ulong addr1, addr2; + tcg_target_ulong r1, r2; + unsigned shift; + do_unaligned_access: + addr1 = addr & ~(size - 1); + addr2 = addr1 + size; + r1 = load_helper(env, addr1, oi, retaddr, size, big_endian, code_read); + r2 = load_helper(env, addr2, oi, retaddr, size, big_endian, code_read); + shift = (addr & (size - 1)) * 8; + + if (big_endian) { + /* Big-endian combine. */ + res = (r1 << shift) | (r2 >> ((size * 8) - shift)); + } else { + /* Little-endian combine. */ + res = (r1 >> shift) | (r2 << ((size * 8) - shift)); + } + return res & MAKE_64BIT_MASK(0, size * 8); + } + + haddr = (void *)((uintptr_t)addr + entry->addend); + + switch (size) { + case 1: + res = ldub_p(haddr); + break; + case 2: + if (big_endian) { + res = lduw_be_p(haddr); + } else { + res = lduw_le_p(haddr); + } + break; + case 4: + if (big_endian) { + res = (uint32_t)ldl_be_p(haddr); + } else { + res = (uint32_t)ldl_le_p(haddr); + } + break; + case 8: + if (big_endian) { + res = ldq_be_p(haddr); + } else { + res = ldq_le_p(haddr); + } + break; + default: + g_assert_not_reached(); + } + + return res; +} + +/* + * For the benefit of TCG generated code, we want to avoid the + * complication of ABI-specific return type promotion and always + * return a value extended to the register size of the host. This is + * tcg_target_long, except in the case of a 32-bit host and 64-bit + * data, and for that we always have uint64_t. + * + * We don't bother with this widened value for SOFTMMU_CODE_ACCESS. + */ + +tcg_target_ulong __attribute__((flatten)) +helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 1, false, false); +} + +tcg_target_ulong __attribute__((flatten)) +helper_le_lduw_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 2, false, false); +} + +tcg_target_ulong __attribute__((flatten)) +helper_be_lduw_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 2, true, false); +} + +tcg_target_ulong __attribute__((flatten)) +helper_le_ldul_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 4, false, false); +} + +tcg_target_ulong __attribute__((flatten)) +helper_be_ldul_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 4, true, false); +} + +uint64_t __attribute__((flatten)) +helper_le_ldq_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 8, false, false); +} + +uint64_t __attribute__((flatten)) +helper_be_ldq_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 8, true, false); +} + +/* + * Provide signed versions of the load routines as well. We can of course + * avoid this for 64-bit data, or for 32-bit data on 32-bit host. + */ + + +tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + return (int8_t)helper_ret_ldub_mmu(env, addr, oi, retaddr); +} + +tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + return (int16_t)helper_le_lduw_mmu(env, addr, oi, retaddr); +} + +tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + return (int16_t)helper_be_lduw_mmu(env, addr, oi, retaddr); +} + +tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + return (int32_t)helper_le_ldul_mmu(env, addr, oi, retaddr); +} + +tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + return (int32_t)helper_be_ldul_mmu(env, addr, oi, retaddr); +} + +/* + * Store Helpers + */ + +static void store_helper(CPUArchState *env, target_ulong addr, uint64_t val, + TCGMemOpIdx oi, uintptr_t retaddr, size_t size, + bool big_endian) +{ + uintptr_t mmu_idx = get_mmuidx(oi); + uintptr_t index = tlb_index(env, mmu_idx, addr); + CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr); + target_ulong tlb_addr = tlb_addr_write(entry); + const size_t tlb_off = offsetof(CPUTLBEntry, addr_write); + unsigned a_bits = get_alignment_bits(get_memop(oi)); + void *haddr; + + /* Handle CPU specific unaligned behaviour */ + if (addr & ((1 << a_bits) - 1)) { + cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE, + mmu_idx, retaddr); + } + + /* If the TLB entry is for a different page, reload and try again. */ + if (!tlb_hit(tlb_addr, addr)) { + if (!victim_tlb_hit(env, mmu_idx, index, tlb_off, + addr & TARGET_PAGE_MASK)) { + tlb_fill(ENV_GET_CPU(env), addr, size, MMU_DATA_STORE, + mmu_idx, retaddr); + index = tlb_index(env, mmu_idx, addr); + entry = tlb_entry(env, mmu_idx, addr); + } + tlb_addr = tlb_addr_write(entry) & ~TLB_INVALID_MASK; + } + + /* Handle an IO access. */ + if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { + CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index]; + + if ((addr & (size - 1)) != 0) { + goto do_unaligned_access; + } + + io_writex(env, iotlbentry, mmu_idx, + handle_bswap(val, size, big_endian), + addr, retaddr, tlb_addr & TLB_RECHECK, size); + return; + } + + /* Handle slow unaligned access (it spans two pages or IO). */ + if (size > 1 + && unlikely((addr & ~TARGET_PAGE_MASK) + size - 1 + >= TARGET_PAGE_SIZE)) { + int i; + uintptr_t index2; + CPUTLBEntry *entry2; + target_ulong page2, tlb_addr2; + do_unaligned_access: + /* + * Ensure the second page is in the TLB. Note that the first page + * is already guaranteed to be filled, and that the second page + * cannot evict the first. + */ + page2 = (addr + size) & TARGET_PAGE_MASK; + index2 = tlb_index(env, mmu_idx, page2); + entry2 = tlb_entry(env, mmu_idx, page2); + tlb_addr2 = tlb_addr_write(entry2); + if (!tlb_hit_page(tlb_addr2, page2) + && !victim_tlb_hit(env, mmu_idx, index2, tlb_off, + page2 & TARGET_PAGE_MASK)) { + tlb_fill(ENV_GET_CPU(env), page2, size, MMU_DATA_STORE, + mmu_idx, retaddr); + } + + /* + * XXX: not efficient, but simple. + * This loop must go in the forward direction to avoid issues + * with self-modifying code in Windows 64-bit. + */ + for (i = 0; i < size; ++i) { + uint8_t val8; + if (big_endian) { + /* Big-endian extract. */ + val8 = val >> (((size - 1) * 8) - (i * 8)); + } else { + /* Little-endian extract. */ + val8 = val >> (i * 8); + } + store_helper(env, addr + i, val8, oi, retaddr, 1, big_endian); + } + return; + } + + haddr = (void *)((uintptr_t)addr + entry->addend); + + switch (size) { + case 1: + stb_p(haddr, val); + break; + case 2: + if (big_endian) { + stw_be_p(haddr, val); + } else { + stw_le_p(haddr, val); + } + break; + case 4: + if (big_endian) { + stl_be_p(haddr, val); + } else { + stl_le_p(haddr, val); + } + break; + case 8: + if (big_endian) { + stq_be_p(haddr, val); + } else { + stq_le_p(haddr, val); + } + break; + default: + g_assert_not_reached(); + break; + } +} + +void __attribute__((flatten)) +helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + store_helper(env, addr, val, oi, retaddr, 1, false); +} + +void __attribute__((flatten)) +helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + store_helper(env, addr, val, oi, retaddr, 2, false); +} + +void __attribute__((flatten)) +helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + store_helper(env, addr, val, oi, retaddr, 2, true); +} + +void __attribute__((flatten)) +helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + store_helper(env, addr, val, oi, retaddr, 4, false); +} + +void __attribute__((flatten)) +helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + store_helper(env, addr, val, oi, retaddr, 4, true); +} + +void __attribute__((flatten)) +helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + store_helper(env, addr, val, oi, retaddr, 8, false); +} + +void __attribute__((flatten)) +helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + store_helper(env, addr, val, oi, retaddr, 8, true); +} /* First set of helpers allows passing in of OI and RETADDR. This makes them callable from other helpers. */ @@ -1248,20 +1643,51 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, /* Code access functions. */ -#undef MMUSUFFIX -#define MMUSUFFIX _cmmu -#undef GETPC -#define GETPC() ((uintptr_t)0) -#define SOFTMMU_CODE_ACCESS +uint8_t __attribute__((flatten)) +helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 1, false, true); +} -#define DATA_SIZE 1 -#include "softmmu_template.h" +uint16_t __attribute__((flatten)) +helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 2, false, true); +} -#define DATA_SIZE 2 -#include "softmmu_template.h" +uint16_t __attribute__((flatten)) +helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 2, true, true); +} -#define DATA_SIZE 4 -#include "softmmu_template.h" +uint32_t __attribute__((flatten)) +helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 4, false, true); +} -#define DATA_SIZE 8 -#include "softmmu_template.h" +uint32_t __attribute__((flatten)) +helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 4, true, true); +} + +uint64_t __attribute__((flatten)) +helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 8, false, true); +} + +uint64_t __attribute__((flatten)) +helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 8, true, true); +} From patchwork Tue Apr 30 16:52:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 163141 Delivered-To: patch@linaro.org Received: by 2002:a92:7e86:0:0:0:0:0 with SMTP id q6csp3487324ill; Tue, 30 Apr 2019 10:05:44 -0700 (PDT) X-Google-Smtp-Source: APXvYqyznqv7Ja/noTbrTQ/rRr6ShuABsxRURpi8sdGfgHz0Ml3Qm6h5UV2KX7C1ozxKC7D80L4N X-Received: by 2002:adf:e9c2:: with SMTP id l2mr10649761wrn.116.1556643944753; Tue, 30 Apr 2019 10:05:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556643944; cv=none; d=google.com; s=arc-20160816; b=F1xoroA6PdmiLM14w2/+a6ilM9eLUAgBm2h8BeD240gs3/4B8Rb81sP8dkFFSxsvb1 w8S+FTqOA1YpyNiGaRO2knICr0toq0FaDS0mwF0N2ofIcejE2y/DqyJX6rHBUq38t5Bq zKhoRKeMASummuKuqe/X0P+TY+tY7mvlAszp03cR+4wvCa6CxRtFR62dCdMkKqXJyogr KHFcYd2C+EC3riv3ocUT6fPNf+cDphJoPJ1Rb4jPA0TBKidJVtZ1yKD4CDcvquwNFffE oqOFVis6NUMEMgPy7svbXQ9e7Pzq6uaCwPNRPMsCkdajdbjfckVli8ruamSu180Q2So8 0MzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=GOofkeCu83ckHUz9cHZWU7kbKyGza94dcNFhXd5mzrA=; b=sI74rIVlfZWRttviJyAUjzuF4QvJTIaPYMfeJ3/5fJRg+r0DdmbH7jPD6gVJq7UfAr JVJxW4TsvX4J8r5bpxrBmbc7/hlvl8M2mA7Fn8tM57Enb3YOnoQ2QOdZp9g/ORiwlIIn ubx+u8M+BxjeCeVv7stzFXE+2jVBfos5OG10tA1pbL8opQET26rTeYI713qj4c5DykyF ZrhuvqNF3m81Dn3fMEujGOpCgB7eGL8FjJFmn+ZdyqPp2k2AGDXZq2KYIr6G9ySNZTWa rwNQYLfRbCX94+O+yvfAnRhQKC7Z/eARypx8PzvLADJGwHq6Y+VlSo/bJaorOuUTVRmi qxqA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fW7Su2rO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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(localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id E07C21FF98; Tue, 30 Apr 2019 17:52:34 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Tue, 30 Apr 2019 17:52:27 +0100 Message-Id: <20190430165234.32272-9-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190430165234.32272-1-alex.bennee@linaro.org> References: <20190430165234.32272-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH v5 08/15] cputlb: Move TLB_RECHECK handling into load/store_helper X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , qemu-arm@nongnu.org, mark.cave-ayland@ilande.co.uk, cota@braap.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Having this in io_readx/io_writex meant that we forgot to re-compute index after tlb_fill. It also means we can use the normal aligned memory load path. It also fixes a bug in that we had cached a use of index across a tlb_fill. Signed-off-by: Richard Henderson Signed-off-by: Alex Bennée --- accel/tcg/cputlb.c | 126 ++++++++++++++++++++------------------------- 1 file changed, 55 insertions(+), 71 deletions(-) -- 2.20.1 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 12f21865ee..9c04eb1687 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -856,9 +856,8 @@ static inline ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr) } static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, - int mmu_idx, - target_ulong addr, uintptr_t retaddr, - bool recheck, MMUAccessType access_type, int size) + int mmu_idx, target_ulong addr, uintptr_t retaddr, + MMUAccessType access_type, int size) { CPUState *cpu = ENV_GET_CPU(env); hwaddr mr_offset; @@ -868,30 +867,6 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, bool locked = false; MemTxResult r; - if (recheck) { - /* - * This is a TLB_RECHECK access, where the MMU protection - * covers a smaller range than a target page, and we must - * repeat the MMU check here. This tlb_fill() call might - * longjump out if this access should cause a guest exception. - */ - CPUTLBEntry *entry; - target_ulong tlb_addr; - - tlb_fill(cpu, addr, size, access_type, mmu_idx, retaddr); - - entry = tlb_entry(env, mmu_idx, addr); - tlb_addr = (access_type == MMU_DATA_LOAD ? - entry->addr_read : entry->addr_code); - if (!(tlb_addr & ~(TARGET_PAGE_MASK | TLB_RECHECK))) { - /* RAM access */ - uintptr_t haddr = addr + entry->addend; - - return ldn_p((void *)haddr, size); - } - /* Fall through for handling IO accesses */ - } - section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); mr = section->mr; mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr; @@ -925,9 +900,8 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, } static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, - int mmu_idx, - uint64_t val, target_ulong addr, - uintptr_t retaddr, bool recheck, int size) + int mmu_idx, uint64_t val, target_ulong addr, + uintptr_t retaddr, int size) { CPUState *cpu = ENV_GET_CPU(env); hwaddr mr_offset; @@ -936,30 +910,6 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, bool locked = false; MemTxResult r; - if (recheck) { - /* - * This is a TLB_RECHECK access, where the MMU protection - * covers a smaller range than a target page, and we must - * repeat the MMU check here. This tlb_fill() call might - * longjump out if this access should cause a guest exception. - */ - CPUTLBEntry *entry; - target_ulong tlb_addr; - - tlb_fill(cpu, addr, size, MMU_DATA_STORE, mmu_idx, retaddr); - - entry = tlb_entry(env, mmu_idx, addr); - tlb_addr = tlb_addr_write(entry); - if (!(tlb_addr & ~(TARGET_PAGE_MASK | TLB_RECHECK))) { - /* RAM access */ - uintptr_t haddr = addr + entry->addend; - - stn_p((void *)haddr, size, val); - return; - } - /* Fall through for handling IO accesses */ - } - section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); mr = section->mr; mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr; @@ -1218,14 +1168,15 @@ static uint64_t load_helper(CPUArchState *env, target_ulong addr, target_ulong tlb_addr = code_read ? entry->addr_code : entry->addr_read; const size_t tlb_off = code_read ? offsetof(CPUTLBEntry, addr_code) : offsetof(CPUTLBEntry, addr_read); + const MMUAccessType access_type = + code_read ? MMU_INST_FETCH : MMU_DATA_LOAD; unsigned a_bits = get_alignment_bits(get_memop(oi)); void *haddr; uint64_t res; /* Handle CPU specific unaligned behaviour */ if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(ENV_GET_CPU(env), addr, - code_read ? MMU_INST_FETCH : MMU_DATA_LOAD, + cpu_unaligned_access(ENV_GET_CPU(env), addr, access_type, mmu_idx, retaddr); } @@ -1234,8 +1185,7 @@ static uint64_t load_helper(CPUArchState *env, target_ulong addr, if (!victim_tlb_hit(env, mmu_idx, index, tlb_off, addr & TARGET_PAGE_MASK)) { tlb_fill(ENV_GET_CPU(env), addr, size, - code_read ? MMU_INST_FETCH : MMU_DATA_LOAD, - mmu_idx, retaddr); + access_type, mmu_idx, retaddr); index = tlb_index(env, mmu_idx, addr); entry = tlb_entry(env, mmu_idx, addr); } @@ -1244,17 +1194,33 @@ static uint64_t load_helper(CPUArchState *env, target_ulong addr, /* Handle an IO access. */ if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index]; - uint64_t tmp; - if ((addr & (size - 1)) != 0) { goto do_unaligned_access; } - tmp = io_readx(env, iotlbentry, mmu_idx, addr, retaddr, - tlb_addr & TLB_RECHECK, - code_read ? MMU_INST_FETCH : MMU_DATA_LOAD, size); - return handle_bswap(tmp, size, big_endian); + if (tlb_addr & TLB_RECHECK) { + /* + * This is a TLB_RECHECK access, where the MMU protection + * covers a smaller range than a target page, and we must + * repeat the MMU check here. This tlb_fill() call might + * longjump out if this access should cause a guest exception. + */ + tlb_fill(ENV_GET_CPU(env), addr, size, + access_type, mmu_idx, retaddr); + index = tlb_index(env, mmu_idx, addr); + entry = tlb_entry(env, mmu_idx, addr); + + tlb_addr = code_read ? entry->addr_code : entry->addr_read; + tlb_addr &= ~TLB_RECHECK; + if (!(tlb_addr & ~TARGET_PAGE_MASK)) { + /* RAM access */ + goto do_aligned_access; + } + } + + res = io_readx(env, &env->iotlb[mmu_idx][index], mmu_idx, addr, + retaddr, access_type, size); + return handle_bswap(res, size, big_endian); } /* Handle slow unaligned access (it spans two pages or IO). */ @@ -1281,8 +1247,8 @@ static uint64_t load_helper(CPUArchState *env, target_ulong addr, return res & MAKE_64BIT_MASK(0, size * 8); } + do_aligned_access: haddr = (void *)((uintptr_t)addr + entry->addend); - switch (size) { case 1: res = ldub_p(haddr); @@ -1446,15 +1412,33 @@ static void store_helper(CPUArchState *env, target_ulong addr, uint64_t val, /* Handle an IO access. */ if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index]; - if ((addr & (size - 1)) != 0) { goto do_unaligned_access; } - io_writex(env, iotlbentry, mmu_idx, + if (tlb_addr & TLB_RECHECK) { + /* + * This is a TLB_RECHECK access, where the MMU protection + * covers a smaller range than a target page, and we must + * repeat the MMU check here. This tlb_fill() call might + * longjump out if this access should cause a guest exception. + */ + tlb_fill(ENV_GET_CPU(env), addr, size, MMU_DATA_STORE, + mmu_idx, retaddr); + index = tlb_index(env, mmu_idx, addr); + entry = tlb_entry(env, mmu_idx, addr); + + tlb_addr = tlb_addr_write(entry); + tlb_addr &= ~TLB_RECHECK; + if (!(tlb_addr & ~TARGET_PAGE_MASK)) { + /* RAM access */ + goto do_aligned_access; + } + } + + io_writex(env, &env->iotlb[mmu_idx][index], mmu_idx, handle_bswap(val, size, big_endian), - addr, retaddr, tlb_addr & TLB_RECHECK, size); + addr, retaddr, size); return; } @@ -1502,8 +1486,8 @@ static void store_helper(CPUArchState *env, target_ulong addr, uint64_t val, return; } + do_aligned_access: haddr = (void *)((uintptr_t)addr + entry->addend); - switch (size) { case 1: stb_p(haddr, val); From patchwork Tue Apr 30 16:52:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 163135 Delivered-To: patch@linaro.org Received: by 2002:a92:7e86:0:0:0:0:0 with SMTP id q6csp3486354ill; Tue, 30 Apr 2019 10:05:00 -0700 (PDT) X-Google-Smtp-Source: APXvYqwjAe+Ai8ErmjYJnSibBSWohtPPLIETbX9tcY8JMEHYmg/xe1NophGEoLrDSEy8FCaV5n0m X-Received: by 2002:a1c:4d1a:: with SMTP id o26mr3494018wmh.133.1556643900633; Tue, 30 Apr 2019 10:05:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556643900; cv=none; d=google.com; s=arc-20160816; b=L+soJU9tz4Yy69yZcvcU+8TGDjwBqYzSo8fsCxjPReIk8IWwamPoLnAYGslxKXZp8x 4K9k2IEFd0vmaEz8bDbxxJuTrVCRWzIrxrUdThiwf+8LKijGspPpf/6otFXIwLX6QCF3 8W/lMhnO05XEYdrGfK+dnHKqK8s80UPS6iSH/cuVvQ2FOKNRBuG6hR64y5LqWrF0Rfo7 VK7MMZJ1OfZjXPgAVXuN6KwcAxrilWQPozALzcBq1BLR3z/bKL3PApw76/4EljgamtDn jHDMQIW4LDeCb2UoLqOzjL1vJyl8WtvnoCwUgSzNiEOS4TNcPJHvkeZ8yT9DTJnzowNp Mn+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=I2WWTWSrfKtkbYm70GW7LAsIG/jwfqxPsVSlM/O0Py4=; b=QlEUVbVSVJZsyR4umXqBkvTk7hbLGj9hqyq0dhe+gksF86C/ISLFm9WFmQsgyJzQF/ 75JA2xTRadtMn0qZxiKJkWtgZSZwwtiraRsxa30BBEyxVcFVpmZUW9q2zYlHwLsfvE8A BK2rdYvDyVfZ3UoHS3ocwfqosZ31s0TSbw71XKvme1YzLwF1RDK/Mzpndxu8hyfKd6Ed cb9IxbMfo7+83M5+3UD7If1ChHnD3AEypFC5vJQF27qusRV1WLZZpWeROkQkzzd3pP0r UTwK6r4AduRv3q7qo+Cvm3jqYySyHSSNnT70KkmB+cLl/QB+Gz62qbP2A/p6pxYSqHbt pTGA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=HtdWiDwL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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(localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id EC3D21FF99; Tue, 30 Apr 2019 17:52:34 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Tue, 30 Apr 2019 17:52:28 +0100 Message-Id: <20190430165234.32272-10-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190430165234.32272-1-alex.bennee@linaro.org> References: <20190430165234.32272-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH v5 09/15] accel/tcg: remove softmmu_template.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, mark.cave-ayland@ilande.co.uk, cota@braap.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée --- accel/tcg/softmmu_template.h | 454 ----------------------------------- 1 file changed, 454 deletions(-) delete mode 100644 accel/tcg/softmmu_template.h -- 2.20.1 diff --git a/accel/tcg/softmmu_template.h b/accel/tcg/softmmu_template.h deleted file mode 100644 index e970a8b378..0000000000 --- a/accel/tcg/softmmu_template.h +++ /dev/null @@ -1,454 +0,0 @@ -/* - * Software MMU support - * - * Generate helpers used by TCG for qemu_ld/st ops and code load - * functions. - * - * Included from target op helpers and exec.c. - * - * Copyright (c) 2003 Fabrice Bellard - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ -#if DATA_SIZE == 8 -#define SUFFIX q -#define LSUFFIX q -#define SDATA_TYPE int64_t -#define DATA_TYPE uint64_t -#elif DATA_SIZE == 4 -#define SUFFIX l -#define LSUFFIX l -#define SDATA_TYPE int32_t -#define DATA_TYPE uint32_t -#elif DATA_SIZE == 2 -#define SUFFIX w -#define LSUFFIX uw -#define SDATA_TYPE int16_t -#define DATA_TYPE uint16_t -#elif DATA_SIZE == 1 -#define SUFFIX b -#define LSUFFIX ub -#define SDATA_TYPE int8_t -#define DATA_TYPE uint8_t -#else -#error unsupported data size -#endif - - -/* For the benefit of TCG generated code, we want to avoid the complication - of ABI-specific return type promotion and always return a value extended - to the register size of the host. This is tcg_target_long, except in the - case of a 32-bit host and 64-bit data, and for that we always have - uint64_t. Don't bother with this widened value for SOFTMMU_CODE_ACCESS. */ -#if defined(SOFTMMU_CODE_ACCESS) || DATA_SIZE == 8 -# define WORD_TYPE DATA_TYPE -# define USUFFIX SUFFIX -#else -# define WORD_TYPE tcg_target_ulong -# define USUFFIX glue(u, SUFFIX) -# define SSUFFIX glue(s, SUFFIX) -#endif - -#ifdef SOFTMMU_CODE_ACCESS -#define READ_ACCESS_TYPE MMU_INST_FETCH -#define ADDR_READ addr_code -#else -#define READ_ACCESS_TYPE MMU_DATA_LOAD -#define ADDR_READ addr_read -#endif - -#if DATA_SIZE == 8 -# define BSWAP(X) bswap64(X) -#elif DATA_SIZE == 4 -# define BSWAP(X) bswap32(X) -#elif DATA_SIZE == 2 -# define BSWAP(X) bswap16(X) -#else -# define BSWAP(X) (X) -#endif - -#if DATA_SIZE == 1 -# define helper_le_ld_name glue(glue(helper_ret_ld, USUFFIX), MMUSUFFIX) -# define helper_be_ld_name helper_le_ld_name -# define helper_le_lds_name glue(glue(helper_ret_ld, SSUFFIX), MMUSUFFIX) -# define helper_be_lds_name helper_le_lds_name -# define helper_le_st_name glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX) -# define helper_be_st_name helper_le_st_name -#else -# define helper_le_ld_name glue(glue(helper_le_ld, USUFFIX), MMUSUFFIX) -# define helper_be_ld_name glue(glue(helper_be_ld, USUFFIX), MMUSUFFIX) -# define helper_le_lds_name glue(glue(helper_le_ld, SSUFFIX), MMUSUFFIX) -# define helper_be_lds_name glue(glue(helper_be_ld, SSUFFIX), MMUSUFFIX) -# define helper_le_st_name glue(glue(helper_le_st, SUFFIX), MMUSUFFIX) -# define helper_be_st_name glue(glue(helper_be_st, SUFFIX), MMUSUFFIX) -#endif - -#ifndef SOFTMMU_CODE_ACCESS -static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env, - size_t mmu_idx, size_t index, - target_ulong addr, - uintptr_t retaddr, - bool recheck, - MMUAccessType access_type) -{ - CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index]; - return io_readx(env, iotlbentry, mmu_idx, addr, retaddr, recheck, - access_type, DATA_SIZE); -} -#endif - -WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) -{ - uintptr_t mmu_idx = get_mmuidx(oi); - uintptr_t index = tlb_index(env, mmu_idx, addr); - CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr); - target_ulong tlb_addr = entry->ADDR_READ; - unsigned a_bits = get_alignment_bits(get_memop(oi)); - uintptr_t haddr; - DATA_TYPE res; - - if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE, - mmu_idx, retaddr); - } - - /* If the TLB entry is for a different page, reload and try again. */ - if (!tlb_hit(tlb_addr, addr)) { - if (!VICTIM_TLB_HIT(ADDR_READ, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, READ_ACCESS_TYPE, - mmu_idx, retaddr); - index = tlb_index(env, mmu_idx, addr); - entry = tlb_entry(env, mmu_idx, addr); - } - tlb_addr = entry->ADDR_READ; - } - - /* Handle an IO access. */ - if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - if ((addr & (DATA_SIZE - 1)) != 0) { - goto do_unaligned_access; - } - - /* ??? Note that the io helpers always read data in the target - byte ordering. We should push the LE/BE request down into io. */ - res = glue(io_read, SUFFIX)(env, mmu_idx, index, addr, retaddr, - tlb_addr & TLB_RECHECK, - READ_ACCESS_TYPE); - res = TGT_LE(res); - return res; - } - - /* Handle slow unaligned access (it spans two pages or IO). */ - if (DATA_SIZE > 1 - && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1 - >= TARGET_PAGE_SIZE)) { - target_ulong addr1, addr2; - DATA_TYPE res1, res2; - unsigned shift; - do_unaligned_access: - addr1 = addr & ~(DATA_SIZE - 1); - addr2 = addr1 + DATA_SIZE; - res1 = helper_le_ld_name(env, addr1, oi, retaddr); - res2 = helper_le_ld_name(env, addr2, oi, retaddr); - shift = (addr & (DATA_SIZE - 1)) * 8; - - /* Little-endian combine. */ - res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift)); - return res; - } - - haddr = addr + entry->addend; -#if DATA_SIZE == 1 - res = glue(glue(ld, LSUFFIX), _p)((uint8_t *)haddr); -#else - res = glue(glue(ld, LSUFFIX), _le_p)((uint8_t *)haddr); -#endif - return res; -} - -#if DATA_SIZE > 1 -WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) -{ - uintptr_t mmu_idx = get_mmuidx(oi); - uintptr_t index = tlb_index(env, mmu_idx, addr); - CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr); - target_ulong tlb_addr = entry->ADDR_READ; - unsigned a_bits = get_alignment_bits(get_memop(oi)); - uintptr_t haddr; - DATA_TYPE res; - - if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE, - mmu_idx, retaddr); - } - - /* If the TLB entry is for a different page, reload and try again. */ - if (!tlb_hit(tlb_addr, addr)) { - if (!VICTIM_TLB_HIT(ADDR_READ, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, READ_ACCESS_TYPE, - mmu_idx, retaddr); - index = tlb_index(env, mmu_idx, addr); - entry = tlb_entry(env, mmu_idx, addr); - } - tlb_addr = entry->ADDR_READ; - } - - /* Handle an IO access. */ - if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - if ((addr & (DATA_SIZE - 1)) != 0) { - goto do_unaligned_access; - } - - /* ??? Note that the io helpers always read data in the target - byte ordering. We should push the LE/BE request down into io. */ - res = glue(io_read, SUFFIX)(env, mmu_idx, index, addr, retaddr, - tlb_addr & TLB_RECHECK, - READ_ACCESS_TYPE); - res = TGT_BE(res); - return res; - } - - /* Handle slow unaligned access (it spans two pages or IO). */ - if (DATA_SIZE > 1 - && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1 - >= TARGET_PAGE_SIZE)) { - target_ulong addr1, addr2; - DATA_TYPE res1, res2; - unsigned shift; - do_unaligned_access: - addr1 = addr & ~(DATA_SIZE - 1); - addr2 = addr1 + DATA_SIZE; - res1 = helper_be_ld_name(env, addr1, oi, retaddr); - res2 = helper_be_ld_name(env, addr2, oi, retaddr); - shift = (addr & (DATA_SIZE - 1)) * 8; - - /* Big-endian combine. */ - res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift)); - return res; - } - - haddr = addr + entry->addend; - res = glue(glue(ld, LSUFFIX), _be_p)((uint8_t *)haddr); - return res; -} -#endif /* DATA_SIZE > 1 */ - -#ifndef SOFTMMU_CODE_ACCESS - -/* Provide signed versions of the load routines as well. We can of course - avoid this for 64-bit data, or for 32-bit data on 32-bit host. */ -#if DATA_SIZE * 8 < TCG_TARGET_REG_BITS -WORD_TYPE helper_le_lds_name(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) -{ - return (SDATA_TYPE)helper_le_ld_name(env, addr, oi, retaddr); -} - -# if DATA_SIZE > 1 -WORD_TYPE helper_be_lds_name(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) -{ - return (SDATA_TYPE)helper_be_ld_name(env, addr, oi, retaddr); -} -# endif -#endif - -static inline void glue(io_write, SUFFIX)(CPUArchState *env, - size_t mmu_idx, size_t index, - DATA_TYPE val, - target_ulong addr, - uintptr_t retaddr, - bool recheck) -{ - CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index]; - return io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr, - recheck, DATA_SIZE); -} - -void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, - TCGMemOpIdx oi, uintptr_t retaddr) -{ - uintptr_t mmu_idx = get_mmuidx(oi); - uintptr_t index = tlb_index(env, mmu_idx, addr); - CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr); - target_ulong tlb_addr = tlb_addr_write(entry); - unsigned a_bits = get_alignment_bits(get_memop(oi)); - uintptr_t haddr; - - if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE, - mmu_idx, retaddr); - } - - /* If the TLB entry is for a different page, reload and try again. */ - if (!tlb_hit(tlb_addr, addr)) { - if (!VICTIM_TLB_HIT(addr_write, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, MMU_DATA_STORE, - mmu_idx, retaddr); - index = tlb_index(env, mmu_idx, addr); - entry = tlb_entry(env, mmu_idx, addr); - } - tlb_addr = tlb_addr_write(entry) & ~TLB_INVALID_MASK; - } - - /* Handle an IO access. */ - if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - if ((addr & (DATA_SIZE - 1)) != 0) { - goto do_unaligned_access; - } - - /* ??? Note that the io helpers always read data in the target - byte ordering. We should push the LE/BE request down into io. */ - val = TGT_LE(val); - glue(io_write, SUFFIX)(env, mmu_idx, index, val, addr, - retaddr, tlb_addr & TLB_RECHECK); - return; - } - - /* Handle slow unaligned access (it spans two pages or IO). */ - if (DATA_SIZE > 1 - && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1 - >= TARGET_PAGE_SIZE)) { - int i; - target_ulong page2; - CPUTLBEntry *entry2; - do_unaligned_access: - /* Ensure the second page is in the TLB. Note that the first page - is already guaranteed to be filled, and that the second page - cannot evict the first. */ - page2 = (addr + DATA_SIZE) & TARGET_PAGE_MASK; - entry2 = tlb_entry(env, mmu_idx, page2); - if (!tlb_hit_page(tlb_addr_write(entry2), page2) - && !VICTIM_TLB_HIT(addr_write, page2)) { - tlb_fill(ENV_GET_CPU(env), page2, DATA_SIZE, MMU_DATA_STORE, - mmu_idx, retaddr); - } - - /* XXX: not efficient, but simple. */ - /* This loop must go in the forward direction to avoid issues - with self-modifying code in Windows 64-bit. */ - for (i = 0; i < DATA_SIZE; ++i) { - /* Little-endian extract. */ - uint8_t val8 = val >> (i * 8); - glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8, - oi, retaddr); - } - return; - } - - haddr = addr + entry->addend; -#if DATA_SIZE == 1 - glue(glue(st, SUFFIX), _p)((uint8_t *)haddr, val); -#else - glue(glue(st, SUFFIX), _le_p)((uint8_t *)haddr, val); -#endif -} - -#if DATA_SIZE > 1 -void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, - TCGMemOpIdx oi, uintptr_t retaddr) -{ - uintptr_t mmu_idx = get_mmuidx(oi); - uintptr_t index = tlb_index(env, mmu_idx, addr); - CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr); - target_ulong tlb_addr = tlb_addr_write(entry); - unsigned a_bits = get_alignment_bits(get_memop(oi)); - uintptr_t haddr; - - if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE, - mmu_idx, retaddr); - } - - /* If the TLB entry is for a different page, reload and try again. */ - if (!tlb_hit(tlb_addr, addr)) { - if (!VICTIM_TLB_HIT(addr_write, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, MMU_DATA_STORE, - mmu_idx, retaddr); - index = tlb_index(env, mmu_idx, addr); - entry = tlb_entry(env, mmu_idx, addr); - } - tlb_addr = tlb_addr_write(entry) & ~TLB_INVALID_MASK; - } - - /* Handle an IO access. */ - if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - if ((addr & (DATA_SIZE - 1)) != 0) { - goto do_unaligned_access; - } - - /* ??? Note that the io helpers always read data in the target - byte ordering. We should push the LE/BE request down into io. */ - val = TGT_BE(val); - glue(io_write, SUFFIX)(env, mmu_idx, index, val, addr, retaddr, - tlb_addr & TLB_RECHECK); - return; - } - - /* Handle slow unaligned access (it spans two pages or IO). */ - if (DATA_SIZE > 1 - && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1 - >= TARGET_PAGE_SIZE)) { - int i; - target_ulong page2; - CPUTLBEntry *entry2; - do_unaligned_access: - /* Ensure the second page is in the TLB. Note that the first page - is already guaranteed to be filled, and that the second page - cannot evict the first. */ - page2 = (addr + DATA_SIZE) & TARGET_PAGE_MASK; - entry2 = tlb_entry(env, mmu_idx, page2); - if (!tlb_hit_page(tlb_addr_write(entry2), page2) - && !VICTIM_TLB_HIT(addr_write, page2)) { - tlb_fill(ENV_GET_CPU(env), page2, DATA_SIZE, MMU_DATA_STORE, - mmu_idx, retaddr); - } - - /* XXX: not efficient, but simple */ - /* This loop must go in the forward direction to avoid issues - with self-modifying code. */ - for (i = 0; i < DATA_SIZE; ++i) { - /* Big-endian extract. */ - uint8_t val8 = val >> (((DATA_SIZE - 1) * 8) - (i * 8)); - glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8, - oi, retaddr); - } - return; - } - - haddr = addr + entry->addend; - glue(glue(st, SUFFIX), _be_p)((uint8_t *)haddr, val); -} -#endif /* DATA_SIZE > 1 */ -#endif /* !defined(SOFTMMU_CODE_ACCESS) */ - -#undef READ_ACCESS_TYPE -#undef DATA_TYPE -#undef SUFFIX -#undef LSUFFIX -#undef DATA_SIZE -#undef ADDR_READ -#undef WORD_TYPE -#undef SDATA_TYPE -#undef USUFFIX -#undef SSUFFIX -#undef BSWAP -#undef helper_le_ld_name -#undef helper_be_ld_name -#undef helper_le_lds_name -#undef helper_be_lds_name -#undef helper_le_st_name -#undef helper_be_st_name From patchwork Tue Apr 30 16:52:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 163145 Delivered-To: patch@linaro.org Received: by 2002:a92:7e86:0:0:0:0:0 with SMTP id q6csp3490648ill; Tue, 30 Apr 2019 10:08:21 -0700 (PDT) X-Google-Smtp-Source: APXvYqxtwNsH8bAg77UYiNAfEW+ucKQS2z7l0BqWxPyfTUfxdMKgezD53LABxKE0epN0BT6yDXfD X-Received: by 2002:adf:f64f:: with SMTP id x15mr25267817wrp.202.1556644101611; Tue, 30 Apr 2019 10:08:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556644101; cv=none; d=google.com; s=arc-20160816; b=NoTWA4kB44TGiQ7GgIIgt7Q0lZ3+5n66FFOSTS1v4j9qqVF6fUWAN0MJjlMnm5zvWV PbnzGbrfmNQC8HkJacbQeSWV4QrVZR7XAhHBdBGFeIetmxC3Kpv4xlHUheO+fv0i6uxq t8xm1+o10kGep09NwmxKgDkIU6UeOW//y8zPmRFj8mj/d7DykjcLLIibBa3Nx8I7hwKw yB3EMtGO3j9McPNMd0YWDEGof+Hx9TXslkfvA3MwgWdG7+HT6Fiv9PdqxQBQ96eBk8ok K8lzgIoUizN3PSMZslNoxIjUqcm0N8J+sbcLvv3FdlbE3rrnLEh2GPep78TdPg7NEf+c GKeQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=kdE7tNIM4QnjfnkeRvliaIVYu9qjQMZSsX2l5cVNhzA=; b=uhG4uhnLVNl8SUT3Ab8Sy8fL2NRnBvo6XkfRELbqmaBmk+AinikY+PJMj01lyqxV1k XWa/6Zw0Tjrp4J80TXNgsAgrP/iLkFQRSAD6ee58wW/L4eMMyhDo4gzbjdnraotkztUt AJ1vc/vHhahJifkN0sttq+82lSXu9gs7T4fgSYLPQzxkO1r8iOylk5QShktdAE8hXF5O mwL+K76FCv+RCNTFnocoqzOJg9c1srROGvW+OKB15ege+hpS6gnZsvEc91Ua+1hWXSfw GoljK9Ghu9oDWJ2LQxRlDHTP3FPfrSEseYy6vrK8dqdxp1yOinmC8h/339kwLvhOLeRV OrAA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=MIEKJpeq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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(localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 03BF81FF9A; Tue, 30 Apr 2019 17:52:35 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Tue, 30 Apr 2019 17:52:29 +0100 Message-Id: <20190430165234.32272-11-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190430165234.32272-1-alex.bennee@linaro.org> References: <20190430165234.32272-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32a Subject: [Qemu-devel] [PATCH v5 10/15] cputlb: Drop attribute flatten X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , qemu-arm@nongnu.org, mark.cave-ayland@ilande.co.uk, cota@braap.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Going to approach this problem via __attribute__((always_inline)) instead, but full conversion will take several steps. Signed-off-by: Richard Henderson Signed-off-by: Alex Bennée --- accel/tcg/cputlb.c | 105 ++++++++++++++++++--------------------------- 1 file changed, 42 insertions(+), 63 deletions(-) -- 2.20.1 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 9c04eb1687..ccbb47d8d1 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1291,51 +1291,44 @@ static uint64_t load_helper(CPUArchState *env, target_ulong addr, * We don't bother with this widened value for SOFTMMU_CODE_ACCESS. */ -tcg_target_ulong __attribute__((flatten)) -helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, - uintptr_t retaddr) +tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 1, false, false); } -tcg_target_ulong __attribute__((flatten)) -helper_le_lduw_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, - uintptr_t retaddr) +tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 2, false, false); } -tcg_target_ulong __attribute__((flatten)) -helper_be_lduw_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, - uintptr_t retaddr) +tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 2, true, false); } -tcg_target_ulong __attribute__((flatten)) -helper_le_ldul_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, - uintptr_t retaddr) +tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 4, false, false); } -tcg_target_ulong __attribute__((flatten)) -helper_be_ldul_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, - uintptr_t retaddr) +tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 4, true, false); } -uint64_t __attribute__((flatten)) -helper_le_ldq_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, - uintptr_t retaddr) +uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 8, false, false); } -uint64_t __attribute__((flatten)) -helper_be_ldq_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, - uintptr_t retaddr) +uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 8, true, false); } @@ -1519,51 +1512,44 @@ static void store_helper(CPUArchState *env, target_ulong addr, uint64_t val, } } -void __attribute__((flatten)) -helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, - TCGMemOpIdx oi, uintptr_t retaddr) +void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, + TCGMemOpIdx oi, uintptr_t retaddr) { store_helper(env, addr, val, oi, retaddr, 1, false); } -void __attribute__((flatten)) -helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, - TCGMemOpIdx oi, uintptr_t retaddr) +void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, + TCGMemOpIdx oi, uintptr_t retaddr) { store_helper(env, addr, val, oi, retaddr, 2, false); } -void __attribute__((flatten)) -helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, - TCGMemOpIdx oi, uintptr_t retaddr) +void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, + TCGMemOpIdx oi, uintptr_t retaddr) { store_helper(env, addr, val, oi, retaddr, 2, true); } -void __attribute__((flatten)) -helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, - TCGMemOpIdx oi, uintptr_t retaddr) +void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, + TCGMemOpIdx oi, uintptr_t retaddr) { store_helper(env, addr, val, oi, retaddr, 4, false); } -void __attribute__((flatten)) -helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, - TCGMemOpIdx oi, uintptr_t retaddr) +void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, + TCGMemOpIdx oi, uintptr_t retaddr) { store_helper(env, addr, val, oi, retaddr, 4, true); } -void __attribute__((flatten)) -helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, - TCGMemOpIdx oi, uintptr_t retaddr) +void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, + TCGMemOpIdx oi, uintptr_t retaddr) { store_helper(env, addr, val, oi, retaddr, 8, false); } -void __attribute__((flatten)) -helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, - TCGMemOpIdx oi, uintptr_t retaddr) +void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, + TCGMemOpIdx oi, uintptr_t retaddr) { store_helper(env, addr, val, oi, retaddr, 8, true); } @@ -1627,51 +1613,44 @@ helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, /* Code access functions. */ -uint8_t __attribute__((flatten)) -helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, - uintptr_t retaddr) +uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 1, false, true); } -uint16_t __attribute__((flatten)) -helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, - uintptr_t retaddr) +uint16_t helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 2, false, true); } -uint16_t __attribute__((flatten)) -helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, - uintptr_t retaddr) +uint16_t helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 2, true, true); } -uint32_t __attribute__((flatten)) -helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, - uintptr_t retaddr) +uint32_t helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 4, false, true); } -uint32_t __attribute__((flatten)) -helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, - uintptr_t retaddr) +uint32_t helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 4, true, true); } -uint64_t __attribute__((flatten)) -helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, - uintptr_t retaddr) +uint64_t helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 8, false, true); } -uint64_t __attribute__((flatten)) -helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, - uintptr_t retaddr) +uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 8, true, true); } From patchwork Tue Apr 30 16:52:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 163131 Delivered-To: patch@linaro.org Received: by 2002:a92:7e86:0:0:0:0:0 with SMTP id q6csp3479569ill; Tue, 30 Apr 2019 09:59:42 -0700 (PDT) X-Google-Smtp-Source: APXvYqxljCeyciEwamOACoNG7gFlbcTZf2d499cVj7znSDZoQT/geBYcRcxFFgmfOPrAWJ3EFdnl X-Received: by 2002:a1c:491:: with SMTP id 139mr2741069wme.64.1556643582587; Tue, 30 Apr 2019 09:59:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556643582; cv=none; d=google.com; s=arc-20160816; b=AvPgP80HCAhMLembQfNf9CPFMsDxqEYaPlVt3RsbRgwucsO6nnk/w4iRg24p24Jyzm G+8DxoLcxYMPfhjD+QO/HvqCyU4kt8kU9oOoUUR8j/hnoWpmrfeX9I4d9b71m9/sjsqz fx9zBNrNIkDK0DA2KTSb78Oc8462c4jJL7mplS7GRsYL0NjuExZ/KB0m+v85HTig3ky5 kmunhKKu0SE1M5m1y0+arf+tKm7RsmbCtQ5JtGQEuSGs5f3XAloPg2IOu54/fy8dJk0K Gr0Yw6COYHwgDOOMBRiVZ1+8qxVDiaC3y4/53iYLplxP0QOPU+RrmsRlsA27RIC0d/dy k1ng== ARC-Message-Signature: i=1; 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(localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 0F7DC1FF9B; Tue, 30 Apr 2019 17:52:35 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Tue, 30 Apr 2019 17:52:30 +0100 Message-Id: <20190430165234.32272-12-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190430165234.32272-1-alex.bennee@linaro.org> References: <20190430165234.32272-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH v5 11/15] cputlb: Do unaligned load recursion to outermost function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , qemu-arm@nongnu.org, mark.cave-ayland@ilande.co.uk, cota@braap.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson If we attempt to recurse from load_helper back to load_helper, even via intermediary, we do not get all of the constants expanded away as desired. But if we recurse back to the original helper (or a shim that has a consistent function signature), the operands are folded away as desired. Signed-off-by: Richard Henderson Signed-off-by: Alex Bennée --- accel/tcg/cputlb.c | 117 +++++++++++++++++++++++++++++++++++++-------- 1 file changed, 97 insertions(+), 20 deletions(-) -- 2.20.1 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index ccbb47d8d1..e4d0c94301 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1157,10 +1157,13 @@ static inline uint64_t handle_bswap(uint64_t val, int size, bool big_endian) * is disassembled. It shouldn't be called directly by guest code. */ -static uint64_t load_helper(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr, - size_t size, bool big_endian, - bool code_read) +typedef uint64_t FullLoadHelper(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr); + +static inline uint64_t __attribute__((always_inline)) +load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr, size_t size, bool big_endian, bool code_read, + FullLoadHelper *full_load) { uintptr_t mmu_idx = get_mmuidx(oi); uintptr_t index = tlb_index(env, mmu_idx, addr); @@ -1233,8 +1236,8 @@ static uint64_t load_helper(CPUArchState *env, target_ulong addr, do_unaligned_access: addr1 = addr & ~(size - 1); addr2 = addr1 + size; - r1 = load_helper(env, addr1, oi, retaddr, size, big_endian, code_read); - r2 = load_helper(env, addr2, oi, retaddr, size, big_endian, code_read); + r1 = full_load(env, addr1, oi, retaddr); + r2 = full_load(env, addr2, oi, retaddr); shift = (addr & (size - 1)) * 8; if (big_endian) { @@ -1291,46 +1294,83 @@ static uint64_t load_helper(CPUArchState *env, target_ulong addr, * We don't bother with this widened value for SOFTMMU_CODE_ACCESS. */ +static uint64_t full_ldub_mmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 1, false, false, + full_ldub_mmu); +} + tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 1, false, false); + return full_ldub_mmu(env, addr, oi, retaddr); +} + +static uint64_t full_le_lduw_mmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 2, false, false, + full_le_lduw_mmu); } tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 2, false, false); + return full_le_lduw_mmu(env, addr, oi, retaddr); +} + +static uint64_t full_be_lduw_mmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 2, true, false, + full_be_lduw_mmu); } tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 2, true, false); + return full_be_lduw_mmu(env, addr, oi, retaddr); +} + +static uint64_t full_le_ldul_mmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 4, false, false, + full_le_ldul_mmu); } tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 4, false, false); + return full_le_ldul_mmu(env, addr, oi, retaddr); +} + +static uint64_t full_be_ldul_mmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 4, true, false, + full_be_ldul_mmu); } tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 4, true, false); + return full_be_ldul_mmu(env, addr, oi, retaddr); } uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 8, false, false); + return load_helper(env, addr, oi, retaddr, 8, false, false, + helper_le_ldq_mmu); } uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 8, true, false); + return load_helper(env, addr, oi, retaddr, 8, true, false, + helper_be_ldq_mmu); } /* @@ -1613,44 +1653,81 @@ void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, /* Code access functions. */ +static uint64_t full_ldub_cmmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 1, false, true, + full_ldub_cmmu); +} + uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 1, false, true); + return full_ldub_cmmu(env, addr, oi, retaddr); +} + +static uint64_t full_le_lduw_cmmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 2, false, true, + full_le_lduw_cmmu); } uint16_t helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 2, false, true); + return full_le_lduw_cmmu(env, addr, oi, retaddr); +} + +static uint64_t full_be_lduw_cmmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 2, true, true, + full_be_lduw_cmmu); } uint16_t helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 2, true, true); + return full_be_lduw_cmmu(env, addr, oi, retaddr); +} + +static uint64_t full_le_ldul_cmmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 4, false, true, + full_le_ldul_cmmu); } uint32_t helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 4, false, true); + return full_le_ldul_cmmu(env, addr, oi, retaddr); +} + +static uint64_t full_be_ldul_cmmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 4, true, true, + full_be_ldul_cmmu); } uint32_t helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 4, true, true); + return full_be_ldul_cmmu(env, addr, oi, retaddr); } uint64_t helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 8, false, true); + return load_helper(env, addr, oi, retaddr, 8, false, true, + helper_le_ldq_cmmu); } uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 8, true, true); + return load_helper(env, addr, oi, retaddr, 8, true, true, + helper_be_ldq_cmmu); } From patchwork Tue Apr 30 16:52:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 163150 Delivered-To: patch@linaro.org Received: by 2002:a92:7e86:0:0:0:0:0 with SMTP id q6csp3497629ill; Tue, 30 Apr 2019 10:14:05 -0700 (PDT) X-Google-Smtp-Source: APXvYqw4f6J1YM1IkcfbTHtEsSQ1sa7Q92UUDFV0z+yx7ulCSeTNOVVYRA/2DVtFQUCuFDBti4+L X-Received: by 2002:a5d:4690:: with SMTP id u16mr7897037wrq.198.1556644444963; Tue, 30 Apr 2019 10:14:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556644444; cv=none; d=google.com; s=arc-20160816; b=AP/sTqoT3+GhHEIYi5JpGRD1DG7AYR5EnT42Os9WzNss1O+t4ntcGBzvx4+OaRyXZZ iN4vRss8oLfaVDWiiz37spJ9aaDuDrx+uQDPcyVdLxKk9rlt8A/LsA1pPTdOQ87Kn4Vw QjS8Pr3RZdb0UtbCG018WIkSiAw5GxyCJKNnZ1Sl8O/lXbaDOYdjNPKLf7V9ejPNb1iU 7JyMEOMxTaZzsVFJx7GT9W5ZDZPZ7YPqdJjnx8qCT6yt/aa9jQUC5hvcCrtf46ZcuYEy PbAKwEkFUEEc9mQLFFUS/OAIY6UZgEsq5wpuxIaNgmk/m4NiEoGSvVpxyEqU6m05sJo9 t8zQ== ARC-Message-Signature: i=1; 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(localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 1B1311FF9C; Tue, 30 Apr 2019 17:52:35 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Tue, 30 Apr 2019 17:52:31 +0100 Message-Id: <20190430165234.32272-13-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190430165234.32272-1-alex.bennee@linaro.org> References: <20190430165234.32272-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH v5 12/15] cputlb: Do unaligned store recursion to outermost function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , qemu-arm@nongnu.org, mark.cave-ayland@ilande.co.uk, cota@braap.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson This is less tricky than for loads, because we always fall back to single byte stores to implement unaligned stores. Signed-off-by: Richard Henderson Signed-off-by: Alex Bennée --- accel/tcg/cputlb.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.20.1 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index e4d0c94301..a083324768 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1413,9 +1413,9 @@ tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr, * Store Helpers */ -static void store_helper(CPUArchState *env, target_ulong addr, uint64_t val, - TCGMemOpIdx oi, uintptr_t retaddr, size_t size, - bool big_endian) +static inline void __attribute__((always_inline)) +store_helper(CPUArchState *env, target_ulong addr, uint64_t val, + TCGMemOpIdx oi, uintptr_t retaddr, size_t size, bool big_endian) { uintptr_t mmu_idx = get_mmuidx(oi); uintptr_t index = tlb_index(env, mmu_idx, addr); @@ -1514,7 +1514,7 @@ static void store_helper(CPUArchState *env, target_ulong addr, uint64_t val, /* Little-endian extract. */ val8 = val >> (i * 8); } - store_helper(env, addr + i, val8, oi, retaddr, 1, big_endian); + helper_ret_stb_mmu(env, addr + i, val8, oi, retaddr); } return; } From patchwork Tue Apr 30 16:52:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 163133 Delivered-To: patch@linaro.org Received: by 2002:a92:7e86:0:0:0:0:0 with SMTP id q6csp3481746ill; Tue, 30 Apr 2019 10:01:27 -0700 (PDT) X-Google-Smtp-Source: APXvYqyVVxLb49pfOEFKcTLGBQP4DEZqIv7Q/yYlrgZ9QCLo2IzjQmXLgjPXAghljDmw4bc+B6DJ X-Received: by 2002:adf:ba93:: with SMTP id p19mr16431131wrg.195.1556643687846; Tue, 30 Apr 2019 10:01:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556643687; cv=none; d=google.com; s=arc-20160816; b=Y0XE2bdMex1jlD1SlEKiCGDHlZpO/fbwq20f+4HG+3Sj64gM2FMFyhrKfddK5COpK8 FseUvGGt1IJiyTe1fpEdnFCl5dJws46kq6qzE17/85qnkkdVU1F1Z1wDf6p6lXObgsJz 7KkXBdm8pd0mnawP1KVqK7Q0+X6dFfBGxOIo9jaxvyYwTG3Tx9PyWLr+4icZUxdeBpRz 0iI1xcuYOezmxJvjsKdYHCL0gtEDu0E+ojg4Lfex9oo1rORYveo7Ju7M5Esaz5tL8sN+ 8/mcrTuJOihuVanA43llsSHBl10d7NNlpKg8eP+CvKrc0oNkRze++rG4B8tIl7a4k+MC tuXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=6QQdh13NNxE5UoxkV4nhJZifhNMFpyl1bUv+VGDgceM=; b=vZKSxSLGgx/Z1JSCb42nfscvLGKRPdnRQnNoWhrS74b+p2jEoNlWQ7hTHuUbcv1cyq k0NzAx9zFiNJugqawv3tl/eYn9xN9mVPm2tiz4oY2Cdv3UYAB6tffyR8JgbzFNvxaGd4 n7bJuBMDqQ45JsqmyM2J1JV9ERUnDV3fSK1xW5UWdbh9cDowDlWKQH03IkQhhMd5jypY WT7792r4QEeqLLhyP9TQOS+NjNFHVJEXAzqAKS0/ReqWJYi0sYEyP9CT7RYZ08xvt3Rn YtccDDsOBb0ldsjcxInnQ0XZ16yiriVsRk2XQGM9FXI7mAZeCVaHA+YPPmWQdS0jQrfC CbLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=s7zetSty; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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(localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 26AA41FF9D; Tue, 30 Apr 2019 17:52:35 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Tue, 30 Apr 2019 17:52:32 +0100 Message-Id: <20190430165234.32272-14-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190430165234.32272-1-alex.bennee@linaro.org> References: <20190430165234.32272-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH v5 13/15] Makefile: fix coverage-report reference to BUILD_DIR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, mark.cave-ayland@ilande.co.uk, cota@braap.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Commit 337f2311f actually claimed to do this in the commit log but didn't actually. Oops. Signed-off-by: Alex Bennée --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/Makefile b/Makefile index 626a04d305..45dfe1b585 100644 --- a/Makefile +++ b/Makefile @@ -992,7 +992,7 @@ $(filter %.1 %.7 %.8,$(DOCS)): scripts/texi2pod.pl %/coverage-report.html: @mkdir -p $* $(call quiet-command,\ - gcovr -r $(SRC_PATH) --object-directory $(BUILD_PATH) \ + gcovr -r $(SRC_PATH) --object-directory $(BUILD_DIR) \ -p --html --html-details -o $@, \ "GEN", "coverage-report.html") From patchwork Tue Apr 30 16:52:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 163130 Delivered-To: patch@linaro.org Received: by 2002:a92:7e86:0:0:0:0:0 with SMTP id q6csp3478570ill; Tue, 30 Apr 2019 09:58:40 -0700 (PDT) X-Google-Smtp-Source: APXvYqwOkCPqDq8i15AIvjgyCD5bxsdI47dN9/sb8YswDLuS7Idx6qVEDSmEgtQVozquOnDCj7/o X-Received: by 2002:adf:ec8f:: with SMTP id z15mr522108wrn.61.1556643519965; Tue, 30 Apr 2019 09:58:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556643519; cv=none; d=google.com; s=arc-20160816; b=GhfI+q6wgCY6USj4x1cgs+BrKAPJSN9SVWeOsW3CF+gShHZtGrb1F8Oi7Uxj5Dx4p3 4Vntp2w56qUqBZ4X5O4oIvcB9k82P8XtyLs+RvajE1zpT+UQuwFMGNwi/IdCuP1y0Cd9 rFLY9SyxlWq8W4RYfvQ6t5/9A3nnwp0Zmx2dWNTk1Cf48ElNN9cr3nQ5hNx7SsANKHQJ 2CXu+zA4BATTT4iD8jK42TOq27I09dv7SIg+23L0093OFvIZ8Zo7LJjH/Ppq2vzW8UKw SPhMC63LGOBc7XZ/FhBvU/UHWEB1+FsG4mkMG3hQC7HTFEPFxVsN4DiEIAIPtbg6RVOQ /Qtw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=wZWYsS060hsAv0hcVng0aTY1nyv7SpuxTkdVT9m0hYA=; b=0jJ4R0QxVS8AxYQlJvgb7ydfCO/kOxITM1Fy+5CNw6e/bBXb627qhR4LO3A2xAZahf A7/5Y4Senmkeqe+phwY4KEPSUdkjZ0Su4wIOGSAo1kseiSqbYJtOjCTG7NAmAqFS9e2k wHlsRN08uhYoZBWm/ghP5/7M3vsUIkCLmzG85CLjYOKxCHxnkLaPKIACOTTnwH/Qv8Lq gbC0ZOotRnMf6JRfR7flxf5rBZkIAHaxDz3NbUoxUBvbNxHFf41haOE1tg60JLCpgABa 4q6e1wxC29azlFO8UnFjg0KqkhPem1XNWvXUWcqlaG2TNXvRWtkQeenaNQa6rzNEr4HG zTeQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cJ7JBATh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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(localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 3283F1FF9E; Tue, 30 Apr 2019 17:52:35 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Tue, 30 Apr 2019 17:52:33 +0100 Message-Id: <20190430165234.32272-15-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190430165234.32272-1-alex.bennee@linaro.org> References: <20190430165234.32272-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH v5 14/15] Makefile: include per-target build directories in coverage report X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, mark.cave-ayland@ilande.co.uk, cota@braap.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée --- Makefile | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/Makefile b/Makefile index 45dfe1b585..bb17b0d692 100644 --- a/Makefile +++ b/Makefile @@ -992,7 +992,9 @@ $(filter %.1 %.7 %.8,$(DOCS)): scripts/texi2pod.pl %/coverage-report.html: @mkdir -p $* $(call quiet-command,\ - gcovr -r $(SRC_PATH) --object-directory $(BUILD_DIR) \ + gcovr -r $(SRC_PATH) \ + $(foreach t, $(TARGET_DIRS), --object-directory $(BUILD_DIR)/$(t)) \ + --object-directory $(BUILD_DIR) \ -p --html --html-details -o $@, \ "GEN", "coverage-report.html") From patchwork Tue Apr 30 16:52:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 163132 Delivered-To: patch@linaro.org Received: by 2002:a92:7e86:0:0:0:0:0 with SMTP id q6csp3481459ill; Tue, 30 Apr 2019 10:01:15 -0700 (PDT) X-Google-Smtp-Source: APXvYqzlwlA9YhAlPvOZrnrQe05C9hFE1tqH0Lv4gNhmfDp1hI/RqHIj8LJaJGBDPmmcFdoHQzyZ X-Received: by 2002:a1c:3cc2:: with SMTP id j185mr3960051wma.26.1556643674970; Tue, 30 Apr 2019 10:01:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556643674; cv=none; d=google.com; s=arc-20160816; b=bYhZqff6dXrdu4WxJQ4yOynGkyYQrs3Fv9imB4Zg5QQMTXRY4cvbhp2TDLzjlk3z0s CcJO708BRu0YnpCv8wqN3MZ1SGIx0d+KEO6Jn3wpzST2b7r//ufvdyeihPUYjgzZi7S6 U/2Pjh7QxH9dXpsbfPxgUcS1RY/mIe76AdBSll7GkpN0tGieIGY1m7juw7IQ8TZyOKy+ w2/BiQI2SlXM35VfdV5zWQ6N5ZAQxDuWr6HV4OkDsPlCtbv3QtJoVnq39IKSzPO3Hu0p 5kLJvXnMl//sPLsPpI+ikzbSS0iwPIlWqE7QsbnbPSVdWwNOOgA3M2VWw+2TgupWcu0k LAxA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=RExLEUbU+WhAIZTJBGlgOhgxBRk7o/x1G7uPxMvM+Ao=; b=SaDcRiTqwpwrmhj+PTSZZjhtQkcUeEYEqGzzmeqLkYO+uz7N6KFD1XqdETjTzQcrxV e5oLF42K0eJymJ8MBx/8rJ9UZAFTmTRdjbjnaO9gjLSY4ZrJO8ehwqal2OdPmMX2yaW7 GApA3nnCLPONia18Q2t9jkHCVqtiQP4uvq0Gd5Exc056yBg9/Wot/33iI3jR1SkcfiIY f3Vuaw83k8G7bMtXJUYgAUZS2NLb032vGDfE9dNpgeAi/3DDi9Dbahd4kOQRyonUUMub IYLvSmrNfKef6B4fj43HFMgJcPI9aTeHCg/FQ4RJkt//7Uja71TDP9ll9nEPJgYmiJce bsig== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=aiobEaZV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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(localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 3E2711FF9F; Tue, 30 Apr 2019 17:52:35 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Tue, 30 Apr 2019 17:52:34 +0100 Message-Id: <20190430165234.32272-16-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190430165234.32272-1-alex.bennee@linaro.org> References: <20190430165234.32272-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH v5 15/15] Makefile.target: support per-target coverage reports X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, mark.cave-ayland@ilande.co.uk, cota@braap.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add support for generating a single targets coverage report. Execute: make coverage-report In the target build directory. This coverage report only cares about target specific blobs so only searches the target build subdirectory. Signed-off-by: Alex Bennée --- Makefile.target | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/Makefile.target b/Makefile.target index ae02495951..aa5d9d6ba6 100644 --- a/Makefile.target +++ b/Makefile.target @@ -238,3 +238,19 @@ endif GENERATED_FILES += config-target.h Makefile: $(GENERATED_FILES) + +# Reports/Analysis +# +# The target specific coverage report only cares about target specific +# blobs and not the shared code. +# + +%/coverage-report.html: + @mkdir -p $* + $(call quiet-command,\ + gcovr -r $(SRC_PATH) --object-directory $(CURDIR) \ + -p --html --html-details -o $@, \ + "GEN", "coverage-report.html") + +.PHONY: coverage-report +coverage-report: $(CURDIR)/reports/coverage/coverage-report.html