From patchwork Thu Feb 9 22:38:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 652159 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F569C05027 for ; Thu, 9 Feb 2023 22:38:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230404AbjBIWip (ORCPT ); Thu, 9 Feb 2023 17:38:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41330 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230390AbjBIWig (ORCPT ); Thu, 9 Feb 2023 17:38:36 -0500 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2075.outbound.protection.outlook.com [40.107.223.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 099155A9C5; Thu, 9 Feb 2023 14:38:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=aYtzV/OI2SsXeOATgNxWA3VBDVsnaEAf/pd/ZlmOCAcqxXN+weYdt3Q6GNp1on6Qb1Qpr9YIbawmJ1XdYBggjpu7B+B2SBBa/nlYRvDbgnWMVn3lCEZlCSI5zQxiOsPZ/9gziXpSSpcZWSIJAHXCHycNnHHAiyGWZNzW8kzuc4nyUupT6M6ihL3ThkFiEF490qnWxhLThIYHdqiYigwmjtyelHte2pQzxM077iDO3Gakiu28kaaY3RO1TtF6hhOhvR01U5QBtkx7JNyx3bocUKs7kuJxTQVMcUv8YxbEEUN0+PXmgR1DTYpE10PbvqIYaI8EAJmnVowX8ZR0bLdRTw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=gUb7EiIkTIWL/SydqJnkGCvmei2QBIJ2vw0AMSW8l0M=; b=ntw+1JjfnGZAnXXuAXeZYMjABRhKcILx8o8KtbUa1jBA32WEBz8M9vc+4dNt+/4XtlGrX6UjYg6wbeXAI3EHIl+dpkjjQldkmRQKY/m0dYD9BNC3JGKKz2l7iJW1/8HBSRP/EZYUt8dm8siO5b97Qly5CcVyXM5Kzp23zyN21aMTiYnTEEodRzVmfjuE8yoYntBUuu6jJVi8+kgYNDvFdn/XQJYMKLJfpsTZq+Wp3brrrhhq7rr+cXi4LTDiT+6mSX+9ACHGOIsVy/1IPZh8SY+G0TFoDVv05ImbU2p5jgJrLKqpm+WUA2/RriYtDiw/7oLFQth7Uf/CHmH425Aasg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=semihalf.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=gUb7EiIkTIWL/SydqJnkGCvmei2QBIJ2vw0AMSW8l0M=; b=XDX7zOx7FZR8kr9kqmpmrdX/wFeB9qpA7u03FkaINgfyS44xKW3ubSGr07Ds4JAWV2W6S9dHo8z1g0SBBMR/tBYPt+1VpZEGVCsIwn23fIEPk5lvRSn3UAQeAIJqfEtXNxK0gjolDWeIOm1VCkSTibQSSKtTxuvTwWKZpo/74ak= Received: from DM6PR05CA0037.namprd05.prod.outlook.com (2603:10b6:5:335::6) by IA1PR12MB6233.namprd12.prod.outlook.com (2603:10b6:208:3e7::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6064.34; Thu, 9 Feb 2023 22:38:32 +0000 Received: from DM6NAM11FT109.eop-nam11.prod.protection.outlook.com (2603:10b6:5:335:cafe::57) by DM6PR05CA0037.outlook.office365.com (2603:10b6:5:335::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6111.5 via Frontend Transport; Thu, 9 Feb 2023 22:38:32 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT109.mail.protection.outlook.com (10.13.173.178) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6086.19 via Frontend Transport; Thu, 9 Feb 2023 22:38:32 +0000 Received: from AUS-LX-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Thu, 9 Feb 2023 16:38:30 -0600 From: Mario Limonciello To: =?utf-8?b?SmFuIETEhWJyb8Wb?= , Grzegorz Bernacki , Thomas Rijo-john , "Lendacky Thomas" , , "Sean Christopherson" , Paolo Bonzini , Brijesh Singh , Tom Lendacky , John Allen , Jarkko Nikula , Andy Shevchenko , Mika Westerberg CC: , , , Mario Limonciello , Thomas Gleixner , "Ingo Molnar" , Borislav Petkov , Dave Hansen , , "H. Peter Anvin" , "David S. Miller" , Jens Wiklander , Sumit Garg , , Subject: [PATCH 2/6] crypto: ccp: Add a header for multiple drivers to use `__psp_pa` Date: Thu, 9 Feb 2023 16:38:04 -0600 Message-ID: <20230209223811.4993-3-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230209223811.4993-1-mario.limonciello@amd.com> References: <20230209223811.4993-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT109:EE_|IA1PR12MB6233:EE_ X-MS-Office365-Filtering-Correlation-Id: fd363c51-4dbb-4615-fdb4-08db0aee5f97 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 9+PEu65gMCcrAPJte+Fq2vtE5U8J0g4Bv7lhbajVdloJ8DT4HKckojwug+FADKAj5+yzS9TjB7/fbZYqbuZ1X+cRTcJlyVXo3JnfO5xzSqIo+3Ro2hkKsWfvU7CSfFq4+50X6qzut+TSOt40ZXrc1xRNyiYz6Lw4byeEV2IX0GO7ljMVn2XbWpiPnPFSkF1UPx6OmKGuGpjj3OYq8DXXgX1qHLW9lgPBzzgI2+Qte6a6+day6oZlVLzeSSVHBhY5ZZU2ATEjrjUw2YfJVxCkFRDxlPAYYm4TQiUc4hGOhebBotgnnQAtwYiKVamL8lNC2nLBYgdlUe01us7JCmX54OPURS/6Nx74DuZSAMLFmt+yF8NTALNpYbKDEbPutjWS79ICVXqGpYiPMhp3BTbCE6vHrJzrgB3eidqJVb7cywNO5m6F2O4VD96LF91/R1lyHVtZvtMU0Fi7WN8BHJ5gjkQRfKvkSCfUcooS+ktzki8DNax1hM8Zvk3NI8xDcbrH/jStYE6k3iKRcE3LPe0Lurcr+vbRQBMdZmNXMah3JquypBSLwt498zODVNCXbyxNoKL1zydwm/cUjmQgZiuivi+UoeUTYBhToIj4RTi02QeU250Cj6JLpPO3AqhdZLhTeKUa20r+hraj2QwGdoyZnh8vYM0LmJHrdGxcYbvzsx+CDZSMOxlp5c+ZQhWK9QgoeUNjmj5r9P4pek82GyOO9DhMPI3rxNdc95MN+MQ1ba7TF4ZYMsVvbJjxpN/zaMeZ2Gq52uR/8zXfOAGEL+ztRQ== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230025)(4636009)(39860400002)(346002)(136003)(396003)(376002)(451199018)(40470700004)(36840700001)(46966006)(16526019)(86362001)(7416002)(921005)(186003)(26005)(5660300002)(44832011)(81166007)(8936002)(6666004)(82740400003)(2906002)(82310400005)(70586007)(70206006)(4326008)(356005)(8676002)(41300700001)(36860700001)(316002)(40480700001)(1076003)(40460700003)(426003)(2616005)(478600001)(47076005)(7696005)(54906003)(36756003)(83380400001)(336012)(110136005)(81973001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Feb 2023 22:38:32.4722 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fd363c51-4dbb-4615-fdb4-08db0aee5f97 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT109.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6233 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org The TEE subdriver for CCP, the amdtee driver and the i2c-designware-amdpsp drivers all include `psp-sev.h` even though they don't use SEV functionality. Move the definition of `__psp_pa` into a common header to be included by all of these drivers. Signed-off-by: Mario Limonciello Reviewed-by: Jan Dabros Acked-by: Sumit Garg Acked-by: Jarkko Nikula --- arch/x86/kvm/svm/sev.c | 1 + drivers/crypto/ccp/sev-dev.c | 1 + drivers/crypto/ccp/tee-dev.c | 2 +- drivers/i2c/busses/i2c-designware-amdpsp.c | 2 +- drivers/tee/amdtee/call.c | 2 +- drivers/tee/amdtee/shm_pool.c | 2 +- include/linux/psp-sev.h | 8 -------- include/linux/psp.h | 14 ++++++++++++++ 8 files changed, 20 insertions(+), 12 deletions(-) create mode 100644 include/linux/psp.h diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index 86d6897f48068..ee8e9053f4468 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/crypto/ccp/sev-dev.c b/drivers/crypto/ccp/sev-dev.c index e2f25926eb514..28945ca7c8563 100644 --- a/drivers/crypto/ccp/sev-dev.c +++ b/drivers/crypto/ccp/sev-dev.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include diff --git a/drivers/crypto/ccp/tee-dev.c b/drivers/crypto/ccp/tee-dev.c index 5c9d47f3be375..f24fc953718a0 100644 --- a/drivers/crypto/ccp/tee-dev.c +++ b/drivers/crypto/ccp/tee-dev.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include "psp-dev.h" diff --git a/drivers/i2c/busses/i2c-designware-amdpsp.c b/drivers/i2c/busses/i2c-designware-amdpsp.c index 8f36167bce624..80f28a1bbbef6 100644 --- a/drivers/i2c/busses/i2c-designware-amdpsp.c +++ b/drivers/i2c/busses/i2c-designware-amdpsp.c @@ -4,7 +4,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/tee/amdtee/call.c b/drivers/tee/amdtee/call.c index cec6e70f0ac92..e8cd9aaa34675 100644 --- a/drivers/tee/amdtee/call.c +++ b/drivers/tee/amdtee/call.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include "amdtee_if.h" #include "amdtee_private.h" diff --git a/drivers/tee/amdtee/shm_pool.c b/drivers/tee/amdtee/shm_pool.c index f87f96a291c99..f0303126f199d 100644 --- a/drivers/tee/amdtee/shm_pool.c +++ b/drivers/tee/amdtee/shm_pool.c @@ -5,7 +5,7 @@ #include #include -#include +#include #include "amdtee_private.h" static int pool_op_alloc(struct tee_shm_pool *pool, struct tee_shm *shm, diff --git a/include/linux/psp-sev.h b/include/linux/psp-sev.h index 1595088c428b4..7fd17e82bab43 100644 --- a/include/linux/psp-sev.h +++ b/include/linux/psp-sev.h @@ -14,14 +14,6 @@ #include -#ifdef CONFIG_X86 -#include - -#define __psp_pa(x) __sme_pa(x) -#else -#define __psp_pa(x) __pa(x) -#endif - #define SEV_FW_BLOB_MAX_SIZE 0x4000 /* 16KB */ /** diff --git a/include/linux/psp.h b/include/linux/psp.h new file mode 100644 index 0000000000000..202162487ec3b --- /dev/null +++ b/include/linux/psp.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __PSP_H +#define __PSP_H + +#ifdef CONFIG_X86 +#include + +#define __psp_pa(x) __sme_pa(x) +#else +#define __psp_pa(x) __pa(x) +#endif + +#endif /* __PSP_H */ From patchwork Thu Feb 9 22:38:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 652157 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 626B5C64EC6 for ; Thu, 9 Feb 2023 22:38:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230333AbjBIWiy (ORCPT ); Thu, 9 Feb 2023 17:38:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41550 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230400AbjBIWip (ORCPT ); Thu, 9 Feb 2023 17:38:45 -0500 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2049.outbound.protection.outlook.com [40.107.93.49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5F6945B741; Thu, 9 Feb 2023 14:38:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=AYqk+q9SXgfZ/oBaNoAwWQzqqdvVljpBMxluDpDFayrZg/uuhS+mYG+weexlgbcjacUGIZfDRdiPp0xlyu24VNHko+Tn/AWoouBTRP42PFddBxyqQyK7qs2+oCJsL1mQ1Ump9ORtRLHEIAMAnw5ydVv4KcJdm+rvz6vZrvximolHWsVr9PeY8szlagNiQEAmv04dX6GbZSlDP37eEHnnmXooH6G7L4pL40DtHUCzXnuAA1I6Z05yj+YY7isgdhayLi1IEEA3WqMqyZGJJ01kQdmHUD5A83d/Mw32wHUFV4rjgjPtt/VCFgHetTWLu0b5EiuJBC7GSBUZ9QLQF6pdWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=R8hFz63hgO8+POp8dkPJbWrXjVUvk3qiCntz1kWc8b4=; b=BMgIeh84iO8Mhqjbba/0jM+/Dcg2fGUPbsYhQarhglVD7ay/H30tGv1H8q+WLlAgE2knY+U9FalLwTWsrWYEy6vuaoOMCXpCth69/3n8rssTQ7+jJgh3hzKkTUMa4d5N+zAhrKEesnRrhBZZRnOKOydioV/gjWomp2W+Sy3ClxJw8j36ddp9eRN+11OOeocnajH2ZytFZdox78K2s7haD/pa60ucFlMPcuzI2D2pJnj8rAdaOjjpTGD6YmWLStgURzMuD5evT/hJsKygFbwC5c7OrSF105lNPmAfEVlU2tz2gUedXhhQFboyowU6STANM2gq89V72wThmUjoooGKUw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=semihalf.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=R8hFz63hgO8+POp8dkPJbWrXjVUvk3qiCntz1kWc8b4=; b=CKyTHKb+09PsaN74dAziE5ezdknOIsbKp1oSIjz7tX6S7xS/oYCd2ptz5ft0v4NSQIlwYrLi29n5h8eRdghkYqiU7zZRMGsSwOx7QtgBAc6MchX0pOyoR98mZ3wJQj4q2p7Iz7hUzqOUTrKRie+yXpX5CpNblkndktvqZ+FZrxI= Received: from DM6PR02CA0082.namprd02.prod.outlook.com (2603:10b6:5:1f4::23) by PH7PR12MB7355.namprd12.prod.outlook.com (2603:10b6:510:20e::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6086.19; Thu, 9 Feb 2023 22:38:34 +0000 Received: from DM6NAM11FT110.eop-nam11.prod.protection.outlook.com (2603:10b6:5:1f4:cafe::3a) by DM6PR02CA0082.outlook.office365.com (2603:10b6:5:1f4::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6086.19 via Frontend Transport; Thu, 9 Feb 2023 22:38:34 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT110.mail.protection.outlook.com (10.13.173.205) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6086.19 via Frontend Transport; Thu, 9 Feb 2023 22:38:34 +0000 Received: from AUS-LX-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Thu, 9 Feb 2023 16:38:33 -0600 From: Mario Limonciello To: =?utf-8?b?SmFuIETEhWJyb8Wb?= , Grzegorz Bernacki , Thomas Rijo-john , "Lendacky Thomas" , , Tom Lendacky , John Allen , Brijesh Singh , Jarkko Nikula , "Andy Shevchenko" , Mika Westerberg CC: , , , Mario Limonciello , "David S. Miller" Subject: [PATCH 3/6] crypto: ccp: Move some PSP mailbox bit definitions into common header Date: Thu, 9 Feb 2023 16:38:05 -0600 Message-ID: <20230209223811.4993-4-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230209223811.4993-1-mario.limonciello@amd.com> References: <20230209223811.4993-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT110:EE_|PH7PR12MB7355:EE_ X-MS-Office365-Filtering-Correlation-Id: 5d845270-9cc8-4e5a-0818-08db0aee60c5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: QplvDRtgg+6+VGDqYpCBWpZ5gJ664Iy7SYayfYFBeq61D9+DWAxRBrN3wuho6+bO2iXljXRlqB6LM1oabAIZZpjwIeHW+VSQz0c/X5b6TsWyLSmYT8htwmYxRyYntwGk00cPrxVJxtYzxrLlmV+Oi2Vn25yFc/H4h4+0vBY0s9Lj3hYLcZI7M1n5HRDUrSOzM6nLuQV0RkOUqGEdWX5x4vFyUQIjhX3CCwLC/JzQrrr/rMydiMYc7fwdw5WWdXZmN6bkhGaRtH+oChvTqU8lmWjTwuM1MZD33gSHuCyl6TZUV6psWTKqGel0cMB3dxcYEKjUe9OBix25da1lPJ5ubDLk4mD053h84XUUsZxgEyOZYDiSoj2b36sNRoqeZkX7Gqspu3e3j8P6WIBl0BQ++pvBQqI15HgC6M9+l9b0VV+kagCp2e/hke1xg4f+Rhl382mHgCmfct0slgktqeAjqDBFzpgyQQAH31eQOZ6s54lYfzJ+fuiJjSDfL19+4UmX9YTvJCMjZ/dMsN+8CDvt4B3DVMeBr6gVPbu1Ee0nIV8OAtwBYf0k6mmevtfTvjal1We+nwXWnTxVCiqm5JPrFsWKO4jt5o3MVKiIj5kk0fq7m2BLOdykx6/5xHdLZa41uD/jozamRn/TfhxDQW71O07Ha0l+/aWwt/HLHHjMJ5LthXMmx2/wyxKca0yH8l3YFs8iSUPDt7dl4FDcpirbalVdEfHsKMSIjihyyoj6d3Roh5nto+uQBsqd4f1Qu1zs X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230025)(4636009)(396003)(376002)(39860400002)(136003)(346002)(451199018)(46966006)(40470700004)(36840700001)(83380400001)(110136005)(82310400005)(86362001)(54906003)(186003)(26005)(7696005)(336012)(426003)(47076005)(36756003)(40480700001)(7416002)(16526019)(40460700003)(2906002)(8936002)(15650500001)(44832011)(36860700001)(5660300002)(70586007)(8676002)(41300700001)(70206006)(4326008)(6666004)(478600001)(2616005)(1076003)(82740400003)(356005)(81166007)(921005)(316002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Feb 2023 22:38:34.4451 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5d845270-9cc8-4e5a-0818-08db0aee60c5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT110.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7355 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Some of the bits and fields used for mailboxes communicating with the PSP are common across all mailbox implementations (SEV, TEE, etc). Move these bits into the common `linux/psp.h` so they don't need to be re-defined for each implementation. Signed-off-by: Mario Limonciello --- drivers/crypto/ccp/psp-dev.h | 3 --- drivers/crypto/ccp/sev-dev.c | 15 +++++++-------- drivers/crypto/ccp/sev-dev.h | 2 +- drivers/crypto/ccp/tee-dev.c | 15 ++++++++------- drivers/i2c/busses/i2c-designware-amdpsp.c | 14 ++++---------- include/linux/psp.h | 12 ++++++++++++ 6 files changed, 32 insertions(+), 29 deletions(-) diff --git a/drivers/crypto/ccp/psp-dev.h b/drivers/crypto/ccp/psp-dev.h index 06e1f317216d2..55f54bb2b3fba 100644 --- a/drivers/crypto/ccp/psp-dev.h +++ b/drivers/crypto/ccp/psp-dev.h @@ -17,9 +17,6 @@ #include "sp-dev.h" -#define PSP_CMDRESP_RESP BIT(31) -#define PSP_CMDRESP_ERR_MASK 0xffff - #define MAX_PSP_NAME_LEN 16 extern struct psp_device *psp_master; diff --git a/drivers/crypto/ccp/sev-dev.c b/drivers/crypto/ccp/sev-dev.c index 28945ca7c8563..6440d35dfa4ee 100644 --- a/drivers/crypto/ccp/sev-dev.c +++ b/drivers/crypto/ccp/sev-dev.c @@ -7,6 +7,7 @@ * Author: Brijesh Singh */ +#include #include #include #include @@ -103,7 +104,7 @@ static void sev_irq_handler(int irq, void *data, unsigned int status) /* Check if it is SEV command completion: */ reg = ioread32(sev->io_regs + sev->vdata->cmdresp_reg); - if (reg & PSP_CMDRESP_RESP) { + if (FIELD_GET(PSP_CMDRESP_RESP, reg)) { sev->int_rcvd = 1; wake_up(&sev->int_queue); } @@ -347,9 +348,7 @@ static int __sev_do_cmd_locked(int cmd, void *data, int *psp_ret) sev->int_rcvd = 0; - reg = cmd; - reg <<= SEV_CMDRESP_CMD_SHIFT; - reg |= SEV_CMDRESP_IOC; + reg = FIELD_PREP(SEV_CMDRESP_CMD, cmd) | SEV_CMDRESP_IOC; iowrite32(reg, sev->io_regs + sev->vdata->cmdresp_reg); /* wait for command completion */ @@ -367,11 +366,11 @@ static int __sev_do_cmd_locked(int cmd, void *data, int *psp_ret) psp_timeout = psp_cmd_timeout; if (psp_ret) - *psp_ret = reg & PSP_CMDRESP_ERR_MASK; + *psp_ret = FIELD_GET(PSP_CMDRESP_STS, reg); - if (reg & PSP_CMDRESP_ERR_MASK) { - dev_dbg(sev->dev, "sev command %#x failed (%#010x)\n", - cmd, reg & PSP_CMDRESP_ERR_MASK); + if (FIELD_GET(PSP_CMDRESP_STS, reg)) { + dev_dbg(sev->dev, "sev command %#x failed (%#010lx)\n", + cmd, FIELD_GET(PSP_CMDRESP_STS, reg)); ret = -EIO; } else { ret = sev_write_init_ex_file_if_required(cmd); diff --git a/drivers/crypto/ccp/sev-dev.h b/drivers/crypto/ccp/sev-dev.h index 666c21eb81ab3..778c95155e745 100644 --- a/drivers/crypto/ccp/sev-dev.h +++ b/drivers/crypto/ccp/sev-dev.h @@ -25,8 +25,8 @@ #include #include +#define SEV_CMDRESP_CMD GENMASK(26, 16) #define SEV_CMD_COMPLETE BIT(1) -#define SEV_CMDRESP_CMD_SHIFT 16 #define SEV_CMDRESP_IOC BIT(0) struct sev_misc_dev { diff --git a/drivers/crypto/ccp/tee-dev.c b/drivers/crypto/ccp/tee-dev.c index f24fc953718a0..5560bf8329a12 100644 --- a/drivers/crypto/ccp/tee-dev.c +++ b/drivers/crypto/ccp/tee-dev.c @@ -8,6 +8,7 @@ * Copyright (C) 2019,2021 Advanced Micro Devices, Inc. */ +#include #include #include #include @@ -69,7 +70,7 @@ static int tee_wait_cmd_poll(struct psp_tee_device *tee, unsigned int timeout, while (--nloop) { *reg = ioread32(tee->io_regs + tee->vdata->cmdresp_reg); - if (*reg & PSP_CMDRESP_RESP) + if (FIELD_GET(PSP_CMDRESP_RESP, *reg)) return 0; usleep_range(10000, 10100); @@ -149,9 +150,9 @@ static int tee_init_ring(struct psp_tee_device *tee) goto free_buf; } - if (reg & PSP_CMDRESP_ERR_MASK) { - dev_err(tee->dev, "tee: ring init command failed (%#010x)\n", - reg & PSP_CMDRESP_ERR_MASK); + if (FIELD_GET(PSP_CMDRESP_STS, reg)) { + dev_err(tee->dev, "tee: ring init command failed (%#010lx)\n", + FIELD_GET(PSP_CMDRESP_STS, reg)); tee_free_ring(tee); ret = -EIO; } @@ -179,9 +180,9 @@ static void tee_destroy_ring(struct psp_tee_device *tee) ret = tee_wait_cmd_poll(tee, TEE_DEFAULT_TIMEOUT, ®); if (ret) { dev_err(tee->dev, "tee: ring destroy command timed out\n"); - } else if (reg & PSP_CMDRESP_ERR_MASK) { - dev_err(tee->dev, "tee: ring destroy command failed (%#010x)\n", - reg & PSP_CMDRESP_ERR_MASK); + } else if (FIELD_GET(PSP_CMDRESP_STS, reg)) { + dev_err(tee->dev, "tee: ring destroy command failed (%#010lx)\n", + FIELD_GET(PSP_CMDRESP_STS, reg)); } free_ring: diff --git a/drivers/i2c/busses/i2c-designware-amdpsp.c b/drivers/i2c/busses/i2c-designware-amdpsp.c index 80f28a1bbbef6..85d91cb6b9056 100644 --- a/drivers/i2c/busses/i2c-designware-amdpsp.c +++ b/drivers/i2c/busses/i2c-designware-amdpsp.c @@ -25,12 +25,6 @@ #define PSP_I2C_REQ_STS_BUS_BUSY 0x1 #define PSP_I2C_REQ_STS_INV_PARAM 0x3 -#define PSP_MBOX_FIELDS_STS GENMASK(15, 0) -#define PSP_MBOX_FIELDS_CMD GENMASK(23, 16) -#define PSP_MBOX_FIELDS_RESERVED GENMASK(29, 24) -#define PSP_MBOX_FIELDS_RECOVERY BIT(30) -#define PSP_MBOX_FIELDS_READY BIT(31) - struct psp_req_buffer_hdr { u32 total_size; u32 status; @@ -99,7 +93,7 @@ static int psp_check_mbox_recovery(struct psp_mbox __iomem *mbox) tmp = readl(&mbox->cmd_fields); - return FIELD_GET(PSP_MBOX_FIELDS_RECOVERY, tmp); + return FIELD_GET(PSP_CMDRESP_RECOVERY, tmp); } static int psp_wait_cmd(struct psp_mbox __iomem *mbox) @@ -107,7 +101,7 @@ static int psp_wait_cmd(struct psp_mbox __iomem *mbox) u32 tmp, expected; /* Expect mbox_cmd to be cleared and ready bit to be set by PSP */ - expected = FIELD_PREP(PSP_MBOX_FIELDS_READY, 1); + expected = FIELD_PREP(PSP_CMDRESP_RESP, 1); /* * Check for readiness of PSP mailbox in a tight loop in order to @@ -124,7 +118,7 @@ static u32 psp_check_mbox_sts(struct psp_mbox __iomem *mbox) cmd_reg = readl(&mbox->cmd_fields); - return FIELD_GET(PSP_MBOX_FIELDS_STS, cmd_reg); + return FIELD_GET(PSP_CMDRESP_STS, cmd_reg); } static int psp_send_cmd(struct psp_i2c_req *req) @@ -148,7 +142,7 @@ static int psp_send_cmd(struct psp_i2c_req *req) writeq(req_addr, &mbox->i2c_req_addr); /* Write command register to trigger processing */ - cmd_reg = FIELD_PREP(PSP_MBOX_FIELDS_CMD, PSP_I2C_REQ_BUS_CMD); + cmd_reg = FIELD_PREP(PSP_CMDRESP_CMD, PSP_I2C_REQ_BUS_CMD); writel(cmd_reg, &mbox->cmd_fields); if (psp_wait_cmd(mbox)) diff --git a/include/linux/psp.h b/include/linux/psp.h index 202162487ec3b..d3424790a70eb 100644 --- a/include/linux/psp.h +++ b/include/linux/psp.h @@ -11,4 +11,16 @@ #define __psp_pa(x) __pa(x) #endif +/* + * Fields and bits used by most PSP mailboxes + * + * Note: Some mailboxes (such as SEV) have extra bits or different meanings + * and should include an appropriate local definition in their source file. + */ +#define PSP_CMDRESP_STS GENMASK(15, 0) +#define PSP_CMDRESP_CMD GENMASK(23, 16) +#define PSP_CMDRESP_RESERVED GENMASK(29, 24) +#define PSP_CMDRESP_RECOVERY BIT(30) +#define PSP_CMDRESP_RESP BIT(31) + #endif /* __PSP_H */ From patchwork Thu Feb 9 22:38:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 652158 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B417FC636D3 for ; Thu, 9 Feb 2023 22:38:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230405AbjBIWiu (ORCPT ); Thu, 9 Feb 2023 17:38:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41568 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230402AbjBIWip (ORCPT ); Thu, 9 Feb 2023 17:38:45 -0500 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2041.outbound.protection.outlook.com [40.107.236.41]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3CE7160D49; Thu, 9 Feb 2023 14:38:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=mG328BDZQdWJCnktP+5rEvKEtSwFq9W28k5pBizHsL9CwL4RtWAInC8MLOeR+CV452G0d8GAkKXF2JESEzK3jo81N196ZTAEuxXYFB52ECb6oNr1wR/0xT3jDMSejqGNk3OXzlA+2O5+eLcfvFoVMyTKGRJ8ExjVoWeBjpnmdZRCE2q4BmtdNgXk5QpLQm4+Lb7yInx8lFxhi83kzrcrW6wVd7xut1X7IgLWpRimsrOGeYKEwrDF7+uU2qBgrL5hTt2ypeJyUAMcOOQIL02HDbIpTBwVUkzXAXJSv7Cvpo1P0RwzFRgIQpWnV8hAzGOeVgZLmP49JYk7AEWo+ptO7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=C9qnQtcHYlxKhIJk5LC1e/eVODtX66bQnfF7jFH02nU=; b=jVj1XyzyG/iE/09UvajxNae0VqZ39nPCHHCq7xvWMyTRqY522xIG7u6ypJSydJ31S7ZGi0Ei/OYj0w45OKw0wWIplxuRrHFOCb4sDNjeX8xGn+jZhRw77w4JznLG1JGJoZs0r4wqGa0AAhEERqDkadLoDQLQM6XIDlHvkvLYw/fKHmLEGFnVqCiiJb/NzzlI7S/mp3dTZHishC9FNYnV6EU+LmkRxz8QeM0ItAuYR2axjT8kIzRLADwXUlPYnoxmgJgwBEffrYB6VANcIriXesfNwBaYCt7FXDn8+lMs16BWbl5maChZIR2ZLM5VrBDSeTG79BK9i0cN6ahNi1E8Hg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=semihalf.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=C9qnQtcHYlxKhIJk5LC1e/eVODtX66bQnfF7jFH02nU=; b=hH5Y9KMhkNZHo5DtzSwZ0eCJRxzim2JprYMWeZ5p0ox4OQeW4rJ5hdK+M8sriLL6VwmY3jARXDsCNezcqT+lOj/lc84pxaEl/86lroWTJLm2PDEpD7fRd7rg6lGGHgDH4Fttd6YXwuvtXCnJB1P3OAmUN3xAJTVdLWZRH7KBc78= Received: from DS7PR03CA0153.namprd03.prod.outlook.com (2603:10b6:5:3b2::8) by MN0PR12MB5762.namprd12.prod.outlook.com (2603:10b6:208:375::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6086.19; Thu, 9 Feb 2023 22:38:37 +0000 Received: from DM6NAM11FT051.eop-nam11.prod.protection.outlook.com (2603:10b6:5:3b2:cafe::7b) by DS7PR03CA0153.outlook.office365.com (2603:10b6:5:3b2::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6086.17 via Frontend Transport; Thu, 9 Feb 2023 22:38:36 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT051.mail.protection.outlook.com (10.13.172.243) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6086.19 via Frontend Transport; Thu, 9 Feb 2023 22:38:36 +0000 Received: from AUS-LX-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Thu, 9 Feb 2023 16:38:35 -0600 From: Mario Limonciello To: =?utf-8?b?SmFuIETEhWJyb8Wb?= , Grzegorz Bernacki , Thomas Rijo-john , "Lendacky Thomas" , , Tom Lendacky , John Allen CC: , , , , "Mario Limonciello" , "David S. Miller" Subject: [PATCH 4/6] crypto: ccp: Add support for an interface for platform features Date: Thu, 9 Feb 2023 16:38:06 -0600 Message-ID: <20230209223811.4993-5-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230209223811.4993-1-mario.limonciello@amd.com> References: <20230209223811.4993-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT051:EE_|MN0PR12MB5762:EE_ X-MS-Office365-Filtering-Correlation-Id: 4022432e-001f-492b-b69b-08db0aee6220 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: TLkAZCXimThTcz7/dlmGZoXrQ3vg9OPECh434BKduiiC8JkCampWuWbdc+WOJaxJ9OuLq2IXjBFEDEcdk6dUmgqB11yysOwbKBlLJl7mHsqb3K+T69uL3fO4j8+TjlYSlm5oPwjvBa9FjoPwomims3gWdC98O0X2gOA2u2YOy9KPKfYd9wYCvQk/nyzbTCesy9OrAGKB2n9COh9k5fDIaFyAkrFCLnNBpSh+eKlU05xitpcWPrLPKpwIxtEkU4AO1txk5HaS/dplPCI8XQPtkONQb62AN6KdDF+3M2aV6hHLRsFMURXcfoh8mLpsptyI7j281AG2YBGWybQ8GJPJoLSK1Qe70zZBm2YXTZBB1taAtu3tXP1cl5CNbjGEBLTOLQ8+MviF71SKGjgpAMk164G4iRTU6NSnZrE3j+YrKKsXA76iOjgLOU8xC6+pT9CnB7cjDxnU5Wp77H+1d61pjT4NvwZSN6tiUywc/X6Eqro+Bm7BvT5WRpjipq09SWjKu6g+HShUJCKMFgwcSq4xe1ETn2gu1Q36RNmxFZpVkHc3/vfB18i1WK+jOp7Z7PtnVM25CnWvNZSH+1zFyVbvU/V5HQOeePixPoORO0usMaPl67Y7tNLs3vI8t2FqZvTZGs/xk/oQDyiKcY9N8pP9pmC2NJfudjAUeBStGl1fqOn39Nnrx8uQCDCaUqdrPR1niXhLrAvK34KFwZ93VSVOa6TAe7O7ey1mugln8Z8OCxAWjJEWMiTw0ZOgVlhoPFXcJRyJNJUTFJVbFvYyAVIZDQ== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230025)(4636009)(376002)(346002)(39860400002)(396003)(136003)(451199018)(46966006)(36840700001)(40470700004)(8936002)(2906002)(2616005)(336012)(426003)(186003)(83380400001)(40460700003)(47076005)(316002)(478600001)(54906003)(8676002)(4326008)(7696005)(70206006)(70586007)(6636002)(26005)(110136005)(1076003)(40480700001)(6666004)(44832011)(30864003)(16526019)(41300700001)(356005)(5660300002)(82740400003)(36756003)(86362001)(82310400005)(36860700001)(81166007)(36900700001)(134885004); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Feb 2023 22:38:36.7081 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4022432e-001f-492b-b69b-08db0aee6220 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT051.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5762 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Some platforms with a PSP support an interface for features that interact directly with the PSP instead of through a SEV or TEE environment. Initialize this interface so that other drivers can consume it. These drivers may either be subdrivers for the ccp module or external modules. For external modules, export a symbol for them to utilize. Signed-off-by: Mario Limonciello --- drivers/crypto/ccp/Makefile | 3 +- drivers/crypto/ccp/platform-access.c | 166 +++++++++++++++++++++++++++ drivers/crypto/ccp/platform-access.h | 34 ++++++ drivers/crypto/ccp/psp-dev.c | 17 +++ drivers/crypto/ccp/psp-dev.h | 1 + drivers/crypto/ccp/sp-dev.h | 7 ++ include/linux/psp-platform-access.h | 49 ++++++++ 7 files changed, 276 insertions(+), 1 deletion(-) create mode 100644 drivers/crypto/ccp/platform-access.c create mode 100644 drivers/crypto/ccp/platform-access.h create mode 100644 include/linux/psp-platform-access.h diff --git a/drivers/crypto/ccp/Makefile b/drivers/crypto/ccp/Makefile index db362fe472ea3..f6196495e862d 100644 --- a/drivers/crypto/ccp/Makefile +++ b/drivers/crypto/ccp/Makefile @@ -10,7 +10,8 @@ ccp-$(CONFIG_CRYPTO_DEV_CCP_DEBUGFS) += ccp-debugfs.o ccp-$(CONFIG_PCI) += sp-pci.o ccp-$(CONFIG_CRYPTO_DEV_SP_PSP) += psp-dev.o \ sev-dev.o \ - tee-dev.o + tee-dev.o \ + platform-access.o obj-$(CONFIG_CRYPTO_DEV_CCP_CRYPTO) += ccp-crypto.o ccp-crypto-objs := ccp-crypto-main.o \ diff --git a/drivers/crypto/ccp/platform-access.c b/drivers/crypto/ccp/platform-access.c new file mode 100644 index 0000000000000..8cd165ba915b9 --- /dev/null +++ b/drivers/crypto/ccp/platform-access.c @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AMD Platform Security Processor (PSP) Platform Access interface + * + * Copyright (C) 2023 Advanced Micro Devices, Inc. + * + * Author: Mario Limonciello + * + * Some of this code is adapted from drivers/i2c/busses/i2c-designware-amdpsp.c + * developed by Jan Dabros and Copyright (C) 2022 Google Inc. + * + */ + +#include +#include +#include +#include + +#include "platform-access.h" + +#define PSP_CMD_TIMEOUT_US (500 * USEC_PER_MSEC) + +/* Recovery field should be equal 0 to start sending commands */ +static int check_recovery(u32 __iomem *cmd) +{ + return FIELD_GET(PSP_CMDRESP_RECOVERY, ioread32(cmd)); +} + +static int wait_cmd(u32 __iomem *cmd) +{ + u32 tmp, expected; + + /* Expect mbox_cmd to be cleared and ready bit to be set by PSP */ + expected = FIELD_PREP(PSP_CMDRESP_RESP, 1); + + /* + * Check for readiness of PSP mailbox in a tight loop in order to + * process further as soon as command was consumed. + */ + return readl_poll_timeout(cmd, tmp, (tmp & expected), 0, + PSP_CMD_TIMEOUT_US); +} + +int psp_check_platform_access_status(void) +{ + struct psp_device *psp = psp_get_master_device(); + + if (!psp || !psp->platform_access_data) + return -ENODEV; + + return 0; +} +EXPORT_SYMBOL(psp_check_platform_access_status); + +int psp_send_platform_access_msg(enum psp_platform_access_msg msg, + struct psp_request *req) +{ + struct psp_device *psp = psp_get_master_device(); + u32 __iomem *cmd, __iomem *lo, __iomem *hi; + struct psp_platform_access_device *pa_dev; + phys_addr_t req_addr; + u32 cmd_reg; + int ret; + + if (!psp || !psp->platform_access_data) + return -ENODEV; + + pa_dev = psp->platform_access_data; + cmd = psp->io_regs + pa_dev->vdata->cmdresp_reg; + lo = psp->io_regs + pa_dev->vdata->cmdbuff_addr_lo_reg; + hi = psp->io_regs + pa_dev->vdata->cmdbuff_addr_hi_reg; + + mutex_lock(&pa_dev->mutex); + + if (check_recovery(cmd)) { + dev_dbg(psp->dev, "in recovery\n"); + ret = -EBUSY; + goto unlock; + } + + if (wait_cmd(cmd)) { + dev_dbg(psp->dev, "not done processing command\n"); + ret = -EBUSY; + goto unlock; + } + + /* + * Fill mailbox with address of command-response buffer, which will be + * used for sending i2c requests as well as reading status returned by + * PSP. Use physical address of buffer, since PSP will map this region. + */ + req_addr = __psp_pa(req); + iowrite32(lower_32_bits(req_addr), lo); + iowrite32(upper_32_bits(req_addr), hi); + + print_hex_dump_debug("->psp ", DUMP_PREFIX_OFFSET, 16, 2, req, + req->header.payload_size, false); + + /* Write command register to trigger processing */ + cmd_reg = FIELD_PREP(PSP_CMDRESP_CMD, msg); + iowrite32(cmd_reg, cmd); + + if (wait_cmd(cmd)) { + ret = -ETIMEDOUT; + goto unlock; + } + + /* Ensure it was triggered by this driver */ + if (ioread32(lo) != lower_32_bits(req_addr) || + ioread32(hi) != upper_32_bits(req_addr)) { + ret = -EBUSY; + goto unlock; + } + + /* Store the status in request header for caller to investigate */ + cmd_reg = ioread32(cmd); + req->header.status = FIELD_GET(PSP_CMDRESP_STS, cmd_reg); + if (req->header.status) { + ret = -EIO; + goto unlock; + } + + print_hex_dump_debug("<-psp ", DUMP_PREFIX_OFFSET, 16, 2, req, + req->header.payload_size, false); + + ret = 0; + +unlock: + mutex_unlock(&pa_dev->mutex); + + return ret; +} +EXPORT_SYMBOL_GPL(psp_send_platform_access_msg); + +void platform_access_dev_destroy(struct psp_device *psp) +{ + struct psp_platform_access_device *pa_dev = psp->platform_access_data; + + if (!pa_dev) + return; + + mutex_destroy(&pa_dev->mutex); + psp->platform_access_data = NULL; +} + +int platform_access_dev_init(struct psp_device *psp) +{ + struct device *dev = psp->dev; + struct psp_platform_access_device *pa_dev; + + pa_dev = devm_kzalloc(dev, sizeof(*pa_dev), GFP_KERNEL); + if (!pa_dev) + return -ENOMEM; + + psp->platform_access_data = pa_dev; + pa_dev->psp = psp; + pa_dev->dev = dev; + + pa_dev->vdata = (struct platform_access_vdata *)psp->vdata->platform_access; + + mutex_init(&pa_dev->mutex); + + dev_dbg(dev, "platform access enabled\n"); + + return 0; +} diff --git a/drivers/crypto/ccp/platform-access.h b/drivers/crypto/ccp/platform-access.h new file mode 100644 index 0000000000000..56bc8eabeacc8 --- /dev/null +++ b/drivers/crypto/ccp/platform-access.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * AMD Platform Security Processor (PSP) Platform Access interface + * + * Copyright (C) 2023 Advanced Micro Devices, Inc. + * + * Author: Mario Limonciello + */ + +#ifndef __PSP_PLATFORM_ACCESS_H__ +#define __PSP_PLATFORM_ACCESS_H__ + +#include +#include +#include +#include + +#include "psp-dev.h" + +struct psp_platform_access_device { + struct device *dev; + struct psp_device *psp; + + struct platform_access_vdata *vdata; + + struct mutex mutex; + + void *platform_access_data; +}; + +void platform_access_dev_destroy(struct psp_device *psp); +int platform_access_dev_init(struct psp_device *psp); + +#endif /* __PSP_PLATFORM_ACCESS_H__ */ diff --git a/drivers/crypto/ccp/psp-dev.c b/drivers/crypto/ccp/psp-dev.c index cd8d1974726a8..ec98f19800de7 100644 --- a/drivers/crypto/ccp/psp-dev.c +++ b/drivers/crypto/ccp/psp-dev.c @@ -14,6 +14,7 @@ #include "psp-dev.h" #include "sev-dev.h" #include "tee-dev.h" +#include "platform-access.h" struct psp_device *psp_master; @@ -102,6 +103,17 @@ static int psp_check_tee_support(struct psp_device *psp) return 0; } +static void psp_init_platform_access(struct psp_device *psp) +{ + int ret; + + ret = platform_access_dev_init(psp); + if (ret) { + dev_warn(psp->dev, "platform access init failed: %d\n", ret); + return; + } +} + static int psp_init(struct psp_device *psp) { int ret; @@ -118,6 +130,9 @@ static int psp_init(struct psp_device *psp) return ret; } + if (psp->vdata->platform_access) + psp_init_platform_access(psp); + return 0; } @@ -198,6 +213,8 @@ void psp_dev_destroy(struct sp_device *sp) tee_dev_destroy(psp); + platform_access_dev_destroy(psp); + sp_free_psp_irq(sp, psp); if (sp->clear_psp_master_device) diff --git a/drivers/crypto/ccp/psp-dev.h b/drivers/crypto/ccp/psp-dev.h index 55f54bb2b3fba..505e4bdeaca84 100644 --- a/drivers/crypto/ccp/psp-dev.h +++ b/drivers/crypto/ccp/psp-dev.h @@ -39,6 +39,7 @@ struct psp_device { void *sev_data; void *tee_data; + void *platform_access_data; unsigned int capability; }; diff --git a/drivers/crypto/ccp/sp-dev.h b/drivers/crypto/ccp/sp-dev.h index 20377e67f65df..5ec6c219a731b 100644 --- a/drivers/crypto/ccp/sp-dev.h +++ b/drivers/crypto/ccp/sp-dev.h @@ -53,9 +53,16 @@ struct tee_vdata { const unsigned int ring_rptr_reg; }; +struct platform_access_vdata { + const unsigned int cmdresp_reg; + const unsigned int cmdbuff_addr_lo_reg; + const unsigned int cmdbuff_addr_hi_reg; +}; + struct psp_vdata { const struct sev_vdata *sev; const struct tee_vdata *tee; + const struct platform_access_vdata *platform_access; const unsigned int feature_reg; const unsigned int inten_reg; const unsigned int intsts_reg; diff --git a/include/linux/psp-platform-access.h b/include/linux/psp-platform-access.h new file mode 100644 index 0000000000000..60bfd5f0b045e --- /dev/null +++ b/include/linux/psp-platform-access.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __PSP_PLATFORM_ACCESS_H +#define __PSP_PLATFORM_ACCESS_H + +#include + +enum psp_platform_access_msg { + PSP_CMD_NONE = 0x0, +}; + +struct psp_req_buffer_hdr { + u32 payload_size; + u32 status; +} __packed; + +struct psp_request { + struct psp_req_buffer_hdr header; + void *buf; +} __packed; + +/** + * psp_send_platform_access_msg() - Send a message to control platform features + * + * This function is intended to be used by drivers outside of ccp to determine + * if platform features has initialized. + * + * Returns: + * 0: success + * -%EBUSY: mailbox in recovery or in use + * -%ENODEV: driver not bound with PSP device + * -%ETIMEDOUT: request timed out + * -%EIO: unknown error (see kernel log) + */ +int psp_send_platform_access_msg(enum psp_platform_access_msg, struct psp_request *req); + +/** + * psp_check_platform_access_status() - Checks whether platform features is ready + * + * This function is intended to be used by drivers outside of ccp to determine + * if platform features has initialized. + * + * Returns: + * 0 platform features is ready + * -%ENODEV platform features is not ready or present + */ +int psp_check_platform_access_status(void); + +#endif /* __PSP_PLATFORM_ACCESS_H */