From patchwork Wed Feb 8 09:21:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moudy Ho X-Patchwork-Id: 651946 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0548C64EC5 for ; Wed, 8 Feb 2023 09:24:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231388AbjBHJY3 (ORCPT ); Wed, 8 Feb 2023 04:24:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39018 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231228AbjBHJX7 (ORCPT ); Wed, 8 Feb 2023 04:23:59 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 44C4F4617D; Wed, 8 Feb 2023 01:22:19 -0800 (PST) X-UUID: 119aac38a79211ed945fc101203acc17-20230208 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=ANfh8Sp6RDP1BEKj58c80tDv8uSSZSoV0eHp6LVwnNQ=; b=M+b31tzl6Gn5bkEaTvcmuE0zAn7ragRpSK3DZ3dCbwlawwMtlaFlCFk+cIXWwa6u/v8sWdrgdmSX9R8lPSreBkZZKC/1c4zp4kLs2qKvkkA6gD/SssqxvdFlppj5xfnMr0i9fZv9dr4U1GgE/jKGhT4e/RMKl4oouEW1aGvMRbc=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.19, REQID:2646509c-e406-41ea-a71e-83ad13400877, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:885ddb2, CLOUDID:cd98d4f7-ff42-4fb0-b929-626456a83c14, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0 X-CID-BVR: 0,NGT X-UUID: 119aac38a79211ed945fc101203acc17-20230208 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 612659513; Wed, 08 Feb 2023 17:22:12 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 8 Feb 2023 17:22:10 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 8 Feb 2023 17:22:10 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Matthias Brugger CC: , , , , , , Moudy Ho Subject: [PATCH v4 02/16] arm64: dts: mediatek: mt8183: correct MDP3 DMA-related nodes Date: Wed, 8 Feb 2023 17:21:55 +0800 Message-ID: <20230208092209.19472-3-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230208092209.19472-1-moudy.ho@mediatek.com> References: <20230208092209.19472-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In order to generalize the node names, the DMA-related nodes corresponding to MT8183 MDP3 need to be corrected. Fixes: 60a2fb8d202a ("arm64: dts: mt8183: add MediaTek MDP3 nodes") Signed-off-by: Moudy Ho --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 3d1d7870a5f1..d7011e6511e1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1781,7 +1781,7 @@ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; }; - mdp3-rdma0@14001000 { + dma-controller0@14001000 { compatible = "mediatek,mt8183-mdp3-rdma"; reg = <0 0x14001000 0 0x1000>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>; @@ -1793,6 +1793,7 @@ iommus = <&iommu M4U_PORT_MDP_RDMA0>; mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>, <&gce 21 CMDQ_THR_PRIO_LOWEST 0>; + #dma-cells = <1>; }; mdp3-rsz0@14003000 { @@ -1813,7 +1814,7 @@ clocks = <&mmsys CLK_MM_MDP_RSZ1>; }; - mdp3-wrot0@14005000 { + dma-controller@14005000 { compatible = "mediatek,mt8183-mdp3-wrot"; reg = <0 0x14005000 0 0x1000>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; @@ -1822,6 +1823,7 @@ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_MDP_WROT0>; iommus = <&iommu M4U_PORT_MDP_WROT0>; + #dma-cells = <1>; }; mdp3-wdma@14006000 { From patchwork Wed Feb 8 09:21:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moudy Ho X-Patchwork-Id: 651943 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB069C64ED9 for ; Wed, 8 Feb 2023 09:24:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229739AbjBHJYc (ORCPT ); Wed, 8 Feb 2023 04:24:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39026 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229539AbjBHJX7 (ORCPT ); Wed, 8 Feb 2023 04:23:59 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B4A7646701; Wed, 8 Feb 2023 01:22:19 -0800 (PST) X-UUID: 11a81454a79211eda06fc9ecc4dadd91-20230208 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=oMr9KDANkq6TC7wPHlHBzMnxVz9frFbOetK3BNIplc8=; b=dwd6HnH5JIubT85nkxqAuTxVqTyPo0RY21afH///cQN4axFz/zyrkrSE1DEfjMqtQiK6OZn7kPB/pZLD7LxMQcwl/m43nmZZc0vJYsqxb7oJJqYE8pUcAHYmjA+ibWIXsDJMTQBfKGflJ8viPnTir4il1jRNycftf4yVOBJQIpA=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.19, REQID:b7bb5165-6e0c-41fb-b2de-aa252390f0fe, IP:0, U RL:25,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:20 X-CID-META: VersionHash:885ddb2, CLOUDID:fc98d4f7-ff42-4fb0-b929-626456a83c14, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0 X-CID-BVR: 0,NGT X-UUID: 11a81454a79211eda06fc9ecc4dadd91-20230208 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1795196795; Wed, 08 Feb 2023 17:22:12 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Wed, 8 Feb 2023 17:22:10 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 8 Feb 2023 17:22:10 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Matthias Brugger CC: , , , , , , Moudy Ho Subject: [PATCH v4 03/16] dt-binding: mediatek: add MediaTek mt8195 MDP3 components Date: Wed, 8 Feb 2023 17:21:56 +0800 Message-ID: <20230208092209.19472-4-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230208092209.19472-1-moudy.ho@mediatek.com> References: <20230208092209.19472-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Adds support for MT8195 MDP3 RDMA, and introduce more MDP3 components present in MT8195. Signed-off-by: Moudy Ho --- .../bindings/media/mediatek,mdp3-rdma.yaml | 30 +-- .../bindings/media/mediatek,mdp3-rsz.yaml | 5 +- .../bindings/media/mediatek,mt8195-mdp3.yaml | 174 ++++++++++++++++++ 3 files changed, 197 insertions(+), 12 deletions(-) create mode 100644 Documentation/devicetree/bindings/media/mediatek,mt8195-mdp3.yaml diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml index 46730687c662..abc3284b21d0 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml @@ -20,8 +20,9 @@ description: | properties: compatible: - items: - - const: mediatek,mt8183-mdp3-rdma + enum: + - mediatek,mt8183-mdp3-rdma + - mediatek,mt8195-mdp3-rdma reg: maxItems: 1 @@ -46,20 +47,28 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32-array power-domains: - maxItems: 1 + oneOf: + - items: + - description: for RDMA + - items: + - description: for vppsys 0 + - description: for vppsys 1 clocks: - items: - - description: RDMA clock - - description: RSZ clock + minItems: 2 + maxItems: 19 iommus: - maxItems: 1 + oneOf: + - items: + - description: RDMA port + - items: + - description: RDMA port + - description: RDMA to WROT DL port mboxes: - items: - - description: used for 1st data pipe from RDMA - - description: used for 2nd data pipe from RDMA + minItems: 1 + maxItems: 5 '#dma-cells': const: 1 @@ -72,7 +81,6 @@ required: - power-domains - clocks - iommus - - mboxes - '#dma-cells' additionalProperties: false diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml index 78f9de6192ef..4bc5ac112d2a 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml @@ -43,12 +43,15 @@ properties: clocks: minItems: 1 + maxItems: 2 + + power-domains: + maxItems: 1 required: - compatible - reg - mediatek,gce-client-reg - - mediatek,gce-events - clocks additionalProperties: false diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8195-mdp3.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8195-mdp3.yaml new file mode 100644 index 000000000000..d2b01456c495 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mt8195-mdp3.yaml @@ -0,0 +1,174 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mt8195-mdp3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Media Data Path 3 display components + +maintainers: + - Matthias Brugger + - Moudy Ho + +description: + A group of display pipeline components for image quality adjustment, + color format conversion and data flow control, and the abbreviations + are explained below. + AAL - Ambient-light Adaptive Luma. + Color - Enhance or reduce color in Y/S/H channel. + FG - Fime Grain for AV1 spec. + HDR - Perform HDR to SDR. + MERGE - Used to merge two slice-per-line into one side-by-side. + OVL - Perform alpha blending. + PAD - Predefined alpha or color value insertion. + SPLIT - Split a HDMI stream into two ouptut. + STITCH - Combine multiple video frame with overlapping fields of view. + TCC - HDR gamma curve conversion support. + TDSHP - Sharpness and contrast improvement. + +properties: + compatible: + enum: + - mediatek,mt8195-mdp3-aal + - mediatek,mt8195-mdp3-color + - mediatek,mt8195-mdp3-fg + - mediatek,mt8195-mdp3-hdr + - mediatek,mt8195-mdp3-merge + - mediatek,mt8195-mdp3-ovl + - mediatek,mt8195-mdp3-pad + - mediatek,mt8195-mdp3-split + - mediatek,mt8195-mdp3-stitch + - mediatek,mt8195-mdp3-tcc + - mediatek,mt8195-mdp3-tdshp + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle of GCE + - description: GCE subsys id + - description: register offset + - description: register size + description: + Each GCE subsys id is mapping to a base address of display function blocks + register which is defined in . + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 7 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - mediatek,gce-client-reg + - clocks + - power-domains + +additionalProperties: false + +examples: + - | + #include + #include + #include + + display@14002000 { + compatible = "mediatek,mt8195-mdp3-fg"; + reg = <0x14002000 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_FG>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + display@14003000 { + compatible = "mediatek,mt8195-mdp3-stitch"; + reg = <0x14003000 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_STITCH>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + display@14004000 { + compatible = "mediatek,mt8195-mdp3-hdr"; + reg = <0x14004000 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_HDR>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + display@14005000 { + compatible = "mediatek,mt8195-mdp3-aal"; + reg = <0x14005000 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_AAL>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + display@14f06000 { + compatible = "mediatek,mt8195-mdp3-split"; + reg = <0x14f06000 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x6000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_VPP_SPLIT>, + <&vppsys1 CLK_VPP1_HDMI_META>, + <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>, + <&vppsys1 CLK_VPP1_DGI_IN>, + <&vppsys1 CLK_VPP1_DGI_OUT>, + <&vppsys1 CLK_VPP1_VPP_SPLIT_DGI>, + <&vppsys1 CLK_VPP1_VPP_SPLIT_26M>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14007000 { + compatible = "mediatek,mt8195-mdp3-tdshp"; + reg = <0x14007000 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + display@14008000 { + compatible = "mediatek,mt8195-mdp3-color"; + reg = <0x14008000 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + display@14009000 { + compatible = "mediatek,mt8195-mdp3-ovl"; + reg = <0x14009000 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_OVL>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + display@1400a000 { + compatible = "mediatek,mt8195-mdp3-pad"; + reg = <0x1400a000 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_PADDING>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + display@1400b000 { + compatible = "mediatek,mt8195-mdp3-tcc"; + reg = <0x1400b000 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_TCC>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + display@14f1a000 { + compatible = "mediatek,mt8195-mdp3-merge"; + reg = <0x14f1a000 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xa000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; From patchwork Wed Feb 8 09:21:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moudy Ho X-Patchwork-Id: 651939 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2FBE9C05027 for ; Wed, 8 Feb 2023 09:24:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229942AbjBHJYl (ORCPT ); Wed, 8 Feb 2023 04:24:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39340 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230025AbjBHJYB (ORCPT ); Wed, 8 Feb 2023 04:24:01 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B66974670B; Wed, 8 Feb 2023 01:22:20 -0800 (PST) X-UUID: 11a9de1aa79211eda06fc9ecc4dadd91-20230208 DKIM-Signature: v=1; a=rsa-sha256; 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Wed, 08 Feb 2023 17:22:12 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Wed, 8 Feb 2023 17:22:10 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 8 Feb 2023 17:22:10 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Matthias Brugger CC: , , , , , , Moudy Ho Subject: [PATCH v4 04/16] arm64: dts: mediatek: mt8195: add MDP3 nodes Date: Wed, 8 Feb 2023 17:21:57 +0800 Message-ID: <20230208092209.19472-5-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230208092209.19472-1-moudy.ho@mediatek.com> References: <20230208092209.19472-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add device nodes for Media Data Path 3 (MDP3) modules. Signed-off-by: Moudy Ho --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 426 +++++++++++++++++++++++ 1 file changed, 426 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 8fc527570791..0aa7f140897b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1801,6 +1801,135 @@ #clock-cells = <1>; }; + dma-controller@14001000 { + compatible = "mediatek,mt8195-mdp3-rdma"; + reg = <0 0x14001000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>; + mediatek,gce-events = , + ; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>, + <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + iommus = <&iommu_vpp M4U_PORT_L4_MDP_RDMA>, + <&iommu_vpp M4U_PORT_L4_MDP_WROT>; + clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>, + <&topckgen CLK_TOP_CFG_VPP0>, + <&topckgen CLK_TOP_CFG_26M_VPP0>, + <&vppsys0 CLK_VPP0_WARP0_ASYNC_TX>, + <&vppsys0 CLK_VPP0_WARP0_RELAY>, + <&vppsys0 CLK_VPP0_WARP0_MDP_DL_ASYNC>, + <&vppsys0 CLK_VPP0_WARP1_ASYNC_TX>, + <&vppsys0 CLK_VPP0_WARP1_RELAY>, + <&vppsys0 CLK_VPP0_WARP1_MDP_DL_ASYNC>, + <&vppsys0 CLK_VPP0_VPP02VPP1_RELAY>, + <&vppsys1 CLK_VPP1_DL_ASYNC>, + <&vppsys1 CLK_VPP1_VPP0_DL_ASYNC>, + <&vppsys1 CLK_VPP1_VPP0_DL_RELAY>, + <&vppsys0 CLK_VPP0_VPP12VPP0_ASYNC>, + <&vppsys1 CLK_VPP1_VPP0_DL1_RELAY>, + <&vppsys1 CLK_VPP1_SVPP2_VDO0_DL_RELAY>, + <&vppsys1 CLK_VPP1_SVPP3_VDO1_DL_RELAY>, + <&vppsys1 CLK_VPP1_SVPP2_VDO1_DL_RELAY>, + <&vppsys1 CLK_VPP1_SVPP3_VDO0_DL_RELAY>; + mboxes = <&gce1 12 CMDQ_THR_PRIO_1>, + <&gce1 13 CMDQ_THR_PRIO_1>, + <&gce1 14 CMDQ_THR_PRIO_1>, + <&gce1 21 CMDQ_THR_PRIO_1>, + <&gce1 22 CMDQ_THR_PRIO_1>; + #dma-cells = <1>; + }; + + display@14002000 { + compatible = "mediatek,mt8195-mdp3-fg"; + reg = <0 0x14002000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_FG>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + display@14003000 { + compatible = "mediatek,mt8195-mdp3-stitch"; + reg = <0 0x14003000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_STITCH>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + display@14004000 { + compatible = "mediatek,mt8195-mdp3-hdr"; + reg = <0 0x14004000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_HDR>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + display@14005000 { + compatible = "mediatek,mt8195-mdp3-aal"; + reg = <0 0x14005000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_AAL>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + display@14006000 { + compatible = "mediatek,mt8183-mdp3-rsz"; + reg = <0 0x14006000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + display@14007000 { + compatible = "mediatek,mt8195-mdp3-tdshp"; + reg = <0 0x14007000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + display@14008000 { + compatible = "mediatek,mt8195-mdp3-color"; + reg = <0 0x14008000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + display@14009000 { + compatible = "mediatek,mt8195-mdp3-ovl"; + reg = <0 0x14009000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_OVL>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + display@1400a000 { + compatible = "mediatek,mt8195-mdp3-pad"; + reg = <0 0x1400a000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_PADDING>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + display@1400b000 { + compatible = "mediatek,mt8195-mdp3-tcc"; + reg = <0 0x1400b000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_TCC>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + dma-controller@1400c000 { + compatible = "mediatek,mt8183-mdp3-wrot"; + reg = <0 0x1400c000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>; + mediatek,gce-events = , + ; + clocks = <&vppsys0 CLK_VPP0_MDP_WROT>; + iommus = <&iommu_vpp M4U_PORT_L4_MDP_WROT>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + #dma-cells = <1>; + }; + mutex@1400f000 { compatible = "mediatek,mt8195-vpp-mutex"; reg = <0 0x1400f000 0 0x1000>; @@ -1948,6 +2077,303 @@ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; }; + display@14f06000 { + compatible = "mediatek,mt8195-mdp3-split"; + reg = <0 0x14f06000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x6000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_VPP_SPLIT>, + <&vppsys1 CLK_VPP1_HDMI_META>, + <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>, + <&vppsys1 CLK_VPP1_DGI_IN>, + <&vppsys1 CLK_VPP1_DGI_OUT>, + <&vppsys1 CLK_VPP1_VPP_SPLIT_DGI>, + <&vppsys1 CLK_VPP1_VPP_SPLIT_26M>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f07000 { + compatible = "mediatek,mt8195-mdp3-tcc"; + reg = <0 0x14f07000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x7000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TCC>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + dma-controller@14f08000 { + compatible = "mediatek,mt8195-mdp3-rdma"; + reg = <0 0x14f08000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x8000 0x1000>; + mediatek,gce-events = , + ; + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RDMA>, + <&topckgen CLK_TOP_CFG_VPP1>, + <&topckgen CLK_TOP_CFG_26M_VPP1>; + iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_RDMA>, + <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_WROT>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + #dma-cells = <1>; + }; + + dma-controller@14f09000 { + compatible = "mediatek,mt8195-mdp3-rdma"; + reg = <0 0x14f09000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>; + mediatek,gce-events = , + ; + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>, + <&topckgen CLK_TOP_CFG_VPP1>, + <&topckgen CLK_TOP_CFG_26M_VPP1>; + iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_RDMA>, + <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_WROT>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + #dma-cells = <1>; + }; + + dma-controller@14f0a000 { + compatible = "mediatek,mt8195-mdp3-rdma"; + reg = <0 0x14f0a000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>; + mediatek,gce-events = , + ; + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>, + <&topckgen CLK_TOP_CFG_VPP1>, + <&topckgen CLK_TOP_CFG_26M_VPP1>; + iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_RDMA>, + <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_WROT>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + #dma-cells = <1>; + }; + + display@14f0b000 { + compatible = "mediatek,mt8195-mdp3-fg"; + reg = <0 0x14f0b000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xb000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_FG>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f0c000 { + compatible = "mediatek,mt8195-mdp3-fg"; + reg = <0 0x14f0c000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_FG>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f0d000 { + compatible = "mediatek,mt8195-mdp3-fg"; + reg = <0 0x14f0d000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_FG>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f0e000 { + compatible = "mediatek,mt8195-mdp3-hdr"; + reg = <0 0x14f0e000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xe000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_HDR>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f0f000 { + compatible = "mediatek,mt8195-mdp3-hdr"; + reg = <0 0x14f0f000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_HDR>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f10000 { + compatible = "mediatek,mt8195-mdp3-hdr"; + reg = <0 0x14f10000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_HDR>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f11000 { + compatible = "mediatek,mt8195-mdp3-aal"; + reg = <0 0x14f11000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x1000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_AAL>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f12000 { + compatible = "mediatek,mt8195-mdp3-aal"; + reg = <0 0x14f12000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_AAL>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f13000 { + compatible = "mediatek,mt8195-mdp3-aal"; + reg = <0 0x14f13000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_AAL>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f14000 { + compatible = "mediatek,mt8183-mdp3-rsz"; + reg = <0 0x14f14000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x4000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RSZ>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f15000 { + compatible = "mediatek,mt8183-mdp3-rsz"; + reg = <0 0x14f15000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>, + <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f16000 { + compatible = "mediatek,mt8183-mdp3-rsz"; + reg = <0 0x14f16000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>, + <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f17000 { + compatible = "mediatek,mt8195-mdp3-tdshp"; + reg = <0 0x14f17000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x7000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TDSHP>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f18000 { + compatible = "mediatek,mt8195-mdp3-tdshp"; + reg = <0 0x14f18000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f19000 { + compatible = "mediatek,mt8195-mdp3-tdshp"; + reg = <0 0x14f19000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f1a000 { + compatible = "mediatek,mt8195-mdp3-merge"; + reg = <0 0x14f1a000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xa000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f1b000 { + compatible = "mediatek,mt8195-mdp3-merge"; + reg = <0 0x14f1b000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xb000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f1c000 { + compatible = "mediatek,mt8195-mdp3-color"; + reg = <0 0x14f1c000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xc000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_COLOR>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f1d000 { + compatible = "mediatek,mt8195-mdp3-color"; + reg = <0 0x14f1d000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_COLOR>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f1e000 { + compatible = "mediatek,mt8195-mdp3-color"; + reg = <0 0x14f1e000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_COLOR>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f1f000 { + compatible = "mediatek,mt8195-mdp3-ovl"; + reg = <0 0x14f1f000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xf000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_OVL>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f20000 { + compatible = "mediatek,mt8195-mdp3-pad"; + reg = <0 0x14f20000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP1_VPP_PAD>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f21000 { + compatible = "mediatek,mt8195-mdp3-pad"; + reg = <0 0x14f21000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x1000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_PAD>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f22000 { + compatible = "mediatek,mt8195-mdp3-pad"; + reg = <0 0x14f22000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x2000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_PAD>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + dma-controller@14f23000 { + compatible = "mediatek,mt8183-mdp3-wrot"; + reg = <0 0x14f23000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x3000 0x1000>; + mediatek,gce-events = , + ; + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_WROT>; + iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_WROT>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + #dma-cells = <1>; + }; + + dma-controller@14f24000 { + compatible = "mediatek,mt8183-mdp3-wrot"; + reg = <0 0x14f24000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x4000 0x1000>; + mediatek,gce-events = , + ; + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>; + iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_WROT>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + #dma-cells = <1>; + }; + + dma-controller@14f25000 { + compatible = "mediatek,mt8183-mdp3-wrot"; + reg = <0 0x14f25000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x5000 0x1000>; + mediatek,gce-events = , + ; + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>; + iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_WROT>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + #dma-cells = <1>; + }; + imgsys: clock-controller@15000000 { compatible = "mediatek,mt8195-imgsys"; reg = <0 0x15000000 0 0x1000>; From patchwork Wed Feb 8 09:22:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moudy Ho X-Patchwork-Id: 651941 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A979C636CC for ; Wed, 8 Feb 2023 09:24:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231489AbjBHJYg (ORCPT ); Wed, 8 Feb 2023 04:24:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39042 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229781AbjBHJYB (ORCPT ); Wed, 8 Feb 2023 04:24:01 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A57946723; Wed, 8 Feb 2023 01:22:21 -0800 (PST) X-UUID: 121e561ea79211ed945fc101203acc17-20230208 DKIM-Signature: v=1; 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Wed, 08 Feb 2023 17:22:12 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 8 Feb 2023 17:22:11 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 8 Feb 2023 17:22:11 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Matthias Brugger CC: , , , , , , Moudy Ho Subject: [PATCH v4 08/16] media: platform: mtk-mdp3: introduce more MDP3 components Date: Wed, 8 Feb 2023 17:22:01 +0800 Message-ID: <20230208092209.19472-9-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230208092209.19472-1-moudy.ho@mediatek.com> References: <20230208092209.19472-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add configuration of more components in MT8195 MDP3. Signed-off-by: Moudy Ho --- .../platform/mediatek/mdp3/mdp_reg_aal.h | 25 ++++++ .../platform/mediatek/mdp3/mdp_reg_color.h | 31 +++++++ .../media/platform/mediatek/mdp3/mdp_reg_fg.h | 23 +++++ .../platform/mediatek/mdp3/mdp_reg_hdr.h | 31 +++++++ .../platform/mediatek/mdp3/mdp_reg_merge.h | 25 ++++++ .../platform/mediatek/mdp3/mdp_reg_ovl.h | 25 ++++++ .../platform/mediatek/mdp3/mdp_reg_pad.h | 21 +++++ .../platform/mediatek/mdp3/mdp_reg_rdma.h | 24 ++++++ .../platform/mediatek/mdp3/mdp_reg_rsz.h | 2 + .../platform/mediatek/mdp3/mdp_reg_tdshp.h | 34 ++++++++ .../platform/mediatek/mdp3/mdp_reg_wrot.h | 8 ++ .../platform/mediatek/mdp3/mtk-mdp3-comp.h | 85 +++++++++++++++---- 12 files changed, 318 insertions(+), 16 deletions(-) create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_aal.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_color.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_fg.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_hdr.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_merge.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_ovl.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_pad.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_tdshp.h diff --git a/drivers/media/platform/mediatek/mdp3/mdp_reg_aal.h b/drivers/media/platform/mediatek/mdp3/mdp_reg_aal.h new file mode 100644 index 000000000000..4b9513e54543 --- /dev/null +++ b/drivers/media/platform/mediatek/mdp3/mdp_reg_aal.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Ping-Hsun Wu + */ + +#ifndef __MDP_REG_AAL_H__ +#define __MDP_REG_AAL_H__ + +#define MDP_AAL_EN (0x000) +#define MDP_AAL_CFG (0x020) +#define MDP_AAL_SIZE (0x030) +#define MDP_AAL_OUTPUT_SIZE (0x034) +#define MDP_AAL_OUTPUT_OFFSET (0x038) +#define MDP_AAL_CFG_MAIN (0x200) + +/* MASK */ +#define MDP_AAL_EN_MASK (0x01) +#define MDP_AAL_CFG_MASK (0x70FF00B3) +#define MDP_AAL_SIZE_MASK (0x1FFF1FFF) +#define MDP_AAL_OUTPUT_SIZE_MASK (0x1FFF1FFF) +#define MDP_AAL_OUTPUT_OFFSET_MASK (0x0FF00FF) +#define MDP_AAL_CFG_MAIN_MASK (0x0FE) + +#endif // __MDP_REG_AAL_H__ diff --git a/drivers/media/platform/mediatek/mdp3/mdp_reg_color.h b/drivers/media/platform/mediatek/mdp3/mdp_reg_color.h new file mode 100644 index 000000000000..f72503975b24 --- /dev/null +++ b/drivers/media/platform/mediatek/mdp3/mdp_reg_color.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Ping-Hsun Wu + */ + +#ifndef __MDP_REG_COLOR_H__ +#define __MDP_REG_COLOR_H__ + +#define MDP_COLOR_WIN_X_MAIN (0x40C) +#define MDP_COLOR_WIN_Y_MAIN (0x410) +#define MDP_COLOR_START (0xC00) +#define MDP_COLOR_INTEN (0xC04) +#define MDP_COLOR_OUT_SEL (0xC0C) +#define MDP_COLOR_INTERNAL_IP_WIDTH (0xC50) +#define MDP_COLOR_INTERNAL_IP_HEIGHT (0xC54) +#define MDP_COLOR_CM1_EN (0xC60) +#define MDP_COLOR_CM2_EN (0xCA0) + +/* MASK */ +#define MDP_COLOR_WIN_X_MAIN_MASK (0xFFFFFFFF) +#define MDP_COLOR_WIN_Y_MAIN_MASK (0xFFFFFFFF) +#define MDP_COLOR_START_MASK (0x0FF013F) +#define MDP_COLOR_INTEN_MASK (0x07) +#define MDP_COLOR_OUT_SEL_MASK (0x0777) +#define MDP_COLOR_INTERNAL_IP_WIDTH_MASK (0x03FFF) +#define MDP_COLOR_INTERNAL_IP_HEIGHT_MASK (0x03FFF) +#define MDP_COLOR_CM1_EN_MASK (0x03) +#define MDP_COLOR_CM2_EN_MASK (0x017) + +#endif // __MDP_REG_COLOR_H__ diff --git a/drivers/media/platform/mediatek/mdp3/mdp_reg_fg.h b/drivers/media/platform/mediatek/mdp3/mdp_reg_fg.h new file mode 100644 index 000000000000..d90bcad33a59 --- /dev/null +++ b/drivers/media/platform/mediatek/mdp3/mdp_reg_fg.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Ping-Hsun Wu + */ + +#ifndef __MDP_REG_FG_H__ +#define __MDP_REG_FG_H__ + +#define MDP_FG_TRIGGER (0x0) +#define MDP_FG_FG_CTRL_0 (0x20) +#define MDP_FG_FG_CK_EN (0x24) +#define MDP_FG_TILE_INFO_0 (0x418) +#define MDP_FG_TILE_INFO_1 (0x41c) + +/* MASK */ +#define MDP_FG_TRIGGER_MASK (0x00000007) +#define MDP_FG_FG_CTRL_0_MASK (0x00000033) +#define MDP_FG_FG_CK_EN_MASK (0x0000000F) +#define MDP_FG_TILE_INFO_0_MASK (0xFFFFFFFF) +#define MDP_FG_TILE_INFO_1_MASK (0xFFFFFFFF) + +#endif //__MDP_REG_FG_H__ diff --git a/drivers/media/platform/mediatek/mdp3/mdp_reg_hdr.h b/drivers/media/platform/mediatek/mdp3/mdp_reg_hdr.h new file mode 100644 index 000000000000..c19fbba39fc0 --- /dev/null +++ b/drivers/media/platform/mediatek/mdp3/mdp_reg_hdr.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Ping-Hsun Wu + */ + +#ifndef __MDP_REG_HDR_H__ +#define __MDP_REG_HDR_H__ + +#define MDP_HDR_TOP (0x000) +#define MDP_HDR_RELAY (0x004) +#define MDP_HDR_SIZE_0 (0x014) +#define MDP_HDR_SIZE_1 (0x018) +#define MDP_HDR_SIZE_2 (0x01C) +#define MDP_HDR_HIST_CTRL_0 (0x020) +#define MDP_HDR_HIST_CTRL_1 (0x024) +#define MDP_HDR_HIST_ADDR (0x0DC) +#define MDP_HDR_TILE_POS (0x118) + +/* MASK */ +#define MDP_HDR_RELAY_MASK (0x01) +#define MDP_HDR_TOP_MASK (0xFF0FEB6D) +#define MDP_HDR_SIZE_0_MASK (0x1FFF1FFF) +#define MDP_HDR_SIZE_1_MASK (0x1FFF1FFF) +#define MDP_HDR_SIZE_2_MASK (0x1FFF1FFF) +#define MDP_HDR_HIST_CTRL_0_MASK (0x1FFF1FFF) +#define MDP_HDR_HIST_CTRL_1_MASK (0x1FFF1FFF) +#define MDP_HDR_HIST_ADDR_MASK (0xBF3F2F3F) +#define MDP_HDR_TILE_POS_MASK (0x1FFF1FFF) + +#endif // __MDP_REG_HDR_H__ diff --git a/drivers/media/platform/mediatek/mdp3/mdp_reg_merge.h b/drivers/media/platform/mediatek/mdp3/mdp_reg_merge.h new file mode 100644 index 000000000000..46be27e2a656 --- /dev/null +++ b/drivers/media/platform/mediatek/mdp3/mdp_reg_merge.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Ping-Hsun Wu + */ + +#ifndef __MDP_REG_MERGE_H__ +#define __MDP_REG_MERGE_H__ + +#define MDP_MERGE_ENABLE (0x000) +#define MDP_MERGE_CFG_0 (0x010) +#define MDP_MERGE_CFG_4 (0x020) +#define MDP_MERGE_CFG_12 (0x040) +#define MDP_MERGE_CFG_24 (0x070) +#define MDP_MERGE_CFG_25 (0x074) + +/* MASK */ +#define MDP_MERGE_ENABLE_MASK (0xFFFFFFFF) +#define MDP_MERGE_CFG_0_MASK (0xFFFFFFFF) +#define MDP_MERGE_CFG_4_MASK (0xFFFFFFFF) +#define MDP_MERGE_CFG_12_MASK (0xFFFFFFFF) +#define MDP_MERGE_CFG_24_MASK (0xFFFFFFFF) +#define MDP_MERGE_CFG_25_MASK (0xFFFFFFFF) + +#endif //__MDP_REG_MERGE_H__ diff --git a/drivers/media/platform/mediatek/mdp3/mdp_reg_ovl.h b/drivers/media/platform/mediatek/mdp3/mdp_reg_ovl.h new file mode 100644 index 000000000000..21d2d0323293 --- /dev/null +++ b/drivers/media/platform/mediatek/mdp3/mdp_reg_ovl.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Ping-Hsun Wu + */ + +#ifndef __MDP_REG_OVL_H__ +#define __MDP_REG_OVL_H__ + +#define MDP_OVL_EN (0x00c) +#define MDP_OVL_ROI_SIZE (0x020) +#define MDP_OVL_DP_CON (0x024) +#define MDP_OVL_SRC_CON (0x02c) +#define MDP_OVL_L0_CON (0x030) +#define MDP_OVL_L0_SRC_SIZE (0x038) + +/* MASK */ +#define MDP_OVL_DP_CON_MASK (0x0FFFFFFF) +#define MDP_OVL_EN_MASK (0xB07D07B1) +#define MDP_OVL_L0_CON_MASK (0xFFFFFFFF) +#define MDP_OVL_L0_SRC_SIZE_MASK (0x1FFF1FFF) +#define MDP_OVL_ROI_SIZE_MASK (0x1FFF1FFF) +#define MDP_OVL_SRC_CON_MASK (0x0000031F) + +#endif //__MDP_REG_OVL_H__ diff --git a/drivers/media/platform/mediatek/mdp3/mdp_reg_pad.h b/drivers/media/platform/mediatek/mdp3/mdp_reg_pad.h new file mode 100644 index 000000000000..0e89f1db19ed --- /dev/null +++ b/drivers/media/platform/mediatek/mdp3/mdp_reg_pad.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Ping-Hsun Wu + */ + +#ifndef __MDP_REG_PAD_H__ +#define __MDP_REG_PAD_H__ + +#define MDP_PAD_CON (0x000) +#define MDP_PAD_PIC_SIZE (0x004) +#define MDP_PAD_W_SIZE (0x008) +#define MDP_PAD_H_SIZE (0x00c) + +/* MASK */ +#define MDP_PAD_CON_MASK (0x00000007) +#define MDP_PAD_PIC_SIZE_MASK (0xFFFFFFFF) +#define MDP_PAD_W_SIZE_MASK (0x1FFF1FFF) +#define MDP_PAD_H_SIZE_MASK (0x1FFF1FFF) + +#endif // __MDP_REG_PAD_H__ diff --git a/drivers/media/platform/mediatek/mdp3/mdp_reg_rdma.h b/drivers/media/platform/mediatek/mdp3/mdp_reg_rdma.h index be4065e252d3..0affb2a3b958 100644 --- a/drivers/media/platform/mediatek/mdp3/mdp_reg_rdma.h +++ b/drivers/media/platform/mediatek/mdp3/mdp_reg_rdma.h @@ -26,6 +26,18 @@ #define MDP_RDMA_SRC_OFFSET_2 0x128 #define MDP_RDMA_SRC_OFFSET_0_P 0x148 #define MDP_RDMA_TRANSFORM_0 0x200 +#define MDP_RDMA_DMABUF_CON_0 0x240 +#define MDP_RDMA_ULTRA_TH_HIGH_CON_0 0x248 +#define MDP_RDMA_ULTRA_TH_LOW_CON_0 0x250 +#define MDP_RDMA_DMABUF_CON_1 0x258 +#define MDP_RDMA_ULTRA_TH_HIGH_CON_1 0x260 +#define MDP_RDMA_ULTRA_TH_LOW_CON_1 0x268 +#define MDP_RDMA_DMABUF_CON_2 0x270 +#define MDP_RDMA_ULTRA_TH_HIGH_CON_2 0x278 +#define MDP_RDMA_ULTRA_TH_LOW_CON_2 0x280 +#define MDP_RDMA_DMABUF_CON_3 0x288 +#define MDP_RDMA_ULTRA_TH_HIGH_CON_3 0x290 +#define MDP_RDMA_ULTRA_TH_LOW_CON_3 0x298 #define MDP_RDMA_RESV_DUMMY_0 0x2a0 #define MDP_RDMA_MON_STA_1 0x408 #define MDP_RDMA_SRC_BASE_0 0xf00 @@ -54,6 +66,18 @@ #define MDP_RDMA_SRC_OFFSET_2_MASK 0xffffffff #define MDP_RDMA_SRC_OFFSET_0_P_MASK 0xffffffff #define MDP_RDMA_TRANSFORM_0_MASK 0xff110777 +#define MDP_RDMA_DMABUF_CON_0_MASK 0x0fff00ff +#define MDP_RDMA_ULTRA_TH_HIGH_CON_0_MASK 0x3fffffff +#define MDP_RDMA_ULTRA_TH_LOW_CON_0_MASK 0x3fffffff +#define MDP_RDMA_DMABUF_CON_1_MASK 0x0f7f007f +#define MDP_RDMA_ULTRA_TH_HIGH_CON_1_MASK 0x3fffffff +#define MDP_RDMA_ULTRA_TH_LOW_CON_1_MASK 0x3fffffff +#define MDP_RDMA_DMABUF_CON_2_MASK 0x0f3f003f +#define MDP_RDMA_ULTRA_TH_HIGH_CON_2_MASK 0x3fffffff +#define MDP_RDMA_ULTRA_TH_LOW_CON_2_MASK 0x3fffffff +#define MDP_RDMA_DMABUF_CON_3_MASK 0x0f3f003f +#define MDP_RDMA_ULTRA_TH_HIGH_CON_3_MASK 0x3fffffff +#define MDP_RDMA_ULTRA_TH_LOW_CON_3_MASK 0x3fffffff #define MDP_RDMA_RESV_DUMMY_0_MASK 0xffffffff #define MDP_RDMA_MON_STA_1_MASK 0xffffffff #define MDP_RDMA_SRC_BASE_0_MASK 0xffffffff diff --git a/drivers/media/platform/mediatek/mdp3/mdp_reg_rsz.h b/drivers/media/platform/mediatek/mdp3/mdp_reg_rsz.h index 484f6d60641f..187531db8e3b 100644 --- a/drivers/media/platform/mediatek/mdp3/mdp_reg_rsz.h +++ b/drivers/media/platform/mediatek/mdp3/mdp_reg_rsz.h @@ -20,6 +20,7 @@ #define PRZ_LUMA_VERTICAL_SUBPIXEL_OFFSET 0x02c #define PRZ_CHROMA_HORIZONTAL_INTEGER_OFFSET 0x030 #define PRZ_CHROMA_HORIZONTAL_SUBPIXEL_OFFSET 0x034 +#define RSZ_ETC_CONTROL 0x22c /* MASK */ #define PRZ_ENABLE_MASK 0x00010001 @@ -35,5 +36,6 @@ #define PRZ_LUMA_VERTICAL_SUBPIXEL_OFFSET_MASK 0x001fffff #define PRZ_CHROMA_HORIZONTAL_INTEGER_OFFSET_MASK 0x0000ffff #define PRZ_CHROMA_HORIZONTAL_SUBPIXEL_OFFSET_MASK 0x001fffff +#define RSZ_ETC_CONTROL_MASK 0xff770000 #endif // __MDP_REG_RSZ_H__ diff --git a/drivers/media/platform/mediatek/mdp3/mdp_reg_tdshp.h b/drivers/media/platform/mediatek/mdp3/mdp_reg_tdshp.h new file mode 100644 index 000000000000..83b5f9b432d8 --- /dev/null +++ b/drivers/media/platform/mediatek/mdp3/mdp_reg_tdshp.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Ping-Hsun Wu + */ + +#ifndef __MDP_REG_TDSHP_H__ +#define __MDP_REG_TDSHP_H__ + +#define MDP_HIST_CFG_00 (0x064) +#define MDP_HIST_CFG_01 (0x068) +#define MDP_TDSHP_CTRL (0x100) +#define MDP_TDSHP_CFG (0x110) +#define MDP_TDSHP_INPUT_SIZE (0x120) +#define MDP_TDSHP_OUTPUT_OFFSET (0x124) +#define MDP_TDSHP_OUTPUT_SIZE (0x128) +#define MDP_LUMA_HIST_INIT (0x200) +#define MDP_DC_TWO_D_W1_RESULT_INIT (0x260) +#define MDP_CONTOUR_HIST_INIT (0x398) + +/* MASK */ +#define MDP_HIST_CFG_00_MASK (0xFFFFFFFF) +#define MDP_HIST_CFG_01_MASK (0xFFFFFFFF) +#define MDP_LUMA_HIST_MASK (0xFFFFFFFF) +#define MDP_TDSHP_CTRL_MASK (0x07) +#define MDP_TDSHP_CFG_MASK (0x03F7) +#define MDP_TDSHP_INPUT_SIZE_MASK (0x1FFF1FFF) +#define MDP_TDSHP_OUTPUT_OFFSET_MASK (0x0FF00FF) +#define MDP_TDSHP_OUTPUT_SIZE_MASK (0x1FFF1FFF) +#define MDP_LUMA_HIST_INIT_MASK (0xFFFFFFFF) +#define MDP_DC_TWO_D_W1_RESULT_INIT_MASK (0x007FFFFF) +#define MDP_CONTOUR_HIST_INIT_MASK (0xFFFFFFFF) + +#endif // __MDP_REG_TDSHP_H__ diff --git a/drivers/media/platform/mediatek/mdp3/mdp_reg_wrot.h b/drivers/media/platform/mediatek/mdp3/mdp_reg_wrot.h index 6d3ff0e2b672..b6f016d2c29d 100644 --- a/drivers/media/platform/mediatek/mdp3/mdp_reg_wrot.h +++ b/drivers/media/platform/mediatek/mdp3/mdp_reg_wrot.h @@ -17,14 +17,18 @@ #define VIDO_STRIDE 0x030 #define VIDO_OFST_ADDR_C 0x038 #define VIDO_STRIDE_C 0x03c +#define VIDO_CTRL_2 0x048 #define VIDO_DITHER 0x054 #define VIDO_STRIDE_V 0x06c #define VIDO_OFST_ADDR_V 0x068 #define VIDO_RSV_1 0x070 +#define VIDO_DMA_PREULTRA 0x074 #define VIDO_IN_SIZE 0x078 #define VIDO_ROT_EN 0x07c #define VIDO_FIFO_TEST 0x080 #define VIDO_MAT_CTRL 0x084 +#define VIDO_SCAN_10BIT 0x0dc +#define VIDO_PENDING_ZERO 0x0e0 #define VIDO_BASE_ADDR 0xf00 #define VIDO_BASE_ADDR_C 0xf04 #define VIDO_BASE_ADDR_V 0xf08 @@ -40,14 +44,18 @@ #define VIDO_STRIDE_MASK 0x0000ffff #define VIDO_OFST_ADDR_C_MASK 0x0fffffff #define VIDO_STRIDE_C_MASK 0x0000ffff +#define VIDO_CTRL_2_MASK 0x0000000f #define VIDO_DITHER_MASK 0xff000001 #define VIDO_STRIDE_V_MASK 0x0000ffff #define VIDO_OFST_ADDR_V_MASK 0x0fffffff #define VIDO_RSV_1_MASK 0xffffffff +#define VIDO_DMA_PREULTRA_MASK 0x00ffffff #define VIDO_IN_SIZE_MASK 0x1fff1fff #define VIDO_ROT_EN_MASK 0x00000001 #define VIDO_FIFO_TEST_MASK 0x00000fff #define VIDO_MAT_CTRL_MASK 0x000000f3 +#define VIDO_SCAN_10BIT_MASK 0x0000000f +#define VIDO_PENDING_ZERO_MASK 0x07ffffff #define VIDO_BASE_ADDR_MASK 0xffffffff #define VIDO_BASE_ADDR_C_MASK 0xffffffff #define VIDO_BASE_ADDR_V_MASK 0xffffffff diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h index ddc6b654864a..09e46dfe4f02 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h @@ -84,22 +84,66 @@ enum mtk_mdp_comp_id { MDP_COMP_CAMIN, /* 9 */ MDP_COMP_CAMIN2, /* 10 */ MDP_COMP_RDMA0, /* 11 */ - MDP_COMP_AAL0, /* 12 */ - MDP_COMP_CCORR0, /* 13 */ - MDP_COMP_RSZ0, /* 14 */ - MDP_COMP_RSZ1, /* 15 */ - MDP_COMP_TDSHP0, /* 16 */ - MDP_COMP_COLOR0, /* 17 */ - MDP_COMP_PATH0_SOUT, /* 18 */ - MDP_COMP_PATH1_SOUT, /* 19 */ - MDP_COMP_WROT0, /* 20 */ - MDP_COMP_WDMA, /* 21 */ - - /* Dummy Engine */ - MDP_COMP_RDMA1, /* 22 */ - MDP_COMP_RSZ2, /* 23 */ - MDP_COMP_TDSHP1, /* 24 */ - MDP_COMP_WROT1, /* 25 */ + MDP_COMP_RDMA1, /* 12 */ + MDP_COMP_RDMA2, /* 13 */ + MDP_COMP_RDMA3, /* 14 */ + MDP_COMP_AAL0, /* 15 */ + MDP_COMP_AAL1, /* 16 */ + MDP_COMP_AAL2, /* 17 */ + MDP_COMP_AAL3, /* 18 */ + MDP_COMP_CCORR0, /* 19 */ + MDP_COMP_RSZ0, /* 20 */ + MDP_COMP_RSZ1, /* 21 */ + MDP_COMP_RSZ2, /* 22 */ + MDP_COMP_RSZ3, /* 23 */ + MDP_COMP_TDSHP0, /* 24 */ + MDP_COMP_TDSHP1, /* 25 */ + MDP_COMP_TDSHP2, /* 26 */ + MDP_COMP_TDSHP3, /* 27 */ + MDP_COMP_COLOR0, /* 28 */ + MDP_COMP_COLOR1, /* 29 */ + MDP_COMP_COLOR2, /* 30 */ + MDP_COMP_COLOR3, /* 31 */ + MDP_COMP_PATH0_SOUT, /* 32 */ + MDP_COMP_PATH1_SOUT, /* 33 */ + MDP_COMP_WROT0, /* 34 */ + MDP_COMP_WROT1, /* 35 */ + MDP_COMP_WROT2, /* 36 */ + MDP_COMP_WROT3, /* 37 */ + MDP_COMP_WDMA, /* 38 */ + MDP_COMP_SPLIT, /* 39 */ + MDP_COMP_SPLIT2, /* 40 */ + MDP_COMP_STITCH, /* 41 */ + MDP_COMP_FG0, /* 42 */ + MDP_COMP_FG1, /* 43 */ + MDP_COMP_FG2, /* 44 */ + MDP_COMP_FG3, /* 45 */ + MDP_COMP_TO_SVPP2MOUT, /* 46 */ + MDP_COMP_TO_SVPP3MOUT, /* 47 */ + MDP_COMP_TO_WARP0MOUT, /* 48 */ + MDP_COMP_TO_WARP1MOUT, /* 49 */ + MDP_COMP_VPP0_SOUT, /* 50 */ + MDP_COMP_VPP1_SOUT, /* 51 */ + MDP_COMP_PQ0_SOUT, /* 52 */ + MDP_COMP_PQ1_SOUT, /* 53 */ + MDP_COMP_HDR0, /* 54 */ + MDP_COMP_HDR1, /* 55 */ + MDP_COMP_HDR2, /* 56 */ + MDP_COMP_HDR3, /* 57 */ + MDP_COMP_OVL0, /* 58 */ + MDP_COMP_OVL1, /* 59 */ + MDP_COMP_PAD0, /* 60 */ + MDP_COMP_PAD1, /* 61 */ + MDP_COMP_PAD2, /* 62 */ + MDP_COMP_PAD3, /* 63 */ + MDP_COMP_TCC0, /* 64 */ + MDP_COMP_TCC1, /* 65 */ + MDP_COMP_MERGE2, /* 66 */ + MDP_COMP_MERGE3, /* 67 */ + MDP_COMP_VDO0DL0, /* 68 */ + MDP_COMP_VDO1DL0, /* 69 */ + MDP_COMP_VDO0DL1, /* 70 */ + MDP_COMP_VDO1DL1, /* 71 */ MDP_MAX_COMP_COUNT /* ALWAYS keep at the end */ }; @@ -117,12 +161,21 @@ enum mdp_comp_type { MDP_COMP_TYPE_COLOR, MDP_COMP_TYPE_DRE, MDP_COMP_TYPE_CCORR, + MDP_COMP_TYPE_AAL, + MDP_COMP_TYPE_TCC, MDP_COMP_TYPE_HDR, + MDP_COMP_TYPE_SPLIT, + MDP_COMP_TYPE_STITCH, + MDP_COMP_TYPE_FG, + MDP_COMP_TYPE_OVL, + MDP_COMP_TYPE_PAD, + MDP_COMP_TYPE_MERGE, MDP_COMP_TYPE_IMGI, MDP_COMP_TYPE_WPEI, MDP_COMP_TYPE_EXTO, /* External path */ MDP_COMP_TYPE_DL_PATH, /* Direct-link path */ + MDP_COMP_TYPE_DUMMY, MDP_COMP_TYPE_COUNT /* ALWAYS keep at the end */ }; From patchwork Wed Feb 8 09:22:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moudy Ho X-Patchwork-Id: 651944 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F50EC64ED8 for ; Wed, 8 Feb 2023 09:24:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229934AbjBHJYb (ORCPT ); Wed, 8 Feb 2023 04:24:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39440 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231143AbjBHJX6 (ORCPT ); Wed, 8 Feb 2023 04:23:58 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DC42D460A7; Wed, 8 Feb 2023 01:22:18 -0800 (PST) X-UUID: 12af0b6ea79211eda06fc9ecc4dadd91-20230208 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; 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17:22:13 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 8 Feb 2023 17:22:11 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 8 Feb 2023 17:22:11 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Matthias Brugger CC: , , , , , , Moudy Ho Subject: [PATCH v4 10/16] media: platform: mtk-mdp3: avoid multiple driver registrations Date: Wed, 8 Feb 2023 17:22:03 +0800 Message-ID: <20230208092209.19472-11-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230208092209.19472-1-moudy.ho@mediatek.com> References: <20230208092209.19472-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The number of MDP3 driver probes depends on the registered clocks of MMSYS. Because VPPSYS0 and VPPSYS1 are used in MT8195 MDP3, it is necessary to avoid multiple driver registrations. Signed-off-by: Moudy Ho --- drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c | 1 + drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c | 9 ++++++++- drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h | 1 + 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c index eafd2fbe39a0..0c65b64c6266 100644 --- a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c +++ b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c @@ -410,6 +410,7 @@ static const struct mdp_pipe_info mt8183_pipe_info[] = { const struct mtk_mdp_driver_data mt8183_mdp_driver_data = { .mdp_plat_id = MT8183, + .mdp_con_res = 0x14001000, .mdp_probe_infra = mt8183_mdp_probe_infra, .mdp_cfg = &mt8183_plat_cfg, .mdp_mutex_table_idx = mt8183_mutex_idx, diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c index bf64f88c29fe..09cad71aef69 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c @@ -161,6 +161,7 @@ static int mdp_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct mdp_dev *mdp; struct platform_device *mm_pdev, *mm2_pdev; + struct resource *res; int ret, i, mutex_id; mdp = kzalloc(sizeof(*mdp), GFP_KERNEL); @@ -172,6 +173,12 @@ static int mdp_probe(struct platform_device *pdev) mdp->pdev = pdev; mdp->mdp_data = of_device_get_match_data(&pdev->dev); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res->start != mdp->mdp_data->mdp_con_res) { + platform_set_drvdata(pdev, mdp); + goto success_return; + } + mm_pdev = __get_pdev_by_id(pdev, NULL, MDP_INFRA_MMSYS); if (IS_ERR_OR_NULL(mm_pdev)) { ret = -ENODEV; @@ -209,7 +216,6 @@ static int mdp_probe(struct platform_device *pdev) p = (id && mm2_pdev) ? mm2_pdev : mm_pdev; m = (id && mm2_pdev) ? mdp->mdp_mutex2 : mdp->mdp_mutex; - if (m[mutex_id]) continue; m[mutex_id] = mtk_mutex_get(&p->dev); @@ -278,6 +284,7 @@ static int mdp_probe(struct platform_device *pdev) goto err_unregister_device; } +success_return: dev_dbg(dev, "mdp-%d registered successfully\n", pdev->id); return 0; diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h index e4ffa25b9271..a063a655248c 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h @@ -61,6 +61,7 @@ enum mdp_pipe_id { struct mtk_mdp_driver_data { const int mdp_plat_id; + const resource_size_t mdp_con_res; const struct of_device_id *mdp_probe_infra; const struct mdp_platform_config *mdp_cfg; const u32 *mdp_mutex_table_idx; From patchwork Wed Feb 8 09:22:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moudy Ho X-Patchwork-Id: 651942 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5EB93C6FA95 for ; Wed, 8 Feb 2023 09:24:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230340AbjBHJYe (ORCPT ); Wed, 8 Feb 2023 04:24:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39444 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229822AbjBHJYA (ORCPT ); Wed, 8 Feb 2023 04:24:00 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F09446708; Wed, 8 Feb 2023 01:22:20 -0800 (PST) X-UUID: 125da76aa79211ed945fc101203acc17-20230208 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=FT0LWsd9AjDEQ7vWn5+ZXoEKaeXKNpvThm2222pl+LI=; b=AP1rhTx589qTdqyf28NkYxh9I17ojNxxYFdG+boFEN6/tG1/yjxT+qe0ONX0vkMaINzAspnVPBEIZZZfnsOY7VL3WX4yyStA34yscC3ajQBXSnWZMGFuuoGKYGL7OpTcFRpcYEwWlRkVp6Wfk4/8XILoLQ8tGJybcqut+fHTJo0=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.19, REQID:70d09a6b-189e-4afa-bc2d-512d3be79cbf, IP:0, U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:885ddb2, CLOUDID:ffd7aa56-dd49-462e-a4be-2143a3ddc739, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0 X-CID-BVR: 0,NGT X-UUID: 125da76aa79211ed945fc101203acc17-20230208 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1660909357; Wed, 08 Feb 2023 17:22:13 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Wed, 8 Feb 2023 17:22:12 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 8 Feb 2023 17:22:11 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Matthias Brugger CC: , , , , , , Moudy Ho Subject: [PATCH v4 11/16] media: platform: mtk-mdp3: extend GCE event waiting in RDMA and WROT Date: Wed, 8 Feb 2023 17:22:04 +0800 Message-ID: <20230208092209.19472-12-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230208092209.19472-1-moudy.ho@mediatek.com> References: <20230208092209.19472-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Support for multiple RDMA/WROT waits for GCE events. Signed-off-by: Moudy Ho --- .../media/platform/mediatek/mdp3/mdp_cfg_data.c | 2 ++ .../platform/mediatek/mdp3/mtk-mdp3-comp.c | 17 +++++++++++------ .../platform/mediatek/mdp3/mtk-mdp3-core.h | 2 ++ 3 files changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c index 0c65b64c6266..eafb0c235867 100644 --- a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c +++ b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c @@ -56,8 +56,10 @@ static const struct mdp_platform_config mt8183_plat_cfg = { .rdma_support_10bit = true, .rdma_rsz1_sram_sharing = true, .rdma_upsample_repeat_only = true, + .rdma_event_num = 1, .rsz_disable_dcm_small_sample = false, .wrot_filter_constraint = false, + .wrot_event_num = 1, }; static const u32 mt8183_mutex_idx[MDP_MAX_COMP_COUNT] = { diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c index 75c92e282fa2..3d6cf55153f1 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c @@ -251,14 +251,17 @@ static int config_rdma_subfrm(struct mdp_comp_ctx *ctx, static int wait_rdma_event(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) { + const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx); struct device *dev = &ctx->comp->mdp_dev->pdev->dev; phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; - if (ctx->comp->alias_id == 0) + if (ctx->comp->alias_id < mdp_cfg->rdma_event_num) { MM_REG_WAIT(cmd, ctx->comp->gce_event[MDP_GCE_EVENT_EOF]); - else - dev_err(dev, "Do not support RDMA1_DONE event\n"); + } else { + dev_err(dev, "Invalid RDMA event %d\n", ctx->comp->alias_id); + return -EINVAL; + } /* Disable RDMA */ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_EN, 0x0, BIT(0)); @@ -553,10 +556,12 @@ static int wait_wrot_event(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; - if (ctx->comp->alias_id == 0) + if (ctx->comp->alias_id < mdp_cfg->wrot_event_num) { MM_REG_WAIT(cmd, ctx->comp->gce_event[MDP_GCE_EVENT_EOF]); - else - dev_err(dev, "Do not support WROT1_DONE event\n"); + } else { + dev_err(dev, "Invalid WROT event %d!\n", ctx->comp->alias_id); + return -EINVAL; + } if (mdp_cfg && mdp_cfg->wrot_filter_constraint) MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, 0x0, diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h index a063a655248c..b2a3e4b2ee1a 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h @@ -39,8 +39,10 @@ struct mdp_platform_config { bool rdma_support_10bit; bool rdma_rsz1_sram_sharing; bool rdma_upsample_repeat_only; + u32 rdma_event_num; bool rsz_disable_dcm_small_sample; bool wrot_filter_constraint; + u32 wrot_event_num; }; /* indicate which mutex is used by each pipepline */ From patchwork Wed Feb 8 09:22:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moudy Ho X-Patchwork-Id: 651940 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98570C64ED6 for ; Wed, 8 Feb 2023 09:24:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231161AbjBHJYj (ORCPT ); Wed, 8 Feb 2023 04:24:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39452 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230310AbjBHJYC (ORCPT ); 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Wed, 08 Feb 2023 17:22:13 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 8 Feb 2023 17:22:12 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 8 Feb 2023 17:22:12 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Matthias Brugger CC: , , , , , , Moudy Ho Subject: [PATCH v4 13/16] media: platform: mtk-mdp3: add mt8195 platform configuration Date: Wed, 8 Feb 2023 17:22:06 +0800 Message-ID: <20230208092209.19472-14-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230208092209.19472-1-moudy.ho@mediatek.com> References: <20230208092209.19472-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add MT8195 MDP3 basic configuration in file "mdp_cfg_data.c" and corresponding driver data. Signed-off-by: Moudy Ho --- .../platform/mediatek/mdp3/mdp_cfg_data.c | 666 ++++++++++++++++++ .../platform/mediatek/mdp3/mtk-mdp3-cfg.h | 1 + .../platform/mediatek/mdp3/mtk-mdp3-comp.c | 36 + .../platform/mediatek/mdp3/mtk-mdp3-core.c | 3 + .../platform/mediatek/mdp3/mtk-mdp3-core.h | 6 + 5 files changed, 712 insertions(+) diff --git a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c index eafb0c235867..588c36c67900 100644 --- a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c +++ b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c @@ -46,12 +46,91 @@ enum mt8183_mdp_comp_id { MT8183_MDP_COMP_WROT1, /* 25 */ }; +enum mt8195_mdp_comp_id { + /* MT8195 Comp id */ + /* ISP */ + MT8195_MDP_COMP_WPEI = 0, + MT8195_MDP_COMP_WPEO, /* 1 */ + MT8195_MDP_COMP_WPEI2, /* 2 */ + MT8195_MDP_COMP_WPEO2, /* 3 */ + + /* MDP */ + MT8195_MDP_COMP_CAMIN, /* 4 */ + MT8195_MDP_COMP_CAMIN2, /* 5 */ + MT8195_MDP_COMP_SPLIT, /* 6 */ + MT8195_MDP_COMP_SPLIT2, /* 7 */ + MT8195_MDP_COMP_RDMA0, /* 8 */ + MT8195_MDP_COMP_RDMA1, /* 9 */ + MT8195_MDP_COMP_RDMA2, /* 10 */ + MT8195_MDP_COMP_RDMA3, /* 11 */ + MT8195_MDP_COMP_STITCH, /* 12 */ + MT8195_MDP_COMP_FG0, /* 13 */ + MT8195_MDP_COMP_FG1, /* 14 */ + MT8195_MDP_COMP_FG2, /* 15 */ + MT8195_MDP_COMP_FG3, /* 16 */ + MT8195_MDP_COMP_TO_SVPP2MOUT, /* 17 */ + MT8195_MDP_COMP_TO_SVPP3MOUT, /* 18 */ + MT8195_MDP_COMP_TO_WARP0MOUT, /* 19 */ + MT8195_MDP_COMP_TO_WARP1MOUT, /* 20 */ + MT8195_MDP_COMP_VPP0_SOUT, /* 21 */ + MT8195_MDP_COMP_VPP1_SOUT, /* 22 */ + MT8195_MDP_COMP_PQ0_SOUT, /* 23 */ + MT8195_MDP_COMP_PQ1_SOUT, /* 24 */ + MT8195_MDP_COMP_HDR0, /* 25 */ + MT8195_MDP_COMP_HDR1, /* 26 */ + MT8195_MDP_COMP_HDR2, /* 27 */ + MT8195_MDP_COMP_HDR3, /* 28 */ + MT8195_MDP_COMP_AAL0, /* 29 */ + MT8195_MDP_COMP_AAL1, /* 30 */ + MT8195_MDP_COMP_AAL2, /* 31 */ + MT8195_MDP_COMP_AAL3, /* 32 */ + MT8195_MDP_COMP_RSZ0, /* 33 */ + MT8195_MDP_COMP_RSZ1, /* 34 */ + MT8195_MDP_COMP_RSZ2, /* 35 */ + MT8195_MDP_COMP_RSZ3, /* 36 */ + MT8195_MDP_COMP_TDSHP0, /* 37 */ + MT8195_MDP_COMP_TDSHP1, /* 38 */ + MT8195_MDP_COMP_TDSHP2, /* 39 */ + MT8195_MDP_COMP_TDSHP3, /* 40 */ + MT8195_MDP_COMP_COLOR0, /* 41 */ + MT8195_MDP_COMP_COLOR1, /* 42 */ + MT8195_MDP_COMP_COLOR2, /* 43 */ + MT8195_MDP_COMP_COLOR3, /* 44 */ + MT8195_MDP_COMP_OVL0, /* 45 */ + MT8195_MDP_COMP_OVL1, /* 46 */ + MT8195_MDP_COMP_PAD0, /* 47 */ + MT8195_MDP_COMP_PAD1, /* 48 */ + MT8195_MDP_COMP_PAD2, /* 49 */ + MT8195_MDP_COMP_PAD3, /* 50 */ + MT8195_MDP_COMP_TCC0, /* 51 */ + MT8195_MDP_COMP_TCC1, /* 52 */ + MT8195_MDP_COMP_WROT0, /* 53 */ + MT8195_MDP_COMP_WROT1, /* 54 */ + MT8195_MDP_COMP_WROT2, /* 55 */ + MT8195_MDP_COMP_WROT3, /* 56 */ + MT8195_MDP_COMP_MERGE2, /* 57 */ + MT8195_MDP_COMP_MERGE3, /* 58 */ + + MT8195_MDP_COMP_VDO0DL0, /* 59 */ + MT8195_MDP_COMP_VDO1DL0, /* 60 */ + MT8195_MDP_COMP_VDO0DL1, /* 61 */ + MT8195_MDP_COMP_VDO1DL1, /* 62 */ +}; + static const struct of_device_id mt8183_mdp_probe_infra[MDP_INFRA_MAX] = { [MDP_INFRA_MMSYS] = { .compatible = "mediatek,mt8183-mmsys" }, [MDP_INFRA_MUTEX] = { .compatible = "mediatek,mt8183-disp-mutex" }, [MDP_INFRA_SCP] = { .compatible = "mediatek,mt8183-scp" } }; +static const struct of_device_id mt8195_mdp_probe_infra[MDP_INFRA_MAX] = { + [MDP_INFRA_MMSYS] = { .compatible = "mediatek,mt8195-vppsys0" }, + [MDP_INFRA_MMSYS2] = { .compatible = "mediatek,mt8195-vppsys1" }, + [MDP_INFRA_MUTEX] = { .compatible = "mediatek,mt8195-vpp-mutex" }, + [MDP_INFRA_MUTEX2] = { .compatible = "mediatek,mt8195-vpp-mutex" }, + [MDP_INFRA_SCP] = { .compatible = "mediatek,mt8195-scp" } +}; + static const struct mdp_platform_config mt8183_plat_cfg = { .rdma_support_10bit = true, .rdma_rsz1_sram_sharing = true, @@ -62,6 +141,21 @@ static const struct mdp_platform_config mt8183_plat_cfg = { .wrot_event_num = 1, }; +static const struct mdp_platform_config mt8195_plat_cfg = { + .rdma_support_10bit = true, + .rdma_rsz1_sram_sharing = false, + .rdma_upsample_repeat_only = false, + .rdma_esl_setting = true, + .rdma_event_num = 4, + .rsz_disable_dcm_small_sample = false, + .rsz_etc_control = true, + .wrot_filter_constraint = false, + .wrot_event_num = 4, + .tdshp_hist_num = 17, + .tdshp_constrain = true, + .tdshp_contour = true, +}; + static const u32 mt8183_mutex_idx[MDP_MAX_COMP_COUNT] = { [MDP_COMP_RDMA0] = MUTEX_MOD_IDX_MDP_RDMA0, [MDP_COMP_RSZ0] = MUTEX_MOD_IDX_MDP_RSZ0, @@ -73,6 +167,52 @@ static const u32 mt8183_mutex_idx[MDP_MAX_COMP_COUNT] = { [MDP_COMP_CCORR0] = MUTEX_MOD_IDX_MDP_CCORR0, }; +static const u32 mt8195_mutex_idx[MDP_MAX_COMP_COUNT] = { + [MDP_COMP_RDMA0] = MUTEX_MOD_IDX_MDP_RDMA0, + [MDP_COMP_RDMA1] = MUTEX_MOD_IDX_MDP_RDMA1, + [MDP_COMP_RDMA2] = MUTEX_MOD_IDX_MDP_RDMA2, + [MDP_COMP_RDMA3] = MUTEX_MOD_IDX_MDP_RDMA3, + [MDP_COMP_STITCH] = MUTEX_MOD_IDX_MDP_STITCH0, + [MDP_COMP_FG0] = MUTEX_MOD_IDX_MDP_FG0, + [MDP_COMP_FG1] = MUTEX_MOD_IDX_MDP_FG1, + [MDP_COMP_FG2] = MUTEX_MOD_IDX_MDP_FG2, + [MDP_COMP_FG3] = MUTEX_MOD_IDX_MDP_FG3, + [MDP_COMP_HDR0] = MUTEX_MOD_IDX_MDP_HDR0, + [MDP_COMP_HDR1] = MUTEX_MOD_IDX_MDP_HDR1, + [MDP_COMP_HDR2] = MUTEX_MOD_IDX_MDP_HDR2, + [MDP_COMP_HDR3] = MUTEX_MOD_IDX_MDP_HDR3, + [MDP_COMP_AAL0] = MUTEX_MOD_IDX_MDP_AAL0, + [MDP_COMP_AAL1] = MUTEX_MOD_IDX_MDP_AAL1, + [MDP_COMP_AAL2] = MUTEX_MOD_IDX_MDP_AAL2, + [MDP_COMP_AAL3] = MUTEX_MOD_IDX_MDP_AAL3, + [MDP_COMP_RSZ0] = MUTEX_MOD_IDX_MDP_RSZ0, + [MDP_COMP_RSZ1] = MUTEX_MOD_IDX_MDP_RSZ1, + [MDP_COMP_RSZ2] = MUTEX_MOD_IDX_MDP_RSZ2, + [MDP_COMP_RSZ3] = MUTEX_MOD_IDX_MDP_RSZ3, + [MDP_COMP_MERGE2] = MUTEX_MOD_IDX_MDP_MERGE2, + [MDP_COMP_MERGE3] = MUTEX_MOD_IDX_MDP_MERGE3, + [MDP_COMP_TDSHP0] = MUTEX_MOD_IDX_MDP_TDSHP0, + [MDP_COMP_TDSHP1] = MUTEX_MOD_IDX_MDP_TDSHP1, + [MDP_COMP_TDSHP2] = MUTEX_MOD_IDX_MDP_TDSHP2, + [MDP_COMP_TDSHP3] = MUTEX_MOD_IDX_MDP_TDSHP3, + [MDP_COMP_COLOR0] = MUTEX_MOD_IDX_MDP_COLOR0, + [MDP_COMP_COLOR1] = MUTEX_MOD_IDX_MDP_COLOR1, + [MDP_COMP_COLOR2] = MUTEX_MOD_IDX_MDP_COLOR2, + [MDP_COMP_COLOR3] = MUTEX_MOD_IDX_MDP_COLOR3, + [MDP_COMP_OVL0] = MUTEX_MOD_IDX_MDP_OVL0, + [MDP_COMP_OVL1] = MUTEX_MOD_IDX_MDP_OVL1, + [MDP_COMP_PAD0] = MUTEX_MOD_IDX_MDP_PAD0, + [MDP_COMP_PAD1] = MUTEX_MOD_IDX_MDP_PAD1, + [MDP_COMP_PAD2] = MUTEX_MOD_IDX_MDP_PAD2, + [MDP_COMP_PAD3] = MUTEX_MOD_IDX_MDP_PAD3, + [MDP_COMP_TCC0] = MUTEX_MOD_IDX_MDP_TCC0, + [MDP_COMP_TCC1] = MUTEX_MOD_IDX_MDP_TCC1, + [MDP_COMP_WROT0] = MUTEX_MOD_IDX_MDP_WROT0, + [MDP_COMP_WROT1] = MUTEX_MOD_IDX_MDP_WROT1, + [MDP_COMP_WROT2] = MUTEX_MOD_IDX_MDP_WROT2, + [MDP_COMP_WROT3] = MUTEX_MOD_IDX_MDP_WROT3, +}; + static const struct mdp_comp_data mt8183_mdp_comp_data[MDP_MAX_COMP_COUNT] = { [MDP_COMP_WPEI] = { {MDP_COMP_TYPE_WPEI, 0, MT8183_MDP_COMP_WPEI, 0}, @@ -148,6 +288,263 @@ static const struct mdp_comp_data mt8183_mdp_comp_data[MDP_MAX_COMP_COUNT] = { }, }; +static const struct mdp_comp_data mt8195_mdp_comp_data[MDP_MAX_COMP_COUNT] = { + [MDP_COMP_WPEI] = { + {MDP_COMP_TYPE_WPEI, 0, MT8195_MDP_COMP_WPEI, 0}, + {0, 0, 0} + }, + [MDP_COMP_WPEO] = { + {MDP_COMP_TYPE_EXTO, 2, MT8195_MDP_COMP_WPEO, 0}, + {0, 0, 0} + }, + [MDP_COMP_WPEI2] = { + {MDP_COMP_TYPE_WPEI, 1, MT8195_MDP_COMP_WPEI2, 0}, + {0, 0, 0} + }, + [MDP_COMP_WPEO2] = { + {MDP_COMP_TYPE_EXTO, 3, MT8195_MDP_COMP_WPEO2, 0}, + {0, 0, 0} + }, + [MDP_COMP_CAMIN] = { + {MDP_COMP_TYPE_DL_PATH, 0, MT8195_MDP_COMP_CAMIN, 0}, + {3, 3, 0} + }, + [MDP_COMP_CAMIN2] = { + {MDP_COMP_TYPE_DL_PATH, 1, MT8195_MDP_COMP_CAMIN2, 0}, + {3, 6, 0} + }, + [MDP_COMP_SPLIT] = { + {MDP_COMP_TYPE_SPLIT, 0, MT8195_MDP_COMP_SPLIT, 1}, + {7, 0, 0} + }, + [MDP_COMP_SPLIT2] = { + {MDP_COMP_TYPE_SPLIT, 1, MT8195_MDP_COMP_SPLIT2, 1}, + {7, 0, 0} + }, + [MDP_COMP_RDMA0] = { + {MDP_COMP_TYPE_RDMA, 0, MT8195_MDP_COMP_RDMA0, 0}, + {3, 0, 0} + }, + [MDP_COMP_RDMA1] = { + {MDP_COMP_TYPE_RDMA, 1, MT8195_MDP_COMP_RDMA1, 1}, + {3, 0, 0} + }, + [MDP_COMP_RDMA2] = { + {MDP_COMP_TYPE_RDMA, 2, MT8195_MDP_COMP_RDMA2, 1}, + {3, 0, 0} + }, + [MDP_COMP_RDMA3] = { + {MDP_COMP_TYPE_RDMA, 3, MT8195_MDP_COMP_RDMA3, 1}, + {3, 0, 0} + }, + [MDP_COMP_STITCH] = { + {MDP_COMP_TYPE_STITCH, 0, MT8195_MDP_COMP_STITCH, 0}, + {1, 0, 0} + }, + [MDP_COMP_FG0] = { + {MDP_COMP_TYPE_FG, 0, MT8195_MDP_COMP_FG0, 0}, + {1, 0, 0} + }, + [MDP_COMP_FG1] = { + {MDP_COMP_TYPE_FG, 1, MT8195_MDP_COMP_FG1, 1}, + {1, 0, 0} + }, + [MDP_COMP_FG2] = { + {MDP_COMP_TYPE_FG, 2, MT8195_MDP_COMP_FG2, 1}, + {1, 0, 0} + }, + [MDP_COMP_FG3] = { + {MDP_COMP_TYPE_FG, 3, MT8195_MDP_COMP_FG3, 1}, + {1, 0, 0} + }, + [MDP_COMP_HDR0] = { + {MDP_COMP_TYPE_HDR, 0, MT8195_MDP_COMP_HDR0, 0}, + {1, 0, 0} + }, + [MDP_COMP_HDR1] = { + {MDP_COMP_TYPE_HDR, 1, MT8195_MDP_COMP_HDR1, 1}, + {1, 0, 0} + }, + [MDP_COMP_HDR2] = { + {MDP_COMP_TYPE_HDR, 2, MT8195_MDP_COMP_HDR2, 1}, + {1, 0, 0} + }, + [MDP_COMP_HDR3] = { + {MDP_COMP_TYPE_HDR, 3, MT8195_MDP_COMP_HDR3, 1}, + {1, 0, 0} + }, + [MDP_COMP_AAL0] = { + {MDP_COMP_TYPE_AAL, 0, MT8195_MDP_COMP_AAL0, 0}, + {1, 0, 0} + }, + [MDP_COMP_AAL1] = { + {MDP_COMP_TYPE_AAL, 1, MT8195_MDP_COMP_AAL1, 1}, + {1, 0, 0} + }, + [MDP_COMP_AAL2] = { + {MDP_COMP_TYPE_AAL, 2, MT8195_MDP_COMP_AAL2, 1}, + {1, 0, 0} + }, + [MDP_COMP_AAL3] = { + {MDP_COMP_TYPE_AAL, 3, MT8195_MDP_COMP_AAL3, 1}, + {1, 0, 0} + }, + [MDP_COMP_RSZ0] = { + {MDP_COMP_TYPE_RSZ, 0, MT8195_MDP_COMP_RSZ0, 0}, + {1, 0, 0} + }, + [MDP_COMP_RSZ1] = { + {MDP_COMP_TYPE_RSZ, 1, MT8195_MDP_COMP_RSZ1, 1}, + {1, 0, 0} + }, + [MDP_COMP_RSZ2] = { + {MDP_COMP_TYPE_RSZ, 2, MT8195_MDP_COMP_RSZ2, 1}, + {2, 0, 0}, + {true, MDP_COMP_MERGE2} + }, + [MDP_COMP_RSZ3] = { + {MDP_COMP_TYPE_RSZ, 3, MT8195_MDP_COMP_RSZ3, 1}, + {2, 0, 0}, + {true, MDP_COMP_MERGE3} + }, + [MDP_COMP_TDSHP0] = { + {MDP_COMP_TYPE_TDSHP, 0, MT8195_MDP_COMP_TDSHP0, 0}, + {1, 0, 0} + }, + [MDP_COMP_TDSHP1] = { + {MDP_COMP_TYPE_TDSHP, 1, MT8195_MDP_COMP_TDSHP1, 1}, + {1, 0, 0} + }, + [MDP_COMP_TDSHP2] = { + {MDP_COMP_TYPE_TDSHP, 2, MT8195_MDP_COMP_TDSHP2, 1}, + {1, 0, 0} + }, + [MDP_COMP_TDSHP3] = { + {MDP_COMP_TYPE_TDSHP, 3, MT8195_MDP_COMP_TDSHP3, 1}, + {1, 0, 0} + }, + [MDP_COMP_COLOR0] = { + {MDP_COMP_TYPE_COLOR, 0, MT8195_MDP_COMP_COLOR0, 0}, + {1, 0, 0} + }, + [MDP_COMP_COLOR1] = { + {MDP_COMP_TYPE_COLOR, 1, MT8195_MDP_COMP_COLOR1, 1}, + {1, 0, 0} + }, + [MDP_COMP_COLOR2] = { + {MDP_COMP_TYPE_COLOR, 2, MT8195_MDP_COMP_COLOR2, 1}, + {1, 0, 0} + }, + [MDP_COMP_COLOR3] = { + {MDP_COMP_TYPE_COLOR, 3, MT8195_MDP_COMP_COLOR3, 1}, + {1, 0, 0} + }, + [MDP_COMP_OVL0] = { + {MDP_COMP_TYPE_OVL, 0, MT8195_MDP_COMP_OVL0, 0}, + {1, 0, 0} + }, + [MDP_COMP_OVL1] = { + {MDP_COMP_TYPE_OVL, 1, MT8195_MDP_COMP_OVL1, 1}, + {1, 0, 0} + }, + [MDP_COMP_PAD0] = { + {MDP_COMP_TYPE_PAD, 0, MT8195_MDP_COMP_PAD0, 0}, + {1, 0, 0} + }, + [MDP_COMP_PAD1] = { + {MDP_COMP_TYPE_PAD, 1, MT8195_MDP_COMP_PAD1, 1}, + {1, 0, 0} + }, + [MDP_COMP_PAD2] = { + {MDP_COMP_TYPE_PAD, 2, MT8195_MDP_COMP_PAD2, 1}, + {1, 0, 0} + }, + [MDP_COMP_PAD3] = { + {MDP_COMP_TYPE_PAD, 3, MT8195_MDP_COMP_PAD3, 1}, + {1, 0, 0} + }, + [MDP_COMP_TCC0] = { + {MDP_COMP_TYPE_TCC, 0, MT8195_MDP_COMP_TCC0, 0}, + {1, 0, 0} + }, + [MDP_COMP_TCC1] = { + {MDP_COMP_TYPE_TCC, 1, MT8195_MDP_COMP_TCC1, 1}, + {1, 0, 0} + }, + [MDP_COMP_WROT0] = { + {MDP_COMP_TYPE_WROT, 0, MT8195_MDP_COMP_WROT0, 0}, + {1, 0, 0} + }, + [MDP_COMP_WROT1] = { + {MDP_COMP_TYPE_WROT, 1, MT8195_MDP_COMP_WROT1, 1}, + {1, 0, 0} + }, + [MDP_COMP_WROT2] = { + {MDP_COMP_TYPE_WROT, 2, MT8195_MDP_COMP_WROT2, 1}, + {1, 0, 0} + }, + [MDP_COMP_WROT3] = { + {MDP_COMP_TYPE_WROT, 3, MT8195_MDP_COMP_WROT3, 1}, + {1, 0, 0} + }, + [MDP_COMP_MERGE2] = { + {MDP_COMP_TYPE_MERGE, 0, MT8195_MDP_COMP_MERGE2, 1}, + {1, 0, 0} + }, + [MDP_COMP_MERGE3] = { + {MDP_COMP_TYPE_MERGE, 1, MT8195_MDP_COMP_MERGE3, 1}, + {1, 0, 0} + }, + [MDP_COMP_PQ0_SOUT] = { + {MDP_COMP_TYPE_DUMMY, 0, MT8195_MDP_COMP_PQ0_SOUT, 0}, + {0, 0, 0} + }, + [MDP_COMP_PQ1_SOUT] = { + {MDP_COMP_TYPE_DUMMY, 1, MT8195_MDP_COMP_PQ1_SOUT, 1}, + {0, 0, 0} + }, + [MDP_COMP_TO_WARP0MOUT] = { + {MDP_COMP_TYPE_DUMMY, 2, MT8195_MDP_COMP_TO_WARP0MOUT, 0}, + {0, 0, 0} + }, + [MDP_COMP_TO_WARP1MOUT] = { + {MDP_COMP_TYPE_DUMMY, 3, MT8195_MDP_COMP_TO_WARP1MOUT, 0}, + {0, 0, 0} + }, + [MDP_COMP_TO_SVPP2MOUT] = { + {MDP_COMP_TYPE_DUMMY, 4, MT8195_MDP_COMP_TO_SVPP2MOUT, 1}, + {0, 0, 0} + }, + [MDP_COMP_TO_SVPP3MOUT] = { + {MDP_COMP_TYPE_DUMMY, 5, MT8195_MDP_COMP_TO_SVPP3MOUT, 1}, + {0, 0, 0} + }, + [MDP_COMP_VPP0_SOUT] = { + {MDP_COMP_TYPE_PATH, 0, MT8195_MDP_COMP_VPP0_SOUT, 1}, + {4, 9, 0} + }, + [MDP_COMP_VPP1_SOUT] = { + {MDP_COMP_TYPE_PATH, 1, MT8195_MDP_COMP_VPP1_SOUT, 0}, + {2, 13, 0} + }, + [MDP_COMP_VDO0DL0] = { + {MDP_COMP_TYPE_DL_PATH, 0, MT8195_MDP_COMP_VDO0DL0, 1}, + {1, 15, 0} + }, + [MDP_COMP_VDO1DL0] = { + {MDP_COMP_TYPE_DL_PATH, 0, MT8195_MDP_COMP_VDO1DL0, 1}, + {1, 17, 0} + }, + [MDP_COMP_VDO0DL1] = { + {MDP_COMP_TYPE_DL_PATH, 0, MT8195_MDP_COMP_VDO0DL1, 1}, + {1, 18, 0} + }, + [MDP_COMP_VDO1DL1] = { + {MDP_COMP_TYPE_DL_PATH, 0, MT8195_MDP_COMP_VDO1DL1, 1}, + {1, 16, 0} + }, +}; + static const struct of_device_id mt8183_sub_comp_dt_ids[] = { { .compatible = "mediatek,mt8183-mdp3-wdma", @@ -159,6 +556,10 @@ static const struct of_device_id mt8183_sub_comp_dt_ids[] = { {} }; +static const struct of_device_id mt8195_sub_comp_dt_ids[] = { + {} +}; + /* * All 10-bit related formats are not added in the basic format list, * please add the corresponding format settings before use. @@ -384,6 +785,222 @@ static const struct mdp_format mt8183_formats[] = { } }; +static const struct mdp_format mt8195_formats[] = { + { + .pixelformat = V4L2_PIX_FMT_GREY, + .mdp_color = MDP_COLOR_GREY, + .depth = { 8 }, + .row_depth = { 8 }, + .num_planes = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_RGB565X, + .mdp_color = MDP_COLOR_BGR565, + .depth = { 16 }, + .row_depth = { 16 }, + .num_planes = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_RGB565, + .mdp_color = MDP_COLOR_RGB565, + .depth = { 16 }, + .row_depth = { 16 }, + .num_planes = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_RGB24, + .mdp_color = MDP_COLOR_RGB888, + .depth = { 24 }, + .row_depth = { 24 }, + .num_planes = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_BGR24, + .mdp_color = MDP_COLOR_BGR888, + .depth = { 24 }, + .row_depth = { 24 }, + .num_planes = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_ABGR32, + .mdp_color = MDP_COLOR_BGRA8888, + .depth = { 32 }, + .row_depth = { 32 }, + .num_planes = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_ARGB32, + .mdp_color = MDP_COLOR_ARGB8888, + .depth = { 32 }, + .row_depth = { 32 }, + .num_planes = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_UYVY, + .mdp_color = MDP_COLOR_UYVY, + .depth = { 16 }, + .row_depth = { 16 }, + .num_planes = 1, + .walign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_VYUY, + .mdp_color = MDP_COLOR_VYUY, + .depth = { 16 }, + .row_depth = { 16 }, + .num_planes = 1, + .walign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_YUYV, + .mdp_color = MDP_COLOR_YUYV, + .depth = { 16 }, + .row_depth = { 16 }, + .num_planes = 1, + .walign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_YVYU, + .mdp_color = MDP_COLOR_YVYU, + .depth = { 16 }, + .row_depth = { 16 }, + .num_planes = 1, + .walign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_YUV420, + .mdp_color = MDP_COLOR_I420, + .depth = { 12 }, + .row_depth = { 8 }, + .num_planes = 1, + .walign = 1, + .halign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_YVU420, + .mdp_color = MDP_COLOR_YV12, + .depth = { 12 }, + .row_depth = { 8 }, + .num_planes = 1, + .walign = 1, + .halign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_NV12, + .mdp_color = MDP_COLOR_NV12, + .depth = { 12 }, + .row_depth = { 8 }, + .num_planes = 1, + .walign = 1, + .halign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_NV21, + .mdp_color = MDP_COLOR_NV21, + .depth = { 12 }, + .row_depth = { 8 }, + .num_planes = 1, + .walign = 1, + .halign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_NV16, + .mdp_color = MDP_COLOR_NV16, + .depth = { 16 }, + .row_depth = { 8 }, + .num_planes = 1, + .walign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_NV61, + .mdp_color = MDP_COLOR_NV61, + .depth = { 16 }, + .row_depth = { 8 }, + .num_planes = 1, + .walign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_NV12M, + .mdp_color = MDP_COLOR_NV12, + .depth = { 8, 4 }, + .row_depth = { 8, 8 }, + .num_planes = 2, + .walign = 1, + .halign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_MM21, + .mdp_color = MDP_COLOR_420_BLK, + .depth = { 8, 4 }, + .row_depth = { 8, 8 }, + .num_planes = 2, + .walign = 6, + .halign = 6, + .flags = MDP_FMT_FLAG_OUTPUT, + }, { + .pixelformat = V4L2_PIX_FMT_NV21M, + .mdp_color = MDP_COLOR_NV21, + .depth = { 8, 4 }, + .row_depth = { 8, 8 }, + .num_planes = 2, + .walign = 1, + .halign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_NV16M, + .mdp_color = MDP_COLOR_NV16, + .depth = { 8, 8 }, + .row_depth = { 8, 8 }, + .num_planes = 2, + .walign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_NV61M, + .mdp_color = MDP_COLOR_NV61, + .depth = { 8, 8 }, + .row_depth = { 8, 8 }, + .num_planes = 2, + .walign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_YUV420M, + .mdp_color = MDP_COLOR_I420, + .depth = { 8, 2, 2 }, + .row_depth = { 8, 4, 4 }, + .num_planes = 3, + .walign = 1, + .halign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_YVU420M, + .mdp_color = MDP_COLOR_YV12, + .depth = { 8, 2, 2 }, + .row_depth = { 8, 4, 4 }, + .num_planes = 3, + .walign = 1, + .halign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_YUV422M, + .mdp_color = MDP_COLOR_I422, + .depth = { 8, 4, 4 }, + .row_depth = { 8, 4, 4 }, + .num_planes = 3, + .walign = 1, + .halign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + }, { + .pixelformat = V4L2_PIX_FMT_YVU422M, + .mdp_color = MDP_COLOR_YV16, + .depth = { 8, 4, 4 }, + .row_depth = { 8, 4, 4 }, + .num_planes = 3, + .walign = 1, + .halign = 1, + .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE, + } +}; + static const struct mdp_limit mt8183_mdp_def_limit = { .out_limit = { .wmin = 16, @@ -403,6 +1020,25 @@ static const struct mdp_limit mt8183_mdp_def_limit = { .v_scale_down_max = 128, }; +static const struct mdp_limit mt8195_mdp_def_limit = { + .out_limit = { + .wmin = 64, + .hmin = 64, + .wmax = 8192, + .hmax = 8192, + }, + .cap_limit = { + .wmin = 64, + .hmin = 64, + .wmax = 8192, + .hmax = 8192, + }, + .h_scale_up_max = 64, + .v_scale_up_max = 64, + .h_scale_down_max = 128, + .v_scale_down_max = 128, +}; + static const struct mdp_pipe_info mt8183_pipe_info[] = { [MDP_PIPE_WPEI] = {MDP_PIPE_WPEI, 0, 0}, [MDP_PIPE_WPEI2] = {MDP_PIPE_WPEI2, 0, 1}, @@ -410,6 +1046,20 @@ static const struct mdp_pipe_info mt8183_pipe_info[] = { [MDP_PIPE_RDMA0] = {MDP_PIPE_RDMA0, 0, 3} }; +static const struct mdp_pipe_info mt8195_pipe_info[] = { + [MDP_PIPE_WPEI] = {MDP_PIPE_WPEI, 0, 0}, + [MDP_PIPE_WPEI2] = {MDP_PIPE_WPEI2, 0, 1}, + [MDP_PIPE_IMGI] = {MDP_PIPE_IMGI, 0, 2}, + [MDP_PIPE_RDMA0] = {MDP_PIPE_RDMA0, 0, 3}, + [MDP_PIPE_RDMA1] = {MDP_PIPE_RDMA1, 1, 0}, + [MDP_PIPE_RDMA2] = {MDP_PIPE_RDMA2, 1, 1}, + [MDP_PIPE_RDMA3] = {MDP_PIPE_RDMA3, 1, 2}, + [MDP_PIPE_SPLIT] = {MDP_PIPE_SPLIT, 1, 3}, + [MDP_PIPE_SPLIT2] = {MDP_PIPE_SPLIT2, 1, 4}, + [MDP_PIPE_VPP1_SOUT] = {MDP_PIPE_VPP1_SOUT, 0, 4}, + [MDP_PIPE_VPP0_SOUT] = {MDP_PIPE_VPP0_SOUT, 1, 5}, +}; + const struct mtk_mdp_driver_data mt8183_mdp_driver_data = { .mdp_plat_id = MT8183, .mdp_con_res = 0x14001000, @@ -426,6 +1076,22 @@ const struct mtk_mdp_driver_data mt8183_mdp_driver_data = { .pipe_info_len = ARRAY_SIZE(mt8183_pipe_info), }; +const struct mtk_mdp_driver_data mt8195_mdp_driver_data = { + .mdp_plat_id = MT8195, + .mdp_con_res = 0x14001000, + .mdp_probe_infra = mt8195_mdp_probe_infra, + .mdp_sub_comp_dt_ids = mt8195_sub_comp_dt_ids, + .mdp_cfg = &mt8195_plat_cfg, + .mdp_mutex_table_idx = mt8195_mutex_idx, + .comp_data = mt8195_mdp_comp_data, + .comp_data_len = ARRAY_SIZE(mt8195_mdp_comp_data), + .format = mt8195_formats, + .format_len = ARRAY_SIZE(mt8195_formats), + .def_limit = &mt8195_mdp_def_limit, + .pipe_info = mt8195_pipe_info, + .pipe_info_len = ARRAY_SIZE(mt8195_pipe_info), +}; + s32 mdp_cfg_get_id_inner(struct mdp_dev *mdp_dev, enum mtk_mdp_comp_id id) { if (!mdp_dev) diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cfg.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cfg.h index dfffc72868e4..49cdf45f6e59 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cfg.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cfg.h @@ -10,6 +10,7 @@ #include extern const struct mtk_mdp_driver_data mt8183_mdp_driver_data; +extern const struct mtk_mdp_driver_data mt8195_mdp_driver_data; struct mdp_dev; enum mtk_mdp_comp_id; diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c index 3d6cf55153f1..cf823179531a 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c @@ -767,6 +767,42 @@ static const struct of_device_id mdp_comp_dt_ids[] = { }, { .compatible = "mediatek,mt8183-mdp3-wdma", .data = (void *)MDP_COMP_TYPE_WDMA, + }, { + .compatible = "mediatek,mt8195-mdp3-rdma", + .data = (void *)MDP_COMP_TYPE_RDMA, + }, { + .compatible = "mediatek,mt8195-mdp3-split", + .data = (void *)MDP_COMP_TYPE_SPLIT, + }, { + .compatible = "mediatek,mt8195-mdp3-stitch", + .data = (void *)MDP_COMP_TYPE_STITCH, + }, { + .compatible = "mediatek,mt8195-mdp3-fg", + .data = (void *)MDP_COMP_TYPE_FG, + }, { + .compatible = "mediatek,mt8195-mdp3-hdr", + .data = (void *)MDP_COMP_TYPE_HDR, + }, { + .compatible = "mediatek,mt8195-mdp3-aal", + .data = (void *)MDP_COMP_TYPE_AAL, + }, { + .compatible = "mediatek,mt8195-mdp3-merge", + .data = (void *)MDP_COMP_TYPE_MERGE, + }, { + .compatible = "mediatek,mt8195-mdp3-tdshp", + .data = (void *)MDP_COMP_TYPE_TDSHP, + }, { + .compatible = "mediatek,mt8195-mdp3-color", + .data = (void *)MDP_COMP_TYPE_COLOR, + }, { + .compatible = "mediatek,mt8195-mdp3-ovl", + .data = (void *)MDP_COMP_TYPE_OVL, + }, { + .compatible = "mediatek,mt8195-mdp3-pad", + .data = (void *)MDP_COMP_TYPE_PAD, + }, { + .compatible = "mediatek,mt8195-mdp3-tcc", + .data = (void *)MDP_COMP_TYPE_TCC, }, {} }; diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c index 09cad71aef69..a6cfd191010a 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c @@ -21,6 +21,9 @@ static const struct of_device_id mdp_of_ids[] = { { .compatible = "mediatek,mt8183-mdp3-rdma", .data = &mt8183_mdp_driver_data, }, + { .compatible = "mediatek,mt8195-mdp3-rdma", + .data = &mt8195_mdp_driver_data, + }, {}, }; MODULE_DEVICE_TABLE(of, mdp_of_ids); diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h index b2a3e4b2ee1a..3dd8a89cd6ab 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h @@ -39,10 +39,16 @@ struct mdp_platform_config { bool rdma_support_10bit; bool rdma_rsz1_sram_sharing; bool rdma_upsample_repeat_only; + bool rdma_esl_setting; u32 rdma_event_num; bool rsz_disable_dcm_small_sample; + bool rsz_etc_control; bool wrot_filter_constraint; + bool wrot_support_10bit; u32 wrot_event_num; + u32 tdshp_hist_num; + bool tdshp_constrain; + bool tdshp_contour; }; /* indicate which mutex is used by each pipepline */ From patchwork Wed Feb 8 09:22:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moudy Ho X-Patchwork-Id: 651938 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with 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Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 8 Feb 2023 17:22:12 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 8 Feb 2023 17:22:12 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Matthias Brugger CC: , , , , , , Moudy Ho Subject: [PATCH v4 15/16] media: platform: mtk-mdp3: add mt8195 MDP3 component settings Date: Wed, 8 Feb 2023 17:22:08 +0800 Message-ID: <20230208092209.19472-16-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230208092209.19472-1-moudy.ho@mediatek.com> References: <20230208092209.19472-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Extend the component settings used in MT8195 MDP3. Besides, all component settings need to be read in a specific way to align shared memory data structure lengths in each platform. Signed-off-by: Moudy Ho --- .../platform/mediatek/mdp3/mtk-mdp3-cmdq.c | 57 ++ .../platform/mediatek/mdp3/mtk-mdp3-comp.c | 787 +++++++++++++++++- 2 files changed, 840 insertions(+), 4 deletions(-) diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c index 259217233570..22f5fe9966b4 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c @@ -40,6 +40,10 @@ static bool is_output_disabled(int p_id, const struct img_compparam *param, u32 num = CFG_COMP(MT8183, param, num_subfrms); dis_output = CFG_COMP(MT8183, param, frame.output_disable); dis_tile = CFG_COMP(MT8183, param, frame.output_disable); + } else if (CFG_CHECK(MT8195, p_id)) { + num = CFG_COMP(MT8195, param, num_subfrms); + dis_output = CFG_COMP(MT8195, param, frame.output_disable); + dis_tile = CFG_COMP(MT8195, param, frame.output_disable); } return (count < num) ? (dis_output || dis_tile) : true; @@ -108,6 +112,8 @@ static int mdp_path_subfrm_require(const struct mdp_path *path, if (CFG_CHECK(MT8183, p_id)) num_comp = CFG_GET(MT8183, path->config, num_components); + else if (CFG_CHECK(MT8195, p_id)) + num_comp = CFG_GET(MT8195, path->config, num_components); /* Decide which mutex to use based on the current pipeline */ index = __get_pipe(path->mdp_dev, path->comps[0].comp->public_id); @@ -121,6 +127,9 @@ static int mdp_path_subfrm_require(const struct mdp_path *path, if (CFG_CHECK(MT8183, p_id)) inner_id = CFG_GET(MT8183, path->config, components[index].type); + else if (CFG_CHECK(MT8195, p_id)) + inner_id = CFG_GET(MT8195, path->config, components[index].type); + if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) continue; ctx = &path->comps[index]; @@ -161,12 +170,17 @@ static int mdp_path_subfrm_run(const struct mdp_path *path, if (CFG_CHECK(MT8183, p_id)) num_comp = CFG_GET(MT8183, path->config, num_components); + else if (CFG_CHECK(MT8195, p_id)) + num_comp = CFG_GET(MT8195, path->config, num_components); /* Wait WROT SRAM shared to DISP RDMA */ /* Clear SOF event for each engine */ for (index = 0; index < num_comp; index++) { if (CFG_CHECK(MT8183, p_id)) inner_id = CFG_GET(MT8183, path->config, components[index].type); + else if (CFG_CHECK(MT8195, p_id)) + inner_id = CFG_GET(MT8195, path->config, components[index].type); + if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) continue; ctx = &path->comps[index]; @@ -185,6 +199,9 @@ static int mdp_path_subfrm_run(const struct mdp_path *path, for (index = 0; index < num_comp; index++) { if (CFG_CHECK(MT8183, p_id)) inner_id = CFG_GET(MT8183, path->config, components[index].type); + else if (CFG_CHECK(MT8195, p_id)) + inner_id = CFG_GET(MT8195, path->config, components[index].type); + if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) continue; ctx = &path->comps[index]; @@ -207,6 +224,8 @@ static int mdp_path_ctx_init(struct mdp_dev *mdp, struct mdp_path *path) if (CFG_CHECK(MT8183, p_id)) num_comp = CFG_GET(MT8183, path->config, num_components); + else if (CFG_CHECK(MT8195, p_id)) + num_comp = CFG_GET(MT8195, path->config, num_components); if (num_comp < 1) return -EINVAL; @@ -216,10 +235,15 @@ static int mdp_path_ctx_init(struct mdp_dev *mdp, struct mdp_path *path) if (CFG_CHECK(MT8183, p_id)) inner_id = CFG_GET(MT8183, path->config, components[index].type); + else if (CFG_CHECK(MT8195, p_id)) + inner_id = CFG_GET(MT8195, path->config, components[index].type); + if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) continue; if (CFG_CHECK(MT8183, p_id)) param = (void *)CFG_ADDR(MT8183, path->config, components[index]); + else if (CFG_CHECK(MT8195, p_id)) + param = (void *)CFG_ADDR(MT8195, path->config, components[index]); ret = mdp_comp_ctx_config(mdp, &path->comps[index], param, path->param); if (ret) @@ -243,9 +267,13 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd, if (CFG_CHECK(MT8183, p_id)) num_comp = CFG_GET(MT8183, path->config, num_components); + else if (CFG_CHECK(MT8195, p_id)) + num_comp = CFG_GET(MT8195, path->config, num_components); if (CFG_CHECK(MT8183, p_id)) ctrl = CFG_ADDR(MT8183, path->config, ctrls[count]); + else if (CFG_CHECK(MT8195, p_id)) + ctrl = CFG_ADDR(MT8195, path->config, ctrls[count]); /* Acquire components */ ret = mdp_path_subfrm_require(path, cmd, &pipe, count); @@ -261,6 +289,9 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd, for (index = (num_comp - 1); index >= 0; index--) { if (CFG_CHECK(MT8183, p_id)) inner_id = CFG_GET(MT8183, path->config, components[index].type); + else if (CFG_CHECK(MT8195, p_id)) + inner_id = CFG_GET(MT8195, path->config, components[index].type); + if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) continue; ctx = &path->comps[index]; @@ -278,6 +309,9 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd, for (index = 0; index < num_comp; index++) { if (CFG_CHECK(MT8183, p_id)) inner_id = CFG_GET(MT8183, path->config, components[index].type); + else if (CFG_CHECK(MT8195, p_id)) + inner_id = CFG_GET(MT8195, path->config, components[index].type); + if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) continue; ctx = &path->comps[index]; @@ -291,6 +325,9 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd, for (index = 0; index < num_comp; index++) { if (CFG_CHECK(MT8183, p_id)) inner_id = CFG_GET(MT8183, path->config, components[index].type); + else if (CFG_CHECK(MT8195, p_id)) + inner_id = CFG_GET(MT8195, path->config, components[index].type); + if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) continue; ctx = &path->comps[index]; @@ -320,15 +357,22 @@ static int mdp_path_config(struct mdp_dev *mdp, struct mdp_cmdq_cmd *cmd, if (CFG_CHECK(MT8183, p_id)) num_comp = CFG_GET(MT8183, path->config, num_components); + else if (CFG_CHECK(MT8195, p_id)) + num_comp = CFG_GET(MT8195, path->config, num_components); if (CFG_CHECK(MT8183, p_id)) num_sub = CFG_GET(MT8183, path->config, num_subfrms); + else if (CFG_CHECK(MT8195, p_id)) + num_sub = CFG_GET(MT8195, path->config, num_subfrms); /* Config path frame */ /* Reset components */ for (index = 0; index < num_comp; index++) { if (CFG_CHECK(MT8183, p_id)) inner_id = CFG_GET(MT8183, path->config, components[index].type); + else if (CFG_CHECK(MT8195, p_id)) + inner_id = CFG_GET(MT8195, path->config, components[index].type); + if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) continue; ctx = &path->comps[index]; @@ -343,11 +387,16 @@ static int mdp_path_config(struct mdp_dev *mdp, struct mdp_cmdq_cmd *cmd, if (CFG_CHECK(MT8183, p_id)) inner_id = CFG_GET(MT8183, path->config, components[index].type); + else if (CFG_CHECK(MT8195, p_id)) + inner_id = CFG_GET(MT8195, path->config, components[index].type); + if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) continue; if (CFG_CHECK(MT8183, p_id)) out = CFG_COMP(MT8183, ctx->param, outputs[0]); + else if (CFG_CHECK(MT8195, p_id)) + out = CFG_COMP(MT8195, ctx->param, outputs[0]); compose = path->composes[out]; ctx = &path->comps[index]; @@ -366,6 +415,9 @@ static int mdp_path_config(struct mdp_dev *mdp, struct mdp_cmdq_cmd *cmd, for (index = 0; index < num_comp; index++) { if (CFG_CHECK(MT8183, p_id)) inner_id = CFG_GET(MT8183, path->config, components[index].type); + else if (CFG_CHECK(MT8195, p_id)) + inner_id = CFG_GET(MT8195, path->config, components[index].type); + if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) continue; ctx = &path->comps[index]; @@ -520,6 +572,8 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param) if (CFG_CHECK(MT8183, p_id)) { num_comp = CFG_GET(MT8183, param->config, num_components); + } else if (CFG_CHECK(MT8195, p_id)) { + num_comp = CFG_GET(MT8195, param->config, num_components); } else { ret = -EINVAL; goto err_destroy_pkt; @@ -575,6 +629,9 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param) if (CFG_CHECK(MT8183, p_id)) inner_id = CFG_GET(MT8183, path->config, components[i].type); + else if (CFG_CHECK(MT8195, p_id)) + inner_id = CFG_GET(MT8195, path->config, components[i].type); + if (mdp_cfg_comp_is_dummy(mdp, inner_id)) continue; memcpy(&comps[i], path->comps[i].comp, diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c index cf823179531a..33119bee59b8 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c @@ -13,11 +13,19 @@ #include "mtk-mdp3-core.h" #include "mtk-mdp3-regs.h" -#include "mdp_reg_rdma.h" +#include "mdp_reg_aal.h" #include "mdp_reg_ccorr.h" +#include "mdp_reg_color.h" +#include "mdp_reg_fg.h" +#include "mdp_reg_hdr.h" +#include "mdp_reg_merge.h" +#include "mdp_reg_ovl.h" +#include "mdp_reg_pad.h" +#include "mdp_reg_rdma.h" #include "mdp_reg_rsz.h" -#include "mdp_reg_wrot.h" +#include "mdp_reg_tdshp.h" #include "mdp_reg_wdma.h" +#include "mdp_reg_wrot.h" static u32 mdp_comp_alias_id[MDP_COMP_TYPE_COUNT]; static int p_id; @@ -85,6 +93,7 @@ static int config_rdma_frame(struct mdp_comp_ctx *ctx, bool en_ufo = MDP_COLOR_IS_UFP(colorformat); phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; + u32 rdma_con_mask = 0; u32 reg = 0; if (mdp_cfg && mdp_cfg->rdma_support_10bit) { @@ -105,6 +114,8 @@ static int config_rdma_frame(struct mdp_comp_ctx *ctx, /* Setup source frame info */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.src_ctrl); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.src_ctrl); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_CON, reg, 0x03C8FE0F); @@ -113,69 +124,161 @@ static int config_rdma_frame(struct mdp_comp_ctx *ctx, /* Setup source buffer base */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.ufo_dec_y); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.ufo_dec_y); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_UFO_DEC_LENGTH_BASE_Y, reg, 0xFFFFFFFF); + if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.ufo_dec_c); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.ufo_dec_c); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_UFO_DEC_LENGTH_BASE_C, reg, 0xFFFFFFFF); + /* Set 10bit source frame pitch */ if (block10bit) { if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.mf_bkgd_in_pxl); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.mf_bkgd_in_pxl); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_BKGD_SIZE_IN_PXL, reg, 0x001FFFFF); } } - if (CFG_CHECK(MT8183, p_id)) + if (CFG_CHECK(MT8183, p_id)) { reg = CFG_COMP(MT8183, ctx->param, rdma.control); + rdma_con_mask = 0x1110; + } else if (CFG_CHECK(MT8195, p_id)) { + reg = CFG_COMP(MT8195, ctx->param, rdma.control); + rdma_con_mask = 0x1130; + } MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_CON, reg, - 0x1110); + rdma_con_mask); + /* Setup source buffer base */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.iova[0]); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.iova[0]); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_0, reg, 0xFFFFFFFF); + if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.iova[1]); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.iova[1]); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_1, reg, 0xFFFFFFFF); + if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.iova[2]); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.iova[2]); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_2, reg, 0xFFFFFFFF); + /* Setup source buffer end */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.iova_end[0]); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.iova_end[0]); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_0, reg, 0xFFFFFFFF); + if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.iova_end[1]); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.iova_end[1]); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_1, reg, 0xFFFFFFFF); + if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.iova_end[2]); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.iova_end[2]); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_2, reg, 0xFFFFFFFF); + /* Setup source frame pitch */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.mf_bkgd); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.mf_bkgd); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_BKGD_SIZE_IN_BYTE, reg, 0x001FFFFF); + if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.sf_bkgd); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.sf_bkgd); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SF_BKGD_SIZE_IN_BYTE, reg, 0x001FFFFF); + /* Setup color transform */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.transform); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.transform); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_TRANSFORM_0, reg, 0x0F110000); + if (mdp_cfg && mdp_cfg->rdma_esl_setting) { + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.dmabuf_con0); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_0, + reg, 0x0FFF00FF); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_high_con0); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_HIGH_CON_0, + reg, 0x3FFFFFFF); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_low_con0); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_LOW_CON_0, + reg, 0x3FFFFFFF); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.dmabuf_con1); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_1, + reg, 0x0F7F007F); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_high_con1); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_HIGH_CON_1, + reg, 0x3FFFFFFF); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_low_con1); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_LOW_CON_1, + reg, 0x3FFFFFFF); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.dmabuf_con2); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_2, + reg, 0x0F3F003F); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_high_con2); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_HIGH_CON_2, + reg, 0x3FFFFFFF); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_low_con2); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_LOW_CON_2, + reg, 0x3FFFFFFF); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.dmabuf_con3); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_3, + reg, 0x0F3F003F); + } + return 0; } @@ -197,6 +300,8 @@ static int config_rdma_subfrm(struct mdp_comp_ctx *ctx, /* Set Y pixel offset */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset[0]); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].offset[0]); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_0, reg, 0xFFFFFFFF); @@ -205,6 +310,8 @@ static int config_rdma_subfrm(struct mdp_comp_ctx *ctx, if (mdp_cfg->rdma_support_10bit && block10bit && en_ufo) { if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset_0_p); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].offset_0_p); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_0_P, reg, 0xFFFFFFFF); @@ -214,32 +321,49 @@ static int config_rdma_subfrm(struct mdp_comp_ctx *ctx, /* Set U pixel offset */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset[1]); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].offset[1]); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_1, reg, 0xFFFFFFFF); + /* Set V pixel offset */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset[2]); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].offset[2]); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_2, reg, 0xFFFFFFFF); + /* Set source size */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].src); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].src); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_SRC_SIZE, reg, 0x1FFF1FFF); + /* Set target size */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].clip); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].clip); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_CLIP_SIZE, reg, 0x1FFF1FFF); + /* Set crop offset */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].clip_ofst); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].clip_ofst); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_OFFSET_1, reg, 0x003F001F); if (CFG_CHECK(MT8183, p_id)) { csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left); csf_r = CFG_COMP(MT8183, ctx->param, subfrms[index].in.right); + } else if (CFG_CHECK(MT8195, p_id)) { + csf_l = CFG_COMP(MT8195, ctx->param, subfrms[index].in.left); + csf_r = CFG_COMP(MT8195, ctx->param, subfrms[index].in.right); } if (mdp_cfg && mdp_cfg->rdma_upsample_repeat_only) if ((csf_r - csf_l + 1) > 320) @@ -286,6 +410,11 @@ static int init_rsz(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, 0x0, BIT(16)); /* Enable RSZ */ MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, BIT(0), BIT(0)); + + if (CFG_CHECK(MT8195, p_id)) + mtk_mmsys_vpp_rsz_dcm_config(ctx->comp->mdp_dev->mdp_mmsys2, + true, NULL); + return 0; } @@ -293,13 +422,19 @@ static int config_rsz_frame(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd, const struct v4l2_rect *compose) { + const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx); phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; bool bypass = FALSE; u32 reg = 0; + if (mdp_cfg && mdp_cfg->rsz_etc_control) + MM_REG_WRITE(cmd, subsys_id, base, RSZ_ETC_CONTROL, 0x0, 0xFFFFFFFF); + if (CFG_CHECK(MT8183, p_id)) bypass = CFG_COMP(MT8183, ctx->param, frame.bypass); + else if (CFG_CHECK(MT8195, p_id)) + bypass = CFG_COMP(MT8195, ctx->param, frame.bypass); if (bypass) { /* Disable RSZ */ @@ -309,20 +444,32 @@ static int config_rsz_frame(struct mdp_comp_ctx *ctx, if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rsz.control1); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rsz.control1); MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_1, reg, 0x03FFFDF3); + if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rsz.control2); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rsz.control2); MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_2, reg, 0x0FFFC290); + if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rsz.coeff_step_x); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rsz.coeff_step_x); MM_REG_WRITE(cmd, subsys_id, base, PRZ_HORIZONTAL_COEFF_STEP, reg, 0x007FFFFF); + if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rsz.coeff_step_y); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rsz.coeff_step_y); MM_REG_WRITE(cmd, subsys_id, base, PRZ_VERTICAL_COEFF_STEP, reg, 0x007FFFFF); + return 0; } @@ -332,21 +479,30 @@ static int config_rsz_subfrm(struct mdp_comp_ctx *ctx, const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx); phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; + u32 id; u32 csf_l = 0, csf_r = 0; u32 reg = 0; if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rsz.subfrms[index].control2); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].control2); MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_2, reg, 0x00003800); + if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rsz.subfrms[index].src); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].src); MM_REG_WRITE(cmd, subsys_id, base, PRZ_INPUT_IMAGE, reg, 0xFFFFFFFF); if (CFG_CHECK(MT8183, p_id)) { csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left); csf_r = CFG_COMP(MT8183, ctx->param, subfrms[index].in.right); + } else if (CFG_CHECK(MT8195, p_id)) { + csf_l = CFG_COMP(MT8195, ctx->param, subfrms[index].in.left); + csf_r = CFG_COMP(MT8195, ctx->param, subfrms[index].in.right); } if (mdp_cfg && mdp_cfg->rsz_disable_dcm_small_sample) if ((csf_r - csf_l + 1) <= 16) @@ -355,37 +511,96 @@ static int config_rsz_subfrm(struct mdp_comp_ctx *ctx, if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.left); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, subfrms[index].luma.left); MM_REG_WRITE(cmd, subsys_id, base, PRZ_LUMA_HORIZONTAL_INTEGER_OFFSET, reg, 0xFFFF); + if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.left_subpix); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, subfrms[index].luma.left_subpix); MM_REG_WRITE(cmd, subsys_id, base, PRZ_LUMA_HORIZONTAL_SUBPIXEL_OFFSET, reg, 0x1FFFFF); + if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.top); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, subfrms[index].luma.top); MM_REG_WRITE(cmd, subsys_id, base, PRZ_LUMA_VERTICAL_INTEGER_OFFSET, reg, 0xFFFF); + if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.top_subpix); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, subfrms[index].luma.top_subpix); MM_REG_WRITE(cmd, subsys_id, base, PRZ_LUMA_VERTICAL_SUBPIXEL_OFFSET, reg, 0x1FFFFF); + if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, subfrms[index].chroma.left); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, subfrms[index].chroma.left); MM_REG_WRITE(cmd, subsys_id, base, PRZ_CHROMA_HORIZONTAL_INTEGER_OFFSET, reg, 0xFFFF); + if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, subfrms[index].chroma.left_subpix); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, subfrms[index].chroma.left_subpix); MM_REG_WRITE(cmd, subsys_id, base, PRZ_CHROMA_HORIZONTAL_SUBPIXEL_OFFSET, reg, 0x1FFFFF); if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rsz.subfrms[index].clip); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].clip); MM_REG_WRITE(cmd, subsys_id, base, PRZ_OUTPUT_IMAGE, reg, 0xFFFFFFFF); + if (CFG_CHECK(MT8195, p_id)) { + struct mdp_comp *merge; + const struct mtk_mdp_driver_data *data = ctx->comp->mdp_dev->mdp_data; + enum mtk_mdp_comp_id public_id = ctx->comp->public_id; + + switch (public_id) { + case MDP_COMP_RSZ2: + merge = ctx->comp->mdp_dev->comp[MDP_COMP_MERGE2]; + break; + case MDP_COMP_RSZ3: + merge = ctx->comp->mdp_dev->comp[MDP_COMP_MERGE3]; + break; + default: + goto rsz_subfrm_done; + } + id = data->comp_data[public_id].match.alias_id; + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].rsz_switch); + mtk_mmsys_vpp_rsz_merge_config(ctx->comp->mdp_dev->mdp_mmsys2, id, + reg, NULL); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].merge_cfg); + MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, + MDP_MERGE_CFG_0, reg, 0xFFFFFFFF); + MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, + MDP_MERGE_CFG_4, reg, 0xFFFFFFFF); + MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, + MDP_MERGE_CFG_24, reg, 0xFFFFFFFF); + MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, + MDP_MERGE_CFG_25, reg, 0xFFFFFFFF); + + /* Bypass mode */ + MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, + MDP_MERGE_CFG_12, BIT(0), 0xFFFFFFFF); + MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, + MDP_MERGE_ENABLE, BIT(0), 0xFFFFFFFF); + } + +rsz_subfrm_done: return 0; } @@ -402,6 +617,9 @@ static int advance_rsz_subfrm(struct mdp_comp_ctx *ctx, if (CFG_CHECK(MT8183, p_id)) { csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left); csf_r = CFG_COMP(MT8183, ctx->param, subfrms[index].in.right); + } else if (CFG_CHECK(MT8195, p_id)) { + csf_l = CFG_COMP(MT8195, ctx->param, subfrms[index].in.left); + csf_r = CFG_COMP(MT8195, ctx->param, subfrms[index].in.right); } if ((csf_r - csf_l + 1) <= 16) @@ -428,6 +646,11 @@ static int init_wrot(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) /* Reset WROT */ MM_REG_WRITE(cmd, subsys_id, base, VIDO_SOFT_RST, BIT(0), BIT(0)); MM_REG_POLL(cmd, subsys_id, base, VIDO_SOFT_RST_STAT, BIT(0), BIT(0)); + + /* Reset setting */ + if (CFG_CHECK(MT8195, p_id)) + MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL, 0x0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_SOFT_RST, 0x0, BIT(0)); MM_REG_POLL(cmd, subsys_id, base, VIDO_SOFT_RST_STAT, 0x0, BIT(0)); return 0; @@ -445,57 +668,120 @@ static int config_wrot_frame(struct mdp_comp_ctx *ctx, /* Write frame base address */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.iova[0]); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, wrot.iova[0]); MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR, reg, 0xFFFFFFFF); + if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.iova[1]); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, wrot.iova[1]); MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_C, reg, 0xFFFFFFFF); + if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.iova[2]); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, wrot.iova[2]); MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_V, reg, 0xFFFFFFFF); + + if (mdp_cfg) { + if (mdp_cfg->wrot_support_10bit) { + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, wrot.scan_10bit); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_SCAN_10BIT, + reg, 0x0000000F); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, wrot.pending_zero); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_PENDING_ZERO, + reg, 0x04000000); + } + + if (CFG_CHECK(MT8195, p_id)) { + reg = CFG_COMP(MT8195, ctx->param, wrot.bit_number); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL_2, + reg, 0x00000007); + } + } + /* Write frame related registers */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.control); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, wrot.control); MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL, reg, 0xF131510F); + + /* Write pre-ultra threshold */ + if (CFG_CHECK(MT8195, p_id)) { + reg = CFG_COMP(MT8195, ctx->param, wrot.pre_ultra); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_DMA_PREULTRA, reg, + 0x00FFFFFF); + } + /* Write frame Y pitch */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.stride[0]); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, wrot.stride[0]); MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE, reg, 0x0000FFFF); + /* Write frame UV pitch */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.stride[1]); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, wrot.stride[1]); MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE_C, reg, 0xFFFF); + if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.stride[2]); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, wrot.stride[2]); MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE_V, reg, 0xFFFF); + /* Write matrix control */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.mat_ctrl); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, wrot.mat_ctrl); MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAT_CTRL, reg, 0xF3); /* Set the fixed ALPHA as 0xFF */ MM_REG_WRITE(cmd, subsys_id, base, VIDO_DITHER, 0xFF000000, 0xFF000000); + /* Set VIDO_EOL_SEL */ MM_REG_WRITE(cmd, subsys_id, base, VIDO_RSV_1, BIT(31), BIT(31)); + /* Set VIDO_FIFO_TEST */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.fifo_test); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, wrot.fifo_test); + if (reg != 0) MM_REG_WRITE(cmd, subsys_id, base, VIDO_FIFO_TEST, reg, 0xFFF); + /* Filter enable */ if (mdp_cfg && mdp_cfg->wrot_filter_constraint) { if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.filter); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, wrot.filter); MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, reg, 0x77); + + /* Turn off WROT dma dcm */ + if (CFG_CHECK(MT8195, p_id)) + MM_REG_WRITE(cmd, subsys_id, base, VIDO_ROT_EN, + (0x1 << 23) + (0x1 << 20), 0x900000); } return 0; @@ -511,35 +797,54 @@ static int config_wrot_subfrm(struct mdp_comp_ctx *ctx, /* Write Y pixel offset */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].offset[0]); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].offset[0]); MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR, reg, 0x0FFFFFFF); + /* Write U pixel offset */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].offset[1]); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].offset[1]); MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR_C, reg, 0x0FFFFFFF); + /* Write V pixel offset */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].offset[2]); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].offset[2]); MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR_V, reg, 0x0FFFFFFF); + /* Write source size */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].src); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].src); MM_REG_WRITE(cmd, subsys_id, base, VIDO_IN_SIZE, reg, 0x1FFF1FFF); + /* Write target size */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].clip); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].clip); MM_REG_WRITE(cmd, subsys_id, base, VIDO_TAR_SIZE, reg, 0x1FFF1FFF); + if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].clip_ofst); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].clip_ofst); MM_REG_WRITE(cmd, subsys_id, base, VIDO_CROP_OFST, reg, 0x1FFF1FFF); if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].main_buf); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].main_buf); MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, reg, 0x1FFF7F00); @@ -702,6 +1007,166 @@ static const struct mdp_comp_ops wdma_ops = { .wait_comp_event = wait_wdma_event, }; +static void reset_luma_hist(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) +{ + const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx); + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + u32 hist_num = mdp_cfg->tdshp_hist_num; + u32 i; + + /* Reset histogram */ + for (i = 0; i <= hist_num; i++) + MM_REG_WRITE_MASK(cmd, subsys_id, base, + (MDP_LUMA_HIST_INIT + (i << 2)), + 0, 0xFFFFFFFF); + + if (mdp_cfg && mdp_cfg->tdshp_constrain) + MM_REG_WRITE(cmd, subsys_id, base, + MDP_DC_TWO_D_W1_RESULT_INIT, 0, 0xFFFFFFFF); + + if (mdp_cfg && mdp_cfg->tdshp_contour) + for (i = 0; i < hist_num; i++) + MM_REG_WRITE_MASK(cmd, subsys_id, base, + (MDP_CONTOUR_HIST_INIT + (i << 2)), + 0, 0xFFFFFFFF); +} + +static int init_tdshp(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + + MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_CTRL, BIT(0), BIT(0)); + /* Enable FIFO */ + MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_CFG, BIT(1), BIT(1)); + reset_luma_hist(ctx, cmd); + + return 0; +} + +static int config_tdshp_frame(struct mdp_comp_ctx *ctx, + struct mdp_cmdq_cmd *cmd, + const struct v4l2_rect *compose) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + u32 reg = 0; + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, tdshp.cfg); + MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_CFG, reg, BIT(0)); + + return 0; +} + +static int config_tdshp_subfrm(struct mdp_comp_ctx *ctx, + struct mdp_cmdq_cmd *cmd, u32 index) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + u32 reg = 0; + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].src); + MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_INPUT_SIZE, + reg, MDP_TDSHP_INPUT_SIZE_MASK); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].clip_ofst); + MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_OUTPUT_OFFSET, + reg, 0x00FF00FF); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].clip); + MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_OUTPUT_SIZE, + reg, MDP_TDSHP_OUTPUT_SIZE_MASK); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].hist_cfg_0); + MM_REG_WRITE(cmd, subsys_id, base, MDP_HIST_CFG_00, reg, 0xFFFFFFFF); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].hist_cfg_1); + MM_REG_WRITE(cmd, subsys_id, base, MDP_HIST_CFG_01, reg, 0xFFFFFFFF); + + return 0; +} + +static const struct mdp_comp_ops tdshp_ops = { + .get_comp_flag = get_comp_flag, + .init_comp = init_tdshp, + .config_frame = config_tdshp_frame, + .config_subfrm = config_tdshp_subfrm, +}; + +static int init_color(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + + MM_REG_WRITE(cmd, subsys_id, base, + MDP_COLOR_START, 0x1, BIT(1) | BIT(0)); + MM_REG_WRITE(cmd, subsys_id, base, + MDP_COLOR_WIN_X_MAIN, 0xFFFF0000, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + MDP_COLOR_WIN_Y_MAIN, 0xFFFF0000, 0xFFFFFFFF); + + /* Reset color matrix */ + MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_CM1_EN, 0x0, BIT(0)); + MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_CM2_EN, 0x0, BIT(0)); + + /* Enable interrupt */ + MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_INTEN, 0x7, 0x7); + + MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_OUT_SEL, 0x333, 0x333); + + return 0; +} + +static int config_color_frame(struct mdp_comp_ctx *ctx, + struct mdp_cmdq_cmd *cmd, + const struct v4l2_rect *compose) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + u32 reg = 0; + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, color.start); + MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_START, + reg, MDP_COLOR_START_MASK); + + return 0; +} + +static int config_color_subfrm(struct mdp_comp_ctx *ctx, + struct mdp_cmdq_cmd *cmd, u32 index) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + u32 reg = 0; + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, color.subfrms[index].in_hsize); + MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_INTERNAL_IP_WIDTH, + reg, 0x00003FFF); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, color.subfrms[index].in_vsize); + MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_INTERNAL_IP_HEIGHT, + reg, 0x00003FFF); + + return 0; +} + +static const struct mdp_comp_ops color_ops = { + .get_comp_flag = get_comp_flag, + .init_comp = init_color, + .config_frame = config_color_frame, + .config_subfrm = config_color_subfrm, +}; + static int init_ccorr(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) { phys_addr_t base = ctx->comp->reg_base; @@ -743,12 +1208,318 @@ static const struct mdp_comp_ops ccorr_ops = { .config_subfrm = config_ccorr_subfrm, }; +static int init_aal(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + + /* Always set MDP_AAL enable to 1 */ + MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_EN, BIT(0), BIT(0)); + + return 0; +} + +static int config_aal_frame(struct mdp_comp_ctx *ctx, + struct mdp_cmdq_cmd *cmd, + const struct v4l2_rect *compose) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + u32 reg = 0; + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, aal.cfg_main); + MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_CFG_MAIN, reg, BIT(7)); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, aal.cfg); + MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_CFG, reg, BIT(0)); + + return 0; +} + +static int config_aal_subfrm(struct mdp_comp_ctx *ctx, + struct mdp_cmdq_cmd *cmd, u32 index) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + u32 reg = 0; + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, aal.subfrms[index].src); + MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_SIZE, + reg, MDP_AAL_SIZE_MASK); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, aal.subfrms[index].clip_ofst); + MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_OUTPUT_OFFSET, + reg, 0x00FF00FF); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, aal.subfrms[index].clip); + MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_OUTPUT_SIZE, + reg, MDP_AAL_OUTPUT_SIZE_MASK); + + return 0; +} + +static const struct mdp_comp_ops aal_ops = { + .get_comp_flag = get_comp_flag, + .init_comp = init_aal, + .config_frame = config_aal_frame, + .config_subfrm = config_aal_subfrm, +}; + +static int init_hdr(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + + /* Always set MDP_HDR enable to 1 */ + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TOP, BIT(0), BIT(0)); + + return 0; +} + +static int config_hdr_frame(struct mdp_comp_ctx *ctx, + struct mdp_cmdq_cmd *cmd, + const struct v4l2_rect *compose) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + u32 reg = 0; + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, hdr.top); + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TOP, reg, BIT(29) | BIT(28)); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, hdr.relay); + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_RELAY, reg, BIT(0)); + + return 0; +} + +static int config_hdr_subfrm(struct mdp_comp_ctx *ctx, + struct mdp_cmdq_cmd *cmd, u32 index) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + u32 reg = 0; + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].win_size); + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TILE_POS, + reg, MDP_HDR_TILE_POS_MASK); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].src); + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_SIZE_0, reg, 0x1FFF1FFF); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].clip_ofst0); + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_SIZE_1, reg, 0x1FFF1FFF); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].clip_ofst1); + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_SIZE_2, reg, 0x1FFF1FFF); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].hist_ctrl_0); + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_HIST_CTRL_0, reg, 0x00003FFF); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].hist_ctrl_1); + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_HIST_CTRL_1, reg, 0x00003FFF); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].hdr_top); + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TOP, reg, BIT(6) | BIT(5)); + + /* Enable histogram */ + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].hist_addr); + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_HIST_ADDR, reg, BIT(9)); + + return 0; +} + +static const struct mdp_comp_ops hdr_ops = { + .get_comp_flag = get_comp_flag, + .init_comp = init_hdr, + .config_frame = config_hdr_frame, + .config_subfrm = config_hdr_subfrm, +}; + +static int init_fg(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + + MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TRIGGER, BIT(2), BIT(2)); + MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TRIGGER, 0x0, BIT(2)); + + return 0; +} + +static int config_fg_frame(struct mdp_comp_ctx *ctx, + struct mdp_cmdq_cmd *cmd, + const struct v4l2_rect *compose) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + u32 reg = 0; + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, fg.ctrl_0); + MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_FG_CTRL_0, reg, BIT(0)); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, fg.ck_en); + MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_FG_CK_EN, reg, 0x7); + + return 0; +} + +static int config_fg_subfrm(struct mdp_comp_ctx *ctx, + struct mdp_cmdq_cmd *cmd, u32 index) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + u32 reg = 0; + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, fg.subfrms[index].info_0); + MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TILE_INFO_0, reg, 0xFFFFFFFF); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, fg.subfrms[index].info_1); + MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TILE_INFO_1, reg, 0xFFFFFFFF); + + return 0; +} + +static const struct mdp_comp_ops fg_ops = { + .get_comp_flag = get_comp_flag, + .init_comp = init_fg, + .config_frame = config_fg_frame, + .config_subfrm = config_fg_subfrm, +}; + +static int init_ovl(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + + MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_EN, + BIT(0), MDP_OVL_EN_MASK); + + /* Set to relay mode */ + MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_SRC_CON, + BIT(9), MDP_OVL_SRC_CON_MASK); + MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_DP_CON, + BIT(0), MDP_OVL_DP_CON_MASK); + + return 0; +} + +static int config_ovl_frame(struct mdp_comp_ctx *ctx, + struct mdp_cmdq_cmd *cmd, + const struct v4l2_rect *compose) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + u32 reg = 0; + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, ovl.L0_con); + MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_L0_CON, reg, BIT(29) | BIT(28)); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, ovl.src_con); + MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_SRC_CON, reg, BIT(0)); + + return 0; +} + +static int config_ovl_subfrm(struct mdp_comp_ctx *ctx, + struct mdp_cmdq_cmd *cmd, u32 index) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + u32 reg = 0; + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, ovl.subfrms[index].L0_src_size); + MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_L0_SRC_SIZE, + reg, MDP_OVL_L0_SRC_SIZE_MASK); + + /* Setup output size */ + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, ovl.subfrms[index].roi_size); + MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_ROI_SIZE, + reg, MDP_OVL_ROI_SIZE_MASK); + + return 0; +} + +static const struct mdp_comp_ops ovl_ops = { + .get_comp_flag = get_comp_flag, + .init_comp = init_ovl, + .config_frame = config_ovl_frame, + .config_subfrm = config_ovl_subfrm, +}; + +static int init_pad(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + + MM_REG_WRITE(cmd, subsys_id, base, MDP_PAD_CON, + BIT(1), MDP_PAD_CON_MASK); + /* Reset */ + MM_REG_WRITE(cmd, subsys_id, base, MDP_PAD_W_SIZE, + 0, MDP_PAD_W_SIZE_MASK); + MM_REG_WRITE(cmd, subsys_id, base, MDP_PAD_H_SIZE, + 0, MDP_PAD_H_SIZE_MASK); + + return 0; +} + +static int config_pad_subfrm(struct mdp_comp_ctx *ctx, + struct mdp_cmdq_cmd *cmd, u32 index) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + u32 reg = 0; + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, pad.subfrms[index].pic_size); + MM_REG_WRITE(cmd, subsys_id, base, MDP_PAD_PIC_SIZE, + reg, MDP_PAD_PIC_SIZE_MASK); + + return 0; +} + +static const struct mdp_comp_ops pad_ops = { + .get_comp_flag = get_comp_flag, + .init_comp = init_pad, + .config_subfrm = config_pad_subfrm, +}; + static const struct mdp_comp_ops *mdp_comp_ops[MDP_COMP_TYPE_COUNT] = { [MDP_COMP_TYPE_RDMA] = &rdma_ops, [MDP_COMP_TYPE_RSZ] = &rsz_ops, [MDP_COMP_TYPE_WROT] = &wrot_ops, [MDP_COMP_TYPE_WDMA] = &wdma_ops, + [MDP_COMP_TYPE_TDSHP] = &tdshp_ops, + [MDP_COMP_TYPE_COLOR] = &color_ops, [MDP_COMP_TYPE_CCORR] = &ccorr_ops, + [MDP_COMP_TYPE_AAL] = &aal_ops, + [MDP_COMP_TYPE_HDR] = &hdr_ops, + [MDP_COMP_TYPE_FG] = &fg_ops, + [MDP_COMP_TYPE_OVL] = &ovl_ops, + [MDP_COMP_TYPE_PAD] = &pad_ops, }; static const struct of_device_id mdp_comp_dt_ids[] = { @@ -1206,6 +1977,8 @@ int mdp_comp_ctx_config(struct mdp_dev *mdp, struct mdp_comp_ctx *ctx, if (CFG_CHECK(MT8183, p_id)) arg = CFG_COMP(MT8183, param, type); + else if (CFG_CHECK(MT8195, p_id)) + arg = CFG_COMP(MT8195, param, type); else return -EINVAL; public_id = mdp_cfg_get_id_public(mdp, arg); @@ -1223,16 +1996,22 @@ int mdp_comp_ctx_config(struct mdp_dev *mdp, struct mdp_comp_ctx *ctx, ctx->param = param; if (CFG_CHECK(MT8183, p_id)) arg = CFG_COMP(MT8183, param, input); + else if (CFG_CHECK(MT8195, p_id)) + arg = CFG_COMP(MT8195, param, input); else return -EINVAL; ctx->input = &frame->inputs[arg]; if (CFG_CHECK(MT8183, p_id)) idx = CFG_COMP(MT8183, param, num_outputs); + else if (CFG_CHECK(MT8195, p_id)) + idx = CFG_COMP(MT8195, param, num_outputs); else return -EINVAL; for (i = 0; i < idx; i++) { if (CFG_CHECK(MT8183, p_id)) arg = CFG_COMP(MT8183, param, outputs[i]); + else if (CFG_CHECK(MT8195, p_id)) + arg = CFG_COMP(MT8195, param, outputs[i]); else return -EINVAL; ctx->outputs[i] = &frame->outputs[arg];