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bh=1C1fQPBI+S7EZfRs6MlBqyyoF90UjaDB3OCSeUD7WIY=; b=GhdnAh3Npl4CJG7YU0MDjonw8jYVGI7e/g9adMYwYbHZ0Qkma14YGaqpy0ZN1n9r0L kmd3vRNucPU/7++FmXyZm2cYdRolRBRtNKzI5c3KXcCRvvHbuA7lR3IGo+W1JM+WNj/u dQmH4Vmtdkd4odlAuW4TL+pVYsS6dYw2//0CijL6cYVD3jDZ0ZgLZD067/CViYLd7ad+ p/g6Vr+EgpVwGI/frAGYR9iDDtwhKgScZQfKHxQb8lKEWsXn64i/4KnmzMhLNYc6Cu4z 2laLKxX/PNXWV3gKXn+xJ2KTvQ2J2R0vNQARwL+cIrfSoiIg8QEWkUIVcivgl0kQX/P0 A/nA== X-Gm-Message-State: AO0yUKU8f953wP9SwjKHty/2Us/tLgkmqKheC77NQTAr8jq0aSURf4pf VYq8mAUTQj6lSfDzSzP6B0IK6TAL9PrRlzIR X-Received: by 2002:a17:902:e3c2:b0:198:f907:2a9b with SMTP id r2-20020a170902e3c200b00198f9072a9bmr6285394ple.37.1675889675235; Wed, 08 Feb 2023 12:54:35 -0800 (PST) Received: from localhost ([111.184.129.17]) by smtp.gmail.com with ESMTPSA id x19-20020a170902ea9300b0019956488546sm360424plb.277.2023.02.08.12.54.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Feb 2023 12:54:34 -0800 (PST) From: "Ying-Chun Liu (PaulLiu)" To: u-boot@lists.denx.de Cc: Marc Zyngier , Will Deacon , =?utf-8?q?Pierre-Cl=C3=A9ment_Tosi?= , Ying-Chun Liu , Tom Rini Subject: [PATCH v2 1/2] arm: cpu: Add optional CMOs by VA Date: Thu, 9 Feb 2023 04:54:27 +0800 Message-Id: <20230208205428.1083689-2-paul.liu@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230208205428.1083689-1-paul.liu@linaro.org> References: <20230208205428.1083689-1-paul.liu@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Marc Zyngier Exposing set/way cache maintenance to a virtual machine is unsafe, not least because the instructions are not permission-checked but also because they are not broadcast between CPUs. Consequently, KVM traps and emulates such maintenance in the host kernel using by-VA operations and looping over the stage-2 page-tables. However, when running under protected KVM, these instructions are not able to be emulated and will instead result in an exception being delivered to the guest. Introduce CONFIG_CMO_BY_VA_ONLY so that virtual platforms can select this option and perform by-VA cache maintenance instead of using the set/way instructions. Signed-off-by: Marc Zyngier Signed-off-by: Will Deacon Signed-off-by: Pierre-Clément Tosi [ Paul: pick from the Android tree. Fixup Pierre's commit. And fix some checkpatch warnings. Rebased to upstream. ] Signed-off-by: Ying-Chun Liu (PaulLiu) Cc: Tom Rini Link: https://android.googlesource.com/platform/external/u-boot/+/db5507f47f4f57f766d52f753ff2cc761afc213b Link: https://android.googlesource.com/platform/external/u-boot/+/2baf54e743380a1e4a6bc2dbdde020a2e783ff67 --- v2: Fix the Signed-off-by list. --- arch/arm/cpu/armv8/Kconfig | 4 ++ arch/arm/cpu/armv8/cache.S | 50 +++++++++++++----- arch/arm/cpu/armv8/cache_v8.c | 97 ++++++++++++++++++++++++++++++++++- arch/arm/cpu/armv8/cpu.c | 30 +++++++---- 4 files changed, 155 insertions(+), 26 deletions(-) diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 1305238c9d..7d5cf1594d 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -1,5 +1,9 @@ if ARM64 +config CMO_BY_VA_ONLY + bool "Force cache maintenance to be exclusively by VA" + depends on !SYS_DISABLE_DCACHE_OPS + config ARMV8_SPL_EXCEPTION_VECTORS bool "Install crash dump exception vectors" depends on SPL diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S index d1cee23437..3fe935cf28 100644 --- a/arch/arm/cpu/armv8/cache.S +++ b/arch/arm/cpu/armv8/cache.S @@ -12,6 +12,7 @@ #include #include +#ifndef CONFIG_CMO_BY_VA_ONLY /* * void __asm_dcache_level(level) * @@ -116,6 +117,41 @@ ENTRY(__asm_invalidate_dcache_all) ENDPROC(__asm_invalidate_dcache_all) .popsection +.pushsection .text.__asm_flush_l3_dcache, "ax" +WEAK(__asm_flush_l3_dcache) + mov x0, #0 /* return status as success */ + ret +ENDPROC(__asm_flush_l3_dcache) +.popsection + +.pushsection .text.__asm_invalidate_l3_icache, "ax" +WEAK(__asm_invalidate_l3_icache) + mov x0, #0 /* return status as success */ + ret +ENDPROC(__asm_invalidate_l3_icache) +.popsection + +#else /* CONFIG_CMO_BY_VA */ + +/* + * Define these so that they actively clash with in implementation + * accidentally selecting CONFIG_CMO_BY_VA + */ + +.pushsection .text.__asm_invalidate_l3_icache, "ax" +ENTRY(__asm_invalidate_l3_icache) + mov x0, xzr + ret +ENDPROC(__asm_invalidate_l3_icache) +.popsection +.pushsection .text.__asm_flush_l3_dcache, "ax" +ENTRY(__asm_flush_l3_dcache) + mov x0, xzr + ret +ENDPROC(__asm_flush_l3_dcache) +.popsection +#endif /* CONFIG_CMO_BY_VA */ + /* * void __asm_flush_dcache_range(start, end) * @@ -189,20 +225,6 @@ WEAK(__asm_invalidate_l3_dcache) ENDPROC(__asm_invalidate_l3_dcache) .popsection -.pushsection .text.__asm_flush_l3_dcache, "ax" -WEAK(__asm_flush_l3_dcache) - mov x0, #0 /* return status as success */ - ret -ENDPROC(__asm_flush_l3_dcache) -.popsection - -.pushsection .text.__asm_invalidate_l3_icache, "ax" -WEAK(__asm_invalidate_l3_icache) - mov x0, #0 /* return status as success */ - ret -ENDPROC(__asm_invalidate_l3_icache) -.popsection - /* * void __asm_switch_ttbr(ulong new_ttbr) * diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 2a226fd063..f333ad8889 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -163,6 +163,83 @@ static u64 *find_pte(u64 addr, int level) return NULL; } +#ifdef CONFIG_CMO_BY_VA_ONLY +static void __cmo_on_leaves(void (*cmo_fn)(unsigned long, unsigned long), + u64 pte, int level, u64 base) +{ + u64 *ptep; + int i; + + ptep = (u64 *)(pte & GENMASK_ULL(47, PAGE_SHIFT)); + for (i = 0; i < PAGE_SIZE / sizeof(u64); i++) { + u64 end, va = base + i * BIT(level2shift(level)); + u64 type, attrs; + + pte = ptep[i]; + type = pte & PTE_TYPE_MASK; + attrs = pte & PMD_ATTRINDX_MASK; + debug("PTE %llx at level %d VA %llx\n", pte, level, va); + + /* Not valid? next! */ + if (!(type & PTE_TYPE_VALID)) + continue; + + /* Not a leaf? Recurse on the next level */ + if (!(type == PTE_TYPE_BLOCK || + (level == 3 && type == PTE_TYPE_PAGE))) { + __cmo_on_leaves(cmo_fn, pte, level + 1, va); + continue; + } + + /* + * From this point, this must be a leaf. + * + * Start excluding non memory mappings + */ + if (attrs != PTE_BLOCK_MEMTYPE(MT_NORMAL) && + attrs != PTE_BLOCK_MEMTYPE(MT_NORMAL_NC)) + continue; + + end = va + BIT(level2shift(level)) - 1; + + /* No intersection with RAM? */ + if (end < gd->ram_base || + va >= (gd->ram_base + gd->ram_size)) + continue; + + /* + * OK, we have a partial RAM mapping. However, this + * can cover *more* than the RAM. Yes, u-boot is + * *that* braindead. Compute the intersection we care + * about, and not a byte more. + */ + va = max(va, (u64)gd->ram_base); + end = min(end, gd->ram_base + gd->ram_size); + + debug("Flush PTE %llx at level %d: %llx-%llx\n", + pte, level, va, end); + cmo_fn(va, end); + } +} + +static void apply_cmo_to_mappings(void (*cmo_fn)(unsigned long, unsigned long)) +{ + u64 va_bits; + int sl = 0; + + if (!gd->arch.tlb_addr) + return; + + get_tcr(NULL, &va_bits); + if (va_bits < 39) + sl = 1; + + __cmo_on_leaves(cmo_fn, gd->arch.tlb_addr, sl, 0); +} +#else +static inline void apply_cmo_to_mappings(void *dummy) {} +#endif + /* Returns and creates a new full table (512 entries) */ static u64 *create_table(void) { @@ -447,8 +524,12 @@ __weak void mmu_setup(void) */ void invalidate_dcache_all(void) { +#ifndef CONFIG_CMO_BY_VA_ONLY __asm_invalidate_dcache_all(); __asm_invalidate_l3_dcache(); +#else + apply_cmo_to_mappings(invalidate_dcache_range); +#endif } /* @@ -458,6 +539,7 @@ void invalidate_dcache_all(void) */ inline void flush_dcache_all(void) { +#ifndef CONFIG_CMO_BY_VA_ONLY int ret; __asm_flush_dcache_all(); @@ -466,6 +548,9 @@ inline void flush_dcache_all(void) debug("flushing dcache returns 0x%x\n", ret); else debug("flushing dcache successfully.\n"); +#else + apply_cmo_to_mappings(flush_dcache_range); +#endif } #ifndef CONFIG_SYS_DISABLE_DCACHE_OPS @@ -520,9 +605,19 @@ void dcache_disable(void) if (!(sctlr & CR_C)) return; + if (IS_ENABLED(CONFIG_CMO_BY_VA_ONLY)) { + /* + * When invalidating by VA, do it *before* turning the MMU + * off, so that at least our stack is coherent. + */ + flush_dcache_all(); + } + set_sctlr(sctlr & ~(CR_C|CR_M)); - flush_dcache_all(); + if (!IS_ENABLED(CONFIG_CMO_BY_VA_ONLY)) + flush_dcache_all(); + __asm_invalidate_tlb_all(); } diff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c index db5d460eb4..3c7f36ad8d 100644 --- a/arch/arm/cpu/armv8/cpu.c +++ b/arch/arm/cpu/armv8/cpu.c @@ -48,18 +48,26 @@ int cleanup_before_linux(void) disable_interrupts(); - /* - * Turn off I-cache and invalidate it - */ - icache_disable(); - invalidate_icache_all(); + if (IS_ENABLED(CONFIG_CMO_BY_VA_ONLY)) { + /* + * Disable D-cache. + */ + dcache_disable(); + } else { + /* + * Turn off I-cache and invalidate it + */ + icache_disable(); + invalidate_icache_all(); - /* - * turn off D-cache - * dcache_disable() in turn flushes the d-cache and disables MMU - */ - dcache_disable(); - invalidate_dcache_all(); + /* + * turn off D-cache + * dcache_disable() in turn flushes the d-cache and disables + * MMU + */ + dcache_disable(); + invalidate_dcache_all(); + } return 0; } From patchwork Wed Feb 8 20:54:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Paul Liu X-Patchwork-Id: 651708 Delivered-To: patch@linaro.org Received: by 2002:adf:f90f:0:0:0:0:0 with SMTP id b15csp3722575wrr; Wed, 8 Feb 2023 12:55:17 -0800 (PST) X-Google-Smtp-Source: AK7set8esfgTUocv5HKJUKb9RfLse+9Pzyo0WBDw83N56GklIH0VAodE7Le6X0Ml/SggLCm964E4 X-Received: by 2002:a05:6870:c111:b0:163:83b1:4061 with SMTP id f17-20020a056870c11100b0016383b14061mr4598227oad.0.1675889717358; Wed, 08 Feb 2023 12:55:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675889717; cv=none; d=google.com; s=arc-20160816; b=XQJe5UqhXLhmmSGub9IkyC9/iNUxSCyhKsmalGyWyImSKGxlJHMC9s7c0njZcrKppV 2axdxYBEznx33XnDxNhvo3Idxjfh8BV8Rrmln3EycbuETTEMS7o3c6/7SMxl5JY9C3Qf Sa7GJ1YheQl+klmAoOWu/1ElEam0CyJjcjq7DXDiJf4OlmZLh2ZcRO2yeEd6CvGYLVIl S6UB39fiVimHi/5fzGTDEDmuAXXm1K1Bn5sDhoyQ64skvx2S6tkNM52butqqyvJJZsDu U8R8M57nFsH/p4CSiE8yTbrm4ffgS0SludxZ6HkCOpfTx8Dg24AbU+ooo0KzGTX/WavD ZSrA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=FBbnUCC5G/tQ0vdiErusgxBBIUGpds9aO3c9lpVDmmw=; b=VXdRJdp2J5lnJWAvOJPVsdB3u8QWu05GWwmUB2vHSAJO/OphAw4cXbOpg0QakHiass /t/Y8cyFqYLsSgZMMkEirQx/pTAClb0F88gYnLtuCTx/ZSclgsg2U8OQ6O7CWiI1pQNm 3qkAr9EkIOaaWK15gTwcR0pD6jcIKBekkmkKni+cwBo/q06MRVFdM8u0wK4OYM60B3Yh +0+fTTiUhjYWVU4AtliNE3FIF/M/OBPLS7V8lJey2Zf61Bw7dEDhjLwhK1xYMfO0Yw0p h4qLZ8OXKkm0+qkjmdPuzw+n7SAV8DWcamoq3p+LO91DrTcq7V2z4cbXBAQWVKFLn9Sz Xl+A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="hzrc//JE"; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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As invalidate_dcache_all() will be called before the MMU has been initialized and as that function relies indirectly on the page tables when using CMO_BY_VA_ONLY, these must be in a valid state from their allocation. Signed-off-by: Pierre-Clément Tosi [ Paul: pick from the Android tree. Fix checkpatch warnings, and rebased to the upstream. ] Signed-off-by: Ying-Chun Liu (PaulLiu) Cc: Tom Rini Link: https://android.googlesource.com/platform/external/u-boot/+/e3ceef4230b772186c6853cace4a676a407e6ab7 --- v2: Fix the Signed-off-by list. --- arch/arm/lib/cache.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 1a589c7e2a..7a16015867 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -159,6 +159,15 @@ __weak int arm_reserve_mmu(void) */ gd->arch.tlb_allocated = gd->arch.tlb_addr; #endif + + if (IS_ENABLED(CONFIG_CMO_BY_VA_ONLY)) { + /* + * As invalidate_dcache_all() will be called before + * mmu_setup(), we should make sure that the PTs are + * already in a valid state. + */ + memset((void *)gd->arch.tlb_addr, 0, gd->arch.tlb_size); + } #endif return 0;