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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id gw1-20020a170906f14100b0087bd4e34eb8sm5495533ejb.203.2023.02.06.06.57.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Feb 2023 06:57:11 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Rob Clark , Abhinav Kumar , Sean Paul , dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, David Airlie , Daniel Vetter Subject: [PATCH v2 2/8] dt-bindings: power: qcom,rpmpd: add RPMH_REGULATOR_LEVEL_LOW_SVS_L1 Date: Mon, 6 Feb 2023 16:57:01 +0200 Message-Id: <20230206145707.122937-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230206145707.122937-1-dmitry.baryshkov@linaro.org> References: <20230206145707.122937-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add define for another power saving state used on SM8350 for the GPU. Signed-off-by: Dmitry Baryshkov --- include/dt-bindings/power/qcom-rpmpd.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index 4a30d10e6b7d..1bf8e87ecd7e 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -211,6 +211,7 @@ #define RPMH_REGULATOR_LEVEL_MIN_SVS 48 #define RPMH_REGULATOR_LEVEL_LOW_SVS_D1 56 #define RPMH_REGULATOR_LEVEL_LOW_SVS 64 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_L1 80 #define RPMH_REGULATOR_LEVEL_SVS 128 #define RPMH_REGULATOR_LEVEL_SVS_L0 144 #define RPMH_REGULATOR_LEVEL_SVS_L1 192 From patchwork Mon Feb 6 14:57:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 651085 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B623C64EC4 for ; Mon, 6 Feb 2023 14:57:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230253AbjBFO5Z (ORCPT ); Mon, 6 Feb 2023 09:57:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40396 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229874AbjBFO5Y (ORCPT ); Mon, 6 Feb 2023 09:57:24 -0500 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BA50E234E2 for ; Mon, 6 Feb 2023 06:57:16 -0800 (PST) Received: by mail-ej1-x62d.google.com with SMTP id ud5so34966966ejc.4 for ; Mon, 06 Feb 2023 06:57:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MzeGxqTBPrxIjG9qLHd24E7JXaEtDXkcFzdjyXT/GCk=; b=n1iigRfIDJ4id4dlaMsdX1m8lKOu7PqozI43UZe8WtJ9shvpv4gUaq50yzkLogIm58 MZQ5GwDKEuRSJRFFFU/P/IVQmTgwph9bAekrg0iu9PJZMMt7sCRvGTfxuSB1ecFDlKCF 8QaRzeVY/qpHA/bwi/wRHifnJlod7GCJvRR4+oCnchw8/cPFjdCfK7/09qFYin8ZBToc fC89AIoQT0gEABqEox8ydlMR7hIneaRhTLUKhb7wa6OMYSGAwev9FBhK9Fx3SBPk3PJN Tn/3fOvJSYtFvs0PYRdjTSPjHpe8GWV3xuz6qnKRYkruuZLW0Z31/Gzw71e4TmPd9m2D /hKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MzeGxqTBPrxIjG9qLHd24E7JXaEtDXkcFzdjyXT/GCk=; b=6U3mfAkt64TuBtAxpsZE2h0XONj/p03Hu8DqQfKj5INTwnb6DrSWrL2WOMvygoVmZf 1XuLGdK6So96cErsPKskjrqMd6Kb0n+Blnek5VBSWjCLjMloNqtuEd1hJiP/Fb5aml6j 6pwBJJHxgOAlxV8Ms2cbrRyrE54DJiqPNNev/zuIehXIfoUySgBz0cdFvdSprAhxyZps aYZRxdt/+56ibEkWpKPlvM/fJkBGOcEwzdPEBpmyrBxfGXZwem5an9cwgmZPOt85SjVB 52ytgRX/tZGj0OH8BkNBlWFY82807pRjkbqHyqhHSUkA966yd5g6HvAdhpojoaLmMoo5 ww+g== X-Gm-Message-State: AO0yUKWFKioYEfWQjXFrNKDR8VbaUK/m0pUVrLqJdNB0ZnulMxTMaTPo TgjiPbLXO3oUvX3su7Xhxe2Xjg== X-Google-Smtp-Source: AK7set8+Ka8xWRBWRyo8CYeuiSZaBpz6OfvHTEatEvkOqVzvGaK3uE3CsOn+nTCz1oPIWG/MQmVnkA== X-Received: by 2002:a17:906:7e4a:b0:878:66bc:2280 with SMTP id z10-20020a1709067e4a00b0087866bc2280mr19981633ejr.12.1675695435324; Mon, 06 Feb 2023 06:57:15 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id gw1-20020a170906f14100b0087bd4e34eb8sm5495533ejb.203.2023.02.06.06.57.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Feb 2023 06:57:15 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Rob Clark , Abhinav Kumar , Sean Paul , dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, David Airlie , Daniel Vetter Subject: [PATCH v2 5/8] arm64: dts: qcom: sm8350: move more nodes to correct place Date: Mon, 6 Feb 2023 16:57:04 +0200 Message-Id: <20230206145707.122937-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230206145707.122937-1-dmitry.baryshkov@linaro.org> References: <20230206145707.122937-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Continue ordering DT nodes. Move RNG, UFS, system NoC and SLPI nodes to the proper position. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 314 +++++++++++++-------------- 1 file changed, 157 insertions(+), 157 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 061aa3fec1c4..c327dc925793 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1423,6 +1423,13 @@ spi13: spi@a94000 { }; }; + rng: rng@10d3000 { + compatible = "qcom,prng-ee"; + reg = <0 0x010d3000 0 0x1000>; + clocks = <&rpmhcc RPMH_HWKM_CLK>; + clock-names = "core"; + }; + config_noc: interconnect@1500000 { compatible = "qcom,sm8350-config-noc"; reg = <0 0x01500000 0 0xa580>; @@ -1643,18 +1650,76 @@ pcie1_phy: phy@1c0f000 { status = "disabled"; }; - lpass_ag_noc: interconnect@3c40000 { - compatible = "qcom,sm8350-lpass-ag-noc"; - reg = <0 0x03c40000 0 0xf080>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; + ufs_mem_hc: ufshc@1d84000 { + compatible = "qcom,sm8350-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0 0x01d84000 0 0x3000>; + interrupts = ; + phys = <&ufs_mem_phy_lanes>; + phy-names = "ufsphy"; + lanes-per-direction = <2>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + power-domains = <&gcc UFS_PHY_GDSC>; + + iommus = <&apps_smmu 0xe0 0x0>; + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + status = "disabled"; }; - compute_noc: interconnect@a0c0000 { - compatible = "qcom,sm8350-compute-noc"; - reg = <0 0x0a0c0000 0 0xa180>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; + ufs_mem_phy: phy@1d87000 { + compatible = "qcom,sm8350-qmp-ufs-phy"; + reg = <0 0x01d87000 0 0x1c4>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clock-names = "ref", + "ref_aux"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + status = "disabled"; + + ufs_mem_phy_lanes: phy@1d87400 { + reg = <0 0x01d87400 0 0x188>, + <0 0x01d87600 0 0x200>, + <0 0x01d87c00 0 0x200>, + <0 0x01d87800 0 0x188>, + <0 0x01d87a00 0 0x200>; + #clock-cells = <1>; + #phy-cells = <0>; + }; }; ipa: ipa@1e40000 { @@ -1702,6 +1767,13 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells = <1>; }; + lpass_ag_noc: interconnect@3c40000 { + compatible = "qcom,sm8350-lpass-ag-noc"; + reg = <0 0x03c40000 0 0xf080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + mpss: remoteproc@4080000 { compatible = "qcom,sm8350-mpss-pas"; reg = <0x0 0x04080000 0x0 0x4040>; @@ -1744,6 +1816,74 @@ IPCC_MPROC_SIGNAL_GLINK_QMP }; }; + slpi: remoteproc@5c00000 { + compatible = "qcom,sm8350-slpi-pas"; + reg = <0 0x05c00000 0 0x4000>; + + interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SM8350_LCX>, + <&rpmhpd SM8350_LMX>; + power-domain-names = "lcx", "lmx"; + + memory-region = <&pil_slpi_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_slpi_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_SLPI + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_SLPI + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "slpi"; + qcom,remote-pid = <3>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "sdsp"; + qcom,non-secure-domain; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x0541 0x0>; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x0542 0x0>; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x0543 0x0>; + /* note: shared-cb = <4> in downstream */ + }; + }; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8350-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; @@ -2014,153 +2154,6 @@ qup_i2c19_default: qup-i2c19-default-state { }; }; - rng: rng@10d3000 { - compatible = "qcom,prng-ee"; - reg = <0 0x010d3000 0 0x1000>; - clocks = <&rpmhcc RPMH_HWKM_CLK>; - clock-names = "core"; - }; - - ufs_mem_hc: ufshc@1d84000 { - compatible = "qcom,sm8350-ufshc", "qcom,ufshc", - "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x3000>; - interrupts = ; - phys = <&ufs_mem_phy_lanes>; - phy-names = "ufsphy"; - lanes-per-direction = <2>; - #reset-cells = <1>; - resets = <&gcc GCC_UFS_PHY_BCR>; - reset-names = "rst"; - - power-domains = <&gcc UFS_PHY_GDSC>; - - iommus = <&apps_smmu 0xe0 0x0>; - - clock-names = - "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "rx_lane1_sync_clk"; - clocks = - <&gcc GCC_UFS_PHY_AXI_CLK>, - <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>, - <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; - freq-table-hz = - <75000000 300000000>, - <0 0>, - <0 0>, - <75000000 300000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>; - status = "disabled"; - }; - - ufs_mem_phy: phy@1d87000 { - compatible = "qcom,sm8350-qmp-ufs-phy"; - reg = <0 0x01d87000 0 0x1c4>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clock-names = "ref", - "ref_aux"; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; - - resets = <&ufs_mem_hc 0>; - reset-names = "ufsphy"; - status = "disabled"; - - ufs_mem_phy_lanes: phy@1d87400 { - reg = <0 0x01d87400 0 0x188>, - <0 0x01d87600 0 0x200>, - <0 0x01d87c00 0 0x200>, - <0 0x01d87800 0 0x188>, - <0 0x01d87a00 0 0x200>; - #clock-cells = <1>; - #phy-cells = <0>; - }; - }; - - slpi: remoteproc@5c00000 { - compatible = "qcom,sm8350-slpi-pas"; - reg = <0 0x05c00000 0 0x4000>; - - interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd SM8350_LCX>, - <&rpmhpd SM8350_LMX>; - power-domain-names = "lcx", "lmx"; - - memory-region = <&pil_slpi_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&smp2p_slpi_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_GLINK_QMP>; - - label = "slpi"; - qcom,remote-pid = <3>; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "sdsp"; - qcom,non-secure-domain; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - iommus = <&apps_smmu 0x0541 0x0>; - }; - - compute-cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <2>; - iommus = <&apps_smmu 0x0542 0x0>; - }; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x0543 0x0>; - /* note: shared-cb = <4> in downstream */ - }; - }; - }; - }; - sdhc_2: mmc@8804000 { compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>; @@ -2309,6 +2302,13 @@ system-cache-controller@9200000 { reg-names = "llcc_base", "llcc_broadcast_base"; }; + compute_noc: interconnect@a0c0000 { + compatible = "qcom,sm8350-compute-noc"; + reg = <0 0x0a0c0000 0 0xa180>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + usb_1: usb@a6f8800 { compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; reg = <0 0x0a6f8800 0 0x400>; From patchwork Mon Feb 6 14:57:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 651084 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9226C64ED6 for ; Mon, 6 Feb 2023 14:57:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229700AbjBFO51 (ORCPT ); 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id gw1-20020a170906f14100b0087bd4e34eb8sm5495533ejb.203.2023.02.06.06.57.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Feb 2023 06:57:16 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Rob Clark , Abhinav Kumar , Sean Paul , dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, David Airlie , Daniel Vetter Subject: [PATCH v2 6/8] arm64: dts: qcom: sm8350: finish reordering nodes Date: Mon, 6 Feb 2023 16:57:05 +0200 Message-Id: <20230206145707.122937-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230206145707.122937-1-dmitry.baryshkov@linaro.org> References: <20230206145707.122937-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Finish reordering DT nodes. Move PDC, tsens, AOSS, SRAM, SPMI and TLMM nodes to the proper position. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 764 +++++++++++++-------------- 1 file changed, 382 insertions(+), 382 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index c327dc925793..e5b308957f88 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1884,276 +1884,6 @@ compute-cb@3 { }; }; - pdc: interrupt-controller@b220000 { - compatible = "qcom,sm8350-pdc", "qcom,pdc"; - reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; - qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, - <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, - <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, - <156 716 12>; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupt-controller; - }; - - tsens0: thermal-sensor@c263000 { - compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; - reg = <0 0x0c263000 0 0x1ff>, /* TM */ - <0 0x0c222000 0 0x8>; /* SROT */ - #qcom,sensors = <15>; - interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - tsens1: thermal-sensor@c265000 { - compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; - reg = <0 0x0c265000 0 0x1ff>, /* TM */ - <0 0x0c223000 0 0x8>; /* SROT */ - #qcom,sensors = <14>; - interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - aoss_qmp: power-management@c300000 { - compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp"; - reg = <0 0x0c300000 0 0x400>; - interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; - - #clock-cells = <0>; - }; - - sram@c3f0000 { - compatible = "qcom,rpmh-stats"; - reg = <0 0x0c3f0000 0 0x400>; - }; - - spmi_bus: spmi@c440000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x0 0x0c440000 0x0 0x1100>, - <0x0 0x0c600000 0x0 0x2000000>, - <0x0 0x0e600000 0x0 0x100000>, - <0x0 0x0e700000 0x0 0xa0000>, - <0x0 0x0c40a000 0x0 0x26000>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - }; - - tlmm: pinctrl@f100000 { - compatible = "qcom,sm8350-tlmm"; - reg = <0 0x0f100000 0 0x300000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&tlmm 0 0 204>; - wakeup-parent = <&pdc>; - - sdc2_default_state: sdc2-default-state { - clk-pins { - pins = "sdc2_clk"; - drive-strength = <16>; - bias-disable; - }; - - cmd-pins { - pins = "sdc2_cmd"; - drive-strength = <16>; - bias-pull-up; - }; - - data-pins { - pins = "sdc2_data"; - drive-strength = <16>; - bias-pull-up; - }; - }; - - sdc2_sleep_state: sdc2-sleep-state { - clk-pins { - pins = "sdc2_clk"; - drive-strength = <2>; - bias-disable; - }; - - cmd-pins { - pins = "sdc2_cmd"; - drive-strength = <2>; - bias-pull-up; - }; - - data-pins { - pins = "sdc2_data"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - qup_uart3_default_state: qup-uart3-default-state { - rx-pins { - pins = "gpio18"; - function = "qup3"; - }; - tx-pins { - pins = "gpio19"; - function = "qup3"; - }; - }; - - qup_uart6_default: qup-uart6-default-state { - pins = "gpio30", "gpio31"; - function = "qup6"; - drive-strength = <2>; - bias-disable; - }; - - qup_uart18_default: qup-uart18-default-state { - pins = "gpio58", "gpio59"; - function = "qup18"; - drive-strength = <2>; - bias-disable; - }; - - qup_i2c0_default: qup-i2c0-default-state { - pins = "gpio4", "gpio5"; - function = "qup0"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c1_default: qup-i2c1-default-state { - pins = "gpio8", "gpio9"; - function = "qup1"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c2_default: qup-i2c2-default-state { - pins = "gpio12", "gpio13"; - function = "qup2"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c4_default: qup-i2c4-default-state { - pins = "gpio20", "gpio21"; - function = "qup4"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c5_default: qup-i2c5-default-state { - pins = "gpio24", "gpio25"; - function = "qup5"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c6_default: qup-i2c6-default-state { - pins = "gpio28", "gpio29"; - function = "qup6"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c7_default: qup-i2c7-default-state { - pins = "gpio32", "gpio33"; - function = "qup7"; - drive-strength = <2>; - bias-disable; - }; - - qup_i2c8_default: qup-i2c8-default-state { - pins = "gpio36", "gpio37"; - function = "qup8"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c9_default: qup-i2c9-default-state { - pins = "gpio40", "gpio41"; - function = "qup9"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c10_default: qup-i2c10-default-state { - pins = "gpio44", "gpio45"; - function = "qup10"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c11_default: qup-i2c11-default-state { - pins = "gpio48", "gpio49"; - function = "qup11"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c12_default: qup-i2c12-default-state { - pins = "gpio52", "gpio53"; - function = "qup12"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c13_default: qup-i2c13-default-state { - pins = "gpio0", "gpio1"; - function = "qup13"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c14_default: qup-i2c14-default-state { - pins = "gpio56", "gpio57"; - function = "qup14"; - drive-strength = <2>; - bias-disable; - }; - - qup_i2c15_default: qup-i2c15-default-state { - pins = "gpio60", "gpio61"; - function = "qup15"; - drive-strength = <2>; - bias-disable; - }; - - qup_i2c16_default: qup-i2c16-default-state { - pins = "gpio64", "gpio65"; - function = "qup16"; - drive-strength = <2>; - bias-disable; - }; - - qup_i2c17_default: qup-i2c17-default-state { - pins = "gpio72", "gpio73"; - function = "qup17"; - drive-strength = <2>; - bias-disable; - }; - - qup_i2c19_default: qup-i2c19-default-state { - pins = "gpio76", "gpio77"; - function = "qup19"; - drive-strength = <2>; - bias-disable; - }; - }; - sdhc_2: mmc@8804000 { compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>; @@ -2593,144 +2323,414 @@ mdss_dsi0_out: endpoint { }; }; - mdss_dsi0_phy: phy@ae94400 { - compatible = "qcom,sm8350-dsi-phy-5nm"; - reg = <0 0x0ae94400 0 0x200>, - <0 0x0ae94600 0 0x280>, - <0 0x0ae94900 0 0x27c>; - reg-names = "dsi_phy", - "dsi_phy_lane", - "dsi_pll"; - - #clock-cells = <1>; - #phy-cells = <0>; + mdss_dsi0_phy: phy@ae94400 { + compatible = "qcom,sm8350-dsi-phy-5nm"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94900 0 0x27c>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + mdss_dsi1: dsi@ae96000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae96000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>; + + operating-points-v2 = <&dsi1_opp_table>; + power-domains = <&rpmhpd SM8350_MMCX>; + + phys = <&mdss_dsi1_phy>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + dsi1_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* TODO: opp-187500000 should work with + * &rpmhpd_opp_low_svs, but one some of + * sm8350_hdk boards reboot using this + * opp. + */ + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae96400 { + compatible = "qcom,sm8350-dsi-phy-5nm"; + reg = <0 0x0ae96400 0 0x200>, + <0 0x0ae96600 0 0x280>, + <0 0x0ae96900 0 0x27c>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sm8350-dispcc"; + reg = <0 0x0af00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, + <0>, + <0>; + clock-names = "bi_tcxo", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + power-domains = <&rpmhpd SM8350_MMCX>; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sm8350-pdc", "qcom,pdc"; + reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; + qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, + <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, + <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, + <156 716 12>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + tsens0: thermal-sensor@c263000 { + compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; + reg = <0 0x0c263000 0 0x1ff>, /* TM */ + <0 0x0c222000 0 0x8>; /* SROT */ + #qcom,sensors = <15>; + interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c265000 { + compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; + reg = <0 0x0c265000 0 0x1ff>, /* TM */ + <0 0x0c223000 0 0x8>; /* SROT */ + #qcom,sensors = <14>; + interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + aoss_qmp: power-management@c300000 { + compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp"; + reg = <0 0x0c300000 0 0x400>; + interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells = <0>; + }; + + sram@c3f0000 { + compatible = "qcom,rpmh-stats"; + reg = <0 0x0c3f0000 0 0x400>; + }; + + spmi_bus: spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0 0x0c440000 0x0 0x1100>, + <0x0 0x0c600000 0x0 0x2000000>, + <0x0 0x0e600000 0x0 0x100000>, + <0x0 0x0e700000 0x0 0xa0000>, + <0x0 0x0c40a000 0x0 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + tlmm: pinctrl@f100000 { + compatible = "qcom,sm8350-tlmm"; + reg = <0 0x0f100000 0 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 204>; + wakeup-parent = <&pdc>; + + sdc2_default_state: sdc2-default-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <16>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + sdc2_sleep_state: sdc2-sleep-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <2>; + bias-disable; + }; - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names = "iface", "ref"; + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <2>; + bias-pull-up; + }; - status = "disabled"; + data-pins { + pins = "sdc2_data"; + drive-strength = <2>; + bias-pull-up; + }; }; - mdss_dsi1: dsi@ae96000 { - compatible = "qcom,mdss-dsi-ctrl"; - reg = <0 0x0ae96000 0 0x400>; - reg-names = "dsi_ctrl"; + qup_uart3_default_state: qup-uart3-default-state { + rx-pins { + pins = "gpio18"; + function = "qup3"; + }; + tx-pins { + pins = "gpio19"; + function = "qup3"; + }; + }; - interrupt-parent = <&mdss>; - interrupts = <5>; + qup_uart6_default: qup-uart6-default-state { + pins = "gpio30", "gpio31"; + function = "qup6"; + drive-strength = <2>; + bias-disable; + }; - clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, - <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, - <&dispcc DISP_CC_MDSS_PCLK1_CLK>, - <&dispcc DISP_CC_MDSS_ESC1_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&gcc GCC_DISP_HF_AXI_CLK>; - clock-names = "byte", - "byte_intf", - "pixel", - "core", - "iface", - "bus"; + qup_uart18_default: qup-uart18-default-state { + pins = "gpio58", "gpio59"; + function = "qup18"; + drive-strength = <2>; + bias-disable; + }; - assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, - <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi1_phy 0>, - <&mdss_dsi1_phy 1>; + qup_i2c0_default: qup-i2c0-default-state { + pins = "gpio4", "gpio5"; + function = "qup0"; + drive-strength = <2>; + bias-pull-up; + }; - operating-points-v2 = <&dsi1_opp_table>; - power-domains = <&rpmhpd SM8350_MMCX>; + qup_i2c1_default: qup-i2c1-default-state { + pins = "gpio8", "gpio9"; + function = "qup1"; + drive-strength = <2>; + bias-pull-up; + }; - phys = <&mdss_dsi1_phy>; + qup_i2c2_default: qup-i2c2-default-state { + pins = "gpio12", "gpio13"; + function = "qup2"; + drive-strength = <2>; + bias-pull-up; + }; - #address-cells = <1>; - #size-cells = <0>; + qup_i2c4_default: qup-i2c4-default-state { + pins = "gpio20", "gpio21"; + function = "qup4"; + drive-strength = <2>; + bias-pull-up; + }; - status = "disabled"; + qup_i2c5_default: qup-i2c5-default-state { + pins = "gpio24", "gpio25"; + function = "qup5"; + drive-strength = <2>; + bias-pull-up; + }; - dsi1_opp_table: opp-table { - compatible = "operating-points-v2"; + qup_i2c6_default: qup-i2c6-default-state { + pins = "gpio28", "gpio29"; + function = "qup6"; + drive-strength = <2>; + bias-pull-up; + }; - /* TODO: opp-187500000 should work with - * &rpmhpd_opp_low_svs, but one some of - * sm8350_hdk boards reboot using this - * opp. - */ - opp-187500000 { - opp-hz = /bits/ 64 <187500000>; - required-opps = <&rpmhpd_opp_svs>; - }; + qup_i2c7_default: qup-i2c7-default-state { + pins = "gpio32", "gpio33"; + function = "qup7"; + drive-strength = <2>; + bias-disable; + }; - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - required-opps = <&rpmhpd_opp_svs>; - }; + qup_i2c8_default: qup-i2c8-default-state { + pins = "gpio36", "gpio37"; + function = "qup8"; + drive-strength = <2>; + bias-pull-up; + }; - opp-358000000 { - opp-hz = /bits/ 64 <358000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - }; + qup_i2c9_default: qup-i2c9-default-state { + pins = "gpio40", "gpio41"; + function = "qup9"; + drive-strength = <2>; + bias-pull-up; + }; - ports { - #address-cells = <1>; - #size-cells = <0>; + qup_i2c10_default: qup-i2c10-default-state { + pins = "gpio44", "gpio45"; + function = "qup10"; + drive-strength = <2>; + bias-pull-up; + }; - port@0 { - reg = <0>; - mdss_dsi1_in: endpoint { - remote-endpoint = <&dpu_intf2_out>; - }; - }; + qup_i2c11_default: qup-i2c11-default-state { + pins = "gpio48", "gpio49"; + function = "qup11"; + drive-strength = <2>; + bias-pull-up; + }; - port@1 { - reg = <1>; - mdss_dsi1_out: endpoint { - }; - }; - }; + qup_i2c12_default: qup-i2c12-default-state { + pins = "gpio52", "gpio53"; + function = "qup12"; + drive-strength = <2>; + bias-pull-up; }; - mdss_dsi1_phy: phy@ae96400 { - compatible = "qcom,sm8350-dsi-phy-5nm"; - reg = <0 0x0ae96400 0 0x200>, - <0 0x0ae96600 0 0x280>, - <0 0x0ae96900 0 0x27c>; - reg-names = "dsi_phy", - "dsi_phy_lane", - "dsi_pll"; + qup_i2c13_default: qup-i2c13-default-state { + pins = "gpio0", "gpio1"; + function = "qup13"; + drive-strength = <2>; + bias-pull-up; + }; - #clock-cells = <1>; - #phy-cells = <0>; + qup_i2c14_default: qup-i2c14-default-state { + pins = "gpio56", "gpio57"; + function = "qup14"; + drive-strength = <2>; + bias-disable; + }; - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names = "iface", "ref"; + qup_i2c15_default: qup-i2c15-default-state { + pins = "gpio60", "gpio61"; + function = "qup15"; + drive-strength = <2>; + bias-disable; + }; - status = "disabled"; + qup_i2c16_default: qup-i2c16-default-state { + pins = "gpio64", "gpio65"; + function = "qup16"; + drive-strength = <2>; + bias-disable; }; - }; - dispcc: clock-controller@af00000 { - compatible = "qcom,sm8350-dispcc"; - reg = <0 0x0af00000 0 0x10000>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, - <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, - <0>, - <0>; - clock-names = "bi_tcxo", - "dsi0_phy_pll_out_byteclk", - "dsi0_phy_pll_out_dsiclk", - "dsi1_phy_pll_out_byteclk", - "dsi1_phy_pll_out_dsiclk", - "dp_phy_pll_link_clk", - "dp_phy_pll_vco_div_clk"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; + qup_i2c17_default: qup-i2c17-default-state { + pins = "gpio72", "gpio73"; + function = "qup17"; + drive-strength = <2>; + bias-disable; + }; - power-domains = <&rpmhpd SM8350_MMCX>; + qup_i2c19_default: qup-i2c19-default-state { + pins = "gpio76", "gpio77"; + function = "qup19"; + drive-strength = <2>; + bias-disable; + }; }; apps_smmu: iommu@15000000 { From patchwork Mon Feb 6 14:57:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 651083 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95151C6379F for ; Mon, 6 Feb 2023 14:57:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229874AbjBFO5d (ORCPT ); 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id gw1-20020a170906f14100b0087bd4e34eb8sm5495533ejb.203.2023.02.06.06.57.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Feb 2023 06:57:18 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Rob Clark , Abhinav Kumar , Sean Paul , dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, David Airlie , Daniel Vetter Subject: [PATCH v2 8/8] arm64: dts: qcom: sm8350-hdk: enable GPU Date: Mon, 6 Feb 2023 16:57:07 +0200 Message-Id: <20230206145707.122937-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230206145707.122937-1-dmitry.baryshkov@linaro.org> References: <20230206145707.122937-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enable the GPU on the SM8350-HDK device. The ZAP shader is required for the GPU to function properly. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index df841230d1b7..5e744423a673 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -284,6 +284,14 @@ &gpi_dma1 { status = "okay"; }; +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/sm8350/a660_zap.mbn"; + }; +}; + &i2c15 { clock-frequency = <400000>; status = "okay";