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Mon, 06 Feb 2023 04:17:21 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 1/9] target/arm: Restrict v7-M MMU helpers to sysemu TCG Date: Mon, 6 Feb 2023 13:17:06 +0100 Message-Id: <20230206121714.85084-2-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230206121714.85084-1-philmd@linaro.org> References: <20230206121714.85084-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philmd@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- target/arm/helper.c | 2 +- target/arm/m_helper.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index c62ed05c12..5dbeade787 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11774,7 +11774,7 @@ int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) } } -#ifndef CONFIG_TCG +#if !defined(CONFIG_TCG) || defined(CONFIG_USER_ONLY) ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) { g_assert_not_reached(); diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index e7e746ea18..1e7e4e33bd 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -2854,8 +2854,6 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) return tt_resp; } -#endif /* !CONFIG_USER_ONLY */ - ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, bool secstate, bool priv, bool negpri) { @@ -2892,3 +2890,5 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); } + +#endif /* !CONFIG_USER_ONLY */ From patchwork Mon Feb 6 12:17:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 650935 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp2238056pva; Mon, 6 Feb 2023 04:18:03 -0800 (PST) X-Google-Smtp-Source: AK7set8MM9Aw0SPCD/iim3bXkvKwNZ/uXbPT/Q5u/OPHuX97FlUCZqIBU09pWfN8AwkfGkO6dRoj X-Received: by 2002:ac8:5750:0:b0:3b8:6b23:4fc1 with SMTP id 16-20020ac85750000000b003b86b234fc1mr36555216qtx.2.1675685883829; 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Mon, 06 Feb 2023 04:17:26 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 2/9] target/arm: Constify ID_PFR1 on user emulation Date: Mon, 6 Feb 2023 13:17:07 +0100 Message-Id: <20230206121714.85084-3-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230206121714.85084-1-philmd@linaro.org> References: <20230206121714.85084-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/helper.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 5dbeade787..b58800a1a5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7021,6 +7021,7 @@ static void define_pmu_regs(ARMCPU *cpu) } } +#ifndef CONFIG_USER_ONLY /* * We don't know until after realize whether there's a GICv3 * attached, and that is what registers the gicv3 sysregs. @@ -7038,7 +7039,6 @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) return pfr1; } -#ifndef CONFIG_USER_ONLY static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) { ARMCPU *cpu = env_archcpu(env); @@ -7998,8 +7998,16 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1, .access = PL1_R, .type = ARM_CP_NO_RAW, .accessfn = access_aa32_tid3, +#ifdef CONFIG_USER_ONLY + .type = ARM_CP_CONST, + .resetvalue = cpu->isar.id_pfr1, +#else + .type = ARM_CP_NO_RAW, + .accessfn = access_aa32_tid3, .readfn = id_pfr1_read, - .writefn = arm_cp_write_ignore }, + .writefn = arm_cp_write_ignore +#endif + }, { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST, From patchwork Mon Feb 6 12:17:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 650940 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp2238544pva; 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Move it after the 'end_reset_fields' for consistency. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/cpu.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7bc97fece9..bbbcf2e153 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -721,11 +721,6 @@ typedef struct CPUArchState { ARMVectorReg zarray[ARM_MAX_VQ * 16]; #endif -#if defined(CONFIG_USER_ONLY) - /* For usermode syscall translation. */ - int eabi; -#endif - struct CPUBreakpoint *cpu_breakpoint[16]; struct CPUWatchpoint *cpu_watchpoint[16]; @@ -772,6 +767,10 @@ typedef struct CPUArchState { uint32_t ctrl; } sau; +#if defined(CONFIG_USER_ONLY) + /* For usermode syscall translation. */ + int eabi; +#endif void *nvic; const struct arm_boot_info *boot_info; /* Store GICv3CPUState to access from this struct */ From patchwork Mon Feb 6 12:17:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 650939 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp2238417pva; Mon, 6 Feb 2023 04:18:53 -0800 (PST) X-Google-Smtp-Source: AK7set/kX57wXAuTuPYdJNPYQaFsOVn88cyDAbbKmZmwTSqlkQOIfH2NhZ+6ijQYTpstDc8Y3HgA X-Received: by 2002:ac8:57c8:0:b0:3b8:6c84:aede with SMTP id w8-20020ac857c8000000b003b86c84aedemr33557247qta.17.1675685933062; Mon, 06 Feb 2023 04:18:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675685933; cv=none; d=google.com; s=arc-20160816; b=p5FKPN8KKlI0mYn24PB0LJT2NU/XtJsZBU/YsWZSBOJdLljCYOGHB2yVcNbjhLlXao 6YT341UdqkTjqbH1By7iHnfRnj0KNVML16HaO5Rfck+AOBrQWLblkhAV7WDikEUkNeFc CqDFclUo/D23xmeP5sR9m5DeLaV1wytm0nVU9gkiFHp9iY1vQ9Fg8Lo913c8yCNpZFeB 9FUKrL/cPdJsI+s7Fw0nW/dByJNCS7LlsVlMmDQ50LVxHzfcQGE1fEJgrbtwozeg89Ze bxWwLR69wH5hM+YuM5vk8xFPnyxswnx5emGllv/Ru+D+RAWdAEwT790+0GoUZoSYekyB Yfdw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=LXO14j3VKdWe9oMd0XtD7rpE8pnbdCJDTrrJ4g32Du4=; b=CC8XdxztmOkrD6r4x3WPTiy9RboGu4HZVn/4ni9joRsgMSb0cmgkKZDxnjgqhBFx2f ac2yWYae2CnUfQxZpmG48vamL0VS+VCo245GRtnQc4KiiIDb/olAiZBaCRwts5dN/03x wmj3+pITveu90R30jN9pHlgjTlr9CuhQ1WBu4CCcYGi4m0KmZZ6gLkTGieB7czd2Ba8j eOSuY/h7RzNdJqji2ISMuMAj/GEFU2yu4LFEEIk7W8ZOYm96wf6Vbm2n/xdjHICYXk05 KkEvQJp32OGG6jblqxDqN9dh1mZlMpmmAdFP2rMKquFEGpu6VNpe8i6YsCxVPIpgGIA1 gl8g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tTqa5kVv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Mon, 06 Feb 2023 04:17:36 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 4/9] target/arm: Restrict CPUARMState::arm_boot_info to sysemu Date: Mon, 6 Feb 2023 13:17:09 +0100 Message-Id: <20230206121714.85084-5-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230206121714.85084-1-philmd@linaro.org> References: <20230206121714.85084-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/cpu.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index bbbcf2e153..01d478e9ce 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -770,9 +770,10 @@ typedef struct CPUArchState { #if defined(CONFIG_USER_ONLY) /* For usermode syscall translation. */ int eabi; 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Mon, 06 Feb 2023 04:17:41 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 5/9] target/arm: Restrict CPUARMState::gicv3state to sysemu Date: Mon, 6 Feb 2023 13:17:10 +0100 Message-Id: <20230206121714.85084-6-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230206121714.85084-1-philmd@linaro.org> References: <20230206121714.85084-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 01d478e9ce..61681101a5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -772,10 +772,10 @@ typedef struct CPUArchState { int eabi; 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Use the real type to avoid casting it while debugging. Signed-off-by: Philippe Mathieu-Daudé --- hw/intc/armv7m_nvic.c | 38 ++++++++++------------------- include/hw/intc/armv7m_nvic.h | 5 +--- target/arm/cpu.c | 1 + target/arm/cpu.h | 46 ++++++++++++++++++----------------- target/arm/m_helper.c | 2 +- 5 files changed, 40 insertions(+), 52 deletions(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 1f7763964c..e54553283f 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -389,7 +389,7 @@ static inline int nvic_exec_prio(NVICState *s) return MIN(running, s->exception_prio); } -bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) { /* Return true if the requested execution priority is negative * for the specified security state, ie that security state @@ -399,8 +399,6 @@ bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) * mean we don't allow FAULTMASK_NS to actually make the execution * priority negative). Compare pseudocode IsReqExcPriNeg(). */ - NVICState *s = opaque; - if (s->cpu->env.v7m.faultmask[secure]) { return true; } @@ -418,17 +416,13 @@ bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) return false; } -bool armv7m_nvic_can_take_pending_exception(void *opaque) +bool armv7m_nvic_can_take_pending_exception(NVICState *s) { - NVICState *s = opaque; - return nvic_exec_prio(s) > nvic_pending_prio(s); } -int armv7m_nvic_raw_execution_priority(void *opaque) +int armv7m_nvic_raw_execution_priority(NVICState *s) { - NVICState *s = opaque; - return s->exception_prio; } @@ -506,9 +500,8 @@ static void nvic_irq_update(NVICState *s) * if @secure is true and @irq does not specify one of the fixed set * of architecturally banked exceptions. */ -static void armv7m_nvic_clear_pending(void *opaque, int irq, bool secure) +static void armv7m_nvic_clear_pending(NVICState *s, int irq, bool secure) { - NVICState *s = (NVICState *)opaque; VecInfo *vec; assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); @@ -666,17 +659,17 @@ static void do_armv7m_nvic_set_pending(void *opaque, int irq, bool secure, } } -void armv7m_nvic_set_pending(void *opaque, int irq, bool secure) +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure) { - do_armv7m_nvic_set_pending(opaque, irq, secure, false); + do_armv7m_nvic_set_pending(s, irq, secure, false); } -void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure) +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure) { - do_armv7m_nvic_set_pending(opaque, irq, secure, true); + do_armv7m_nvic_set_pending(s, irq, secure, true); } -void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure) +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure) { /* * Pend an exception during lazy FP stacking. This differs @@ -684,7 +677,6 @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure) * whether we should escalate depends on the saved context * in the FPCCR register, not on the current state of the CPU/NVIC. */ - NVICState *s = (NVICState *)opaque; bool banked = exc_is_banked(irq); VecInfo *vec; bool targets_secure; @@ -773,9 +765,8 @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure) } /* Make pending IRQ active. */ -void armv7m_nvic_acknowledge_irq(void *opaque) +void armv7m_nvic_acknowledge_irq(NVICState *s) { - NVICState *s = (NVICState *)opaque; CPUARMState *env = &s->cpu->env; const int pending = s->vectpending; const int running = nvic_exec_prio(s); @@ -814,10 +805,9 @@ static bool vectpending_targets_secure(NVICState *s) exc_targets_secure(s, s->vectpending); } -void armv7m_nvic_get_pending_irq_info(void *opaque, +void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq, bool *ptargets_secure) { - NVICState *s = (NVICState *)opaque; const int pending = s->vectpending; bool targets_secure; @@ -831,9 +821,8 @@ void armv7m_nvic_get_pending_irq_info(void *opaque, *pirq = pending; } -int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure) +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure) { - NVICState *s = (NVICState *)opaque; VecInfo *vec = NULL; int ret = 0; @@ -915,7 +904,7 @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure) return ret; } -bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure) { /* * Return whether an exception is "ready", i.e. it is enabled and is @@ -926,7 +915,6 @@ bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) * for non-banked exceptions secure is always false; for banked exceptions * it indicates which of the exceptions is required. */ - NVICState *s = (NVICState *)opaque; bool banked = exc_is_banked(irq); VecInfo *vec; int running = nvic_exec_prio(s); diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h index 0180c7b0ca..07f9c21a5f 100644 --- a/include/hw/intc/armv7m_nvic.h +++ b/include/hw/intc/armv7m_nvic.h @@ -16,10 +16,7 @@ #include "qom/object.h" #define TYPE_NVIC "armv7m_nvic" - -typedef struct NVICState NVICState; -DECLARE_INSTANCE_CHECKER(NVICState, NVIC, - TYPE_NVIC) +OBJECT_DECLARE_SIMPLE_TYPE(NVICState, NVIC) /* Highest permitted number of exceptions (architectural limit) */ #define NVIC_MAX_VECTORS 512 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5f63316dbf..b3a2275b08 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -36,6 +36,7 @@ #if !defined(CONFIG_USER_ONLY) #include "hw/loader.h" #include "hw/boards.h" +#include "hw/intc/armv7m_nvic.h" #endif #include "sysemu/tcg.h" #include "sysemu/qtest.h" diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 61681101a5..683e186599 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -227,6 +227,8 @@ typedef struct CPUARMTBFlags { typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; +typedef struct NVICState NVICState; + typedef struct CPUArchState { /* Regs for current mode. */ uint32_t regs[16]; @@ -774,8 +776,8 @@ typedef struct CPUArchState { const struct arm_boot_info *boot_info; /* Store GICv3CPUState to access from this struct */ void *gicv3state; + NVICState *nvic; #endif - void *nvic; #ifdef TARGET_TAGGED_ADDRESSES /* Linux syscall tagged address support */ @@ -2559,16 +2561,16 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, /* Interface between CPU and Interrupt controller. */ #ifndef CONFIG_USER_ONLY -bool armv7m_nvic_can_take_pending_exception(void *opaque); +bool armv7m_nvic_can_take_pending_exception(NVICState *s); #else -static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) +static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s) { return true; } #endif /** * armv7m_nvic_set_pending: mark the specified exception as pending - * @opaque: the NVIC + * @s: the NVIC * @irq: the exception number to mark pending * @secure: false for non-banked exceptions or for the nonsecure * version of a banked exception, true for the secure version of a banked @@ -2578,10 +2580,10 @@ static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) * if @secure is true and @irq does not specify one of the fixed set * of architecturally banked exceptions. */ -void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure); /** * armv7m_nvic_set_pending_derived: mark this derived exception as pending - * @opaque: the NVIC + * @s: the NVIC * @irq: the exception number to mark pending * @secure: false for non-banked exceptions or for the nonsecure * version of a banked exception, true for the secure version of a banked @@ -2591,10 +2593,10 @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); * exceptions (exceptions generated in the course of trying to take * a different exception). */ -void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure); /** * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending - * @opaque: the NVIC + * @s: the NVIC * @irq: the exception number to mark pending * @secure: false for non-banked exceptions or for the nonsecure * version of a banked exception, true for the secure version of a banked @@ -2603,11 +2605,11 @@ void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); * Similar to armv7m_nvic_set_pending(), but specifically for exceptions * generated in the course of lazy stacking of FP registers. */ -void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure); /** * armv7m_nvic_get_pending_irq_info: return highest priority pending * exception, and whether it targets Secure state - * @opaque: the NVIC + * @s: the NVIC * @pirq: set to pending exception number * @ptargets_secure: set to whether pending exception targets Secure * @@ -2617,20 +2619,20 @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); * to true if the current highest priority pending exception should * be taken to Secure state, false for NS. */ -void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, +void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq, bool *ptargets_secure); /** * armv7m_nvic_acknowledge_irq: make highest priority pending exception active - * @opaque: the NVIC + * @s: the NVIC * * Move the current highest priority pending exception from the pending * state to the active state, and update v7m.exception to indicate that * it is the exception currently being handled. */ -void armv7m_nvic_acknowledge_irq(void *opaque); +void armv7m_nvic_acknowledge_irq(NVICState *s); /** * armv7m_nvic_complete_irq: complete specified interrupt or exception - * @opaque: the NVIC + * @s: the NVIC * @irq: the exception number to complete * @secure: true if this exception was secure * @@ -2639,10 +2641,10 @@ void armv7m_nvic_acknowledge_irq(void *opaque); * 0 if there is still an irq active after this one was completed * (Ignoring -1, this is the same as the RETTOBASE value before completion.) */ -int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure); /** * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) - * @opaque: the NVIC + * @s: the NVIC * @irq: the exception number to mark pending * @secure: false for non-banked exceptions or for the nonsecure * version of a banked exception, true for the secure version of a banked @@ -2653,28 +2655,28 @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); * interrupt the current execution priority. This controls whether the * RDY bit for it in the FPCCR is set. */ -bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure); +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure); /** * armv7m_nvic_raw_execution_priority: return the raw execution priority - * @opaque: the NVIC + * @s: the NVIC * * Returns: the raw execution priority as defined by the v8M architecture. * This is the execution priority minus the effects of AIRCR.PRIS, * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. * (v8M ARM ARM I_PKLD.) */ -int armv7m_nvic_raw_execution_priority(void *opaque); +int armv7m_nvic_raw_execution_priority(NVICState *s); /** * armv7m_nvic_neg_prio_requested: return true if the requested execution * priority is negative for the specified security state. - * @opaque: the NVIC + * @s: the NVIC * @secure: the security state to test * This corresponds to the pseudocode IsReqExecPriNeg(). */ #ifndef CONFIG_USER_ONLY -bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure); #else -static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) +static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) { return false; } diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 1e7e4e33bd..f73d3f2264 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -973,7 +973,7 @@ static void v7m_update_fpccr(CPUARMState *env, uint32_t frameptr, * that we will need later in order to do lazy FP reg stacking. */ bool is_secure = env->v7m.secure; - void *nvic = env->nvic; + NVICState *nvic = env->nvic; /* * Some bits are unbanked and live always in fpccr[M_REG_S]; some bits * are banked and we want to update the bit in the bank for the From patchwork Mon Feb 6 12:17:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 650941 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp2238548pva; Mon, 6 Feb 2023 04:19:15 -0800 (PST) X-Google-Smtp-Source: AK7set+2FhdTXn0v+coP4ShhAwXK/6uRJfPzJvh//37X4kseY8jqD46YkYqLnY495ruWZMHscSdJ X-Received: by 2002:a05:622a:1343:b0:3b9:c070:f78d with SMTP id w3-20020a05622a134300b003b9c070f78dmr20838642qtk.39.1675685954924; Mon, 06 Feb 2023 04:19:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675685954; cv=none; d=google.com; s=arc-20160816; b=EpZxN3kNK7qet0y7izzvn/tyqgRQNvbOnzBECi+FwabNVvcVb0KzN2DYDRyuKGof7H Xj2c3niMqoeS7VKZ7A9ym0FCv2AKuiREIZ72Dp22MOW6eG6lt0NB1sOTK6BG11P0iIuh pUdQ2qXCJ8I3KYPQQcOSRCYOvff7zlZOCVOc+tHHekx8bAdfOP1kK0oDbW9P1xV7WBNu qxFkZH0mb51rLBsBkJQ7sJxS6bbCJDPRY3uX0V8rHFURxnvkX/m6QfMOmHsenQugIXg2 07ejw3ew0WoS+2hAJoVOUTxLG8k+EQZN6DsUKOI+hB58hKTh8nw6PvuwXj4yYWNrvx/7 GMSg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=yPKeeXf/qfQjoYgn7xRgNGOMBlz5IgFTpgVgpA92h0k=; b=WbQ3PORoG1Ka32Yt04FAULUlxN/IfsFvlhQndhQhuhQ3KJPax6WV19CeYpokjydfE6 JrASQYVsE/JMidhSEG5DUIrhzTFvFrKgN4ViYfwHiPXS4bfgQxvFXJ+r+yb3oBsDCWD/ pg81dog/QvNRlDsohjcf+uRJIdAArlZT2Ptro1vT38zdNSSh7x3VV2GO61FwztO+6MlD hi24LXG86yZFjGd7CgchyE8ITANmhGFpKMj3pPjKiQRXRAs/inK4ZqAf2owyA4zzLaMp /tURU9XUq5cGwtuOoWWy96kEb75yufWAexDxItGHyIUXfb3TDjxIspKNldOQbUpmMG3r +OHg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="U4/N7ra/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/hw/intc/armv7m_nvic.h | 123 ++++++++++++++++++++++++++++++++++ target/arm/cpu.c | 4 +- target/arm/cpu.h | 123 ---------------------------------- target/arm/cpu_tcg.c | 3 + target/arm/m_helper.c | 3 + 5 files changed, 132 insertions(+), 124 deletions(-) diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h index 07f9c21a5f..1ca262fbf8 100644 --- a/include/hw/intc/armv7m_nvic.h +++ b/include/hw/intc/armv7m_nvic.h @@ -83,4 +83,127 @@ struct NVICState { qemu_irq sysresetreq; }; +/* Interface between CPU and Interrupt controller. */ +/** + * armv7m_nvic_set_pending: mark the specified exception as pending + * @s: the NVIC + * @irq: the exception number to mark pending + * @secure: false for non-banked exceptions or for the nonsecure + * version of a banked exception, true for the secure version of a banked + * exception. + * + * Marks the specified exception as pending. Note that we will assert() + * if @secure is true and @irq does not specify one of the fixed set + * of architecturally banked exceptions. + */ +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure); +/** + * armv7m_nvic_set_pending_derived: mark this derived exception as pending + * @s: the NVIC + * @irq: the exception number to mark pending + * @secure: false for non-banked exceptions or for the nonsecure + * version of a banked exception, true for the secure version of a banked + * exception. + * + * Similar to armv7m_nvic_set_pending(), but specifically for derived + * exceptions (exceptions generated in the course of trying to take + * a different exception). + */ +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure); +/** + * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending + * @s: the NVIC + * @irq: the exception number to mark pending + * @secure: false for non-banked exceptions or for the nonsecure + * version of a banked exception, true for the secure version of a banked + * exception. + * + * Similar to armv7m_nvic_set_pending(), but specifically for exceptions + * generated in the course of lazy stacking of FP registers. + */ +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure); +/** + * armv7m_nvic_get_pending_irq_info: return highest priority pending + * exception, and whether it targets Secure state + * @s: the NVIC + * @pirq: set to pending exception number + * @ptargets_secure: set to whether pending exception targets Secure + * + * This function writes the number of the highest priority pending + * exception (the one which would be made active by + * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure + * to true if the current highest priority pending exception should + * be taken to Secure state, false for NS. + */ +void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq, + bool *ptargets_secure); +/** + * armv7m_nvic_acknowledge_irq: make highest priority pending exception active + * @s: the NVIC + * + * Move the current highest priority pending exception from the pending + * state to the active state, and update v7m.exception to indicate that + * it is the exception currently being handled. + */ +void armv7m_nvic_acknowledge_irq(NVICState *s); +/** + * armv7m_nvic_complete_irq: complete specified interrupt or exception + * @s: the NVIC + * @irq: the exception number to complete + * @secure: true if this exception was secure + * + * Returns: -1 if the irq was not active + * 1 if completing this irq brought us back to base (no active irqs) + * 0 if there is still an irq active after this one was completed + * (Ignoring -1, this is the same as the RETTOBASE value before completion.) + */ +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure); +/** + * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) + * @s: the NVIC + * @irq: the exception number to mark pending + * @secure: false for non-banked exceptions or for the nonsecure + * version of a banked exception, true for the secure version of a banked + * exception. + * + * Return whether an exception is "ready", i.e. whether the exception is + * enabled and is configured at a priority which would allow it to + * interrupt the current execution priority. This controls whether the + * RDY bit for it in the FPCCR is set. + */ +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure); +/** + * armv7m_nvic_raw_execution_priority: return the raw execution priority + * @s: the NVIC + * + * Returns: the raw execution priority as defined by the v8M architecture. + * This is the execution priority minus the effects of AIRCR.PRIS, + * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. + * (v8M ARM ARM I_PKLD.) + */ +int armv7m_nvic_raw_execution_priority(NVICState *s); +/** + * armv7m_nvic_neg_prio_requested: return true if the requested execution + * priority is negative for the specified security state. + * @s: the NVIC + * @secure: the security state to test + * This corresponds to the pseudocode IsReqExecPriNeg(). + */ +#ifndef CONFIG_USER_ONLY +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure); +#else +static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) +{ + return false; +} +#endif +#ifndef CONFIG_USER_ONLY +bool armv7m_nvic_can_take_pending_exception(NVICState *s); +#else +static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s) +{ + return true; +} +#endif + #endif diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b3a2275b08..876ab8f3bf 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -36,8 +36,10 @@ #if !defined(CONFIG_USER_ONLY) #include "hw/loader.h" #include "hw/boards.h" +#ifdef CONFIG_TCG #include "hw/intc/armv7m_nvic.h" -#endif +#endif /* CONFIG_TCG */ +#endif /* !CONFIG_USER_ONLY */ #include "sysemu/tcg.h" #include "sysemu/qtest.h" #include "sysemu/hw_accel.h" diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 683e186599..a6543c2153 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2559,129 +2559,6 @@ void arm_cpu_list(void); uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, uint32_t cur_el, bool secure); -/* Interface between CPU and Interrupt controller. */ -#ifndef CONFIG_USER_ONLY -bool armv7m_nvic_can_take_pending_exception(NVICState *s); -#else -static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s) -{ - return true; -} -#endif -/** - * armv7m_nvic_set_pending: mark the specified exception as pending - * @s: the NVIC - * @irq: the exception number to mark pending - * @secure: false for non-banked exceptions or for the nonsecure - * version of a banked exception, true for the secure version of a banked - * exception. - * - * Marks the specified exception as pending. Note that we will assert() - * if @secure is true and @irq does not specify one of the fixed set - * of architecturally banked exceptions. - */ -void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure); -/** - * armv7m_nvic_set_pending_derived: mark this derived exception as pending - * @s: the NVIC - * @irq: the exception number to mark pending - * @secure: false for non-banked exceptions or for the nonsecure - * version of a banked exception, true for the secure version of a banked - * exception. - * - * Similar to armv7m_nvic_set_pending(), but specifically for derived - * exceptions (exceptions generated in the course of trying to take - * a different exception). - */ -void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure); -/** - * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending - * @s: the NVIC - * @irq: the exception number to mark pending - * @secure: false for non-banked exceptions or for the nonsecure - * version of a banked exception, true for the secure version of a banked - * exception. - * - * Similar to armv7m_nvic_set_pending(), but specifically for exceptions - * generated in the course of lazy stacking of FP registers. - */ -void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure); -/** - * armv7m_nvic_get_pending_irq_info: return highest priority pending - * exception, and whether it targets Secure state - * @s: the NVIC - * @pirq: set to pending exception number - * @ptargets_secure: set to whether pending exception targets Secure - * - * This function writes the number of the highest priority pending - * exception (the one which would be made active by - * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure - * to true if the current highest priority pending exception should - * be taken to Secure state, false for NS. - */ -void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq, - bool *ptargets_secure); -/** - * armv7m_nvic_acknowledge_irq: make highest priority pending exception active - * @s: the NVIC - * - * Move the current highest priority pending exception from the pending - * state to the active state, and update v7m.exception to indicate that - * it is the exception currently being handled. - */ -void armv7m_nvic_acknowledge_irq(NVICState *s); -/** - * armv7m_nvic_complete_irq: complete specified interrupt or exception - * @s: the NVIC - * @irq: the exception number to complete - * @secure: true if this exception was secure - * - * Returns: -1 if the irq was not active - * 1 if completing this irq brought us back to base (no active irqs) - * 0 if there is still an irq active after this one was completed - * (Ignoring -1, this is the same as the RETTOBASE value before completion.) - */ -int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure); -/** - * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) - * @s: the NVIC - * @irq: the exception number to mark pending - * @secure: false for non-banked exceptions or for the nonsecure - * version of a banked exception, true for the secure version of a banked - * exception. - * - * Return whether an exception is "ready", i.e. whether the exception is - * enabled and is configured at a priority which would allow it to - * interrupt the current execution priority. This controls whether the - * RDY bit for it in the FPCCR is set. - */ -bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure); -/** - * armv7m_nvic_raw_execution_priority: return the raw execution priority - * @s: the NVIC - * - * Returns: the raw execution priority as defined by the v8M architecture. - * This is the execution priority minus the effects of AIRCR.PRIS, - * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. - * (v8M ARM ARM I_PKLD.) - */ -int armv7m_nvic_raw_execution_priority(NVICState *s); -/** - * armv7m_nvic_neg_prio_requested: return true if the requested execution - * priority is negative for the specified security state. - * @s: the NVIC - * @secure: the security state to test - * This corresponds to the pseudocode IsReqExecPriNeg(). - */ -#ifndef CONFIG_USER_ONLY -bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure); -#else -static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) -{ - return false; -} -#endif - /* Interface for defining coprocessor registers. * Registers are defined in tables of arm_cp_reginfo structs * which are passed to define_arm_cp_regs(). diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index ccde5080eb..df0c45e523 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -19,6 +19,9 @@ #include "hw/boards.h" #endif #include "cpregs.h" +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) +#include "hw/intc/armv7m_nvic.h" +#endif /* Share AArch32 -cpu max features with AArch64. */ diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index f73d3f2264..4dcb594a6b 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -18,6 +18,9 @@ #include "exec/cpu_ldst.h" #include "semihosting/common-semi.h" #endif +#if !defined(CONFIG_USER_ONLY) +#include "hw/intc/armv7m_nvic.h" +#endif static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, uint32_t reg, uint32_t val) From patchwork Mon Feb 6 12:17:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 650937 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp2238165pva; Mon, 6 Feb 2023 04:18:18 -0800 (PST) X-Google-Smtp-Source: AK7set+nGyEc6LbLC8s0JFkoAycCla05iV53cTdV7Yhn9vLV/s+IqiXUmCqH5RfnA+s1nX42iwDd X-Received: by 2002:a05:6214:508e:b0:56b:3295:4a75 with SMTP id kk14-20020a056214508e00b0056b32954a75mr19040612qvb.1.1675685898329; Mon, 06 Feb 2023 04:18:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675685898; cv=none; d=google.com; s=arc-20160816; b=nXYkplm0PZqLNNmEuRDaIQJOstjC/e9p5vrfNnSgY5wvwMCPz+tbHxmwCYAZWwqPcT VG7WR9fQdbGydmKkAY1J72Y508Gi0bEO6N724in/rhCxNKw+SObd28dLTD9mqnC5ItrY o7ufMnNzPQ+TJwhK4w3ue1nTQywcf4Q9JQX7TSzsm88yTtAMsN75OTWzaLjoqPN8o6UW yenu93WUgW/H97I/ObG1XE4U/KGBlyIuLcqsC13scQF/fKSf5Ynjnva0ueVLHnIrgFrw FXI3c8Bnx/JENKLAPofWJw7L+/+nrsu5YXu6itkCxOH2IJoM88X4z6FdSxEUBWp/qG+N TwYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=q9OtXnoXEv7c1NMHlxcIT3UzncY58Hccqx/D2ForunA=; b=jPGNSmkrnsKklf8gNHuU35eH+3GDjOzxd1WAEZeD+FZPjRdM1PfobM4YVhD4ZJHIei gxjbMg9pIGd03uo7QasrS5t/MHqZO40nTVux3QM2EZzcxKGUZjOR0+61pnjoZ7LFHxMu UNaObBX6OqAH+hgsUH2nFrLzWJvtXvPG0ax+e9AVvyl2yxSiJJ1+/ODC7GAD4y8kCNaC Pd1WeS67tumW0OGFc7i/oVvgxtjpGnFDrq63O86cjWVIXWM6MfPYy9Rbhg4CnyIcWmqK SKCxOBnq/XP2t1YpIc2Gn2dwcxbHB3C2NkoCYQL22Axtr4iwukA/Lx6krxt0BZCLd5vL T05w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uOVsfaed; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Mon, 06 Feb 2023 04:18:04 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 8/9] hw/intc/armv7m_nvic: Allow calling neg_prio_requested on unrealized NVIC Date: Mon, 6 Feb 2023 13:17:13 +0100 Message-Id: <20230206121714.85084-9-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230206121714.85084-1-philmd@linaro.org> References: <20230206121714.85084-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org armv7m_nvic_neg_prio_requested() is called via arm_cpu_reset_hold() during CPU realize() time, when the NVIC isn't yet realized: (lldb) bt * frame #0: 0x10059ed5c armv7m_nvic_neg_prio_requested(opaque=0x1180087b0, secure=true) at armv7m_nvic.c:404:9 frame #1: 0x100383018 arm_v7m_mmu_idx_for_secstate [inlined] arm_v7m_mmu_idx_for_secstate_and_priv(...) at m_helper.c:2882:19 frame #2: 0x10038300c arm_v7m_mmu_idx_for_secstate(..., secstate=true) at m_helper.c:2893:12 frame #3: 0x10036e9bc arm_mmu_idx_el(...) at helper.c:11799:16 [artificial] frame #4: 0x100366cd4 arm_rebuild_hflags [inlined] rebuild_hflags_internal(env=0x118411f30) at helper.c:12129:25 frame #5: 0x100366c18 arm_rebuild_hflags(env=0x118411f30) at helper.c:12142:19 frame #6: 0x10035f1c4 arm_cpu_reset_hold(...) at cpu.c:541:5 [artificial] frame #7: 0x10066b354 resettable_phase_hold(obj=0x118410000, opaque=0x000000000, ...) at resettable.c:0 frame #8: 0x10066ac40 resettable_assert_reset(obj=0x118410000, ...) at resettable.c:60:5 frame #9: 0x10066ab1c resettable_reset(obj=0x118410000, type=RESET_TYPE_COLD) at resettable.c:45:5 frame #10: 0x100669568 device_cold_reset(...) at qdev.c:255:5 [artificial] frame #11: 0x10000ca28 cpu_reset(cpu=0x118410000) at cpu-common.c:114:5 frame #12: 0x10035ec74 arm_cpu_realizefn(dev=0x118410000, errp=0x16fdfb910) at cpu.c:2145:5 frame #13: 0x10066a3e0 device_set_realized(...) at qdev.c:519:13 frame #14: 0x100671b98 property_set_bool(obj=0x118410000, ...) at object.c:2285:5 frame #15: 0x10066fdf4 object_property_set(obj=0x118410000, name="realized", ...) at object.c:1420:5 frame #16: 0x100673da8 object_property_set_qobject(...) at qom-qobject.c:28:10 frame #17: 0x10067026c object_property_set_bool(...) at object.c:1489:15 frame #18: 0x100669600 qdev_realize(...) at qdev.c:292:12 [artificial] frame #19: 0x1003101bc armv7m_realize(dev=0x118008480, ...) at armv7m.c:344:10 frame #20: 0x10066a3e0 device_set_realized(...) at qdev.c:519:13 frame #21: 0x100671b98 property_set_bool(obj=0x118008480, ...) at object.c:2285:5 frame #22: 0x10066fdf4 object_property_set(obj=0x118008480, name="realized", ...) at object.c:1420:5 frame #23: 0x100673da8 object_property_set_qobject(...) at qom-qobject.c:28:10 frame #24: 0x10067026c object_property_set_bool(...) at object.c:1489:15 frame #25: 0x100669600 qdev_realize(...) at qdev.c:292:12 [artificial] frame #26: 0x100092da8 sysbus_realize(...) at sysbus.c:256:12 [artificial] frame #27: 0x100350e1c armsse_realize(dev=0x118008150, ...) at armsse.c:1043:14 frame #28: 0x10066a3e0 device_set_realized(...) at qdev.c:519:13 frame #29: 0x100671b98 property_set_bool(obj=0x118008150, ...) at object.c:2285:5 frame #30: 0x10066fdf4 object_property_set(obj=0x118008150, name="realized", ...) at object.c:1420:5 frame #31: 0x100673da8 object_property_set_qobject(...) at qom-qobject.c:28:10 frame #32: 0x10067026c object_property_set_bool(...) at object.c:1489:15 frame #33: 0x100669600 qdev_realize(...) at qdev.c:292:12 [artificial] frame #34: 0x100092da8 sysbus_realize(...) at sysbus.c:256:12 [artificial] frame #35: 0x100349354 mps2tz_common_init(machine=0x118008000) at mps2-tz.c:834:5 frame #36: 0x10008e6b8 machine_run_board_init(machine=0x118008000, ...) at machine.c:1405:5 (lldb) frame select 12 frame #12: 0x10035ec74 arm_cpu_realizefn(dev=0x118410000, errp=0x16fdfb910) at cpu.c:2145:5 2142 } 2143 2144 qemu_init_vcpu(cs); -> 2145 cpu_reset(cs); 2146 2147 acc->parent_realize(dev, errp); 2148 } Signed-off-by: Philippe Mathieu-Daudé --- hw/intc/armv7m_nvic.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index e54553283f..d9c7e414bc 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -399,6 +399,11 @@ bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) * mean we don't allow FAULTMASK_NS to actually make the execution * priority negative). Compare pseudocode IsReqExcPriNeg(). */ + + if (!DEVICE(s)->realized) { /* XXX Why are we called while not realized? */ + return false; + } + if (s->cpu->env.v7m.faultmask[secure]) { return true; } From patchwork Mon Feb 6 12:17:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 650938 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp2238384pva; Mon, 6 Feb 2023 04:18:50 -0800 (PST) X-Google-Smtp-Source: AK7set+UrIFwbDMoYS5zN5MV1RAYxWUJ0+NSGE6n7pXexwMVePvHPgc/97L/g9YEg4TGiskaOo04 X-Received: by 2002:a05:622a:174a:b0:3b8:4694:b728 with SMTP id l10-20020a05622a174a00b003b84694b728mr39532484qtk.1.1675685929906; Mon, 06 Feb 2023 04:18:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675685929; cv=none; d=google.com; s=arc-20160816; b=07li5JO7/XUWX1EKWPMMJIBIozK3vWh88xfoXge0lHauv11sevggorC4LdI2ttQ6a8 E9gepD34aHIlg1Q3/8aJjMEa1CLY3pNigvkod+jweklsOuBpO3/bW71+b3mCAjdv2EVf Ea6ns8L3d5M0y4qXbo8C3iSB6ZvGDOjO3QPZx0inVKDaMvhJMrjJd+S/AlvanZWR6YIr A3XZLJOh6lQscxRWCGIM2Rz7ekb/KOHu3rN27OJrt4F9W+pA1YH/tAjXrNCG5KsUFtRC upopS68mqcgMeRJy9Vn/cZtH/OlGxXyOCyIxH4xAkBDXImYymxrwLSsdd5k6c8RMN6Tm Uzaw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=xK04lMyGXiTsZ6tKZ58V/KNKtbYzeddWJbilZBnE9nw=; b=VxUP4kMLbf4NoIQK+M7ZghEsyT7nyVhm8cUvpk5hLlMh7eTCPpUO2NjdpOX2OLPohU y7XnKLPWnxvOJUrHMg60hj2ADq3H1vygPkUhVYcf9udDABhzYSRKNnvsHz7xIU+GT3wj O6lPQQDnYlpaUDsSsq+FhBzAIkww4iuAx88tfZN62GZiiAk3eW+9aY2dHABuOKTSqVMi ysLuz00fB5hwq88u2Z4IzJnQ3PgJ1XuzxCgtCVIM8AJinVPUplkiyTHQW2Eifv6YSGSA JGV92ug5m75U8GuG0r+mfWMkZdmmVjRVT8TJQVvGoP3js2Ycpd2JpRqVRWRFTidbaduc VIKg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=D52Limxe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j14-20020ac85c4e000000b003b869542b62si7841471qtj.665.2023.02.06.04.18.49 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 06 Feb 2023 04:18:49 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=D52Limxe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pP0S2-0000xH-Uy; Mon, 06 Feb 2023 07:18:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pP0Rp-0000tY-A9 for qemu-devel@nongnu.org; Mon, 06 Feb 2023 07:18:13 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pP0Rn-0005ur-9W for qemu-devel@nongnu.org; Mon, 06 Feb 2023 07:18:13 -0500 Received: by mail-wr1-x433.google.com with SMTP id ba1so6108101wrb.5 for ; Mon, 06 Feb 2023 04:18:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xK04lMyGXiTsZ6tKZ58V/KNKtbYzeddWJbilZBnE9nw=; b=D52LimxeEnhnCNJrq8EfTT2PUerVJl4kyndYSyRbB/gGkKyoPohRWTWepJF61XLzpy /fuucykyj5jYUspGuIrwPe+3qrmAt6IbHXEZ7bGiqcEXgjfYed8C/9hpgoHIB54OYJyg puv+BTUHHheL6Q2GX6j+auGNckfDa6KA0TMx8ge9MIglNF+hQ4uEzABFbWdtZtErwyv9 9btdeWxECtSOScwqDrjl2kiNgePa3FmXcTlWhB2QaJB3N5cOkgPNuRTjT+cFsptTOddb Qb/uNLeXFOmfSOXrD1uEHAxiPx3pH9IuZV5O8a4zxmk8Ozun0Si8kdACJcBGWtIogIut KE0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xK04lMyGXiTsZ6tKZ58V/KNKtbYzeddWJbilZBnE9nw=; b=cijcULpbKjbQ+2sykU0e7TvzRGuaBLSmzwHlzo3mj4zHYdoPnYeZOuko8giNg7oCbI SL1coX9d4WMAOKmFMpzsMPcECnOTyQRj71YZ8eLfZXrja0tjzMBZ8N9DsMq4lORsYTEI HyNcrC8Vp22FjoNknBK60OIs3LdkKBoWhLJUH9Rix5a2aHyiccSR5rAoEdtcXhNsyv+A C1cK3H6U5SaLrvKSTwbg2uacCEC68sANvLBLDPHQ+NtA2u6G2YuOUTOmmSRWgUKDc4wM UfvBD9QgkdOtMDWaOTQdQog+IU4R39o0SBS0QKiQpKQojUh0IfB4RIy1eoq9l0XjdjB6 UXAg== X-Gm-Message-State: AO0yUKW7S7sesXbuu7JXnzupf4qS0sN3fqkM7Ys7MskSeppbJ+srWavz BTHL86+1DCwtTApejfEcQK1gZIVmnoHMXu+k X-Received: by 2002:a5d:6b0e:0:b0:2c2:6541:7afa with SMTP id v14-20020a5d6b0e000000b002c265417afamr19648680wrw.57.1675685889688; Mon, 06 Feb 2023 04:18:09 -0800 (PST) Received: from localhost.localdomain ([81.0.6.76]) by smtp.gmail.com with ESMTPSA id s14-20020adfa28e000000b002c3be49ef94sm8895439wra.52.2023.02.06.04.18.08 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Feb 2023 04:18:09 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Mark Cave-Ayland Subject: [PATCH 9/9] hw/arm/armv7m: Pass CPU/NVIC using object_property_add_const_link() Date: Mon, 6 Feb 2023 13:17:14 +0100 Message-Id: <20230206121714.85084-10-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230206121714.85084-1-philmd@linaro.org> References: <20230206121714.85084-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Avoid having QOM objects poke at each other internals. Instead, pass references using QOM link properties. Signed-off-by: Philippe Mathieu-Daudé --- Cc: Mark Cave-Ayland --- hw/arm/armv7m.c | 4 ++-- hw/intc/armv7m_nvic.c | 3 ++- target/arm/cpu.c | 3 ++- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 50a9507c0b..edde774da2 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -338,8 +338,8 @@ static void armv7m_realize(DeviceState *dev, Error **errp) * Tell the CPU where the NVIC is; it will fail realize if it doesn't * have one. Similarly, tell the NVIC where its CPU is. */ - s->cpu->env.nvic = &s->nvic; - s->nvic.cpu = s->cpu; + object_property_add_const_link(OBJECT(s->cpu), "nvic", OBJECT(&s->nvic)); + object_property_add_const_link(OBJECT(&s->nvic), "cpu", OBJECT(s->cpu)); if (!qdev_realize(DEVICE(s->cpu), NULL, errp)) { return; diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index d9c7e414bc..e43898a9e0 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2668,7 +2668,8 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp) NVICState *s = NVIC(dev); /* The armv7m container object will have set our CPU pointer */ - if (!s->cpu || !arm_feature(&s->cpu->env, ARM_FEATURE_M)) { + s->cpu = ARM_CPU(object_property_get_link(OBJECT(dev), "cpu", &error_abort)); + if (!arm_feature(&s->cpu->env, ARM_FEATURE_M)) { error_setg(errp, "The NVIC can only be used with a Cortex-M CPU"); return; } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 876ab8f3bf..f081861947 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1573,12 +1573,13 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) * error and will result in segfaults if not caught here. */ if (arm_feature(env, ARM_FEATURE_M)) { + env->nvic = NVIC(object_property_get_link(OBJECT(dev), "nvic", NULL)); if (!env->nvic) { error_setg(errp, "This board cannot be used with Cortex-M CPUs"); return; } } else { - if (env->nvic) { + if (object_property_find(OBJECT(dev), "nvic")) { error_setg(errp, "This board can only be used with Cortex-M CPUs"); return; }