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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id t64sm47261961pfa.86.2019.04.25.12.53.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 12:53:13 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 01/32] coresight: catu: fix clang build warning Date: Thu, 25 Apr 2019 13:52:39 -0600 Message-Id: <20190425195310.31562-2-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190425195310.31562-1-mathieu.poirier@linaro.org> References: <20190425195310.31562-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Arnd Bergmann Clang points out a syntax error, as the etr_catu_buf_ops structure is declared 'static' before the type is known: In file included from drivers/hwtracing/coresight/coresight-tmc-etr.c:12: drivers/hwtracing/coresight/coresight-catu.h:116:40: warning: tentative definition of variable with internal linkage has incomplete non-array type 'const struct etr_buf_operations' [-Wtentative-definition-incomplete-type] static const struct etr_buf_operations etr_catu_buf_ops; ^ drivers/hwtracing/coresight/coresight-catu.h:116:21: note: forward declaration of 'struct etr_buf_operations' static const struct etr_buf_operations etr_catu_buf_ops; This seems worth fixing in the code, so replace pointer to the empty constant structure with a NULL pointer. We need an extra NULL pointer check here, but the result should be better object code otherwise, avoiding the silly empty structure. Fixes: 434d611cddef ("coresight: catu: Plug in CATU as a backend for ETR buffer") Signed-off-by: Arnd Bergmann Reviewed-by: Suzuki K Poulose [Fixed line over 80 characters] Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-catu.h | 5 ----- drivers/hwtracing/coresight/coresight-tmc-etr.c | 5 +++-- 2 files changed, 3 insertions(+), 7 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-catu.h b/drivers/hwtracing/coresight/coresight-catu.h index 1b281f0dcccc..1d2ad183fd92 100644 --- a/drivers/hwtracing/coresight/coresight-catu.h +++ b/drivers/hwtracing/coresight/coresight-catu.h @@ -109,11 +109,6 @@ static inline bool coresight_is_catu_device(struct coresight_device *csdev) return true; } -#ifdef CONFIG_CORESIGHT_CATU extern const struct etr_buf_operations etr_catu_buf_ops; -#else -/* Dummy declaration for the CATU ops */ -static const struct etr_buf_operations etr_catu_buf_ops; -#endif #endif diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index f684283890d3..cf7a32ce209d 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -772,7 +772,8 @@ static inline void tmc_etr_disable_catu(struct tmc_drvdata *drvdata) static const struct etr_buf_operations *etr_buf_ops[] = { [ETR_MODE_FLAT] = &etr_flat_buf_ops, [ETR_MODE_ETR_SG] = &etr_sg_buf_ops, - [ETR_MODE_CATU] = &etr_catu_buf_ops, + [ETR_MODE_CATU] = IS_ENABLED(CONFIG_CORESIGHT_CATU) + ? &etr_catu_buf_ops : NULL, }; static inline int tmc_etr_mode_alloc_buf(int mode, @@ -786,7 +787,7 @@ static inline int tmc_etr_mode_alloc_buf(int mode, case ETR_MODE_FLAT: case ETR_MODE_ETR_SG: case ETR_MODE_CATU: - if (etr_buf_ops[mode]->alloc) + if (etr_buf_ops[mode] && etr_buf_ops[mode]->alloc) rc = etr_buf_ops[mode]->alloc(drvdata, etr_buf, node, pages); if (!rc) From patchwork Thu Apr 25 19:52:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 162860 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2362151jan; Thu, 25 Apr 2019 12:53:24 -0700 (PDT) X-Google-Smtp-Source: APXvYqymZ+Ru332vqoirqnY+6y5YDgPUlikF3p40R/ZNuJTsnyIwPN05eBrwAy0NRsx4+9Zqtc1l X-Received: by 2002:a65:5286:: with SMTP id y6mr38375995pgp.79.1556222004059; Thu, 25 Apr 2019 12:53:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556222004; cv=none; d=google.com; s=arc-20160816; b=QsHiHa/pGRX35aeEyqoSe1vQKU65luD6Kk01LxS/OJQ1CN7f3WPUl8R31ePx6rBmas cLiepP1YBUgAjz/M+/da502Ji4j1VAA2CwOdZL5ikyXKLlAsSLVVk39QC3bv86vGF8Xw +KJXz8LJxslhpGznslID9Bkx3PSSozy8Fk3b9OlyzJwmuuMoKpJ+2xKxao0G6w4kzs/d j5IuKIdZYSIs4h8eNKmVMM+Z1WCoJpAgqFl2lSc531L6wn1pokTgajT09JdFuSJ5NMmx uIS5yZS2QOMcdCToxts9tlZ4oWARw9RJcNOz86oYpKXITiah2ZSnPptosrIWViRqvEuA wjWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=SsYopIRysxpEbj7whdU4UQe3yKdQwJ8mx3qD/71IORY=; b=jx1thLA7gFRTTYFZS5MUf2oakys8td2EneTu9Pa9EO1/tJsCCfCuERUmO5SC4Np0Wc lnzG63mZuUV03MiaZf2QscCAgog1N0NotUowPOMXnO4X2n51nPuLrhBCtu5A7VE9pT/z gKaQsD1TgnMz83A8pAbVX49IWFEwskW9xWxBy7nNrnOrAYJrC4dolOHZCNhDKnDoGI42 uVjOZEc6/IbEln8JaEZDiodAiOnzvo5Qw1iOqo6e7Cf1ECKReJMPj/sTnOIrVjo8S7sQ GGe8oiwqLmAVAuQffuAggps1WjBf5dD/q40oKiA9yfCpgJz9kcoHG62sK+ustp5uEYjG n0VA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pEn3BjDJ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id t64sm47261961pfa.86.2019.04.25.12.53.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 12:53:14 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 02/32] coresight: catu: Make catu_helper_ops and catu_ops static Date: Thu, 25 Apr 2019 13:52:40 -0600 Message-Id: <20190425195310.31562-3-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190425195310.31562-1-mathieu.poirier@linaro.org> References: <20190425195310.31562-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: YueHaibing Fix sparse warnings: drivers/hwtracing/coresight/coresight-catu.c:488:35: warning: symbol 'catu_helper_ops' was not declared. Should it be static? drivers/hwtracing/coresight/coresight-catu.c:493:28: warning: symbol 'catu_ops' was not declared. Should it be static? Signed-off-by: YueHaibing Reviewed-by: Mukesh Ojha Reviewed-by: Suzuki K Poulose Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-catu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-catu.c b/drivers/hwtracing/coresight/coresight-catu.c index 170fbb66bda2..057627a0753d 100644 --- a/drivers/hwtracing/coresight/coresight-catu.c +++ b/drivers/hwtracing/coresight/coresight-catu.c @@ -485,12 +485,12 @@ static int catu_disable(struct coresight_device *csdev, void *__unused) return rc; } -const struct coresight_ops_helper catu_helper_ops = { +static const struct coresight_ops_helper catu_helper_ops = { .enable = catu_enable, .disable = catu_disable, }; -const struct coresight_ops catu_ops = { +static const struct coresight_ops catu_ops = { .helper_ops = &catu_helper_ops, }; From patchwork Thu Apr 25 19:52:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 162858 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2362069jan; Thu, 25 Apr 2019 12:53:19 -0700 (PDT) X-Google-Smtp-Source: APXvYqzGcJjZPxvZmK22SearMOs7NhrHNMhNKMOUwbSv5yEHK/X14HE9rYgvPhmB5why6Xxub/St X-Received: by 2002:a62:a503:: with SMTP id v3mr10141103pfm.32.1556221999346; Thu, 25 Apr 2019 12:53:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556221999; cv=none; d=google.com; s=arc-20160816; b=irLFC0TPhvDTh3u/r4pmc376bE+16fg0yDrj6RjZAXcoaql2eAd2BHICL9D6sMu2Qj C2HDREgRBGyS3g/65u016RzsVzhp18zot+ZlVpHEegD3n6GpaDWGEfl0KACYRqIma4c7 67VcYMnm6B0hnLVoZUGHsd2WeBP9HWWEM9SfN51gmSULhRzGRerT2FI6ewAnww8pWmOo GNdOdgxV5ZYxShXBYd0vlsYGB4OVGfWGg7qOaV1l9AINYQDHxAvUBpPcCD2VdMdQw2SP nSmkveBRh0eJ+1uKbO1xq/OTbrYrEfBc7KMNJyfxOa/5EhTzCbuwdDNoFSfPFqffUozQ H0LQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=4lhsES5zrfmug+wtErL+IQRdyF1VD03Excx4/nk2IFg=; b=EGGXcECwZcCUbnF1P7nBePyfb9PrbzV6k4+M0B602sP316WXy2xDmPRNCvjSMlhDcV 8lowosX9Aekj7L2GLzvTkryl2UXpyerOIfK/CMSI8e4ftwObBYBaGaWa8KVpsRtaIVN1 QzwRcj1oBc8OJXA1aimmehHqNCYLrPBVbpyzWPXjIfGno2GRwTwBZL79d/Le2ReTFZPI BZXB9RcKdKHHo5kErCeWKTsJ4q5F/aqOsriP5AIXfXM92vOh8XeNOoESR6aBicwCwp7S q4yrUB/NlQ4Iey8siF0/Vbs/e90ij9p8PPh2ENL5nVgcZbEgxksEwgJwpqKQ3k3MEINO AAmA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gwNLFIBD; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id t64sm47261961pfa.86.2019.04.25.12.53.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 12:53:15 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 03/32] coresight: tmc: Report DMA setup failures Date: Thu, 25 Apr 2019 13:52:41 -0600 Message-Id: <20190425195310.31562-4-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190425195310.31562-1-mathieu.poirier@linaro.org> References: <20190425195310.31562-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Suzuki K Poulose If we failed to setup the DMA mask for TMC-ETR, report the error before failing the probe. Cc: Mathieu Poirier Signed-off-by: Suzuki K Poulose Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-tmc.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c index 2a02da3d630f..647b6aa93554 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.c +++ b/drivers/hwtracing/coresight/coresight-tmc.c @@ -340,6 +340,8 @@ static inline bool tmc_etr_can_use_sg(struct tmc_drvdata *drvdata) static int tmc_etr_setup_caps(struct tmc_drvdata *drvdata, u32 devid, void *dev_caps) { + int rc; + u32 dma_mask = 0; /* Set the unadvertised capabilities */ @@ -369,7 +371,10 @@ static int tmc_etr_setup_caps(struct tmc_drvdata *drvdata, dma_mask = 40; } - return dma_set_mask_and_coherent(drvdata->dev, DMA_BIT_MASK(dma_mask)); + rc = dma_set_mask_and_coherent(drvdata->dev, DMA_BIT_MASK(dma_mask)); + if (rc) + dev_err(drvdata->dev, "Failed to setup DMA mask: %d\n", rc); + return rc; } static int tmc_probe(struct amba_device *adev, const struct amba_id *id) From patchwork Thu Apr 25 19:52:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 162885 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2364247jan; Thu, 25 Apr 2019 12:55:42 -0700 (PDT) X-Google-Smtp-Source: APXvYqy2jj1PUBCSx/xSJzvrQhBPEC5qvrd1xTR/mRk0cYgZHwG4VEWRklG/UBk6hQxeruw9T3pp X-Received: by 2002:a17:902:f81:: with SMTP id 1mr41402862plz.216.1556222142682; Thu, 25 Apr 2019 12:55:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556222142; cv=none; d=google.com; s=arc-20160816; b=pkQdzBeatGJE2DWKiENxDSOMMVC/vQ6oMR/QxbCmKPhzbh0c+JQPbFuhieQMhBr8ZU yQoXUCfrqJPgELb7rL7aSKMsDVkH1OTt9TxSfGAFKK9SVWeRjyVjxnnvpGiF56JGb1Rk dD27TcdKfdVF0AB4zAtU+lHhzRmqmgZTnbX8mce67Uki3r23O0aVfewy4mbsHNBgtvEs TT8blvDjmbZhQMngivpzh815YISmN8JpG/MTQJsFKFcx49gzkAvyaG2aRNGnXpxjUhiy J35pYO9ZKOEUpV31jW0nFN5ryw7Hb9yDaoczF+GKNpsoh7hBt2x6OoT4rN7D6+lubqet 2Y0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=5yAsUfu+K0x94KW8zQO1OsJicC/LEblGvw0y+dUj4Gg=; b=Kn1svbBrbFzgvuhjeaL8MsSarc7V7Mzu6oXDfzTNMWZ0f1+uolhwCDMCS6zEntzImZ MWuZWpAHCLq1N3e6nTx30ar4iTR9w0gL8OAhdSoVt6AvmPhWtIwwFDTwj54KKLGVm+g9 elZRVWxZJlpySrfXsAg+/zDt3h0Ku3sdAgyCxQSFsJMXLfyAlsMMzjUW0Fl4mMl/4SNH 5eCWHivMwkqRbmZ1/88xtV1JCmb+ZnwKn3STB92wQ3F5GvMaR4WdVug/znX7ntJeTqk6 T9dBPhEBLbOGYEy2KN+tCsxOdgBulvFwapDT5DPQmWW5zdiUeZqlhcRYCc1f+0tnggOZ cA4Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DnXhnAXb; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id t64sm47261961pfa.86.2019.04.25.12.53.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 12:53:17 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 04/32] coresight: dynamic-replicator: Clean up error handling Date: Thu, 25 Apr 2019 13:52:42 -0600 Message-Id: <20190425195310.31562-5-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190425195310.31562-1-mathieu.poirier@linaro.org> References: <20190425195310.31562-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Suzuki K Poulose We fail to disable the clock in case of a failure during the probe. Clean this up. Also, we are supposed to drop the pm reference only when the probing is successful. Cc: Mathieu Poirier Signed-off-by: Suzuki K Poulose Signed-off-by: Mathieu Poirier --- .../coresight/coresight-dynamic-replicator.c | 24 ++++++++++++------- 1 file changed, 16 insertions(+), 8 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-dynamic-replicator.c b/drivers/hwtracing/coresight/coresight-dynamic-replicator.c index 299667b887fc..fe176b987685 100644 --- a/drivers/hwtracing/coresight/coresight-dynamic-replicator.c +++ b/drivers/hwtracing/coresight/coresight-dynamic-replicator.c @@ -150,7 +150,7 @@ static const struct attribute_group *replicator_groups[] = { static int replicator_probe(struct amba_device *adev, const struct amba_id *id) { - int ret; + int ret = 0; struct device *dev = &adev->dev; struct resource *res = &adev->res; struct coresight_platform_data *pdata = NULL; @@ -180,12 +180,13 @@ static int replicator_probe(struct amba_device *adev, const struct amba_id *id) /* Validity for the resource is already checked by the AMBA core */ base = devm_ioremap_resource(dev, res); - if (IS_ERR(base)) - return PTR_ERR(base); + if (IS_ERR(base)) { + ret = PTR_ERR(base); + goto out_disable_clk; + } drvdata->base = base; dev_set_drvdata(dev, drvdata); - pm_runtime_put(&adev->dev); desc.type = CORESIGHT_DEV_TYPE_LINK; desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_SPLIT; @@ -195,11 +196,18 @@ static int replicator_probe(struct amba_device *adev, const struct amba_id *id) desc.groups = replicator_groups; drvdata->csdev = coresight_register(&desc); - if (!IS_ERR(drvdata->csdev)) { - replicator_reset(drvdata); - return 0; + if (IS_ERR(drvdata->csdev)) { + ret = PTR_ERR(drvdata->csdev); + goto out_disable_clk; } - return PTR_ERR(drvdata->csdev); + + replicator_reset(drvdata); + pm_runtime_put(&adev->dev); + +out_disable_clk: + if (ret && !IS_ERR_OR_NULL(drvdata->atclk)) + clk_disable_unprepare(drvdata->atclk); + return ret; } #ifdef CONFIG_PM From patchwork Thu Apr 25 19:52:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 162889 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2364566jan; Thu, 25 Apr 2019 12:56:02 -0700 (PDT) X-Google-Smtp-Source: APXvYqw30Rq1rT70H2M3kkD7oVdMR+INDGzpKqH8NGPxcKLic6wSu4HPN3P2HqBa/pk4Xu2lNx3v X-Received: by 2002:a62:e411:: with SMTP id r17mr42332853pfh.127.1556222162508; Thu, 25 Apr 2019 12:56:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556222162; cv=none; d=google.com; s=arc-20160816; b=cNfSX8+sFvVXr867ATGRq7WUKODG/bZYKRyw+aizM8/Uo+rIfA77InCbppPqPQgllt sGVQainR8u2m67dO1N3Pa98UAQmibPJg6GnrlPvf5PivUJ/e+/8itkKm71/o9j5OL4zx 6Oj4YlCn+rVrCUycncyNAsQIQoftktx9sDYjk4NvG59IidtO076Nizyh8d41M8Vs0cIk 6FFtQBw7FLL3s5b8vtk724q6Ng2XMKT+h7nWnKlvec8dPShCgEsN7DLGIvwdYFxM8fE+ gQmGN8i5wJKE6CY6wJxMaAemDeBKYcZL/vffTqWy8lbYTfhXX5lVaOOxUEO/0hxRPt3S NxFg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=bgGGBhw0+vDHwgRg8Lg3/ie77JvSZeI8JjKHAU8cgFw=; b=huLMxpi2ocK7KZfFwHrV/PFWYHSDc/gU5Pxueq/AwtMPo7BiP/Hbq0iEQSrH9cdvfm n2xpOWHjJf4UEaB0942JyBALdjTNyaC18jp25hvo0bgN3tYlN/Mu8/rnhA831GR2cEav NnnaWu3xQsS6vHBpbTMmOXES1XzLCpDm31KeSxOt4IaKquMLMIlciXz+craNMaEj5unY u2OXTgjkC2gRfmxN0TsTjA7t+fK3UE7cB1A2Zp1/jXwtVSxbKuZUtVwc96kjZVQJbKOr y6JmmqaoH1LpCiLdacDUORydXa7V0l7GtdGwW3la6k96ZA1TWNk5zdLIxXIPtfLZvYFN WeDw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CPnCXH5w; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id t64sm47261961pfa.86.2019.04.25.12.53.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 12:53:18 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 05/32] coresight: replicator: Prepare for merging with dynamic-replicator Date: Thu, 25 Apr 2019 13:52:43 -0600 Message-Id: <20190425195310.31562-6-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190425195310.31562-1-mathieu.poirier@linaro.org> References: <20190425195310.31562-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Suzuki K Poulose As a preparatory step to merge the separate drivers for static and dynamic replicators, annotate the static replicator specific details. Also refactor the probe routine to make it generic in order to merge the drivers easily. Cc: Mathieu Poirier Signed-off-by: Suzuki K Poulose Signed-off-by: Mathieu Poirier --- .../coresight/coresight-replicator.c | 62 +++++++++++-------- 1 file changed, 36 insertions(+), 26 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/hwtracing/coresight/coresight-replicator.c index feac98315471..43cbcf1e7be8 100644 --- a/drivers/hwtracing/coresight/coresight-replicator.c +++ b/drivers/hwtracing/coresight/coresight-replicator.c @@ -56,58 +56,68 @@ static const struct coresight_ops replicator_cs_ops = { .link_ops = &replicator_link_ops, }; -static int replicator_probe(struct platform_device *pdev) +static int replicator_probe(struct device *dev) { - int ret; - struct device *dev = &pdev->dev; + int ret = 0; struct coresight_platform_data *pdata = NULL; struct replicator_drvdata *drvdata; struct coresight_desc desc = { 0 }; - struct device_node *np = pdev->dev.of_node; + struct device_node *np = dev->of_node; if (np) { pdata = of_get_coresight_platform_data(dev, np); if (IS_ERR(pdata)) return PTR_ERR(pdata); - pdev->dev.platform_data = pdata; + dev->platform_data = pdata; } drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); if (!drvdata) return -ENOMEM; - drvdata->dev = &pdev->dev; - drvdata->atclk = devm_clk_get(&pdev->dev, "atclk"); /* optional */ + drvdata->dev = dev; + drvdata->atclk = devm_clk_get(dev, "atclk"); /* optional */ if (!IS_ERR(drvdata->atclk)) { ret = clk_prepare_enable(drvdata->atclk); if (ret) return ret; } - pm_runtime_get_noresume(&pdev->dev); - pm_runtime_set_active(&pdev->dev); - pm_runtime_enable(&pdev->dev); - platform_set_drvdata(pdev, drvdata); + + dev_set_drvdata(dev, drvdata); desc.type = CORESIGHT_DEV_TYPE_LINK; desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_SPLIT; desc.ops = &replicator_cs_ops; - desc.pdata = pdev->dev.platform_data; - desc.dev = &pdev->dev; + desc.pdata = dev->platform_data; + desc.dev = dev; drvdata->csdev = coresight_register(&desc); if (IS_ERR(drvdata->csdev)) { ret = PTR_ERR(drvdata->csdev); - goto out_disable_pm; + goto out_disable_clk; } - pm_runtime_put(&pdev->dev); + pm_runtime_put(dev); - return 0; - -out_disable_pm: - if (!IS_ERR(drvdata->atclk)) +out_disable_clk: + if (ret && !IS_ERR_OR_NULL(drvdata->atclk)) clk_disable_unprepare(drvdata->atclk); - pm_runtime_put_noidle(&pdev->dev); - pm_runtime_disable(&pdev->dev); + return ret; +} + +static int static_replicator_probe(struct platform_device *pdev) +{ + int ret; + + pm_runtime_get_noresume(&pdev->dev); + pm_runtime_set_active(&pdev->dev); + pm_runtime_enable(&pdev->dev); + + ret = replicator_probe(&pdev->dev); + + if (ret) { + pm_runtime_put_noidle(&pdev->dev); + pm_runtime_disable(&pdev->dev); + } return ret; } @@ -139,18 +149,18 @@ static const struct dev_pm_ops replicator_dev_pm_ops = { replicator_runtime_resume, NULL) }; -static const struct of_device_id replicator_match[] = { +static const struct of_device_id static_replicator_match[] = { {.compatible = "arm,coresight-replicator"}, {} }; -static struct platform_driver replicator_driver = { - .probe = replicator_probe, +static struct platform_driver static_replicator_driver = { + .probe = static_replicator_probe, .driver = { .name = "coresight-replicator", - .of_match_table = replicator_match, + .of_match_table = static_replicator_match, .pm = &replicator_dev_pm_ops, .suppress_bind_attrs = true, }, }; -builtin_platform_driver(replicator_driver); +builtin_platform_driver(static_replicator_driver); From patchwork Thu Apr 25 19:52:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 162861 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2362215jan; Thu, 25 Apr 2019 12:53:27 -0700 (PDT) X-Google-Smtp-Source: APXvYqyCJnR24yKWJXMUn8Lj7ZVwn9j8Lm66xq1WuRfb6jHUI4a621eIh1W7vMhaO8apb8DT3QNc X-Received: by 2002:aa7:91d6:: with SMTP id z22mr32966700pfa.242.1556222007604; Thu, 25 Apr 2019 12:53:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556222007; cv=none; d=google.com; s=arc-20160816; b=bmxySvl5rtI1E+rag1g7V7PyqHIR3PyjM1auM2yEw3AUEGJ6iJK/Go/kI8h8rjA4pb pKFPFw9Eu4YIxOi/bhW0T6scinP43godpAYWagGSMt0OYC16NctbMqTVn9n8CI1GDUz2 DyxndWs0N9CUv7uYKEggB3eic92h21x1aJXksnxE6LXz5QmOym9FbbispiJ+TXOtzGHe W6UQdH1vhuX71xw14iDVXOWt9S89KThYCf1LUOk7+eVdFjkEtC/SjRC9MbDypfn+zYLx 8u6yarjnP2cURuki0VXPuO6lAPpyU6hQbX/a6+4k0LIR5B82Ly+2mRlfCBBOP4mNsPux ZVRA== ARC-Message-Signature: i=1; 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id t64sm47261961pfa.86.2019.04.25.12.53.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 12:53:19 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 06/32] coresight: dynamic-replicator: Prepare for merging with static replicator Date: Thu, 25 Apr 2019 13:52:44 -0600 Message-Id: <20190425195310.31562-7-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190425195310.31562-1-mathieu.poirier@linaro.org> References: <20190425195310.31562-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Suzuki K Poulose Rename the dynamic replicator specific routines for merging with the replicator driver. Also re-arrange the probe routine to make it easier to merge. Cc: Mathieu Poirier Signed-off-by: Suzuki K Poulose Signed-off-by: Mathieu Poirier --- .../coresight/coresight-dynamic-replicator.c | 104 +++++++++++------- 1 file changed, 63 insertions(+), 41 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-dynamic-replicator.c b/drivers/hwtracing/coresight/coresight-dynamic-replicator.c index fe176b987685..b7d7c4146f9a 100644 --- a/drivers/hwtracing/coresight/coresight-dynamic-replicator.c +++ b/drivers/hwtracing/coresight/coresight-dynamic-replicator.c @@ -21,13 +21,13 @@ #define REPLICATOR_IDFILTER1 0x004 /** - * struct replicator_state - specifics associated to a replicator component + * struct replicator_drvdata - specifics associated to a replicator component * @base: memory mapped base address for this component. * @dev: the device entity associated with this component * @atclk: optional clock for the core parts of the replicator. * @csdev: component vitals needed by the framework */ -struct replicator_state { +struct replicator_drvdata { void __iomem *base; struct device *dev; struct clk *atclk; @@ -35,9 +35,9 @@ struct replicator_state { }; /* - * replicator_reset : Reset the replicator configuration to sane values. + * dynamic_replicator_reset : Reset the replicator configuration to sane values. */ -static void replicator_reset(struct replicator_state *drvdata) +static void dynamic_replicator_reset(struct replicator_drvdata *drvdata) { CS_UNLOCK(drvdata->base); @@ -50,12 +50,11 @@ static void replicator_reset(struct replicator_state *drvdata) CS_LOCK(drvdata->base); } -static int replicator_enable(struct coresight_device *csdev, int inport, - int outport) +static int dynamic_replicator_enable(struct replicator_drvdata *drvdata, + int inport, int outport) { int rc = 0; u32 reg; - struct replicator_state *drvdata = dev_get_drvdata(csdev->dev.parent); switch (outport) { case 0: @@ -76,21 +75,28 @@ static int replicator_enable(struct coresight_device *csdev, int inport, rc = coresight_claim_device_unlocked(drvdata->base); /* Ensure that the outport is enabled. */ - if (!rc) { + if (!rc) writel_relaxed(0x00, drvdata->base + reg); - dev_dbg(drvdata->dev, "REPLICATOR enabled\n"); - } - CS_LOCK(drvdata->base); return rc; } -static void replicator_disable(struct coresight_device *csdev, int inport, - int outport) +static int replicator_enable(struct coresight_device *csdev, int inport, + int outport) +{ + int rc = 0; + struct replicator_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + rc = dynamic_replicator_enable(drvdata, inport, outport); + dev_dbg(drvdata->dev, "REPLICATOR enabled\n"); + return rc; +} + +static void dynamic_replicator_disable(struct replicator_drvdata *drvdata, + int inport, int outport) { u32 reg; - struct replicator_state *drvdata = dev_get_drvdata(csdev->dev.parent); switch (outport) { case 0: @@ -113,7 +119,14 @@ static void replicator_disable(struct coresight_device *csdev, int inport, (readl_relaxed(drvdata->base + REPLICATOR_IDFILTER1) == 0xff)) coresight_disclaim_device_unlocked(drvdata->base); CS_LOCK(drvdata->base); +} + +static void replicator_disable(struct coresight_device *csdev, int inport, + int outport) +{ + struct replicator_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + dynamic_replicator_disable(drvdata, inport, outport); dev_dbg(drvdata->dev, "REPLICATOR disabled\n"); } @@ -127,7 +140,7 @@ static const struct coresight_ops replicator_cs_ops = { }; #define coresight_replicator_reg(name, offset) \ - coresight_simple_reg32(struct replicator_state, name, offset) + coresight_simple_reg32(struct replicator_drvdata, name, offset) coresight_replicator_reg(idfilter0, REPLICATOR_IDFILTER0); coresight_replicator_reg(idfilter1, REPLICATOR_IDFILTER1); @@ -148,52 +161,55 @@ static const struct attribute_group *replicator_groups[] = { NULL, }; -static int replicator_probe(struct amba_device *adev, const struct amba_id *id) +static int replicator_probe(struct device *dev, struct resource *res) { int ret = 0; - struct device *dev = &adev->dev; - struct resource *res = &adev->res; struct coresight_platform_data *pdata = NULL; - struct replicator_state *drvdata; + struct replicator_drvdata *drvdata; struct coresight_desc desc = { 0 }; - struct device_node *np = adev->dev.of_node; + struct device_node *np = dev->of_node; void __iomem *base; if (np) { pdata = of_get_coresight_platform_data(dev, np); if (IS_ERR(pdata)) return PTR_ERR(pdata); - adev->dev.platform_data = pdata; + dev->platform_data = pdata; } drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); if (!drvdata) return -ENOMEM; - drvdata->dev = &adev->dev; - drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */ + drvdata->dev = dev; + drvdata->atclk = devm_clk_get(dev, "atclk"); /* optional */ if (!IS_ERR(drvdata->atclk)) { ret = clk_prepare_enable(drvdata->atclk); if (ret) return ret; } - /* Validity for the resource is already checked by the AMBA core */ - base = devm_ioremap_resource(dev, res); - if (IS_ERR(base)) { - ret = PTR_ERR(base); - goto out_disable_clk; + /* + * Map the device base for dynamic-replicator, which has been + * validated by AMBA core + */ + if (res) { + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) { + ret = PTR_ERR(base); + goto out_disable_clk; + } + drvdata->base = base; + desc.groups = replicator_groups; } - drvdata->base = base; dev_set_drvdata(dev, drvdata); desc.type = CORESIGHT_DEV_TYPE_LINK; desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_SPLIT; desc.ops = &replicator_cs_ops; - desc.pdata = adev->dev.platform_data; - desc.dev = &adev->dev; - desc.groups = replicator_groups; + desc.pdata = dev->platform_data; + desc.dev = dev; drvdata->csdev = coresight_register(&desc); if (IS_ERR(drvdata->csdev)) { @@ -201,8 +217,8 @@ static int replicator_probe(struct amba_device *adev, const struct amba_id *id) goto out_disable_clk; } - replicator_reset(drvdata); - pm_runtime_put(&adev->dev); + dynamic_replicator_reset(drvdata); + pm_runtime_put(dev); out_disable_clk: if (ret && !IS_ERR_OR_NULL(drvdata->atclk)) @@ -210,10 +226,16 @@ static int replicator_probe(struct amba_device *adev, const struct amba_id *id) return ret; } +static int dynamic_replicator_probe(struct amba_device *adev, + const struct amba_id *id) +{ + return replicator_probe(&adev->dev, &adev->res); +} + #ifdef CONFIG_PM static int replicator_runtime_suspend(struct device *dev) { - struct replicator_state *drvdata = dev_get_drvdata(dev); + struct replicator_drvdata *drvdata = dev_get_drvdata(dev); if (drvdata && !IS_ERR(drvdata->atclk)) clk_disable_unprepare(drvdata->atclk); @@ -223,7 +245,7 @@ static int replicator_runtime_suspend(struct device *dev) static int replicator_runtime_resume(struct device *dev) { - struct replicator_state *drvdata = dev_get_drvdata(dev); + struct replicator_drvdata *drvdata = dev_get_drvdata(dev); if (drvdata && !IS_ERR(drvdata->atclk)) clk_prepare_enable(drvdata->atclk); @@ -238,7 +260,7 @@ static const struct dev_pm_ops replicator_dev_pm_ops = { NULL) }; -static const struct amba_id replicator_ids[] = { +static const struct amba_id dynamic_replicator_ids[] = { { .id = 0x000bb909, .mask = 0x000fffff, @@ -251,13 +273,13 @@ static const struct amba_id replicator_ids[] = { { 0, 0 }, }; -static struct amba_driver replicator_driver = { +static struct amba_driver dynamic_replicator_driver = { .drv = { .name = "coresight-dynamic-replicator", .pm = &replicator_dev_pm_ops, .suppress_bind_attrs = true, }, - .probe = replicator_probe, - .id_table = replicator_ids, + .probe = dynamic_replicator_probe, + .id_table = dynamic_replicator_ids, }; -builtin_amba_driver(replicator_driver); +builtin_amba_driver(dynamic_replicator_driver); From patchwork Thu Apr 25 19:52:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 162888 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2364462jan; Thu, 25 Apr 2019 12:55:54 -0700 (PDT) X-Google-Smtp-Source: APXvYqyV6GHThroOlKokfnlNlAW1QVjJ4sKgHHX7ZNwdtS3e5nmmDYZZjRlVb3Mng8Sl6H1rmvoY X-Received: by 2002:a65:448b:: with SMTP id l11mr38885382pgq.185.1556222154880; Thu, 25 Apr 2019 12:55:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556222154; cv=none; d=google.com; s=arc-20160816; b=BKqMI0howhrUnPMnsNlmeElfpprnAT9v+E8hHN4+RMc+aBNfFoHtNO5fgclY/a3k34 DxJtUD8xSwgJhQYQU4k1EBS3nVVkVA5QgCQnhDecYxwLY5euXkiTpg28w3QttoXgXncG j+O0XJGbouZHMZgvyFjNEMHsPN6ce1LIFS9PEdvkfq9F37+2J0mu6dHcR2h4TGYkRX5n ig2efsTdfXeaZkVV94jf23+iOL4dXvgHynvW00Z+RBF/aNto3dh8OoNr/3ABNu1SrBfd tPyO6XBJDA2qjlqTUt8j53KKk2AiV4PACHKd7jecvjOD2DG3otKTSgvE4ye08YkiR0Mh KEqg== ARC-Message-Signature: i=1; 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id t64sm47261961pfa.86.2019.04.25.12.53.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 12:53:20 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 07/32] coresight: Merge the static and dynamic replicator drivers Date: Thu, 25 Apr 2019 13:52:45 -0600 Message-Id: <20190425195310.31562-8-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190425195310.31562-1-mathieu.poirier@linaro.org> References: <20190425195310.31562-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Suzuki K Poulose Merge the drivers for the two varieties of replicators into a singel one. The dynamic replicator has programming base which can be programmed to filter the trace data. The driver detects the type based on the "base" address value of the device, which is NULL for the static device. Also, while at it, remove the now obsolete DYNAMIC_REPLICATOR config entry. Cc: Mathieu Poirier Signed-off-by: Suzuki K Poulose Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/Kconfig | 8 - drivers/hwtracing/coresight/Makefile | 1 - .../coresight/coresight-dynamic-replicator.c | 285 ------------------ .../coresight/coresight-replicator.c | 174 ++++++++++- 4 files changed, 169 insertions(+), 299 deletions(-) delete mode 100644 drivers/hwtracing/coresight/coresight-dynamic-replicator.c -- 2.17.1 diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index ad34380cac49..a40d796f0a4b 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -81,14 +81,6 @@ config CORESIGHT_SOURCE_ETM4X for instruction level tracing. Depending on the implemented version data tracing may also be available. -config CORESIGHT_DYNAMIC_REPLICATOR - bool "CoreSight Programmable Replicator driver" - depends on CORESIGHT_LINKS_AND_SINKS - help - This enables support for dynamic CoreSight replicator link driver. - The programmable ATB replicator allows independent filtering of the - trace data based on the traceid. - config CORESIGHT_STM bool "CoreSight System Trace Macrocell driver" depends on (ARM && !(CPU_32v3 || CPU_32v4 || CPU_32v4T)) || ARM64 diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index 41870ded51a3..3b435aa42af5 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -15,7 +15,6 @@ obj-$(CONFIG_CORESIGHT_SOURCE_ETM3X) += coresight-etm3x.o coresight-etm-cp14.o \ coresight-etm3x-sysfs.o obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o \ coresight-etm4x-sysfs.o -obj-$(CONFIG_CORESIGHT_DYNAMIC_REPLICATOR) += coresight-dynamic-replicator.o obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o obj-$(CONFIG_CORESIGHT_CATU) += coresight-catu.o diff --git a/drivers/hwtracing/coresight/coresight-dynamic-replicator.c b/drivers/hwtracing/coresight/coresight-dynamic-replicator.c deleted file mode 100644 index b7d7c4146f9a..000000000000 --- a/drivers/hwtracing/coresight/coresight-dynamic-replicator.c +++ /dev/null @@ -1,285 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "coresight-priv.h" - -#define REPLICATOR_IDFILTER0 0x000 -#define REPLICATOR_IDFILTER1 0x004 - -/** - * struct replicator_drvdata - specifics associated to a replicator component - * @base: memory mapped base address for this component. - * @dev: the device entity associated with this component - * @atclk: optional clock for the core parts of the replicator. - * @csdev: component vitals needed by the framework - */ -struct replicator_drvdata { - void __iomem *base; - struct device *dev; - struct clk *atclk; - struct coresight_device *csdev; -}; - -/* - * dynamic_replicator_reset : Reset the replicator configuration to sane values. - */ -static void dynamic_replicator_reset(struct replicator_drvdata *drvdata) -{ - CS_UNLOCK(drvdata->base); - - if (!coresight_claim_device_unlocked(drvdata->base)) { - writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0); - writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER1); - coresight_disclaim_device_unlocked(drvdata->base); - } - - CS_LOCK(drvdata->base); -} - -static int dynamic_replicator_enable(struct replicator_drvdata *drvdata, - int inport, int outport) -{ - int rc = 0; - u32 reg; - - switch (outport) { - case 0: - reg = REPLICATOR_IDFILTER0; - break; - case 1: - reg = REPLICATOR_IDFILTER1; - break; - default: - WARN_ON(1); - return -EINVAL; - } - - CS_UNLOCK(drvdata->base); - - if ((readl_relaxed(drvdata->base + REPLICATOR_IDFILTER0) == 0xff) && - (readl_relaxed(drvdata->base + REPLICATOR_IDFILTER1) == 0xff)) - rc = coresight_claim_device_unlocked(drvdata->base); - - /* Ensure that the outport is enabled. */ - if (!rc) - writel_relaxed(0x00, drvdata->base + reg); - CS_LOCK(drvdata->base); - - return rc; -} - -static int replicator_enable(struct coresight_device *csdev, int inport, - int outport) -{ - int rc = 0; - struct replicator_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - - rc = dynamic_replicator_enable(drvdata, inport, outport); - dev_dbg(drvdata->dev, "REPLICATOR enabled\n"); - return rc; -} - -static void dynamic_replicator_disable(struct replicator_drvdata *drvdata, - int inport, int outport) -{ - u32 reg; - - switch (outport) { - case 0: - reg = REPLICATOR_IDFILTER0; - break; - case 1: - reg = REPLICATOR_IDFILTER1; - break; - default: - WARN_ON(1); - return; - } - - CS_UNLOCK(drvdata->base); - - /* disable the flow of ATB data through port */ - writel_relaxed(0xff, drvdata->base + reg); - - if ((readl_relaxed(drvdata->base + REPLICATOR_IDFILTER0) == 0xff) && - (readl_relaxed(drvdata->base + REPLICATOR_IDFILTER1) == 0xff)) - coresight_disclaim_device_unlocked(drvdata->base); - CS_LOCK(drvdata->base); -} - -static void replicator_disable(struct coresight_device *csdev, int inport, - int outport) -{ - struct replicator_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - - dynamic_replicator_disable(drvdata, inport, outport); - dev_dbg(drvdata->dev, "REPLICATOR disabled\n"); -} - -static const struct coresight_ops_link replicator_link_ops = { - .enable = replicator_enable, - .disable = replicator_disable, -}; - -static const struct coresight_ops replicator_cs_ops = { - .link_ops = &replicator_link_ops, -}; - -#define coresight_replicator_reg(name, offset) \ - coresight_simple_reg32(struct replicator_drvdata, name, offset) - -coresight_replicator_reg(idfilter0, REPLICATOR_IDFILTER0); -coresight_replicator_reg(idfilter1, REPLICATOR_IDFILTER1); - -static struct attribute *replicator_mgmt_attrs[] = { - &dev_attr_idfilter0.attr, - &dev_attr_idfilter1.attr, - NULL, -}; - -static const struct attribute_group replicator_mgmt_group = { - .attrs = replicator_mgmt_attrs, - .name = "mgmt", -}; - -static const struct attribute_group *replicator_groups[] = { - &replicator_mgmt_group, - NULL, -}; - -static int replicator_probe(struct device *dev, struct resource *res) -{ - int ret = 0; - struct coresight_platform_data *pdata = NULL; - struct replicator_drvdata *drvdata; - struct coresight_desc desc = { 0 }; - struct device_node *np = dev->of_node; - void __iomem *base; - - if (np) { - pdata = of_get_coresight_platform_data(dev, np); - if (IS_ERR(pdata)) - return PTR_ERR(pdata); - dev->platform_data = pdata; - } - - drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); - if (!drvdata) - return -ENOMEM; - - drvdata->dev = dev; - drvdata->atclk = devm_clk_get(dev, "atclk"); /* optional */ - if (!IS_ERR(drvdata->atclk)) { - ret = clk_prepare_enable(drvdata->atclk); - if (ret) - return ret; - } - - /* - * Map the device base for dynamic-replicator, which has been - * validated by AMBA core - */ - if (res) { - base = devm_ioremap_resource(dev, res); - if (IS_ERR(base)) { - ret = PTR_ERR(base); - goto out_disable_clk; - } - drvdata->base = base; - desc.groups = replicator_groups; - } - - dev_set_drvdata(dev, drvdata); - - desc.type = CORESIGHT_DEV_TYPE_LINK; - desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_SPLIT; - desc.ops = &replicator_cs_ops; - desc.pdata = dev->platform_data; - desc.dev = dev; - drvdata->csdev = coresight_register(&desc); - - if (IS_ERR(drvdata->csdev)) { - ret = PTR_ERR(drvdata->csdev); - goto out_disable_clk; - } - - dynamic_replicator_reset(drvdata); - pm_runtime_put(dev); - -out_disable_clk: - if (ret && !IS_ERR_OR_NULL(drvdata->atclk)) - clk_disable_unprepare(drvdata->atclk); - return ret; -} - -static int dynamic_replicator_probe(struct amba_device *adev, - const struct amba_id *id) -{ - return replicator_probe(&adev->dev, &adev->res); -} - -#ifdef CONFIG_PM -static int replicator_runtime_suspend(struct device *dev) -{ - struct replicator_drvdata *drvdata = dev_get_drvdata(dev); - - if (drvdata && !IS_ERR(drvdata->atclk)) - clk_disable_unprepare(drvdata->atclk); - - return 0; -} - -static int replicator_runtime_resume(struct device *dev) -{ - struct replicator_drvdata *drvdata = dev_get_drvdata(dev); - - if (drvdata && !IS_ERR(drvdata->atclk)) - clk_prepare_enable(drvdata->atclk); - - return 0; -} -#endif - -static const struct dev_pm_ops replicator_dev_pm_ops = { - SET_RUNTIME_PM_OPS(replicator_runtime_suspend, - replicator_runtime_resume, - NULL) -}; - -static const struct amba_id dynamic_replicator_ids[] = { - { - .id = 0x000bb909, - .mask = 0x000fffff, - }, - { - /* Coresight SoC-600 */ - .id = 0x000bb9ec, - .mask = 0x000fffff, - }, - { 0, 0 }, -}; - -static struct amba_driver dynamic_replicator_driver = { - .drv = { - .name = "coresight-dynamic-replicator", - .pm = &replicator_dev_pm_ops, - .suppress_bind_attrs = true, - }, - .probe = dynamic_replicator_probe, - .id_table = dynamic_replicator_ids, -}; -builtin_amba_driver(dynamic_replicator_driver); diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/hwtracing/coresight/coresight-replicator.c index 43cbcf1e7be8..4e0da85efd2d 100644 --- a/drivers/hwtracing/coresight/coresight-replicator.c +++ b/drivers/hwtracing/coresight/coresight-replicator.c @@ -1,10 +1,11 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved. * * Description: CoreSight Replicator driver */ +#include #include #include #include @@ -18,25 +19,117 @@ #include "coresight-priv.h" +#define REPLICATOR_IDFILTER0 0x000 +#define REPLICATOR_IDFILTER1 0x004 + /** * struct replicator_drvdata - specifics associated to a replicator component + * @base: memory mapped base address for this component. Also indicates + * whether this one is programmable or not. * @dev: the device entity associated with this component * @atclk: optional clock for the core parts of the replicator. * @csdev: component vitals needed by the framework */ struct replicator_drvdata { + void __iomem *base; struct device *dev; struct clk *atclk; struct coresight_device *csdev; }; +static void dynamic_replicator_reset(struct replicator_drvdata *drvdata) +{ + CS_UNLOCK(drvdata->base); + + if (!coresight_claim_device_unlocked(drvdata->base)) { + writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0); + writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER1); + coresight_disclaim_device_unlocked(drvdata->base); + } + + CS_LOCK(drvdata->base); +} + +/* + * replicator_reset : Reset the replicator configuration to sane values. + */ +static inline void replicator_reset(struct replicator_drvdata *drvdata) +{ + if (drvdata->base) + dynamic_replicator_reset(drvdata); +} + +static int dynamic_replicator_enable(struct replicator_drvdata *drvdata, + int inport, int outport) +{ + int rc = 0; + u32 reg; + + switch (outport) { + case 0: + reg = REPLICATOR_IDFILTER0; + break; + case 1: + reg = REPLICATOR_IDFILTER1; + break; + default: + WARN_ON(1); + return -EINVAL; + } + + CS_UNLOCK(drvdata->base); + + if ((readl_relaxed(drvdata->base + REPLICATOR_IDFILTER0) == 0xff) && + (readl_relaxed(drvdata->base + REPLICATOR_IDFILTER1) == 0xff)) + rc = coresight_claim_device_unlocked(drvdata->base); + + /* Ensure that the outport is enabled. */ + if (!rc) + writel_relaxed(0x00, drvdata->base + reg); + CS_LOCK(drvdata->base); + + return rc; +} + static int replicator_enable(struct coresight_device *csdev, int inport, int outport) { + int rc = 0; struct replicator_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - dev_dbg(drvdata->dev, "REPLICATOR enabled\n"); - return 0; + if (drvdata->base) + rc = dynamic_replicator_enable(drvdata, inport, outport); + if (!rc) + dev_dbg(drvdata->dev, "REPLICATOR enabled\n"); + return rc; +} + +static void dynamic_replicator_disable(struct replicator_drvdata *drvdata, + int inport, int outport) +{ + u32 reg; + + switch (outport) { + case 0: + reg = REPLICATOR_IDFILTER0; + break; + case 1: + reg = REPLICATOR_IDFILTER1; + break; + default: + WARN_ON(1); + return; + } + + CS_UNLOCK(drvdata->base); + + /* disable the flow of ATB data through port */ + writel_relaxed(0xff, drvdata->base + reg); + + if ((readl_relaxed(drvdata->base + REPLICATOR_IDFILTER0) == 0xff) && + (readl_relaxed(drvdata->base + REPLICATOR_IDFILTER1) == 0xff)) + coresight_disclaim_device_unlocked(drvdata->base); + CS_LOCK(drvdata->base); } static void replicator_disable(struct coresight_device *csdev, int inport, @@ -44,6 +137,8 @@ static void replicator_disable(struct coresight_device *csdev, int inport, { struct replicator_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + if (drvdata->base) + dynamic_replicator_disable(drvdata, inport, outport); dev_dbg(drvdata->dev, "REPLICATOR disabled\n"); } @@ -56,13 +151,36 @@ static const struct coresight_ops replicator_cs_ops = { .link_ops = &replicator_link_ops, }; -static int replicator_probe(struct device *dev) +#define coresight_replicator_reg(name, offset) \ + coresight_simple_reg32(struct replicator_drvdata, name, offset) + +coresight_replicator_reg(idfilter0, REPLICATOR_IDFILTER0); +coresight_replicator_reg(idfilter1, REPLICATOR_IDFILTER1); + +static struct attribute *replicator_mgmt_attrs[] = { + &dev_attr_idfilter0.attr, + &dev_attr_idfilter1.attr, + NULL, +}; + +static const struct attribute_group replicator_mgmt_group = { + .attrs = replicator_mgmt_attrs, + .name = "mgmt", +}; + +static const struct attribute_group *replicator_groups[] = { + &replicator_mgmt_group, + NULL, +}; + +static int replicator_probe(struct device *dev, struct resource *res) { int ret = 0; struct coresight_platform_data *pdata = NULL; struct replicator_drvdata *drvdata; struct coresight_desc desc = { 0 }; struct device_node *np = dev->of_node; + void __iomem *base; if (np) { pdata = of_get_coresight_platform_data(dev, np); @@ -83,6 +201,20 @@ static int replicator_probe(struct device *dev) return ret; } + /* + * Map the device base for dynamic-replicator, which has been + * validated by AMBA core + */ + if (res) { + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) { + ret = PTR_ERR(base); + goto out_disable_clk; + } + drvdata->base = base; + desc.groups = replicator_groups; + } + dev_set_drvdata(dev, drvdata); desc.type = CORESIGHT_DEV_TYPE_LINK; @@ -96,6 +228,7 @@ static int replicator_probe(struct device *dev) goto out_disable_clk; } + replicator_reset(drvdata); pm_runtime_put(dev); out_disable_clk: @@ -112,7 +245,8 @@ static int static_replicator_probe(struct platform_device *pdev) pm_runtime_set_active(&pdev->dev); pm_runtime_enable(&pdev->dev); - ret = replicator_probe(&pdev->dev); + /* Static replicators do not have programming base */ + ret = replicator_probe(&pdev->dev, NULL); if (ret) { pm_runtime_put_noidle(&pdev->dev); @@ -164,3 +298,33 @@ static struct platform_driver static_replicator_driver = { }, }; builtin_platform_driver(static_replicator_driver); + +static int dynamic_replicator_probe(struct amba_device *adev, + const struct amba_id *id) +{ + return replicator_probe(&adev->dev, &adev->res); +} + +static const struct amba_id dynamic_replicator_ids[] = { + { + .id = 0x000bb909, + .mask = 0x000fffff, + }, + { + /* Coresight SoC-600 */ + .id = 0x000bb9ec, + .mask = 0x000fffff, + }, + { 0, 0 }, +}; + +static struct amba_driver dynamic_replicator_driver = { + .drv = { + .name = "coresight-dynamic-replicator", + .pm = &replicator_dev_pm_ops, + .suppress_bind_attrs = true, + }, + .probe = dynamic_replicator_probe, + .id_table = dynamic_replicator_ids, +}; +builtin_amba_driver(dynamic_replicator_driver); From patchwork Thu Apr 25 19:52:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 162887 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2364387jan; Thu, 25 Apr 2019 12:55:51 -0700 (PDT) X-Google-Smtp-Source: APXvYqyyveTtbdtqpgdSQWt+AnnCr/l4+70l0IC1GauLQVTumuv9/ORh+08r8Om6e7w/J+nimvP9 X-Received: by 2002:a63:4721:: with SMTP id u33mr9125511pga.199.1556222151635; Thu, 25 Apr 2019 12:55:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556222151; cv=none; d=google.com; s=arc-20160816; b=LV1VX1yf7kKfd1XUA/N6IYFhcrdfjE5i8wpGT40P0PL+OJJdGaljW1uHAag7F4PTL/ f/d7/yVbqToiRc4Dce0H2UYT/iM3cG4aNEmRoc5TjFpSCF6qtKMOCY56wZT1AdQcGnyT VI0qXqrP9lnOw3bNIRdAzgaBQF3TvDFUnVt/ZrcEw/fM8m6+wfM9oxxY3QXHHoVBVwV3 MdUznuzx3XNGQGXC/Ha80pkO+PVSthv+JDd2CIlcZYQoW2oj2mhrQWADref6XNF4vUw3 7aeeMGgI3FWmJuH7xq9l7evtl9uA2lQwOv3V4GB2NcU9j/w1zC/16B4aY0QO8siZUSQt BLMA== ARC-Message-Signature: i=1; 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id t64sm47261961pfa.86.2019.04.25.12.53.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 12:53:21 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 08/32] coresight: Fix freeing up the coresight connections Date: Thu, 25 Apr 2019 13:52:46 -0600 Message-Id: <20190425195310.31562-9-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190425195310.31562-1-mathieu.poirier@linaro.org> References: <20190425195310.31562-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Suzuki K Poulose With commit c2c729415b2d2132 ("coresight: platform: Cleanup coresight connection handling"), we switched to re-using coresight_connections for the coresight_device. However, that introduced a mismatch in the alloc/free of the connections. The allocation is made using devm_*, while we use kfree() to release the memory when a device is released (even though we don't support this at the moment). Fix this by leaving it to the automatic freeing of the memory. Fixes: c2c729415b2d2132 ("coresight: platform: Cleanup coresight connection handling") Cc: Mathieu Poirier Signed-off-by: Suzuki K Poulose Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight.c | 1 - 1 file changed, 1 deletion(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c index 29cef898afba..55204dd47479 100644 --- a/drivers/hwtracing/coresight/coresight.c +++ b/drivers/hwtracing/coresight/coresight.c @@ -973,7 +973,6 @@ static void coresight_device_release(struct device *dev) { struct coresight_device *csdev = to_coresight_device(dev); - kfree(csdev->conns); kfree(csdev->refcnt); kfree(csdev); } From patchwork Thu Apr 25 19:52:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 162886 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2364310jan; Thu, 25 Apr 2019 12:55:46 -0700 (PDT) X-Google-Smtp-Source: APXvYqzZD0ocwcFMcQ0ZciYEtLmbGTCyQmy8TK6UMNEesnxKyD8oT6teMfkLMPCr/CqKb8J7UMIi X-Received: by 2002:a17:902:988e:: with SMTP id s14mr41125186plp.167.1556222146818; Thu, 25 Apr 2019 12:55:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556222146; cv=none; d=google.com; s=arc-20160816; b=fmRmlqNAWKCj02SM0Bs7scyA/J044SSgjX4I+e7BF+/VL4JmqersJQnxs3KnJVeeh5 OFA7ekrnVI7syAigdvg8CPfdYgZkQFoJYKSJkfaheSahMvZQaRIRwoIQUsGHYqS71KEb g+vrYZix0beMbpWxhiOh/GVEFb4AxUB2PSYMoz233I854mK108sPDFpsV0JfBxDT00Yq emwr59GW1meLbIP2gLr9wNrarTdBFxDGZRz+VHNqRFXN8Qy27CPX5SnsXTKhI4qiFdUc dR2m+z2EwxnFax2qAMaFbrIHyV4WRUAb0+KCHsunO5Y+llgAmleZK88FV/d2yTrWtJRF hkHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=S4WlHnFG5egtduagk/Bt1xYutlfv3Ip/YBn9x1XM4EU=; b=o6PoUh8HC2Fpalop1ViDfRn4JiYsIFsB2fj3XwKXPC2LHXEAs5xoq0xr2xKXhiPE5i ku9cipnvA5sWtUSuwopJ2WFYokK3oZII1JEfrG8mNH0ZW/AWq25f+1ESorS4xaccx9rb lYpRR5RxN+rlDa7CEfowYUd1OpSs9Vm9ChSTxROjOEIH6zumd8QNpBaO0+Q/pKj9nVo9 g5BQKrWih41w3aDn/S4n2f7w3OESg2GMR2FP56ZEi6yORt3V0GxqbbFYfJPvDZp38uGe dFYkhJtXe0ecm1qBAAu7Wf7nEzQtLsq2sRPrxxrxWqi1UgML9Tdn5GCmgcZIjbcfmUN0 CLBQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Wp3ppGlG; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id t64sm47261961pfa.86.2019.04.25.12.53.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 12:53:23 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 09/32] coresight: etb10: Cleanup power management Date: Thu, 25 Apr 2019 13:52:47 -0600 Message-Id: <20190425195310.31562-10-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190425195310.31562-1-mathieu.poirier@linaro.org> References: <20190425195310.31562-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Suzuki K Poulose We drop the power before we complete the probe successfully. We are supposed to drop it only when we are successful. Also, probing the etb_buffer_length happens with the power turned up. So we don't need to do that again in the helper. Cc: Mathieu Poirier Signed-off-by: Suzuki K Poulose Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etb10.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 105782ea64c7..13c0a601d3be 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -93,17 +93,9 @@ struct etb_drvdata { static int etb_set_buffer(struct coresight_device *csdev, struct perf_output_handle *handle); -static unsigned int etb_get_buffer_depth(struct etb_drvdata *drvdata) +static inline unsigned int etb_get_buffer_depth(struct etb_drvdata *drvdata) { - u32 depth = 0; - - pm_runtime_get_sync(drvdata->dev); - - /* RO registers don't need locking */ - depth = readl_relaxed(drvdata->base + ETB_RAM_DEPTH_REG); - - pm_runtime_put(drvdata->dev); - return depth; + return readl_relaxed(drvdata->base + ETB_RAM_DEPTH_REG); } static void __etb_enable_hw(struct etb_drvdata *drvdata) @@ -720,7 +712,6 @@ static int etb_probe(struct amba_device *adev, const struct amba_id *id) spin_lock_init(&drvdata->spinlock); drvdata->buffer_depth = etb_get_buffer_depth(drvdata); - pm_runtime_put(&adev->dev); if (drvdata->buffer_depth & 0x80000000) return -EINVAL; @@ -747,6 +738,7 @@ static int etb_probe(struct amba_device *adev, const struct amba_id *id) if (ret) goto err_misc_register; + pm_runtime_put(&adev->dev); return 0; err_misc_register: From patchwork Thu Apr 25 19:52:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 162883 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2364105jan; Thu, 25 Apr 2019 12:55:33 -0700 (PDT) X-Google-Smtp-Source: APXvYqyMy+DGK6V+TqQCW26UG9wT7xNnz49A11xuyYX1IH+1bo8DsWNE7YbotkM5F4JdzeYZ2vcB X-Received: by 2002:a17:902:8c89:: with SMTP id t9mr42387547plo.265.1556222133753; Thu, 25 Apr 2019 12:55:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556222133; cv=none; d=google.com; s=arc-20160816; b=ALVnC/2K+EH+ZteG8oJHfcZ/rXLcqWuvHsEls0cd9rGRnR0EpppUxspO/fY/jsI1eG d+DUfRTjeoadpnr5aKMYwUCbf6XVaY4yc3jhQRGdsLWgNFIxWvwDdNpDOkyb2DfZzrC8 SDq22gYOxuyvmlFACKQJWw0n8wLgYrRiFnr0dhxDEaNvvieWjtvDao3RUKcqfTSVxen5 tijj6qN2L6R+iQvadlX3TN9dGDNHDZQfxrV2j8cZSE4p5A1xAGqP/o7tmJrIegsi6Zuo rmhXFO/LsrMiRvR22c+G03mjdTegmPvJ7sssNxLpHj/AOSBM9BltoIKE7ls/VSmA5dQ0 egvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=gDKvnZtlQcJ/F2zJQhfvE482g7t3vSsFp5ROjl2xttU=; b=a+3rXX76pCVdpTaRyynqG8eUORpqLR4WaQgvGXeXjPC2ZFAdM9xPx669e0QE/WsHwY jo1EWyvTk5FhxsvNhhPyfRS+lyk0ef6QsQcQFmHzpcwQ9Ag3tJUhAp4vfVwhNe/srzHT hrWJqK7l5/tt2kanUYETZQ7VE+7+VCtbZpo8Ges9M0Co4hSwzCNQbKNAcot13azjC72/ gVh69vrMUbXorDhD+jSWMKdEbc7xuMig86RkNYHhNBnf354z+gCqt/YBUcObcwYzcQwE qUAZCfxvte6x7/EiEnAsUqbbEPvJjEJzZTAuAiJ/P6jIfIj9xzip2xL3fY74KK26kcw1 sdeQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ldl8eDGE; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id t64sm47261961pfa.86.2019.04.25.12.53.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 12:53:24 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 10/32] coresight: tpiu: Cleanup power management Date: Thu, 25 Apr 2019 13:52:48 -0600 Message-Id: <20190425195310.31562-11-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190425195310.31562-1-mathieu.poirier@linaro.org> References: <20190425195310.31562-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Suzuki K Poulose Drop the power only when we have successfully probed. Otherwise leave it to the amba probe to do the rest. Cc: Mathieu Poirier Signed-off-by: Suzuki K Poulose [Removed extra newline left after original modification] Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-tpiu.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/hwtracing/coresight/coresight-tpiu.c index b2f72a1fa402..93e2ef34e734 100644 --- a/drivers/hwtracing/coresight/coresight-tpiu.c +++ b/drivers/hwtracing/coresight/coresight-tpiu.c @@ -153,8 +153,6 @@ static int tpiu_probe(struct amba_device *adev, const struct amba_id *id) /* Disable tpiu to support older devices */ tpiu_disable_hw(drvdata); - pm_runtime_put(&adev->dev); - desc.type = CORESIGHT_DEV_TYPE_SINK; desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_PORT; desc.ops = &tpiu_cs_ops; @@ -162,7 +160,12 @@ static int tpiu_probe(struct amba_device *adev, const struct amba_id *id) desc.dev = dev; drvdata->csdev = coresight_register(&desc); - return PTR_ERR_OR_ZERO(drvdata->csdev); + if (!IS_ERR(drvdata->csdev)) { + pm_runtime_put(&adev->dev); + return 0; + } + + return PTR_ERR(drvdata->csdev); } #ifdef CONFIG_PM From patchwork Thu Apr 25 19:52:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 162862 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2362275jan; Thu, 25 Apr 2019 12:53:31 -0700 (PDT) X-Google-Smtp-Source: APXvYqwmZKK9lo4k6O/p5WkVTnb76V1RZk4g+p3AHfaC6ZIPq2PPMYJMynexF4GWU1qR17x9EArA X-Received: by 2002:aa7:991b:: with SMTP id z27mr14775597pff.168.1556222011182; Thu, 25 Apr 2019 12:53:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556222011; cv=none; d=google.com; s=arc-20160816; b=RLcaMZer4yuboWaFTCN04rMENoayrWyp5u/ZtXrM8jzjT6F5XT046Lkt9HiYnwPdvv AGPQPFBnzt6Pkjwf56CiYb4a4qnI0uRDQlKbG7E8y9tblq5/qAD0yeMIm6/HtZ4T7bKP 6Pvl1LDSaG3nGpWt8GlV7cKehjWAyULSP2dePveVRWWiJ8Dt/ydGOf7eoSTZJps72/qB /b9zq8fCd1UAn1CZ94sACaXAvHqxx8P9ZRBn1efQ3TvqKY7xBOHoktU4RPTYJQ5WixT9 F49tpINmwWvccnT0YQgPlguUWjB/cPX0S5Y++bOFDz49i/7tqMrATSV1HSh2U86QzQ/z eirg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=Cvob0FDX1MLZ+fYnYf8rcIMYa/saPGP93kDs1sAwGb4=; b=hpzkSQP1XycST/8vxuZbXFfeNd2UiQP0hlm35dv71jNKe0MVfvIWWl0XqJAaWLJNAl 7yhz5ONJCXB+AKjX4/jtfgL8wWD6jiJw9cYs/6r1oB0Od+ZqUBGrjSna12/MG/HBJEuf NcnAjIVXdF1f8apV3x8LigHIlTM1uqfHGyDTbKG9gY30ovWs5Dyd+9aGHjmk/zxOch6W Ud+zTMUtXGydFsWdNMViUT1UdvzaLxAtCIOFCUSo8g5LhfbGBqmbgoHQSY+SivCX2f7N xx7KEpfOTO4kJFVTnSQyv/a//Grj5O4CUSMrX8WbmC4TGwz/WP22kkXxPT0ckdoZ8YiL FXBw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="rh//OABQ"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id t64sm47261961pfa.86.2019.04.25.12.53.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 12:53:25 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 11/32] coresight: catu: Cleanup power management Date: Thu, 25 Apr 2019 13:52:49 -0600 Message-Id: <20190425195310.31562-12-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190425195310.31562-1-mathieu.poirier@linaro.org> References: <20190425195310.31562-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Suzuki K Poulose Drop the power handle only if we were successful. Otherwise the AMBA bus code would do the rest. Cc: Mathieu Poirier Signed-off-by: Suzuki K Poulose Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-catu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-catu.c b/drivers/hwtracing/coresight/coresight-catu.c index 057627a0753d..4ea68a3522e9 100644 --- a/drivers/hwtracing/coresight/coresight-catu.c +++ b/drivers/hwtracing/coresight/coresight-catu.c @@ -557,8 +557,9 @@ static int catu_probe(struct amba_device *adev, const struct amba_id *id) drvdata->csdev = coresight_register(&catu_desc); if (IS_ERR(drvdata->csdev)) ret = PTR_ERR(drvdata->csdev); + else + pm_runtime_put(&adev->dev); out: - pm_runtime_put(&adev->dev); return ret; } From patchwork Thu Apr 25 19:52:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 162884 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2364172jan; Thu, 25 Apr 2019 12:55:37 -0700 (PDT) X-Google-Smtp-Source: APXvYqz7Py/UXYt37/5nROrcSt7sEurkUIfcwVtn2S25vXf/aL/NHdoJ1gAvazO62EmslgnC7x8I X-Received: by 2002:a62:3501:: with SMTP id c1mr18042292pfa.184.1556222137605; Thu, 25 Apr 2019 12:55:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556222137; cv=none; d=google.com; s=arc-20160816; b=fL9eOajPz1fPs6PtGEPXXqwQHXZZq+mL3DNYHcDkLQvxIFby99kCqK0QcdNXoRIgoM YQhJxlkv9Nt9OaTLWdeslG//9aSixYC6Tt4ofXo2W7aO9lAF9OT/6HsXWNHYYt7vDv8u w9kMEIAlaUJaIIjKscPoJXXgRP90/f0dmhpPd5XRX7FxNTSiD1sqEWjqqQzzDOvcH99X GLKLjecsGfB7JWgRavuyP24cCT7BFiB8WiOvfA16rYm5w6b2hhAYzjxjAIc8w3hOU8cd N7CNzmVj7SFR61r6YsxkD0PeYupIzQZVF1ygNcH8UjVx6e1GwAQ/wl7JKWwFSSBQgq6Q dHQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=jtvY10kYu/UgXuic20owCvhI/8GuPQmjFeAnMENcPb8=; b=FyAX1ZKpRs/kL6+kx0LmvefGPW6uXeNcxhOLzgeah3B1n43aKJgXSEObCv9fIl9uky pN5gh4ArtoI/ixMTkiWs6CIhSIpClTa5waRlzFwmVj9A64TWWSDVvqobNDksHk4eP2NC yswK67I0GkvkwOwGBHtGFSlVsU03yGU3OnzW3L1v7I+f9jgydyicUsFmrRA6O9GYWrSn 4TsQVIi3OQPxUa1jqUbQKkgin8pjX5Rx3JOtkW22BWVrNOwvMj49Ft0/wnbsn5vt0bSg Yu2kAM5EBf4gTlPJzUJQEQiXVZ4ONE0sdkYL7rTGfAOxbis9+S64HDzQPq/6/HOPtuy5 CUNQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rhdWvw2W; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id t64sm47261961pfa.86.2019.04.25.12.53.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 12:53:27 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 12/32] coresight: tmc: Cleanup power management Date: Thu, 25 Apr 2019 13:52:50 -0600 Message-Id: <20190425195310.31562-13-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190425195310.31562-1-mathieu.poirier@linaro.org> References: <20190425195310.31562-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Suzuki K Poulose Drop the power only if we were successful in probing the device. Cc: Mathieu Poirier Signed-off-by: Suzuki K Poulose Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-tmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c index 647b6aa93554..c6a5462ebf27 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.c +++ b/drivers/hwtracing/coresight/coresight-tmc.c @@ -432,8 +432,6 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id) drvdata->size = readl_relaxed(drvdata->base + TMC_RSZ) * 4; } - pm_runtime_put(&adev->dev); - desc.pdata = pdata; desc.dev = dev; desc.groups = coresight_tmc_groups; @@ -476,6 +474,8 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id) ret = misc_register(&drvdata->miscdev); if (ret) coresight_unregister(drvdata->csdev); + else + pm_runtime_put(&adev->dev); out: return ret; } From patchwork Thu Apr 25 19:52:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 162863 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2362309jan; Thu, 25 Apr 2019 12:53:33 -0700 (PDT) X-Google-Smtp-Source: APXvYqwonQf4Z4pKZHpYyd2mr+NLIWcWcUPk6hNeBIWyLoVThAPgV1l2M5EOSsKtew06+Xo74NxU X-Received: by 2002:a65:524a:: with SMTP id q10mr37863148pgp.224.1556222013340; Thu, 25 Apr 2019 12:53:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556222013; cv=none; d=google.com; s=arc-20160816; b=DnvmDi+FUIpPPENL483i1ceJvXex1RAPykuS25//S1w0kaWliSn6cd4m0tFlTXRB1s 5VGRcdlLpg9aijWvqweYXFo+ZNTfFoS0JMIk8tpg9cuCo3b50xxP1bg8DzkNOw6jx51V gYQXYaRsI/DYJCDfRRpJeCrxScXKuiede/sQltFsgKF2p/dnX89vWDUOfCA6rp1GkjA8 /7jFU4msMX3yeBb/BwalCQuaJdMOC2bZNjWUifG1BIFPLtCRwzQjDqxrunJIUsM5ir2j z5C0BfLjaF2TQkjf0cEpdpu9gDxCx3yT2kRT2I/FUgKQZ0LwvcyzBGXtM+Pn8hFtBuGX 1MXw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=gMY7lcZqy+WfNIqTjUNw1h7xvc16TKZ0ZukCEucshSQ=; b=dykot93B1nGHe08OT2Ly2UjxACCpIfIStrA7bG+ZdAv4rAH/TAcnTQkqggMNXtrEp5 Ok8jM+zQvp/tUS+aPDJNrqqQHTOZ0sMai03G/g27HLI+2yD/iRz4TbzEiI9xyUXkqNgI b3S6VIS9u9ESAXD0PuQWeNspjzZFxvrhSCWU4hhNbavh1+wzjQ83K0pX47UTd4dSAdeY aYoD+7sOXed7+WgZ9xo9B3YgcKQfesfbEbOs3dI60ZmPtyAwQfXaRxY7ymMa8NOaYbzx 8DI969WaZcuOFBOwCUbAKOVEzh/ydWCF9pXIOhLLf/8U5ZM5h9hIhOx60tEL9SBR8s1C fg0w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TDMARAVv; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id t64sm47261961pfa.86.2019.04.25.12.53.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 12:53:28 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 13/32] coresight: pmu: Adding ITRACE property to cs_etm PMU Date: Thu, 25 Apr 2019 13:52:51 -0600 Message-Id: <20190425195310.31562-14-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190425195310.31562-1-mathieu.poirier@linaro.org> References: <20190425195310.31562-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add to the capabilities the ITRACE property so that ITRACE START events are generated when the PMU is switched on by the core. Signed-off-by: Mathieu Poirier Acked-by: Suzuki K Poulose Tested-by: Leo Yan Tested-by: Robert Walker --- drivers/hwtracing/coresight/coresight-etm-perf.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index 4d5a2b9f9d6a..25ae56e924bb 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -566,7 +566,8 @@ static int __init etm_perf_init(void) { int ret; - etm_pmu.capabilities = PERF_PMU_CAP_EXCLUSIVE; + etm_pmu.capabilities = (PERF_PMU_CAP_EXCLUSIVE | + PERF_PMU_CAP_ITRACE); etm_pmu.attr_groups = etm_pmu_attr_groups; etm_pmu.task_ctx_nr = perf_sw_context; From patchwork Thu Apr 25 19:52:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 162882 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2363872jan; Thu, 25 Apr 2019 12:55:18 -0700 (PDT) X-Google-Smtp-Source: APXvYqxIuXDvWPNNfSUn6VEI7qOlsdi0G9SssuYxbqexGTT002nAUKvGHsYWYnUPvgRyYpslfgfe X-Received: by 2002:a17:902:4a0c:: with SMTP id w12mr24491239pld.52.1556222117975; Thu, 25 Apr 2019 12:55:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556222117; cv=none; d=google.com; s=arc-20160816; b=a4xHDCbth55SXXKhhrJPaF4Zja4AyQPJ05OiBIHkPWrCbX1md4OCE1+RgJUxp1wKvm pY1/Yhetv0432HzmjSRsj63QpYz355u2+6aloOexordVEvYeX7GsXYMUziZeHfCBm+Xx b5kVUYBicmKL9lrp7i+4Zg/9MRBMwb4RYH2fsKKcaRw0/3DD9TtqD4Hm4TRunHKbmvk0 IFnCQ7BmQgNag8qm3Vch3jXrY4WKos5evub9RowwDLazdDOWlby3ZNaSYHuMvdBtCkzl FJBKRQ0R4wOvV3ccSsNypqJsdcUE/88wJwjpbuaeIfE8GL8GdHXx0YNCR0zvBLPPRIWg PRkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=YusN59c3iVe7dOG1Akfa6gDWfbXRGUq+MaL1LI2ES48=; b=jCixX9WZAexpTFuROQb2vvkqipdSPTu6RUPzQCGa4YFhP7q6269ayv/7S0aN4MEd5l NhgSZv2pAuzUYeaVo6XnRZ5IKzpXKf/DlOVMC8uXiEDnr+Aj/OxpeCeJzfqD6/1QWKf9 Vx9cKkszxR4k8bo1fTtO86YNdEVkNDnQ42q2UwpLI2XGT1RmPU/NImBAIgkEf6F+uqi8 RSLi90jpdAWCYzA7bBddTh3ktsdR1JzB8csIRLJi+O8IhAcGtaHCsFc/DngCsXUCXIE1 KZiaOrRkTRHcd9X5xPDaepE9Ss+NNJJ6CvkdJgflLHx3oXrHxSjZKLibLMJmYTKd7tVG T1Iw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="TPX0i/At"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id t64sm47261961pfa.86.2019.04.25.12.53.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 12:53:29 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 14/32] coresight: etm4x: Add kernel configuration for CONTEXTID Date: Thu, 25 Apr 2019 13:52:52 -0600 Message-Id: <20190425195310.31562-15-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190425195310.31562-1-mathieu.poirier@linaro.org> References: <20190425195310.31562-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Set the proper bit in the configuration register when contextID tracing has been requested by user space. That way PE_CONTEXT elements are generated by the tracers when a process is installed on a CPU. Signed-off-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose Tested-by: Leo Yan Tested-by: Robert Walker --- drivers/hwtracing/coresight/Kconfig | 1 + drivers/hwtracing/coresight/coresight-etm-perf.c | 2 ++ drivers/hwtracing/coresight/coresight-etm4x.c | 5 +++++ include/linux/coresight-pmu.h | 2 ++ tools/include/linux/coresight-pmu.h | 2 ++ 5 files changed, 12 insertions(+) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index a40d796f0a4b..18e8d03321d6 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -75,6 +75,7 @@ config CORESIGHT_SOURCE_ETM4X bool "CoreSight Embedded Trace Macrocell 4.x driver" depends on ARM64 select CORESIGHT_LINKS_AND_SINKS + select PID_IN_CONTEXTIDR help This driver provides support for the ETM4.x tracer module, tracing the instructions that a processor is executing. This is primarily useful diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index 25ae56e924bb..bbfed70b3402 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -29,6 +29,7 @@ static DEFINE_PER_CPU(struct coresight_device *, csdev_src); /* ETMv3.5/PTM's ETMCR is 'config' */ PMU_FORMAT_ATTR(cycacc, "config:" __stringify(ETM_OPT_CYCACC)); +PMU_FORMAT_ATTR(contextid, "config:" __stringify(ETM_OPT_CTXTID)); PMU_FORMAT_ATTR(timestamp, "config:" __stringify(ETM_OPT_TS)); PMU_FORMAT_ATTR(retstack, "config:" __stringify(ETM_OPT_RETSTK)); /* Sink ID - same for all ETMs */ @@ -36,6 +37,7 @@ PMU_FORMAT_ATTR(sinkid, "config2:0-31"); static struct attribute *etm_config_formats_attr[] = { &format_attr_cycacc.attr, + &format_attr_contextid.attr, &format_attr_timestamp.attr, &format_attr_retstack.attr, &format_attr_sinkid.attr, diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 08ce37c9475d..732ae12fca9b 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -239,6 +239,11 @@ static int etm4_parse_event_config(struct etmv4_drvdata *drvdata, if (attr->config & BIT(ETM_OPT_TS)) /* bit[11], Global timestamp tracing bit */ config->cfg |= BIT(11); + + if (attr->config & BIT(ETM_OPT_CTXTID)) + /* bit[6], Context ID tracing bit */ + config->cfg |= BIT(ETM4_CFG_BIT_CTXTID); + /* return stack - enable if selected and supported */ if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack) /* bit[12], Return stack enable bit */ diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h index a1a959ba24ff..b0e35eec6499 100644 --- a/include/linux/coresight-pmu.h +++ b/include/linux/coresight-pmu.h @@ -12,11 +12,13 @@ /* ETMv3.5/PTM's ETMCR config bit */ #define ETM_OPT_CYCACC 12 +#define ETM_OPT_CTXTID 14 #define ETM_OPT_TS 28 #define ETM_OPT_RETSTK 29 /* ETMv4 CONFIGR programming bits for the ETM OPTs */ #define ETM4_CFG_BIT_CYCACC 4 +#define ETM4_CFG_BIT_CTXTID 6 #define ETM4_CFG_BIT_TS 11 #define ETM4_CFG_BIT_RETSTK 12 diff --git a/tools/include/linux/coresight-pmu.h b/tools/include/linux/coresight-pmu.h index a1a959ba24ff..b0e35eec6499 100644 --- a/tools/include/linux/coresight-pmu.h +++ b/tools/include/linux/coresight-pmu.h @@ -12,11 +12,13 @@ /* ETMv3.5/PTM's ETMCR config bit */ #define ETM_OPT_CYCACC 12 +#define ETM_OPT_CTXTID 14 #define ETM_OPT_TS 28 #define ETM_OPT_RETSTK 29 /* ETMv4 CONFIGR programming bits for the ETM OPTs */ #define ETM4_CFG_BIT_CYCACC 4 +#define ETM4_CFG_BIT_CTXTID 6 #define ETM4_CFG_BIT_TS 11 #define ETM4_CFG_BIT_RETSTK 12 From patchwork Thu Apr 25 19:52:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 162864 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2362347jan; Thu, 25 Apr 2019 12:53:35 -0700 (PDT) X-Google-Smtp-Source: APXvYqwKy5hq1XOh0V2/p0xUGvtSm68mUR0bDkUSdo7qMwFeDRotG3+9AtCbUkW7IjU5Wou0wWF/ X-Received: by 2002:a17:902:2ec5:: with SMTP id r63mr41654387plb.139.1556222015813; Thu, 25 Apr 2019 12:53:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556222015; cv=none; d=google.com; s=arc-20160816; b=MlzTivNdWdyMrew3PZbFkFbDxL3vGEauYEI4pNHQi2Rvpr3kCC2Jy/SYfA/A6pgCaB iEzF839HffbHuSL2vfN09AU2djHAGOjg0k2RDcrWRR3rFZSIYkwHm5vSGXuK8Pwz9xvE 36w9SX7rRHf1APc5H23D0iu3dBXILMGC/d9KoVdrMUy+gdC9qA39c8ertTa8x7Y7amC4 qhQQF+byZaiHn8QpBNmyq+jxJcxKJUYaiprio1i8nFx8kbuJFX1esTb2qJLpVNVOeQHI cKYzwd2D/O5niA9n9aGz0IWHMI8aio6uH4HVg09YaNpkh5a8I+hSldxp1H0LpKechxLQ nizQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=N4DXUAnG4MgIchB4rUOv3H8mFdzofOw3TD3XHtggT3U=; b=bWV48yLB4OMr7Y1QduySO9Sr7qHOojYykeO0SOXmgqPbVuTB5GAKszwuiA/IQ+Nbmb gp4buifoxgoFE7GtbsBVGqu+oH+b39Ckh6NpMfHcUTPNnxaHdcSMNHWKh0AeaqPj8UUj b79a24jyg9gHu0JZD02IkTR26fY0SXNCLa37GM/67ESurEWzoaV97jGtkbquhoY+Rv+6 PQjf3IviOO1VWxqvfrEBivumbEXyRUS/pTcfSxikPu7yjkTOJbqSeTYx9CpVKS62SaeG 9q+a5E8TDcmTDmj++2lNJRPXJSlYT+xpUL/nXrg33v+rmfWVHV+/jPrpoTTnpH0jgkLk vmzQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="CDD0L/r/"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id t64sm47261961pfa.86.2019.04.25.12.53.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 12:53:31 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 15/32] coresight: etm4x: Skip selector pair 0 Date: Thu, 25 Apr 2019 13:52:53 -0600 Message-Id: <20190425195310.31562-16-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190425195310.31562-1-mathieu.poirier@linaro.org> References: <20190425195310.31562-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Resource selector pair 0 is always implemented and reserved. As such it should not be explicitly programmed. Signed-off-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose Tested-by: Leo Yan Tested-by: Robert Walker --- drivers/hwtracing/coresight/coresight-etm4x.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 732ae12fca9b..d64192c29860 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -138,8 +138,11 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) drvdata->base + TRCCNTVRn(i)); } - /* Resource selector pair 0 is always implemented and reserved */ - for (i = 0; i < drvdata->nr_resource * 2; i++) + /* + * Resource selector pair 0 is always implemented and reserved. As + * such start at 2. + */ + for (i = 2; i < drvdata->nr_resource * 2; i++) writel_relaxed(config->res_ctrl[i], drvdata->base + TRCRSCTLRn(i)); From patchwork Thu Apr 25 19:52:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 162881 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2363787jan; Thu, 25 Apr 2019 12:55:12 -0700 (PDT) X-Google-Smtp-Source: APXvYqxEihDYq+sN1rN5fI604A3m+YoZsh/3ZvieIeYzsvtYgXmkRSUDgP20F4HJVLV7xSJ+JGrw X-Received: by 2002:a17:902:2965:: with SMTP id g92mr41741662plb.267.1556222112471; Thu, 25 Apr 2019 12:55:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556222112; cv=none; d=google.com; s=arc-20160816; b=J11eWrHr0VplDLu7Z2fbjeyQGVXkuAHcJ4Fbd8VEIHsCk1huALzzQJT0D6IbZXoUtB TKH4164I5Tk8qUlo8KFYzQB4gnY1xvvlymDEVTUiHbilcsyubY+p0EkdtNjJp2jtEpuk U6LVZy0vfkn75klPgDrY0LFl+GAs83KMJOngiPs7jNlHzRCTyg/SCdP6m6fH6O9eNIiJ gvtPAarVbD1S+NVy+mMT6KmCqE/Lm3gOgXI2x9L5+3+ORthA26GOgSLyBiF5R9LyzJje HS70YzDguBM77DJMwkhExC8pQZvjhlRg7pu9ZXIfdGQIfWTRyTLJyDoe9Vgsm7P1JtZn /aMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=H6VFr4RzKtwO7p6PtWjll/+gKQ4FjiT+Jt5SNVjQDXc=; b=gYkOU591a7fl9Gu5IIwG2MkfJQKIhekuZHH7rUI2k5em/ShpTqdVPkFzUlbINH58OW JDazl3jGSCMAeLOqMDoRVhTDNnOjkd1RzwZpQD3pQE3rZeyt3KhyzLqBfZYzPgAn6yCl AY41i4RwEL24L3/uJ1UUiVIg2+YiDXR+p1w2mrTfOAhi4fxDtB26wJqnCxzreHB+tmXx X/iLWDOiGCIFjciIDSp/nU4IEGudWgXlAHpxRJf2MINfCLzgTF5O/z39LIxo9fHMxfD4 6C6QKdEdMhiV2p1SC+Hi2sGyRtwu1Gcsc1LCU42LrPwXp0dDXJPQZjEXUe8LQtQSuuX4 GMpQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pQOTPvY7; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id t64sm47261961pfa.86.2019.04.25.12.53.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 12:53:32 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 16/32] coresight: etm4x: Configure tracers to emit timestamps Date: Thu, 25 Apr 2019 13:52:54 -0600 Message-Id: <20190425195310.31562-17-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190425195310.31562-1-mathieu.poirier@linaro.org> References: <20190425195310.31562-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Configure timestamps to be emitted at regular intervals in the trace stream to temporally correlate instructions executed on different CPUs. Signed-off-by: Mathieu Poirier Tested-by: Leo Yan Tested-by: Robert Walker --- drivers/hwtracing/coresight/coresight-etm4x.c | 102 +++++++++++++++++- 1 file changed, 101 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index d64192c29860..8bb0092c7ec2 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -204,6 +204,91 @@ static void etm4_enable_hw_smp_call(void *info) arg->rc = etm4_enable_hw(arg->drvdata); } +/* + * The goal of function etm4_config_timestamp_event() is to configure a + * counter that will tell the tracer to emit a timestamp packet when it + * reaches zero. This is done in order to get a more fine grained idea + * of when instructions are executed so that they can be correlated + * with execution on other CPUs. + * + * To do this the counter itself is configured to self reload and + * TRCRSCTLR1 (always true) used to get the counter to decrement. From + * there a resource selector is configured with the counter and the + * timestamp control register to use the resource selector to trigger the + * event that will insert a timestamp packet in the stream. + */ +static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata) +{ + int ctridx, ret = -EINVAL; + int counter, rselector; + u32 val = 0; + struct etmv4_config *config = &drvdata->config; + + /* No point in trying if we don't have at least one counter */ + if (!drvdata->nr_cntr) + goto out; + + /* Find a counter that hasn't been initialised */ + for (ctridx = 0; ctridx < drvdata->nr_cntr; ctridx++) + if (config->cntr_val[ctridx] == 0) + break; + + /* All the counters have been configured already, bail out */ + if (ctridx == drvdata->nr_cntr) { + pr_debug("%s: no available counter found\n", __func__); + ret = -ENOSPC; + goto out; + } + + /* + * Searching for an available resource selector to use, starting at + * '2' since every implementation has at least 2 resource selector. + * ETMIDR4 gives the number of resource selector _pairs_, + * hence multiply by 2. + */ + for (rselector = 2; rselector < drvdata->nr_resource * 2; rselector++) + if (!config->res_ctrl[rselector]) + break; + + if (rselector == drvdata->nr_resource * 2) { + pr_debug("%s: no available resource selector found\n", + __func__); + ret = -ENOSPC; + goto out; + } + + /* Remember what counter we used */ + counter = 1 << ctridx; + + /* + * Initialise original and reload counter value to the smallest + * possible value in order to get as much precision as we can. + */ + config->cntr_val[ctridx] = 1; + config->cntrldvr[ctridx] = 1; + + /* Set the trace counter control register */ + val = 0x1 << 16 | /* Bit 16, reload counter automatically */ + 0x0 << 7 | /* Select single resource selector */ + 0x1; /* Resource selector 1, i.e always true */ + + config->cntr_ctrl[ctridx] = val; + + val = 0x2 << 16 | /* Group 0b0010 - Counter and sequencers */ + counter << 0; /* Counter to use */ + + config->res_ctrl[rselector] = val; + + val = 0x0 << 7 | /* Select single resource selector */ + rselector; /* Resource selector */ + + config->ts_ctrl = val; + + ret = 0; +out: + return ret; +} + static int etm4_parse_event_config(struct etmv4_drvdata *drvdata, struct perf_event *event) { @@ -239,9 +324,24 @@ static int etm4_parse_event_config(struct etmv4_drvdata *drvdata, /* TRM: Must program this for cycacc to work */ config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT; } - if (attr->config & BIT(ETM_OPT_TS)) + if (attr->config & BIT(ETM_OPT_TS)) { + /* + * Configure timestamps to be emitted at regular intervals in + * order to correlate instructions executed on different CPUs + * (CPU-wide trace scenarios). + */ + ret = etm4_config_timestamp_event(drvdata); + + /* + * No need to go further if timestamp intervals can't + * be configured. + */ + if (ret) + goto out; + /* bit[11], Global timestamp tracing bit */ config->cfg |= BIT(11); + } if (attr->config & BIT(ETM_OPT_CTXTID)) /* bit[6], Context ID tracing bit */ From patchwork Thu Apr 25 19:52:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 162865 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2362401jan; 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id t64sm47261961pfa.86.2019.04.25.12.53.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 12:53:33 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 17/32] coresight: Adding return code to sink::disable() operation Date: Thu, 25 Apr 2019 13:52:55 -0600 Message-Id: <20190425195310.31562-18-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190425195310.31562-1-mathieu.poirier@linaro.org> References: <20190425195310.31562-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In preparation to handle device reference counting inside of the sink drivers, add a return code to the sink::disable() operation so that proper action can be taken if a sink has not been disabled. Signed-off-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose Tested-by: Leo Yan Tested-by: Robert Walker --- drivers/hwtracing/coresight/coresight-etb10.c | 3 ++- drivers/hwtracing/coresight/coresight-tmc-etf.c | 5 +++-- drivers/hwtracing/coresight/coresight-tmc-etr.c | 5 +++-- drivers/hwtracing/coresight/coresight-tpiu.c | 3 ++- drivers/hwtracing/coresight/coresight.c | 6 +++++- include/linux/coresight.h | 2 +- 6 files changed, 16 insertions(+), 8 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 13c0a601d3be..23b049cef19a 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -317,7 +317,7 @@ static void etb_disable_hw(struct etb_drvdata *drvdata) coresight_disclaim_device(drvdata->base); } -static void etb_disable(struct coresight_device *csdev) +static int etb_disable(struct coresight_device *csdev) { struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); unsigned long flags; @@ -332,6 +332,7 @@ static void etb_disable(struct coresight_device *csdev) spin_unlock_irqrestore(&drvdata->spinlock, flags); dev_dbg(drvdata->dev, "ETB disabled\n"); + return 0; } static void *etb_alloc_buffer(struct coresight_device *csdev, int cpu, diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index a5f053f2db2c..d4213e7c2c45 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -273,7 +273,7 @@ static int tmc_enable_etf_sink(struct coresight_device *csdev, return 0; } -static void tmc_disable_etf_sink(struct coresight_device *csdev) +static int tmc_disable_etf_sink(struct coresight_device *csdev) { unsigned long flags; struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); @@ -281,7 +281,7 @@ static void tmc_disable_etf_sink(struct coresight_device *csdev) spin_lock_irqsave(&drvdata->spinlock, flags); if (drvdata->reading) { spin_unlock_irqrestore(&drvdata->spinlock, flags); - return; + return -EBUSY; } /* Disable the TMC only if it needs to */ @@ -293,6 +293,7 @@ static void tmc_disable_etf_sink(struct coresight_device *csdev) spin_unlock_irqrestore(&drvdata->spinlock, flags); dev_dbg(drvdata->dev, "TMC-ETB/ETF disabled\n"); + return 0; } static int tmc_enable_etf_link(struct coresight_device *csdev, diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index cf7a32ce209d..c6a0f5897684 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1393,7 +1393,7 @@ static int tmc_enable_etr_sink(struct coresight_device *csdev, return -EINVAL; } -static void tmc_disable_etr_sink(struct coresight_device *csdev) +static int tmc_disable_etr_sink(struct coresight_device *csdev) { unsigned long flags; struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); @@ -1401,7 +1401,7 @@ static void tmc_disable_etr_sink(struct coresight_device *csdev) spin_lock_irqsave(&drvdata->spinlock, flags); if (drvdata->reading) { spin_unlock_irqrestore(&drvdata->spinlock, flags); - return; + return -EBUSY; } /* Disable the TMC only if it needs to */ @@ -1413,6 +1413,7 @@ static void tmc_disable_etr_sink(struct coresight_device *csdev) spin_unlock_irqrestore(&drvdata->spinlock, flags); dev_dbg(drvdata->dev, "TMC-ETR disabled\n"); + return 0; } static const struct coresight_ops_sink tmc_etr_sink_ops = { diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/hwtracing/coresight/coresight-tpiu.c index 93e2ef34e734..c1b77e3c3187 100644 --- a/drivers/hwtracing/coresight/coresight-tpiu.c +++ b/drivers/hwtracing/coresight/coresight-tpiu.c @@ -94,13 +94,14 @@ static void tpiu_disable_hw(struct tpiu_drvdata *drvdata) CS_LOCK(drvdata->base); } -static void tpiu_disable(struct coresight_device *csdev) +static int tpiu_disable(struct coresight_device *csdev) { struct tpiu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); tpiu_disable_hw(drvdata); dev_dbg(drvdata->dev, "TPIU disabled\n"); + return 0; } static const struct coresight_ops_sink tpiu_sink_ops = { diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c index 55204dd47479..66c25b0a785e 100644 --- a/drivers/hwtracing/coresight/coresight.c +++ b/drivers/hwtracing/coresight/coresight.c @@ -239,9 +239,13 @@ static int coresight_enable_sink(struct coresight_device *csdev, static void coresight_disable_sink(struct coresight_device *csdev) { + int ret; + if (atomic_dec_return(csdev->refcnt) == 0) { if (sink_ops(csdev)->disable) { - sink_ops(csdev)->disable(csdev); + ret = sink_ops(csdev)->disable(csdev); + if (ret) + return; csdev->enable = false; } } diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 7b87965f7a65..189cc6ddc92b 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -192,7 +192,7 @@ struct coresight_device { */ struct coresight_ops_sink { int (*enable)(struct coresight_device *csdev, u32 mode, void *data); - void (*disable)(struct coresight_device *csdev); + int (*disable)(struct coresight_device *csdev); void *(*alloc_buffer)(struct coresight_device *csdev, int cpu, void **pages, int nr_pages, bool overwrite); void (*free_buffer)(void *config); From patchwork Thu Apr 25 19:52:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 162880 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2363646jan; Thu, 25 Apr 2019 12:55:02 -0700 (PDT) X-Google-Smtp-Source: APXvYqwglDwPJlXCy8kW282f5a7PZaPs0PCFn5+C90Z4ZkHyU89lNvOXtJHhtEv+VKW5hiVu2XqB X-Received: by 2002:a17:902:4081:: with SMTP id c1mr41324352pld.169.1556222102454; Thu, 25 Apr 2019 12:55:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556222102; cv=none; d=google.com; s=arc-20160816; b=JCTSbDF+7qhc6cp9w26NwOgrJdsUCw+rmcBkvo0pDOP1V1y4/iBEPPB142kWNyLBKW VYji1dKnVE+PPmplj0u50GDEEFg6q29v3dQ6oShElJwsKElk9E7zUksY3okw1lpWNF+j s+Db/gggLOrDhX2aJQQwUHilmvqo9K3NexJqddgKSMCx7NXJq4D52KBCZoBx4cFjIkdy 1oZv4wGMH+mn8xUtwO9hlbuDt67RxRB1PpTZwsde1/Ufqd6OKHLkidrH/jCb1YSBT+1g ehL6YQ/z7WGTiLxhrB4xGWbsf2fBh1YFAJ6Q9zMiNUcy8BIYrXf9ZMzaXJyMl/TqcPyM vfOA== ARC-Message-Signature: i=1; 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id t64sm47261961pfa.86.2019.04.25.12.53.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 12:53:34 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 18/32] coresight: Move reference counting inside sink drivers Date: Thu, 25 Apr 2019 13:52:56 -0600 Message-Id: <20190425195310.31562-19-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190425195310.31562-1-mathieu.poirier@linaro.org> References: <20190425195310.31562-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When operating in CPU-wide mode with an N:1 source/sink HW topology, multiple CPUs can access a sink concurrently. As such reference counting needs to happen when the device's spinlock is held to avoid racing with other operations (start(), update(), stop()), such as: session A Session B ----- ------- enable_sink atomic_inc(refcount) = 1 ... atomic_dec(refcount) = 0 enable_sink if (refcount == 0) disable_sink atomic_inc() Signed-off-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose Tested-by: Leo Yan Tested-by: Robert Walker --- drivers/hwtracing/coresight/coresight-etb10.c | 21 ++++++++++---- .../hwtracing/coresight/coresight-tmc-etf.c | 21 +++++++++++--- .../hwtracing/coresight/coresight-tmc-etr.c | 19 +++++++++++-- drivers/hwtracing/coresight/coresight-tpiu.c | 6 +++- drivers/hwtracing/coresight/coresight.c | 28 +++++++++---------- 5 files changed, 66 insertions(+), 29 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 23b049cef19a..8e63863cf950 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -5,6 +5,7 @@ * Description: CoreSight Embedded Trace Buffer driver */ +#include #include #include #include @@ -151,14 +152,15 @@ static int etb_enable_sysfs(struct coresight_device *csdev) goto out; } - /* Nothing to do, the tracer is already enabled. */ - if (drvdata->mode == CS_MODE_SYSFS) - goto out; + if (drvdata->mode == CS_MODE_DISABLED) { + ret = etb_enable_hw(drvdata); + if (ret) + goto out; - ret = etb_enable_hw(drvdata); - if (!ret) drvdata->mode = CS_MODE_SYSFS; + } + atomic_inc(csdev->refcnt); out: spin_unlock_irqrestore(&drvdata->spinlock, flags); return ret; @@ -188,8 +190,10 @@ static int etb_enable_perf(struct coresight_device *csdev, void *data) goto out; ret = etb_enable_hw(drvdata); - if (!ret) + if (!ret) { drvdata->mode = CS_MODE_PERF; + atomic_inc(csdev->refcnt); + } out: spin_unlock_irqrestore(&drvdata->spinlock, flags); @@ -324,6 +328,11 @@ static int etb_disable(struct coresight_device *csdev) spin_lock_irqsave(&drvdata->spinlock, flags); + if (atomic_dec_return(csdev->refcnt)) { + spin_unlock_irqrestore(&drvdata->spinlock, flags); + return -EBUSY; + } + /* Disable the ETB only if it needs to */ if (drvdata->mode != CS_MODE_DISABLED) { etb_disable_hw(drvdata); diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index d4213e7c2c45..d50a608a60f1 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -4,6 +4,7 @@ * Author: Mathieu Poirier */ +#include #include #include #include @@ -180,8 +181,10 @@ static int tmc_enable_etf_sink_sysfs(struct coresight_device *csdev) * sink is already enabled no memory is needed and the HW need not be * touched. */ - if (drvdata->mode == CS_MODE_SYSFS) + if (drvdata->mode == CS_MODE_SYSFS) { + atomic_inc(csdev->refcnt); goto out; + } /* * If drvdata::buf isn't NULL, memory was allocated for a previous @@ -200,11 +203,13 @@ static int tmc_enable_etf_sink_sysfs(struct coresight_device *csdev) } ret = tmc_etb_enable_hw(drvdata); - if (!ret) + if (!ret) { drvdata->mode = CS_MODE_SYSFS; - else + atomic_inc(csdev->refcnt); + } else { /* Free up the buffer if we failed to enable */ used = false; + } out: spin_unlock_irqrestore(&drvdata->spinlock, flags); @@ -239,8 +244,10 @@ static int tmc_enable_etf_sink_perf(struct coresight_device *csdev, void *data) if (ret) break; ret = tmc_etb_enable_hw(drvdata); - if (!ret) + if (!ret) { drvdata->mode = CS_MODE_PERF; + atomic_inc(csdev->refcnt); + } } while (0); spin_unlock_irqrestore(&drvdata->spinlock, flags); @@ -279,11 +286,17 @@ static int tmc_disable_etf_sink(struct coresight_device *csdev) struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); spin_lock_irqsave(&drvdata->spinlock, flags); + if (drvdata->reading) { spin_unlock_irqrestore(&drvdata->spinlock, flags); return -EBUSY; } + if (atomic_dec_return(csdev->refcnt)) { + spin_unlock_irqrestore(&drvdata->spinlock, flags); + return -EBUSY; + } + /* Disable the TMC only if it needs to */ if (drvdata->mode != CS_MODE_DISABLED) { tmc_etb_disable_hw(drvdata); diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index c6a0f5897684..6a8f39d03de3 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -4,6 +4,7 @@ * Author: Mathieu Poirier */ +#include #include #include #include @@ -1125,8 +1126,10 @@ static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev) * sink is already enabled no memory is needed and the HW need not be * touched, even if the buffer size has changed. */ - if (drvdata->mode == CS_MODE_SYSFS) + if (drvdata->mode == CS_MODE_SYSFS) { + atomic_inc(csdev->refcnt); goto out; + } /* * If we don't have a buffer or it doesn't match the requested size, @@ -1139,8 +1142,10 @@ static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev) } ret = tmc_etr_enable_hw(drvdata, drvdata->sysfs_buf); - if (!ret) + if (!ret) { drvdata->mode = CS_MODE_SYSFS; + atomic_inc(csdev->refcnt); + } out: spin_unlock_irqrestore(&drvdata->spinlock, flags); @@ -1371,8 +1376,10 @@ static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, void *data) etr_perf->head = PERF_IDX2OFF(handle->head, etr_perf); drvdata->perf_data = etr_perf; rc = tmc_etr_enable_hw(drvdata, etr_perf->etr_buf); - if (!rc) + if (!rc) { drvdata->mode = CS_MODE_PERF; + atomic_inc(csdev->refcnt); + } unlock_out: spin_unlock_irqrestore(&drvdata->spinlock, flags); @@ -1399,11 +1406,17 @@ static int tmc_disable_etr_sink(struct coresight_device *csdev) struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); spin_lock_irqsave(&drvdata->spinlock, flags); + if (drvdata->reading) { spin_unlock_irqrestore(&drvdata->spinlock, flags); return -EBUSY; } + if (atomic_dec_return(csdev->refcnt)) { + spin_unlock_irqrestore(&drvdata->spinlock, flags); + return -EBUSY; + } + /* Disable the TMC only if it needs to */ if (drvdata->mode != CS_MODE_DISABLED) { tmc_etr_disable_hw(drvdata); diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/hwtracing/coresight/coresight-tpiu.c index c1b77e3c3187..63d9af31f57f 100644 --- a/drivers/hwtracing/coresight/coresight-tpiu.c +++ b/drivers/hwtracing/coresight/coresight-tpiu.c @@ -5,6 +5,7 @@ * Description: CoreSight Trace Port Interface Unit driver */ +#include #include #include #include @@ -73,7 +74,7 @@ static int tpiu_enable(struct coresight_device *csdev, u32 mode, void *__unused) struct tpiu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); tpiu_enable_hw(drvdata); - + atomic_inc(csdev->refcnt); dev_dbg(drvdata->dev, "TPIU enabled\n"); return 0; } @@ -98,6 +99,9 @@ static int tpiu_disable(struct coresight_device *csdev) { struct tpiu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + if (atomic_dec_return(csdev->refcnt)) + return -EBUSY; + tpiu_disable_hw(drvdata); dev_dbg(drvdata->dev, "TPIU disabled\n"); diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c index 66c25b0a785e..4b130281236a 100644 --- a/drivers/hwtracing/coresight/coresight.c +++ b/drivers/hwtracing/coresight/coresight.c @@ -225,14 +225,13 @@ static int coresight_enable_sink(struct coresight_device *csdev, * We need to make sure the "new" session is compatible with the * existing "mode" of operation. */ - if (sink_ops(csdev)->enable) { - ret = sink_ops(csdev)->enable(csdev, mode, data); - if (ret) - return ret; - csdev->enable = true; - } + if (!sink_ops(csdev)->enable) + return -EINVAL; - atomic_inc(csdev->refcnt); + ret = sink_ops(csdev)->enable(csdev, mode, data); + if (ret) + return ret; + csdev->enable = true; return 0; } @@ -241,14 +240,13 @@ static void coresight_disable_sink(struct coresight_device *csdev) { int ret; - if (atomic_dec_return(csdev->refcnt) == 0) { - if (sink_ops(csdev)->disable) { - ret = sink_ops(csdev)->disable(csdev); - if (ret) - return; - csdev->enable = false; - } - } + if (!sink_ops(csdev)->disable) + return; + + ret = sink_ops(csdev)->disable(csdev); + if (ret) + return; + csdev->enable = false; } static int coresight_enable_link(struct coresight_device *csdev, From patchwork Thu Apr 25 19:52:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 162877 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2363235jan; Thu, 25 Apr 2019 12:54:36 -0700 (PDT) X-Google-Smtp-Source: APXvYqy7qEX3H61gDZEKlUswOEqPTkn3thtu2fOBigBJmRv5buGYw+vyMhA9WwWt+WBVf9WlAGSE X-Received: by 2002:a17:902:be09:: with SMTP id r9mr41682670pls.215.1556222076235; Thu, 25 Apr 2019 12:54:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556222076; cv=none; d=google.com; s=arc-20160816; b=ERWKJYAzj1GGY3MbTYKKBbcDyavWQq3PtRDyXygd0sadrmtJpApNZcRrb9xoINRrrl aovZqL/qpk/t3GQhDYbWYvTfYA54fQdacXmiDgnTqfGwRpCrHBXd9KYJ8LtBoD5UhH+S YlnnEgV4NpZTAKcTkvIwlRyM2mfZk6QN3wog9BLIEkbqKOy8jpvupDhBQlNrUx9/mUfR T2g6EpobVoEs0ur7U/m3VlRj5mQxgpHGolFsCxeIIZglhjzMo41hyT4HKxTC3nFrz//l EpEq+4xOgiWQwASXFmrO9Phg4L2hkcORIRHz/QBqMo4GjJgO9DJKy/bnYlQ8hd7sNQuL OnFg== ARC-Message-Signature: i=1; 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id t64sm47261961pfa.86.2019.04.25.12.53.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 12:53:36 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 19/32] coresight: Properly address errors in sink::disable() functions Date: Thu, 25 Apr 2019 13:52:57 -0600 Message-Id: <20190425195310.31562-20-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190425195310.31562-1-mathieu.poirier@linaro.org> References: <20190425195310.31562-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When disabling a sink the reference counter ensures the operation goes through if nobody else is using it. As such if drvdata::mode is already set do CS_MODE_DISABLED, it is an error and should be reported as such. Signed-off-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose Tested-by: Leo Yan Tested-by: Robert Walker --- drivers/hwtracing/coresight/coresight-etb10.c | 9 ++++----- drivers/hwtracing/coresight/coresight-tmc-etf.c | 9 ++++----- drivers/hwtracing/coresight/coresight-tmc-etr.c | 9 ++++----- 3 files changed, 12 insertions(+), 15 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 8e63863cf950..6b73bc2e0dbd 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -333,11 +333,10 @@ static int etb_disable(struct coresight_device *csdev) return -EBUSY; } - /* Disable the ETB only if it needs to */ - if (drvdata->mode != CS_MODE_DISABLED) { - etb_disable_hw(drvdata); - drvdata->mode = CS_MODE_DISABLED; - } + /* Complain if we (somehow) got out of sync */ + WARN_ON_ONCE(drvdata->mode == CS_MODE_DISABLED); + etb_disable_hw(drvdata); + drvdata->mode = CS_MODE_DISABLED; spin_unlock_irqrestore(&drvdata->spinlock, flags); dev_dbg(drvdata->dev, "ETB disabled\n"); diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index d50a608a60f1..30f868676540 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -297,11 +297,10 @@ static int tmc_disable_etf_sink(struct coresight_device *csdev) return -EBUSY; } - /* Disable the TMC only if it needs to */ - if (drvdata->mode != CS_MODE_DISABLED) { - tmc_etb_disable_hw(drvdata); - drvdata->mode = CS_MODE_DISABLED; - } + /* Complain if we (somehow) got out of sync */ + WARN_ON_ONCE(drvdata->mode == CS_MODE_DISABLED); + tmc_etb_disable_hw(drvdata); + drvdata->mode = CS_MODE_DISABLED; spin_unlock_irqrestore(&drvdata->spinlock, flags); diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 6a8f39d03de3..9a0b346be58b 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1417,11 +1417,10 @@ static int tmc_disable_etr_sink(struct coresight_device *csdev) return -EBUSY; } - /* Disable the TMC only if it needs to */ - if (drvdata->mode != CS_MODE_DISABLED) { - tmc_etr_disable_hw(drvdata); - drvdata->mode = CS_MODE_DISABLED; - } + /* Complain if we (somehow) got out of sync */ + WARN_ON_ONCE(drvdata->mode == CS_MODE_DISABLED); + tmc_etr_disable_hw(drvdata); + drvdata->mode = CS_MODE_DISABLED; spin_unlock_irqrestore(&drvdata->spinlock, flags); From patchwork Thu Apr 25 19:52:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 162866 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2362481jan; Thu, 25 Apr 2019 12:53:45 -0700 (PDT) X-Google-Smtp-Source: APXvYqyUPVhKcJg8C7y2h/+WooNA4U9kxrSCdt0fffKW1YDjTMI38zBUpSbxBCNDg6/igVXVq39S X-Received: by 2002:a63:ef53:: with SMTP id c19mr15923029pgk.120.1556222025767; Thu, 25 Apr 2019 12:53:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556222025; cv=none; d=google.com; s=arc-20160816; b=QeTanxsdWogxWVVbxHUbUAb43P3QyoF7Nz8Dq5cOjkkccH35ajVbZoihR3p7TO/BGz tWv0hOa68WL+9DMFO80+eBT+SC3b8vArXeOuDj2n5vAYVNiCDRHA9Bg0Otw9gcIuP60U ntL8EAUOKoJ5QxdoykEEjjkDA7+6CVUHcU9X/vwhJanG8pHrlV4Kp8hlPEUFAXdshCiV 634LBwhGOmryPCbu/mUeQLjkXWoD08Dpz9XSe+nhijh7+TMA1UmAE1Z6YR2XZo3bo9BC sy0fOrswdpx0H4grg11qJPsbWFmq1fYILwvwzhTfpxgX5stUW9q650FV8DGSMtsCffsB w7Og== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=aWyPwAmKiV26NYLJXz5kLa0RrGlpEkg6p1STyf3/JXM=; b=Bwc7g6jS92QMSSRylpvvil6SUGcnVZuZwow81SxMhusnGKcMT9D4R6Ew1dJewdlXSI VhDOKMBh4njAFLVRGE5Mg6yX1M/vtJGcDDoGx/VurL4t/5kjbjdbpDAyymuBmITUzMQ6 KaEdWvQUAHDzXLPHE55AKgpxHNfGFe8umCw3/E93ALTKRt06RSaCzm7a5SFUvajQ8aHy f3cNdn200IhXkZqF+9m67uF611XuXdE0jyQtw4Ulq25V0krqXa5lO/xNVQHJsqTNC0Zi Xy+Q39gxMe5I7xr03ht+I8oERlczoO1k8MXB8EG4LZ73ZyVywqP4GvOTkA0IahhnRHPH XFCg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UIgR3XfD; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id t64sm47261961pfa.86.2019.04.25.12.53.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 12:53:37 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 20/32] coresight: Properly address concurrency in sink::update() functions Date: Thu, 25 Apr 2019 13:52:58 -0600 Message-Id: <20190425195310.31562-21-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190425195310.31562-1-mathieu.poirier@linaro.org> References: <20190425195310.31562-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When operating in CPU-wide trace scenarios and working with an N:1 source/sink HW topology, update() functions need to be made atomic in order to avoid racing with start and stop operations. Signed-off-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose Tested-by: Leo Yan Tested-by: Robert Walker --- drivers/hwtracing/coresight/coresight-etb10.c | 4 +++- drivers/hwtracing/coresight/coresight-tmc-etf.c | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 6b73bc2e0dbd..00d664c6a401 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -405,7 +405,7 @@ static unsigned long etb_update_buffer(struct coresight_device *csdev, const u32 *barrier; u32 read_ptr, write_ptr, capacity; u32 status, read_data; - unsigned long offset, to_read; + unsigned long offset, to_read, flags; struct cs_buffers *buf = sink_config; struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); @@ -414,6 +414,7 @@ static unsigned long etb_update_buffer(struct coresight_device *csdev, capacity = drvdata->buffer_depth * ETB_FRAME_SIZE_WORDS; + spin_lock_irqsave(&drvdata->spinlock, flags); __etb_disable_hw(drvdata); CS_UNLOCK(drvdata->base); @@ -524,6 +525,7 @@ static unsigned long etb_update_buffer(struct coresight_device *csdev, } __etb_enable_hw(drvdata); CS_LOCK(drvdata->base); + spin_unlock_irqrestore(&drvdata->spinlock, flags); return to_read; } diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index 30f868676540..a38ad2b0d95a 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -413,7 +413,7 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev, u32 *buf_ptr; u64 read_ptr, write_ptr; u32 status; - unsigned long offset, to_read; + unsigned long offset, to_read, flags; struct cs_buffers *buf = sink_config; struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); @@ -424,6 +424,7 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev, if (WARN_ON_ONCE(drvdata->mode != CS_MODE_PERF)) return 0; + spin_lock_irqsave(&drvdata->spinlock, flags); CS_UNLOCK(drvdata->base); tmc_flush_and_stop(drvdata); @@ -517,6 +518,7 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev, to_read = buf->nr_pages << PAGE_SHIFT; } CS_LOCK(drvdata->base); + spin_unlock_irqrestore(&drvdata->spinlock, flags); return to_read; } From patchwork Thu Apr 25 19:52:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 162879 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2363543jan; Thu, 25 Apr 2019 12:54:55 -0700 (PDT) X-Google-Smtp-Source: APXvYqyfb5u0TYOcUuLm3+MjqQOq0lSgrEQh2MQ2ROJWHSs8Q/HRkcsFEUvbwF9kXof2yt8MIp9h X-Received: by 2002:aa7:8458:: with SMTP id r24mr23408773pfn.231.1556222095645; Thu, 25 Apr 2019 12:54:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556222095; cv=none; d=google.com; s=arc-20160816; b=dpLR4Rv0kvd8BW0iyapk/xSxHCj67ssMyFOkTk5IplZcKjY/4o6HVjbp9B2Eh4fk6R 8PwQZ7zRr6N4Q0SRAHDx+QYZ5e7Um5l16QPlqjIBX7t+AilFTjqxxvMqokHqtQ/UtdbG NUwvBTa3qO+yl2tA4IWb314M8NK50OGiEHakboofJlybfvMCVjUfV4oU/GHuaSVrTvSU b7TWnpiAV6HWmPo8UzxSt04llieEPyVxRegYhMef3LT38k5pDv7UIZGUoAtKdIfi62DB UFfDAVHHED114fMhdBI4tnjRPUdl4P81ygWZdMRUjtu/ebAc8ar6Nnu+9vUOaA1No4gw 8vZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=uoxZQ+Jw0MNrOb10y+jglav9yUL3Ht92euc8TGFiAfY=; b=V0cHZteckdDpW9kBHgiT9VE7SSMsbq7HgMfAXZbC8MIMslwcEJ6gNtyBOdAXMlIi8o IBkXhk7fxabO/z4zVgQ0covIfXjdRO4q9BMccJ4f8mxCUCSxCjXE7rW99ZqiZ5gJsmT7 Sp+CmBhSnGHsOqCyNKk0RJyao83BjJVDPbzQG98o0ILtOYu7/Z6WkH+0flWsbthFwDrH UtcgiWyW+4StQSYQWBEYMOyNQFwuxHM31xJx5q7yDB+uMylQ+mKQ1nKBwu5CHL+Vs4la ebUjhTO76fyKEopS8WEgDzFQ+omHGzQJUaWObD6dOUIwe5eyLsw+4M3zDyawtzPehWBJ aZJg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=c+R6u6VD; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id t64sm47261961pfa.86.2019.04.25.12.53.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 12:53:39 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 21/32] coresight: perf: Clean up function etm_setup_aux() Date: Thu, 25 Apr 2019 13:52:59 -0600 Message-Id: <20190425195310.31562-22-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190425195310.31562-1-mathieu.poirier@linaro.org> References: <20190425195310.31562-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org There is no point in allocating sink memory for a trace session if there is not a way to free it once it is no longer needed. As such make sure the sink API function to allocate and free memory have been implemented before moving ahead with the establishment of a trace session. Signed-off-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose Tested-by: Leo Yan Tested-by: Robert Walker --- drivers/hwtracing/coresight/coresight-etm-perf.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index bbfed70b3402..b8ca3800b56b 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -134,8 +134,7 @@ static void free_event_data(struct work_struct *work) if (event_data->snk_config && !WARN_ON(cpumask_empty(mask))) { cpu = cpumask_first(mask); sink = coresight_get_sink(etm_event_cpu_path(event_data, cpu)); - if (sink_ops(sink)->free_buffer) - sink_ops(sink)->free_buffer(event_data->snk_config); + sink_ops(sink)->free_buffer(event_data->snk_config); } for_each_cpu(cpu, mask) { @@ -215,7 +214,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, sink = coresight_get_enabled_sink(true); } - if (!sink || !sink_ops(sink)->alloc_buffer) + if (!sink) goto err; mask = &event_data->mask; @@ -261,6 +260,9 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, if (cpu >= nr_cpu_ids) goto err; + if (!sink_ops(sink)->alloc_buffer || !sink_ops(sink)->free_buffer) + goto err; + /* Allocate the sink buffer for this session */ event_data->snk_config = sink_ops(sink)->alloc_buffer(sink, cpu, pages, From patchwork Thu Apr 25 19:53:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 162878 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2363283jan; Thu, 25 Apr 2019 12:54:38 -0700 (PDT) X-Google-Smtp-Source: APXvYqyLPLk6CQOzYPbcvCZ2saM1CuJiQUr1/y8gMIVDDoYlW/yRqs6cff1TleQwxFIM2oLnZqod X-Received: by 2002:a62:47d0:: with SMTP id p77mr41492536pfi.95.1556222078780; Thu, 25 Apr 2019 12:54:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556222078; cv=none; d=google.com; s=arc-20160816; b=1I75dABKHzhWWsybB3qEKkVM8NRVRUy+JkVCYQPPYV3cW8L97gFt24fz1IFsQ4Cg5K XZGpzuO6vs2y+C3GfM+wF3uQaT0RCiTbCZHXHz/iNSwVDSjtjsTxDIBKZAqoqfjvXkFA ztRDb7Fds/OjGVBHTwHWzjexsNabPE4yutPxVXnR761VmRRyiAaJ1c/ZpAz/4zZHBcdl yjhSAEb7Q3l6ZWpAdDEqtI3AMluiH1dEicmYTD9ChPGBdyLPF6KSyH/hjoIKfJG/xC03 CbtLvGRzrHRDWMvDYwUjEJG9hqHzd+tSGK9WwI8eJF3IQl1Fp3KjCWzWOQUvA3emnytr fezQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=BWqaSOkHsxJfaZN3QLvNFkWqa4XvxW+N+NDPocOCvzI=; b=jH1SidpWBfXBFVQFGKv7Rw2tt6/z1MDTpMBWYE6uX0tBZT4LFNMVWHzpQxC6Wr7bSr 0KqcKZxXgMYTPgcDAyDys7aGoK7/Hv6cJYdNTVH/tTLBupH5v0xk6HoIS5NaMb9CKnzq kHM3Ydf92K2Vfs5IiikDL/Dw66iQOpV6U12A24B5K2sWf90j2ScQmleSn33ESRSC6/c9 Pib9qbwNyMnmx0TX79NihekOC7lGx+ztH/5kAi2cq+VBXHhozaZmFeWOExbmywHCuWIo OMrz4/qcOx4zxDAb7QeHQhAWuIQhMbJCCqspZMAPzLozcZd2HrijC93pdOF/SStNjIkp L/sA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=z60rd2YZ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id t64sm47261961pfa.86.2019.04.25.12.53.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 12:53:40 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 22/32] coresight: perf: Refactor function free_event_data() Date: Thu, 25 Apr 2019 13:53:00 -0600 Message-Id: <20190425195310.31562-23-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190425195310.31562-1-mathieu.poirier@linaro.org> References: <20190425195310.31562-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Function free_event_data() is already busy and is bound to become worse with the addition of CPU-wide trace scenarios. As such spin off a new function to strickly take care of the sink buffers. Signed-off-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose Tested-by: Leo Yan Tested-by: Robert Walker --- .../hwtracing/coresight/coresight-etm-perf.c | 24 ++++++++++++++----- 1 file changed, 18 insertions(+), 6 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index b8ca3800b56b..806b3dd5872d 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -120,22 +120,34 @@ static int etm_event_init(struct perf_event *event) return ret; } +static void free_sink_buffer(struct etm_event_data *event_data) +{ + int cpu; + cpumask_t *mask = &event_data->mask; + struct coresight_device *sink; + + if (WARN_ON(cpumask_empty(mask))) + return; + + if (!event_data->snk_config) + return; + + cpu = cpumask_first(mask); + sink = coresight_get_sink(etm_event_cpu_path(event_data, cpu)); + sink_ops(sink)->free_buffer(event_data->snk_config); +} + static void free_event_data(struct work_struct *work) { int cpu; cpumask_t *mask; struct etm_event_data *event_data; - struct coresight_device *sink; event_data = container_of(work, struct etm_event_data, work); mask = &event_data->mask; /* Free the sink buffers, if there are any */ - if (event_data->snk_config && !WARN_ON(cpumask_empty(mask))) { - cpu = cpumask_first(mask); - sink = coresight_get_sink(etm_event_cpu_path(event_data, cpu)); - sink_ops(sink)->free_buffer(event_data->snk_config); - } + free_sink_buffer(event_data); for_each_cpu(cpu, mask) { struct list_head **ppath; From patchwork Thu Apr 25 19:53:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 162876 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2363157jan; Thu, 25 Apr 2019 12:54:31 -0700 (PDT) X-Google-Smtp-Source: APXvYqyJjrNV1YqSdcu1hQAZA9OI+FWNQb9NXJyQyGhcZ6415dqWOIw4IBRySTCXlQ5/ytNNQ4z1 X-Received: by 2002:a63:3fc1:: with SMTP id m184mr5549711pga.222.1556222071025; Thu, 25 Apr 2019 12:54:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556222071; cv=none; d=google.com; s=arc-20160816; b=SPojQJhEHWhpLWVbXclv06xL3gjU+Sm3BlPSzdejcL6gwsMrionch5mvGgZTdj0Ikv LoLdqgvJDa97pY0vb5eQwTzfRPDstcb7dG7/QEjTTFJqPbaMknXVnshjl9bZ5kvT1DLR TrLid5wQDGwcTMm41N2bus1fsBXQAaN1IbdgryXrMsXvC5UH9dSlraKC60wOCMOwEYry PKcqtzpktlLitgeSf+xA/0Gre9Ko9pYcjAbANXJnMZZ5MTenN1PveRWUyGpSXkanJP/s tBdxaQPgE/fTzMrPv2fFdNxD+BJgzCXZSS5L3IVbZ3wQwwxWXhlMdkC2+3e/aZzCgS07 zuJg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=lgLjzzRV23KmGDqFjyFr57/D8n2Xmn3ZciLBU3MPiP0=; b=V18/ldajS2z8RtQ5MrB0QsjzJ3NNkPmUssECnEKZGym1gJBlOOF9f7CKZTYjpejDJ9 WAASD+wD0GLuZBa3/inCSxrINkSZMvf6yFhDSqJdC01zfUNm7utvmkspKPY2KK3JyhwB qY38SYDtyKjuFyegpVr0WeI+tmQQz3TMI39r6j6rxCKpnWrkNJODkU1hNEgRgAwfaYCz NtBs8APpGN13niYtn6djKuY2+ncqyPAZm27Atc81cmIlL+cIdVBAQ+O29fmSE8Zd/vvi 8Uhdul2ZihQWRMe2LxS+Owca0t7s+iCiQ6vBYiGlOtLpmh7yfDqWjYy0wULf6sk92Uvk echA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CxeIMdWW; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id t64sm47261961pfa.86.2019.04.25.12.53.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 12:53:41 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 23/32] coresight: Communicate perf event to sink buffer allocation functions Date: Thu, 25 Apr 2019 13:53:01 -0600 Message-Id: <20190425195310.31562-24-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190425195310.31562-1-mathieu.poirier@linaro.org> References: <20190425195310.31562-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Make struct perf_event available to sink buffer allocation functions in order to use the pid they carry to allocate and free buffer memory along with regimenting access to what source a sink can collect data for. Signed-off-by: Mathieu Poirier Tested-by: Leo Yan Tested-by: Robert Walker --- drivers/hwtracing/coresight/coresight-etb10.c | 7 ++++--- .../hwtracing/coresight/coresight-etm-perf.c | 2 +- .../hwtracing/coresight/coresight-tmc-etf.c | 7 ++++--- .../hwtracing/coresight/coresight-tmc-etr.c | 18 ++++++++++-------- include/linux/coresight.h | 5 +++-- 5 files changed, 22 insertions(+), 17 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 00d664c6a401..eeae375c7aed 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -343,10 +343,11 @@ static int etb_disable(struct coresight_device *csdev) return 0; } -static void *etb_alloc_buffer(struct coresight_device *csdev, int cpu, - void **pages, int nr_pages, bool overwrite) +static void *etb_alloc_buffer(struct coresight_device *csdev, + struct perf_event *event, void **pages, + int nr_pages, bool overwrite) { - int node; + int node, cpu = event->cpu; struct cs_buffers *buf; if (cpu == -1) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index 806b3dd5872d..3c6294432748 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -277,7 +277,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, /* Allocate the sink buffer for this session */ event_data->snk_config = - sink_ops(sink)->alloc_buffer(sink, cpu, pages, + sink_ops(sink)->alloc_buffer(sink, event, pages, nr_pages, overwrite); if (!event_data->snk_config) goto err; diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index a38ad2b0d95a..1df1f8fade71 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -350,10 +350,11 @@ static void tmc_disable_etf_link(struct coresight_device *csdev, dev_dbg(drvdata->dev, "TMC-ETF disabled\n"); } -static void *tmc_alloc_etf_buffer(struct coresight_device *csdev, int cpu, - void **pages, int nr_pages, bool overwrite) +static void *tmc_alloc_etf_buffer(struct coresight_device *csdev, + struct perf_event *event, void **pages, + int nr_pages, bool overwrite) { - int node; + int node, cpu = event->cpu; struct cs_buffers *buf; if (cpu == -1) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 9a0b346be58b..55ee0aca321c 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1167,13 +1167,18 @@ static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev) * reaches a minimum limit (1M), beyond which we give up. */ static struct etr_perf_buffer * -tmc_etr_setup_perf_buf(struct tmc_drvdata *drvdata, int node, int nr_pages, - void **pages, bool snapshot) +tmc_etr_setup_perf_buf(struct tmc_drvdata *drvdata, struct perf_event *event, + int nr_pages, void **pages, bool snapshot) { + int node, cpu = event->cpu; struct etr_buf *etr_buf; struct etr_perf_buffer *etr_perf; unsigned long size; + if (cpu == -1) + cpu = smp_processor_id(); + node = cpu_to_node(cpu); + etr_perf = kzalloc_node(sizeof(*etr_perf), GFP_KERNEL, node); if (!etr_perf) return ERR_PTR(-ENOMEM); @@ -1211,16 +1216,13 @@ tmc_etr_setup_perf_buf(struct tmc_drvdata *drvdata, int node, int nr_pages, static void *tmc_alloc_etr_buffer(struct coresight_device *csdev, - int cpu, void **pages, int nr_pages, - bool snapshot) + struct perf_event *event, void **pages, + int nr_pages, bool snapshot) { struct etr_perf_buffer *etr_perf; struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - if (cpu == -1) - cpu = smp_processor_id(); - - etr_perf = tmc_etr_setup_perf_buf(drvdata, cpu_to_node(cpu), + etr_perf = tmc_etr_setup_perf_buf(drvdata, event, nr_pages, pages, snapshot); if (IS_ERR(etr_perf)) { dev_dbg(drvdata->dev, "Unable to allocate ETR buffer\n"); diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 189cc6ddc92b..62a520df8add 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -193,8 +193,9 @@ struct coresight_device { struct coresight_ops_sink { int (*enable)(struct coresight_device *csdev, u32 mode, void *data); int (*disable)(struct coresight_device *csdev); - void *(*alloc_buffer)(struct coresight_device *csdev, int cpu, - void **pages, int nr_pages, bool overwrite); + void *(*alloc_buffer)(struct coresight_device *csdev, + struct perf_event *event, void **pages, + int nr_pages, bool overwrite); void (*free_buffer)(void *config); unsigned long (*update_buffer)(struct coresight_device *csdev, struct perf_output_handle *handle, From patchwork Thu Apr 25 19:53:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 162867 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2362518jan; Thu, 25 Apr 2019 12:53:48 -0700 (PDT) X-Google-Smtp-Source: APXvYqz3VKLFNh5QoK+vSZOanD8dQV7Md46GweVWvESadoGVMPuYjbJwlb7zi/0dlVpWA/cL2nC4 X-Received: by 2002:a17:902:a5ca:: with SMTP id t10mr41751375plq.234.1556222028211; Thu, 25 Apr 2019 12:53:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id t64sm47261961pfa.86.2019.04.25.12.53.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 12:53:42 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 24/32] coresight: tmc-etr: Refactor function tmc_etr_setup_perf_buf() Date: Thu, 25 Apr 2019 13:53:02 -0600 Message-Id: <20190425195310.31562-25-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190425195310.31562-1-mathieu.poirier@linaro.org> References: <20190425195310.31562-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Refactoring function tmc_etr_setup_perf_buf() so that it only deals with the high level etr_perf_buffer, leaving the allocation of the backend buffer (i.e etr_buf) to another function. That way the backend buffer allocation function can decide if it wants to reuse an existing buffer (CPU-wide trace scenarios) or simply create a new one. Signed-off-by: Mathieu Poirier Tested-by: Leo Yan Tested-by: Robert Walker --- .../hwtracing/coresight/coresight-tmc-etr.c | 39 ++++++++++++++----- 1 file changed, 30 insertions(+), 9 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 55ee0aca321c..e1d2128ee757 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1160,29 +1160,24 @@ static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev) } /* - * tmc_etr_setup_perf_buf: Allocate ETR buffer for use by perf. + * alloc_etr_buf: Allocate ETR buffer for use by perf. * The size of the hardware buffer is dependent on the size configured * via sysfs and the perf ring buffer size. We prefer to allocate the * largest possible size, scaling down the size by half until it * reaches a minimum limit (1M), beyond which we give up. */ -static struct etr_perf_buffer * -tmc_etr_setup_perf_buf(struct tmc_drvdata *drvdata, struct perf_event *event, - int nr_pages, void **pages, bool snapshot) +static struct etr_buf * +alloc_etr_buf(struct tmc_drvdata *drvdata, struct perf_event *event, + int nr_pages, void **pages, bool snapshot) { int node, cpu = event->cpu; struct etr_buf *etr_buf; - struct etr_perf_buffer *etr_perf; unsigned long size; if (cpu == -1) cpu = smp_processor_id(); node = cpu_to_node(cpu); - etr_perf = kzalloc_node(sizeof(*etr_perf), GFP_KERNEL, node); - if (!etr_perf) - return ERR_PTR(-ENOMEM); - /* * Try to match the perf ring buffer size if it is larger * than the size requested via sysfs. @@ -1206,6 +1201,32 @@ tmc_etr_setup_perf_buf(struct tmc_drvdata *drvdata, struct perf_event *event, size /= 2; } while (size >= TMC_ETR_PERF_MIN_BUF_SIZE); + return ERR_PTR(-ENOMEM); + +done: + return etr_buf; +} + +static struct etr_perf_buffer * +tmc_etr_setup_perf_buf(struct tmc_drvdata *drvdata, struct perf_event *event, + int nr_pages, void **pages, bool snapshot) +{ + int node, cpu = event->cpu; + struct etr_buf *etr_buf; + struct etr_perf_buffer *etr_perf; + + if (cpu == -1) + cpu = smp_processor_id(); + node = cpu_to_node(cpu); + + etr_perf = kzalloc_node(sizeof(*etr_perf), GFP_KERNEL, node); + if (!etr_perf) + return ERR_PTR(-ENOMEM); + + etr_buf = alloc_etr_buf(drvdata, event, nr_pages, pages, snapshot); + if (!IS_ERR(etr_buf)) + goto done; + kfree(etr_perf); return ERR_PTR(-ENOMEM); From patchwork Thu Apr 25 19:53:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 162874 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2363003jan; Thu, 25 Apr 2019 12:54:20 -0700 (PDT) X-Google-Smtp-Source: APXvYqxDAxIfG5eoSzIOp/CeinyrBhuPCgakWNReXHzOivkghPrPzlEvbBfc1gndm28QoCW7W+RB X-Received: by 2002:aa7:83d1:: with SMTP id j17mr42478065pfn.78.1556222060745; Thu, 25 Apr 2019 12:54:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556222060; cv=none; d=google.com; s=arc-20160816; b=oZYPhF6aZAy3OKqsUndTC9udplp8g//kWiiAuVqkjFmTHLYnHyKxvZg+o0NHSsL4Xy Y3A4kPzvAtuNiH6tNP+xxo3Y45Z39RMYBAvhL6W8L5ofuyBFJhCDQcURIth3wx4jddOk 9tUYu3pA2RNN/KOOS4NkwbnI7ksIWpffZq0Ju7FpNtftiYbA+DSxiAvaEsWJSnAg6gUd UjfbBp/UFP7EuJq/YgKMAro/u5RzzBKCyP2kjooN8dADkjYCqWuJTyGA3nIuoDaZ8prn g/fhEH7+oVK2AwCGuN3pUzpzRhyqL2HeLjFiNlrX26J4/8VGI+CRgFNE00IndG1vhzIt Ccww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=hCKOOh4hib7nPM65HtU8D/wwQ4e+FlOROgf2ArtIPlk=; b=Rcuf+bsfFYJ/JnZz0fc5uAaAmYZrYOd1rg1CVNrXKEgIYS8CUXtI1jFrz7G8cVK5IE hMLNWVtXONXleNxAUKVrHpFA6J2+dzANK0U2Qc307CUX3nB6v2DEqO2Vif63707ga6zA qGvAgu4HCI85ElK6s/pnJ+D6tM3bWHAIy92L2A4rcb2P5f9i9nL+7U3rHHXWAE58bdZO 4M9KvDxFcFDhfMnVbsruBiFAbx9vBmkmfKKOGMMmdke+L9Vt9dz6+BjzJVLN/JGFKJ33 +AgFRiSTLf4sOG8Abg2H1Sdkzuc1d5/pufxLmuVoytYI7dRsqczfVH9idKCnXibCi+4b qqDg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NLl1Qh73; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id t64sm47261961pfa.86.2019.04.25.12.53.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 12:53:44 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 25/32] coresight: tmc-etr: Create per-thread buffer allocation function Date: Thu, 25 Apr 2019 13:53:03 -0600 Message-Id: <20190425195310.31562-26-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190425195310.31562-1-mathieu.poirier@linaro.org> References: <20190425195310.31562-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Buffer allocation is different when dealing with per-thread and CPU-wide sessions. In preparation to support CPU-wide trace scenarios simplify things by keeping allocation functions for both type separate. Signed-off-by: Mathieu Poirier Tested-by: Leo Yan Tested-by: Robert Walker --- .../hwtracing/coresight/coresight-tmc-etr.c | 29 ++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index e1d2128ee757..bca1b2d9ef2e 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1207,6 +1207,33 @@ alloc_etr_buf(struct tmc_drvdata *drvdata, struct perf_event *event, return etr_buf; } +static struct etr_buf * +get_perf_etr_buf_per_thread(struct tmc_drvdata *drvdata, + struct perf_event *event, int nr_pages, + void **pages, bool snapshot) +{ + struct etr_buf *etr_buf; + + /* + * In per-thread mode the etr_buf isn't shared, so just go ahead + * with memory allocation. + */ + etr_buf = alloc_etr_buf(drvdata, event, nr_pages, pages, snapshot); + + return etr_buf; +} + +static struct etr_buf * +get_perf_etr_buf(struct tmc_drvdata *drvdata, struct perf_event *event, + int nr_pages, void **pages, bool snapshot) +{ + if (event->cpu == -1) + return get_perf_etr_buf_per_thread(drvdata, event, nr_pages, + pages, snapshot); + + return ERR_PTR(-ENOENT); +} + static struct etr_perf_buffer * tmc_etr_setup_perf_buf(struct tmc_drvdata *drvdata, struct perf_event *event, int nr_pages, void **pages, bool snapshot) @@ -1223,7 +1250,7 @@ tmc_etr_setup_perf_buf(struct tmc_drvdata *drvdata, struct perf_event *event, if (!etr_perf) return ERR_PTR(-ENOMEM); - etr_buf = alloc_etr_buf(drvdata, event, nr_pages, pages, snapshot); + etr_buf = get_perf_etr_buf(drvdata, event, nr_pages, pages, snapshot); if (!IS_ERR(etr_buf)) goto done; From patchwork Thu Apr 25 19:53:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 162868 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2362609jan; Thu, 25 Apr 2019 12:53:54 -0700 (PDT) X-Google-Smtp-Source: APXvYqzoQ5fBGB6lkFac/qPh+vQcUrlXSWTYc/vxe+lN2SNUhOSpnVItqIFqu7MohZ5C3nV0V22Y X-Received: by 2002:aa7:9a89:: with SMTP id w9mr42148318pfi.213.1556222034051; Thu, 25 Apr 2019 12:53:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556222034; cv=none; d=google.com; s=arc-20160816; b=uaR5XL0OtTnLRkW1rYmf6wludRks6jX/aDeqgCdptSRyMAggIhgZUd+YlzHmKaA8Pg 9phaZSxajkjk+HwBqcWVH0CekLPu96ElaahXf5TfhR8bw4+IdzLOV1xUZUAzK2K4c+MB OEyLRtTP53+feYFCQP0O90gU71aKwdY/AajkT80/GgE+5Gop4TiYXq5DdqjEmCtPcSkx M8Xfr1Fk9KPQLFTNkzN2rj0nHbyimePY6AjobDLzpYHz1eojZDr4oOgwlXLQ5MbrxFNF ZEAkxnTsHmzP0SGiS1DwnBe/gHq2058SPJfT16rmZTIxUw42zjaX3vERZGBc9eR/lOR2 gz8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=riIgjligLeRRiB4uxmqLKgEO+EfIEZ1Ob5vBkh/7tHQ=; b=NiX1zIC2q5z1XT1ITjG7JvpGdzwkckFZbAwpak504FDW22doDNKAgUbt2HJX0HrD7Y ZUf+FtbpbqWzNXf1katBoJ48crCvK1af5HaITZqEQg4qqdje7Fdw8BxWBVv8qOmrAFVZ cYloDJSyVPU4fBi2obIxcsanK3azW8/jSHW2DN/ka4Dy0EmL+VHnwhrzcKDHTuzNaNGT GLOJTLuRpzbXGcRmC3mwnBnuyBLQ6/SFLcktfvu8mCA5AQfxk0niQZJV+xxPszMLpMQN ird8Nv1nj58EOvzQnQ5EdxyKwgV6t/8NQgwHSY4W01ghj1i9agBn8xwqvD3Fn5QOHVJo Q5JQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ILmbs2ao; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id t64sm47261961pfa.86.2019.04.25.12.53.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 12:53:45 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 26/32] coresight: tmc-etr: Introduce the notion of process ID to ETR devices Date: Thu, 25 Apr 2019 13:53:04 -0600 Message-Id: <20190425195310.31562-27-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190425195310.31562-1-mathieu.poirier@linaro.org> References: <20190425195310.31562-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In preparation to support CPU-wide trace scenarios, introduce the notion of process ID to ETR devices. That way events monitoring the same process can use the same etr_buf, allowing multiple CPUs to use the same sink. Signed-off-by: Mathieu Poirier Tested-by: Leo Yan Tested-by: Robert Walker --- drivers/hwtracing/coresight/coresight-tmc-etr.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index bca1b2d9ef2e..1acad42184e6 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include "coresight-catu.h" #include "coresight-etm-perf.h" @@ -25,6 +26,7 @@ struct etr_flat_buf { /* * etr_perf_buffer - Perf buffer used for ETR * @etr_buf - Actual buffer used by the ETR + * @pid - The PID this etr_perf_buffer belongs to. * @snaphost - Perf session mode * @head - handle->head at the beginning of the session. * @nr_pages - Number of pages in the ring buffer. @@ -32,6 +34,7 @@ struct etr_flat_buf { */ struct etr_perf_buffer { struct etr_buf *etr_buf; + pid_t pid; bool snapshot; unsigned long head; int nr_pages; @@ -1277,6 +1280,7 @@ static void *tmc_alloc_etr_buffer(struct coresight_device *csdev, return NULL; } + etr_perf->pid = task_pid_nr(event->owner); etr_perf->snapshot = snapshot; etr_perf->nr_pages = nr_pages; etr_perf->pages = pages; From patchwork Thu Apr 25 19:53:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 162873 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2362928jan; Thu, 25 Apr 2019 12:54:16 -0700 (PDT) X-Google-Smtp-Source: APXvYqyHXGlNHHITpeQrFPjEoII5PxslyOnoOBPKq6I4RJezJtXrEdX0gpt4T3DtM7Y/leeHC7Z1 X-Received: by 2002:a62:4595:: with SMTP id n21mr42949387pfi.79.1556222056736; Thu, 25 Apr 2019 12:54:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556222056; cv=none; d=google.com; s=arc-20160816; b=qb1h34b5UqQ8e/VoOYcQQK45YFCKxFzYjWNvt5+Wxh5sFSe/9Fp9LBLmqWB1rKtoxk ql/3YZGp3H/ipMjdGjX4Ra6Ej2cmgRqCtSig2TqkgdT7mpOPRXroWrvkfWdrxlY7KfNu ZUBSo7JJdu0t/x4xoWVs6IqcBQC1+S3mkU7Hh65wMQNE1jZH2tmxCxxEgydHne0WYcgy UeNuS2TpvIdd3iDtTc/JQEw4lm/jE9gbJBkDNLy+v/H3HsnJB2Y9RyisH3X+AI4kHPMz NVutdri1zSwYzfxsk4ZzPxjWZryf1IdxzXvM0RPJWHo5av8R8YmYu9RcmmhLx6SLFYVj Pt0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=beHUlTV1r7N3uXY3Nh5y6OVMIGz+2muMwcMKI5ehutQ=; b=ynuwCJ+O5Vsi5c54Pdooi8UBRNcM6LXei8Ei2m3TzejwQEmFZOYnFVcfdKinFoBh1z CAx/VrN5WqeLT9gwX35eA9wt37/Xt/VxiIPsOicyrbH7GqKkKpMpu3KIc6q7RyJsXZfk RJTAjmgEb7ptb5qdQO0EAEIxgX7BoReln7QZAJXKdJP55nEVuixd5sl5Ub6RUhie7T13 5Wk8P4YpbS6Y42HQJdG0PJJg5jm41Ct97qGov6+OIki5ZFzPkAILyR4sC9xLwHmhcENV Ky3pSr30Iwrf9j3SRtBXv1TrRhsQnILH5IJfs9mOwv6ZnTYuInJOyLgLvrD8TCVi4+lL 4rUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TMAP7HcQ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id t64sm47261961pfa.86.2019.04.25.12.53.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 12:53:46 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 27/32] coresight: tmc-etr: Introduce the notion of reference counting to ETR devices Date: Thu, 25 Apr 2019 13:53:05 -0600 Message-Id: <20190425195310.31562-28-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190425195310.31562-1-mathieu.poirier@linaro.org> References: <20190425195310.31562-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds reference counting to struct etr_buf so that, in CPU-wide trace scenarios, shared buffers can be disposed of when no longer used. Signed-off-by: Mathieu Poirier Tested-by: Leo Yan Tested-by: Robert Walker --- drivers/hwtracing/coresight/coresight-tmc-etr.c | 5 +++++ drivers/hwtracing/coresight/coresight-tmc.h | 3 +++ 2 files changed, 8 insertions(+) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 1acad42184e6..de33c0391186 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -1222,7 +1223,11 @@ get_perf_etr_buf_per_thread(struct tmc_drvdata *drvdata, * with memory allocation. */ etr_buf = alloc_etr_buf(drvdata, event, nr_pages, pages, snapshot); + if (IS_ERR(etr_buf)) + goto out; + refcount_set(&etr_buf->refcount, 1); +out: return etr_buf; } diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index 487c53701e9c..ee44906dffe8 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -9,6 +9,7 @@ #include #include +#include #define TMC_RSZ 0x004 #define TMC_STS 0x00c @@ -133,6 +134,7 @@ struct etr_buf_operations; /** * struct etr_buf - Details of the buffer used by ETR + * refcount ; Number of sources currently using this etr_buf. * @mode : Mode of the ETR buffer, contiguous, Scatter Gather etc. * @full : Trace data overflow * @size : Size of the buffer. @@ -143,6 +145,7 @@ struct etr_buf_operations; * @private : Backend specific information for the buf */ struct etr_buf { + refcount_t refcount; enum etr_mode mode; bool full; ssize_t size; From patchwork Thu Apr 25 19:53:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 162875 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2363047jan; Thu, 25 Apr 2019 12:54:24 -0700 (PDT) X-Google-Smtp-Source: APXvYqxlhgtDy2iUD1GBIMRHOB5PziRaiFXLgXtBRlvahuh6nav0OSKepPVBvDL92jSI4SWUveDB X-Received: by 2002:a65:4247:: with SMTP id d7mr23213306pgq.114.1556222064253; Thu, 25 Apr 2019 12:54:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556222064; cv=none; d=google.com; s=arc-20160816; b=yJgx9zr8WJSTPqI5sbRobz/jvwV2uVQiAhTFRyIy1W0+Riu7VcrDrGZRO7b6CLUapM Zsp6QF13bZP5oLdbpUA/tPA4kkw3YNrXlaiz9IJ5jp1uaLR8wIkatEcjH45dnqCPKDdD ppAreo8PAKqnPOG+G4r4lCthRc/9gsBwqHD288ccpkqrFzvUymtHNpLdDApTYYkyVBRb XoaWhvCNU7/bm3a0Dp+dm+DlvO7yhcfJJLEX5/6wWkueU5wSnNyMT6SiNHwwBbbHW4tU p30R0DNo+eI5LtOND5LWInf/95gAthz8kBlQ1nUsUlmB7JMpaHDwudG6+FFJALvcuudF TJSg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=tPRA4UlOAMNFpacsoz6vhdGt52ZgMz7HCu722PCoiN0=; b=H+VkjU0QIc8xh8e55KL5Kxe9bgJYa4WwHMG2zwo+SvdxtDk3E4zrsQ64o+Qxswqmfx KjR96ulYpY5bzBl/cS1YQfhv/AmDTd+mwsVbiRR8ReOD9w6mqChVNCfw5hKGuA3WnIWE MokWOmCjuzxHbMrwnuoejp5XdG2my9ZaFPRbFZhFiBwEnflbtdU+0nYF46YwdFMxafVM 04ygM4oA9pseCRiu04A4/4m/g6OaImPUrNPSi+6TdgmerDqQE2P4fbLbySgl0RhjeFaT +W956EIbrfAFt85oDK4uL3IrZTDjMIFi5+gnWktEDhx+y8Bwtl1mSreMtEYUFCeSPK8i n7lw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mWC+GqB4; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id t64sm47261961pfa.86.2019.04.25.12.53.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 12:53:47 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 28/32] coresight: tmc-etr: Introduce the notion of IDR to ETR devices Date: Thu, 25 Apr 2019 13:53:06 -0600 Message-Id: <20190425195310.31562-29-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190425195310.31562-1-mathieu.poirier@linaro.org> References: <20190425195310.31562-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In CPU-wide scenarios with an N:1 source/sink topology, sources share the same sink. In order to reuse the same sink for all sources an IDR is needed to archive events that have already been accounted for. Signed-off-by: Mathieu Poirier Tested-by: Leo Yan Tested-by: Robert Walker --- drivers/hwtracing/coresight/coresight-tmc.c | 4 ++++ drivers/hwtracing/coresight/coresight-tmc.h | 6 ++++++ 2 files changed, 10 insertions(+) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c index c6a5462ebf27..9f9b2c514566 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.c +++ b/drivers/hwtracing/coresight/coresight-tmc.c @@ -8,10 +8,12 @@ #include #include #include +#include #include #include #include #include +#include #include #include #include @@ -450,6 +452,8 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id) coresight_get_uci_data(id)); if (ret) goto out; + idr_init(&drvdata->idr); + mutex_init(&drvdata->idr_mutex); break; case TMC_CONFIG_TYPE_ETF: desc.type = CORESIGHT_DEV_TYPE_LINKSINK; diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index ee44906dffe8..c1b1700b2df7 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -8,7 +8,9 @@ #define _CORESIGHT_TMC_H #include +#include #include +#include #include #define TMC_RSZ 0x004 @@ -173,6 +175,8 @@ struct etr_buf { * @trigger_cntr: amount of words to store after a trigger. * @etr_caps: Bitmask of capabilities of the TMC ETR, inferred from the * device configuration register (DEVID) + * @idr: Holds etr_bufs allocated for this ETR. + * @idr_mutex: Access serialisation for idr. * @perf_data: PERF buffer for ETR. * @sysfs_data: SYSFS buffer for ETR. */ @@ -194,6 +198,8 @@ struct tmc_drvdata { enum tmc_mem_intf_width memwidth; u32 trigger_cntr; u32 etr_caps; + struct idr idr; + struct mutex idr_mutex; struct etr_buf *sysfs_buf; void *perf_data; }; From patchwork Thu Apr 25 19:53:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 162872 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2362892jan; Thu, 25 Apr 2019 12:54:14 -0700 (PDT) X-Google-Smtp-Source: APXvYqwa8s8k09KbEm9IMFT8H42RwoP5n1g58Cvb7OjeeioM8/60+WoX/APr58F7kSt4arno/oVq X-Received: by 2002:a63:f448:: with SMTP id p8mr39323868pgk.50.1556222053946; Thu, 25 Apr 2019 12:54:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556222053; cv=none; d=google.com; s=arc-20160816; b=M4qiJPNDJKZWsUummFXOAq6M/Rx6wIkBZPhskdrW5tJAzgSqXOnraY0zn2OrOq/LNp 8vHyZchtp6Lrg0XjrvH9Qp5KTXf9adz9jTbzVZqBZhdgZIH1Y0IXCLdSBKiV3Dxo4/cj qCjRE2gGMR2hVXIZbnlCiK/SBJ49JKP0nKIowUtXxD5Gg8cXAYRJUCHMSsU+k/rh05EM of4f/NoefROs/muE6ZHPkIjaVbZ17GpS9+hUaxk/b5joEGK9iDi9AiTJqwr3kpvKpmJ0 plEsuvbHBHQrpFOreX+SNRoPhnRIsPlU7ZydQi696QRUiRruluYJLExerdtTA8LB0OEv Wi2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=R2jIvb1354+yjxn5P0goj61vP+hMBRVkIBdNyTFpnwU=; b=QwI+2Yo7a3/z9TlUFoYk0QYZpnlcQis4tx6iC0ueK5hQHjH2cobziZM3U6de2W74N6 cZphjjJ7T4i3/1P4OvmiVuxHPtPjTT3io7FjnF523LmVS5xrdtR45Y/y//B6FjQM4WuF bylKxxJEssVPudNXH3JCBsojVMt4htr75F8NIu6gDg5wNjy0Hyl2k2bbHOPU+4zGXnRr 4baSlzCUXc9qHYpgtKFi+3FoaVi7Ln/CIsA+6gt9V8+jUO4jgvrG1QYn+Ov958V3U9lH 4411F514HDhJvNHwsoUfv9H+assidx04fwhP2wT4GE3veW/KjG2K2RupJxgj+5wXCNjR Hk9g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="CgYCokQ/"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id t64sm47261961pfa.86.2019.04.25.12.53.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 12:53:49 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 29/32] coresight: tmc-etr: Allocate and free ETR memory buffers for CPU-wide scenarios Date: Thu, 25 Apr 2019 13:53:07 -0600 Message-Id: <20190425195310.31562-30-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190425195310.31562-1-mathieu.poirier@linaro.org> References: <20190425195310.31562-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch uses the PID of the process being traced to allocate and free ETR memory buffers for CPU-wide scenarios. The implementation is tailored to handle both N:1 and 1:1 source/sink HW topologies. Signed-off-by: Mathieu Poirier Tested-by: Leo Yan Tested-by: Robert Walker --- .../hwtracing/coresight/coresight-tmc-etr.c | 107 +++++++++++++++++- 1 file changed, 104 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index de33c0391186..8c75800003d2 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -8,6 +8,8 @@ #include #include #include +#include +#include #include #include #include @@ -26,6 +28,7 @@ struct etr_flat_buf { /* * etr_perf_buffer - Perf buffer used for ETR + * @drvdata - The ETR drvdaga this buffer has been allocated for. * @etr_buf - Actual buffer used by the ETR * @pid - The PID this etr_perf_buffer belongs to. * @snaphost - Perf session mode @@ -34,6 +37,7 @@ struct etr_flat_buf { * @pages - Array of Pages in the ring buffer. */ struct etr_perf_buffer { + struct tmc_drvdata *drvdata; struct etr_buf *etr_buf; pid_t pid; bool snapshot; @@ -1211,6 +1215,72 @@ alloc_etr_buf(struct tmc_drvdata *drvdata, struct perf_event *event, return etr_buf; } +static struct etr_buf * +get_perf_etr_buf_cpu_wide(struct tmc_drvdata *drvdata, + struct perf_event *event, int nr_pages, + void **pages, bool snapshot) +{ + int ret; + pid_t pid = task_pid_nr(event->owner); + struct etr_buf *etr_buf; + +retry: + /* + * An etr_perf_buffer is associated with an event and holds a reference + * to the AUX ring buffer that was created for that event. In CPU-wide + * N:1 mode multiple events (one per CPU), each with its own AUX ring + * buffer, share a sink. As such an etr_perf_buffer is created for each + * event but a single etr_buf associated with the ETR is shared between + * them. The last event in a trace session will copy the content of the + * etr_buf to its AUX ring buffer. Ring buffer associated to other + * events are simply not used an freed as events are destoyed. We still + * need to allocate a ring buffer for each event since we don't know + * which event will be last. + */ + + /* + * The first thing to do here is check if an etr_buf has already been + * allocated for this session. If so it is shared with this event, + * otherwise it is created. + */ + mutex_lock(&drvdata->idr_mutex); + etr_buf = idr_find(&drvdata->idr, pid); + if (etr_buf) { + refcount_inc(&etr_buf->refcount); + mutex_unlock(&drvdata->idr_mutex); + return etr_buf; + } + + /* If we made it here no buffer has been allocated, do so now. */ + mutex_unlock(&drvdata->idr_mutex); + + etr_buf = alloc_etr_buf(drvdata, event, nr_pages, pages, snapshot); + if (IS_ERR(etr_buf)) + return etr_buf; + + refcount_set(&etr_buf->refcount, 1); + + /* Now that we have a buffer, add it to the IDR. */ + mutex_lock(&drvdata->idr_mutex); + ret = idr_alloc(&drvdata->idr, etr_buf, pid, pid + 1, GFP_KERNEL); + mutex_unlock(&drvdata->idr_mutex); + + /* Another event with this session ID has allocated this buffer. */ + if (ret == -ENOSPC) { + tmc_free_etr_buf(etr_buf); + goto retry; + } + + /* The IDR can't allocate room for a new session, abandon ship. */ + if (ret == -ENOMEM) { + tmc_free_etr_buf(etr_buf); + return ERR_PTR(ret); + } + + + return etr_buf; +} + static struct etr_buf * get_perf_etr_buf_per_thread(struct tmc_drvdata *drvdata, struct perf_event *event, int nr_pages, @@ -1239,7 +1309,8 @@ get_perf_etr_buf(struct tmc_drvdata *drvdata, struct perf_event *event, return get_perf_etr_buf_per_thread(drvdata, event, nr_pages, pages, snapshot); - return ERR_PTR(-ENOENT); + return get_perf_etr_buf_cpu_wide(drvdata, event, nr_pages, + pages, snapshot); } static struct etr_perf_buffer * @@ -1266,7 +1337,13 @@ tmc_etr_setup_perf_buf(struct tmc_drvdata *drvdata, struct perf_event *event, return ERR_PTR(-ENOMEM); done: + /* + * Keep a reference to the ETR this buffer has been allocated for + * in order to have access to the IDR in tmc_free_etr_buffer(). + */ + etr_perf->drvdata = drvdata; etr_perf->etr_buf = etr_buf; + return etr_perf; } @@ -1296,9 +1373,33 @@ static void *tmc_alloc_etr_buffer(struct coresight_device *csdev, static void tmc_free_etr_buffer(void *config) { struct etr_perf_buffer *etr_perf = config; + struct tmc_drvdata *drvdata = etr_perf->drvdata; + struct etr_buf *buf, *etr_buf = etr_perf->etr_buf; + + if (!etr_buf) + goto free_etr_perf_buffer; + + mutex_lock(&drvdata->idr_mutex); + /* If we are not the last one to use the buffer, don't touch it. */ + if (!refcount_dec_and_test(&etr_buf->refcount)) { + mutex_unlock(&drvdata->idr_mutex); + goto free_etr_perf_buffer; + } + + /* We are the last one, remove from the IDR and free the buffer. */ + buf = idr_remove(&drvdata->idr, etr_perf->pid); + mutex_unlock(&drvdata->idr_mutex); + + /* + * Something went very wrong if the buffer associated with this ID + * is not the same in the IDR. Leak to avoid use after free. + */ + if (buf && WARN_ON(buf != etr_buf)) + goto free_etr_perf_buffer; + + tmc_free_etr_buf(etr_perf->etr_buf); - if (etr_perf->etr_buf) - tmc_free_etr_buf(etr_perf->etr_buf); +free_etr_perf_buffer: kfree(etr_perf); } From patchwork Thu Apr 25 19:53:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 162870 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2362679jan; Thu, 25 Apr 2019 12:53:58 -0700 (PDT) X-Google-Smtp-Source: APXvYqzhJG7VxTv88c5zRzSJ/RxqRmocMGi9MvYuWGnoUCjBPMAxKrV0bueiP50H47MGxo1u2m+x X-Received: by 2002:a17:902:b10a:: with SMTP id q10mr7825870plr.303.1556222038443; Thu, 25 Apr 2019 12:53:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556222038; cv=none; d=google.com; s=arc-20160816; b=O3yehx9HKzq0hS3DTR2scaToLDSBOP8lJyAYUeGfqzx8Xdl922F08vVAqJVdVlpQW3 eG7Z4+AZKlSUrvSL8pO7Lbuuzz744gdxifBvwDCSHTq2Mi/vEExE/nBq6hTNVXpwPEP6 n4dcyaT0rPhLAEQRnb3KYIirskUIYb7Fh1iHsrEOSTTWnf/bNBjz9JqDjA8KC0xjLLGz uGKIB61eEELal3sAsmsuHYUWjll3kpKGRBO80VuD9zoH37ao7qRW3ELVkZs4he/bhnYP ccwCXtJfTsv8G/VYzypVMCibzHFTGMtEvgEcK9RcAnsHN8J+ev9MN42IwyYuoNa7598N qYWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=nvndSiJzhOG7Xw1LUtIIbFBDaU3VT58I2Bl/sSO11+w=; b=hTf8MavACaIXLojz3WCCSCnp7dWvt1gRAS7HTeL2OsWrLP1GHaCzhD2rue9fEm7JFw FQ/3OEVfWMJo0wfWOyIJJ5XFvJ9VG6lw0CVmFDmNqI6HU1TCoTnyfohfuF+pN0SBALp+ IbRjUv4YUIfyfOhDWpW2CGtFuZecoEkTFukdYzPcNftWWRQRq/vd8qZneWKNp/lYTEhL NbP7ibncaRvuywyvygcw+ei+UBtRHk0hv7Y6AhSkD/nbEk5o9jrH05HShHevn7s2RH7i lOifed/gVA+JdYjvYLXhjpTiDxmVpdk18AA2u7gQEh6O48z4VPw0CckrPRyNCPO8282i qzwg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PKo3sGS6; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id t64sm47261961pfa.86.2019.04.25.12.53.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 12:53:50 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 30/32] coresight: tmc-etr: Add support for CPU-wide trace scenarios Date: Thu, 25 Apr 2019 13:53:08 -0600 Message-Id: <20190425195310.31562-31-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190425195310.31562-1-mathieu.poirier@linaro.org> References: <20190425195310.31562-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds support for CPU-wide trace scenarios by making sure that only the sources monitoring the same process have access to a common sink. Because the sink is shared between sources, the first source to use the sink switches it on while the last one does the cleanup. Any attempt to modify the HW is overlooked for as long as more than one source is using a sink. Signed-off-by: Mathieu Poirier Tested-by: Leo Yan Tested-by: Robert Walker --- .../hwtracing/coresight/coresight-tmc-etr.c | 38 ++++++++++++++++--- drivers/hwtracing/coresight/coresight-tmc.c | 2 + drivers/hwtracing/coresight/coresight-tmc.h | 3 ++ 3 files changed, 38 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 8c75800003d2..df6e4b0b84e9 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1474,6 +1474,13 @@ tmc_update_etr_buffer(struct coresight_device *csdev, struct etr_buf *etr_buf = etr_perf->etr_buf; spin_lock_irqsave(&drvdata->spinlock, flags); + + /* Don't do anything if another tracer is using this sink */ + if (atomic_read(csdev->refcnt) != 1) { + spin_unlock_irqrestore(&drvdata->spinlock, flags); + goto out; + } + if (WARN_ON(drvdata->perf_data != etr_perf)) { lost = true; spin_unlock_irqrestore(&drvdata->spinlock, flags); @@ -1513,17 +1520,15 @@ tmc_update_etr_buffer(struct coresight_device *csdev, static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, void *data) { int rc = 0; + pid_t pid; unsigned long flags; struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); struct perf_output_handle *handle = data; struct etr_perf_buffer *etr_perf = etm_perf_sink_config(handle); spin_lock_irqsave(&drvdata->spinlock, flags); - /* - * There can be only one writer per sink in perf mode. If the sink - * is already open in SYSFS mode, we can't use it. - */ - if (drvdata->mode != CS_MODE_DISABLED || WARN_ON(drvdata->perf_data)) { + /* Don't use this sink if it is already claimed by sysFS */ + if (drvdata->mode == CS_MODE_SYSFS) { rc = -EBUSY; goto unlock_out; } @@ -1533,10 +1538,31 @@ static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, void *data) goto unlock_out; } + /* Get a handle on the pid of the process to monitor */ + pid = etr_perf->pid; + + /* Do not proceed if this device is associated with another session */ + if (drvdata->pid != -1 && drvdata->pid != pid) { + rc = -EBUSY; + goto unlock_out; + } + etr_perf->head = PERF_IDX2OFF(handle->head, etr_perf); drvdata->perf_data = etr_perf; + + /* + * No HW configuration is needed if the sink is already in + * use for this session. + */ + if (drvdata->pid == pid) { + atomic_inc(csdev->refcnt); + goto unlock_out; + } + rc = tmc_etr_enable_hw(drvdata, etr_perf->etr_buf); if (!rc) { + /* Associate with monitored process. */ + drvdata->pid = pid; drvdata->mode = CS_MODE_PERF; atomic_inc(csdev->refcnt); } @@ -1580,6 +1606,8 @@ static int tmc_disable_etr_sink(struct coresight_device *csdev) /* Complain if we (somehow) got out of sync */ WARN_ON_ONCE(drvdata->mode == CS_MODE_DISABLED); tmc_etr_disable_hw(drvdata); + /* Dissociate from monitored process. */ + drvdata->pid = -1; drvdata->mode = CS_MODE_DISABLED; spin_unlock_irqrestore(&drvdata->spinlock, flags); diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c index 9f9b2c514566..3f718729d741 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.c +++ b/drivers/hwtracing/coresight/coresight-tmc.c @@ -422,6 +422,8 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id) devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID); drvdata->config_type = BMVAL(devid, 6, 7); drvdata->memwidth = tmc_get_memwidth(devid); + /* This device is not associated with a session */ + drvdata->pid = -1; if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) { if (np) diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index c1b1700b2df7..503f1b3a3741 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -165,6 +165,8 @@ struct etr_buf { * @csdev: component vitals needed by the framework. * @miscdev: specifics to handle "/dev/xyz.tmc" entry. * @spinlock: only one at a time pls. + * @pid: Process ID of the process being monitored by the session + * that is using this component. * @buf: Snapshot of the trace data for ETF/ETB. * @etr_buf: details of buffer used in TMC-ETR * @len: size of the available trace for ETF/ETB. @@ -186,6 +188,7 @@ struct tmc_drvdata { struct coresight_device *csdev; struct miscdevice miscdev; spinlock_t spinlock; + pid_t pid; bool reading; union { char *buf; /* TMC ETB */ From patchwork Thu Apr 25 19:53:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 162869 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2362647jan; Thu, 25 Apr 2019 12:53:56 -0700 (PDT) X-Google-Smtp-Source: APXvYqxwZ0Hoqbiri0U6oBM348UkNgCVY9SGhHEB1NSjI4jnCm9ootyZG2iPiy7WfDNcST/cOC67 X-Received: by 2002:a63:27c5:: with SMTP id n188mr16090868pgn.338.1556222036579; Thu, 25 Apr 2019 12:53:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556222036; cv=none; d=google.com; s=arc-20160816; b=InEczqX0asw9DbxldAZGJN64FpFGqpqUkhDnK8RdupmGRUSsPyPBVSSA/d+c6m3zBH qQWN2JZBrwaxdEUbS9hwgfZGGjLLn6qJLtXaGmNWYYaukUBaoDVg7hMvzWD5M1tfwZqH z8upQz7qQe9h1HWoMH8hcsKQ/FLJOx9YTfTLtBPIYCAbt9RC4nnPwrDPC2QASFqX1s77 2KR0ZZKbSoxsyvYsxXyfUe6SDroPMbU6+IF5k5wsETqEKGDzWHllUl9Tr46XBwKc9cqH hCptS+sraqtgGQ3VU7k3x+jsqol73jWXcCy0DxldOtBYz5iOHaHCf/UusXSmqZaLK+Tb 9Pww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=pqAZxopsE41ccB+0oaBL7u4YFTc9+57RlzLR8hpHiBU=; b=ZD5FA/mwGgitiY0+CDa8S+KFPUS8qTNZ//f/PQBCvoE1DHNeOeuqu551OLqs2WZGwS Cm1ICX/a+Vbw1UZJv3HEcnctj0jsGaSqXko2Gi495QxFgtAZIrc/7MrMGmw9vXpk/uQf saWfOcwTqxqcLVzRa15R5EQeSCMmVsVZRF/E10SE3QobYqyo3t5WXFJCwFQ9hFI1fiGf uAYWD05QiR7ws9rCXI53YmF09t6LUa0fOXH1oBiwpW6DdeYw421GmMklfiUUV31n9PxR 8CMprMZwkQUcfUNpweSZcXpKRikuceZNriRK4fv4s915xLggNBRU+prPqA9J3rlLFEpk u3IA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=k9NLBuC5; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id t64sm47261961pfa.86.2019.04.25.12.53.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 12:53:51 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 31/32] coresight: tmc-etf: Add support for CPU-wide trace scenarios Date: Thu, 25 Apr 2019 13:53:09 -0600 Message-Id: <20190425195310.31562-32-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190425195310.31562-1-mathieu.poirier@linaro.org> References: <20190425195310.31562-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds support for CPU-wide trace scenarios by making sure that only the sources monitoring the same process have access to a common sink. Because the sink is shared between sources, the first source to use the sink switches it on while the last one does the cleanup. Any attempt to modify the HW is overlooked for as long as more than one source is using a sink. Signed-off-by: Mathieu Poirier Tested-by: Leo Yan Tested-by: Robert Walker --- .../hwtracing/coresight/coresight-tmc-etf.c | 40 ++++++++++++++++--- 1 file changed, 35 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index 1df1f8fade71..2527b5d3b65e 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -223,6 +223,7 @@ static int tmc_enable_etf_sink_sysfs(struct coresight_device *csdev) static int tmc_enable_etf_sink_perf(struct coresight_device *csdev, void *data) { int ret = 0; + pid_t pid; unsigned long flags; struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); struct perf_output_handle *handle = data; @@ -233,18 +234,39 @@ static int tmc_enable_etf_sink_perf(struct coresight_device *csdev, void *data) if (drvdata->reading) break; /* - * In Perf mode there can be only one writer per sink. There - * is also no need to continue if the ETB/ETF is already - * operated from sysFS. + * No need to continue if the ETB/ETF is already operated + * from sysFS. */ - if (drvdata->mode != CS_MODE_DISABLED) + if (drvdata->mode == CS_MODE_SYSFS) { + ret = -EBUSY; break; + } + + /* Get a handle on the pid of the process to monitor */ + pid = task_pid_nr(handle->event->owner); + + if (drvdata->pid != -1 && drvdata->pid != pid) { + ret = -EBUSY; + break; + } ret = tmc_set_etf_buffer(csdev, handle); if (ret) break; + + /* + * No HW configuration is needed if the sink is already in + * use for this session. + */ + if (drvdata->pid == pid) { + atomic_inc(csdev->refcnt); + break; + } + ret = tmc_etb_enable_hw(drvdata); if (!ret) { + /* Associate with monitored process. */ + drvdata->pid = pid; drvdata->mode = CS_MODE_PERF; atomic_inc(csdev->refcnt); } @@ -300,6 +322,8 @@ static int tmc_disable_etf_sink(struct coresight_device *csdev) /* Complain if we (somehow) got out of sync */ WARN_ON_ONCE(drvdata->mode == CS_MODE_DISABLED); tmc_etb_disable_hw(drvdata); + /* Dissociate from monitored process. */ + drvdata->pid = -1; drvdata->mode = CS_MODE_DISABLED; spin_unlock_irqrestore(&drvdata->spinlock, flags); @@ -414,7 +438,7 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev, u32 *buf_ptr; u64 read_ptr, write_ptr; u32 status; - unsigned long offset, to_read, flags; + unsigned long offset, to_read = 0, flags; struct cs_buffers *buf = sink_config; struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); @@ -426,6 +450,11 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev, return 0; spin_lock_irqsave(&drvdata->spinlock, flags); + + /* Don't do anything if another tracer is using this sink */ + if (atomic_read(csdev->refcnt) != 1) + goto out; + CS_UNLOCK(drvdata->base); tmc_flush_and_stop(drvdata); @@ -519,6 +548,7 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev, to_read = buf->nr_pages << PAGE_SHIFT; } CS_LOCK(drvdata->base); +out: spin_unlock_irqrestore(&drvdata->spinlock, flags); return to_read; From patchwork Thu Apr 25 19:53:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 162871 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2362778jan; Thu, 25 Apr 2019 12:54:06 -0700 (PDT) X-Google-Smtp-Source: APXvYqzTESp7CG4Unx7QZCWxh3vtHD3GBbvGNg3tpC8Dcbk7NHoad7mLnI7zPHFqTl/Mx8qb6U6g X-Received: by 2002:a65:5246:: with SMTP id q6mr19524562pgp.296.1556222046791; Thu, 25 Apr 2019 12:54:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556222046; cv=none; d=google.com; s=arc-20160816; b=L7E4KGzOR2ZG9qlEMeQMgDOj9lKuLbd5n8JBT/LazXbgT4URk1C4dnJ/A2IKYNDnp2 hRajOHXsNRA+IvxPMbg0c9IH6x03DTOz842B1WZTf/Y+/p8vuercNKLJ2NvJCDAIH8cj xzLT7mQliboa7f2lo7cPTwZgkrLqRIuKyd2iQX6px+1KYCTrOMUu6dPX3sQpPx6QjnlB hM79vWgtEs/mY5RvmYJ7KVBfxlDtks5oReB7pkwRM0lh4fThOkWLcuIRlSOuujMz3FtV aw0OPKa3aYrJqq0mhe6RdpmcSVGgDalP7xZ/4joV892XEKy6a8JSSQogFbXBYz82hHay 78Ng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=jDPyESeyA1XWInOj96ARwqWgZicZRGHOAy5iyflwVzQ=; b=EVFYliwuEyS2Ne9Ndtk7NPoL8RfT4tDInKtk2AmIwyzeibcBBo2Sphy48dxiwceyLO gHSGRo6Qul3z2/0k83v6mLGoAMgdR78JtUEYE4DUZQLoYtq1gW4t00n2NMsXG3C3mBMI F+0EcOe2mA3+fXjlTorsRU0r68hDNB+HAA3f7cyta/TvOqqQYQ7A9XJrbargp80iilqX qOrgaxOhppw8XGIEvXwWXVB5gDY12mvnGpuOg4RSrn29GB7d+c/Ng2ExprY/mZlol181 nZZjlJ1uPeNfwFhzytjAwNge4S9hmZw85hTBLY2drgrZrOKkKgLa6G08/WBlxt+PTx6e RaTg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=e65dAhnT; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id t64sm47261961pfa.86.2019.04.25.12.53.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 12:53:52 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 32/32] coresight: etb10: Add support for CPU-wide trace scenarios Date: Thu, 25 Apr 2019 13:53:10 -0600 Message-Id: <20190425195310.31562-33-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190425195310.31562-1-mathieu.poirier@linaro.org> References: <20190425195310.31562-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds support for CPU-wide trace scenarios by making sure that only the sources monitoring the same process have access to a common sink. Because the sink is shared between sources, the first source to use the sink switches it on while the last one does the cleanup. Any attempt to modify the HW is overlooked for as long as more than one source is using a sink. Signed-off-by: Mathieu Poirier Tested-by: Leo Yan Tested-by: Robert Walker --- drivers/hwtracing/coresight/coresight-etb10.c | 43 +++++++++++++++++-- 1 file changed, 39 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index eeae375c7aed..4ee4c80a4354 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -72,6 +72,8 @@ * @miscdev: specifics to handle "/dev/xyz.etb" entry. * @spinlock: only one at a time pls. * @reading: synchronise user space access to etb buffer. + * @pid: Process ID of the process being monitored by the session + * that is using this component. * @buf: area of memory where ETB buffer content gets sent. * @mode: this ETB is being used. * @buffer_depth: size of @buf. @@ -85,6 +87,7 @@ struct etb_drvdata { struct miscdevice miscdev; spinlock_t spinlock; local_t reading; + pid_t pid; u8 *buf; u32 mode; u32 buffer_depth; @@ -169,28 +172,49 @@ static int etb_enable_sysfs(struct coresight_device *csdev) static int etb_enable_perf(struct coresight_device *csdev, void *data) { int ret = 0; + pid_t pid; unsigned long flags; struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + struct perf_output_handle *handle = data; spin_lock_irqsave(&drvdata->spinlock, flags); - /* No need to continue if the component is already in use. */ - if (drvdata->mode != CS_MODE_DISABLED) { + /* No need to continue if the component is already in used by sysFS. */ + if (drvdata->mode == CS_MODE_SYSFS) { + ret = -EBUSY; + goto out; + } + + /* Get a handle on the pid of the process to monitor */ + pid = task_pid_nr(handle->event->owner); + + if (drvdata->pid != -1 && drvdata->pid != pid) { ret = -EBUSY; goto out; } + /* + * No HW configuration is needed if the sink is already in + * use for this session. + */ + if (drvdata->pid == pid) { + atomic_inc(csdev->refcnt); + goto out; + } + /* * We don't have an internal state to clean up if we fail to setup * the perf buffer. So we can perform the step before we turn the * ETB on and leave without cleaning up. */ - ret = etb_set_buffer(csdev, (struct perf_output_handle *)data); + ret = etb_set_buffer(csdev, handle); if (ret) goto out; ret = etb_enable_hw(drvdata); if (!ret) { + /* Associate with monitored process. */ + drvdata->pid = pid; drvdata->mode = CS_MODE_PERF; atomic_inc(csdev->refcnt); } @@ -336,6 +360,8 @@ static int etb_disable(struct coresight_device *csdev) /* Complain if we (somehow) got out of sync */ WARN_ON_ONCE(drvdata->mode == CS_MODE_DISABLED); etb_disable_hw(drvdata); + /* Dissociate from monitored process. */ + drvdata->pid = -1; drvdata->mode = CS_MODE_DISABLED; spin_unlock_irqrestore(&drvdata->spinlock, flags); @@ -406,7 +432,7 @@ static unsigned long etb_update_buffer(struct coresight_device *csdev, const u32 *barrier; u32 read_ptr, write_ptr, capacity; u32 status, read_data; - unsigned long offset, to_read, flags; + unsigned long offset, to_read = 0, flags; struct cs_buffers *buf = sink_config; struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); @@ -416,6 +442,11 @@ static unsigned long etb_update_buffer(struct coresight_device *csdev, capacity = drvdata->buffer_depth * ETB_FRAME_SIZE_WORDS; spin_lock_irqsave(&drvdata->spinlock, flags); + + /* Don't do anything if another tracer is using this sink */ + if (atomic_read(csdev->refcnt) != 1) + goto out; + __etb_disable_hw(drvdata); CS_UNLOCK(drvdata->base); @@ -526,6 +557,7 @@ static unsigned long etb_update_buffer(struct coresight_device *csdev, } __etb_enable_hw(drvdata); CS_LOCK(drvdata->base); +out: spin_unlock_irqrestore(&drvdata->spinlock, flags); return to_read; @@ -733,6 +765,9 @@ static int etb_probe(struct amba_device *adev, const struct amba_id *id) if (!drvdata->buf) return -ENOMEM; + /* This device is not associated with a session */ + drvdata->pid = -1; + desc.type = CORESIGHT_DEV_TYPE_SINK; desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; desc.ops = &etb_cs_ops;