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[97.113.179.147]) by smtp.gmail.com with ESMTPSA id 128sm26439908pgb.47.2019.04.25.10.26.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 10:26:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 25 Apr 2019 10:26:35 -0700 Message-Id: <20190425172636.11128-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190425172636.11128-1-richard.henderson@linaro.org> References: <20190425172636.11128-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52a Subject: [Qemu-devel] [PATCH 1/2] fixup! target/riscv: Name the argument sets for all of insn32 formats X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@sifive.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" --- target/riscv/translate.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) -- 2.17.1 Reviewed-by: Alistair Francis diff --git a/target/riscv/translate.c b/target/riscv/translate.c index d1f599a92d..009c146e8f 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -713,12 +713,19 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, * initially declared by the 32-bit decoder, which results in duplicate * declaration warnings. Suppress them. */ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wredundant-decls" +#ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE +# pragma GCC diagnostic push +# pragma GCC diagnostic ignored "-Wredundant-decls" +# ifdef __clang__ +# pragma GCC diagnostic ignored "-Wtypedef-redefinition" +# endif +#endif #include "decode_insn16.inc.c" -#pragma GCC diagnostic pop +#ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE +# pragma GCC diagnostic pop +#endif static void decode_opc(DisasContext *ctx) { From patchwork Thu Apr 25 17:26:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 162854 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp2213872jan; Thu, 25 Apr 2019 10:27:02 -0700 (PDT) X-Google-Smtp-Source: APXvYqz/ILwTX4Qk5OKdzcRAI0O2AMO1IaN/zf1OrgsRC6RmfGvDiSUKCLRQIenU9BtbVpw1Jh44 X-Received: by 2002:a7b:c3ce:: with SMTP id t14mr635050wmj.59.1556213222119; Thu, 25 Apr 2019 10:27:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556213222; cv=none; d=google.com; s=arc-20160816; b=q1mhZvS8kihdbsOEo7XPgS8qQqmRqIMFLxjyBPZyDiuIpMV2yUnftcbuneCsw3mgig BQ+v2wUkkkG8aT5ar/pOcT9zbaDAHzdVWx0KGcVq8DBig6Yg5Z/v6jE2JfTFQPVY7OPc eGugsOy3VRtZwmYIeG0HSE65fs/H8t9E9jfOXD95qaLLaJ9kOidfPmna1yLeCiLLUXtR 2U47SC3dP48ly2KB3q9cIdxYOTNp3S5dOdusnS+39dtyEbD3iR0AgGosPs72wVs6kBTc WH/Z1WdLSt5yLQWtdMpr0Ea2QbGYe9SJ5ahcaa8W4oS7Pil7jn6RI7ZVeZSFIqo2itA1 YkHg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=eGOk2C15hrcswvUDv6q+SuerrWLxsrIzu4DTJF3iqAI=; b=WvkxeSDHOHuz75TIYecvHMuFaaBxVOnQSIhyulWp2e0RLwvMJC5l/FhVsnxPVPQmfr PYfhMvOgCs7T/TxEGnK2upLwN3f4WxozQy2k6Ge9IyVCsUgCuqqsprHYy5yf3s8+iJGz sKBvQhSsGWt0y9Exfc24NANhTcHUVwZG4y09hcSnAt0+BR9DXjdAOrG9jRKK9vzhITTm yYDL7jIRurIAN3WNGjghSfjayI4918HB6O9gveZyX9cOo3TaYZS/ULifWY1eEDO5/kLl 0Pb/A85HsIfkPk63cqHmDIElUY92qgHZ2R/LLnC93mrcSkVMstwseAQty1j+Tq048V1R gVhw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=rBGrA1Ij; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.179.147]) by smtp.gmail.com with ESMTPSA id 128sm26439908pgb.47.2019.04.25.10.26.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 10:26:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 25 Apr 2019 10:26:36 -0700 Message-Id: <20190425172636.11128-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190425172636.11128-1-richard.henderson@linaro.org> References: <20190425172636.11128-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH 2/2] target/riscv: Add checks for several RVC reserved operands X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@sifive.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" C.ADDI16SP, C.LWSP, C.JR, C.ADDIW, C.LDSP all have reserved operands that were not diagnosed. Signed-off-by: Richard Henderson --- target/riscv/insn16-64.decode | 10 ++++++++-- target/riscv/insn16.decode | 7 ++++++- 2 files changed, 14 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode index 055859d29f..672e1e916f 100644 --- a/target/riscv/insn16-64.decode +++ b/target/riscv/insn16-64.decode @@ -21,10 +21,16 @@ ld 011 ... ... .. ... 00 @cl_d sd 111 ... ... .. ... 00 @cs_d # *** RV64C Standard Extension (Quadrant 1) *** -addiw 001 . ..... ..... 01 @ci +{ + illegal 001 - 00000 ----- 01 # c.addiw, RES rd=0 + addiw 001 . ..... ..... 01 @ci +} subw 100 1 11 ... 00 ... 01 @cs_2 addw 100 1 11 ... 01 ... 01 @cs_2 # *** RV64C Standard Extension (Quadrant 2) *** -ld 011 . ..... ..... 10 @c_ldsp +{ + illegal 011 - 00000 ----- 10 # c.ldsp, RES rd=0 + ld 011 . ..... ..... 10 @c_ldsp +} sd 111 . ..... ..... 10 @c_sdsp diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index 433c0e8c68..c06073ee72 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -96,6 +96,7 @@ sw 110 ... ... .. ... 00 @cs_w addi 000 . ..... ..... 01 @ci addi 010 . ..... ..... 01 @c_li { + illegal 011 0 ----- 00000 01 # c.addi16sp, RES nzimm=0 addi 011 . 00010 ..... 01 @c_addi16sp lui 011 . ..... ..... 01 @c_lui } @@ -113,8 +114,12 @@ bne 111 ... ... ..... 01 @cb_z # *** RV32/64C Standard Extension (Quadrant 2) *** slli 000 . ..... ..... 10 @c_shift2 fld 001 . ..... ..... 10 @c_ldsp -lw 010 . ..... ..... 10 @c_lwsp { + illegal 010 - 00000 ----- 10 # c.lwsp, RES rd=0 + lw 010 . ..... ..... 10 @c_lwsp +} +{ + illegal 100 0 00000 00000 10 # c.jr, RES rs1=0 jalr 100 0 ..... 00000 10 @c_jalr rd=0 # C.JR addi 100 0 ..... ..... 10 @c_mv }