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[209.51.188.17]) by mx.google.com with ESMTPS id j185-20020a3787c2000000b00704d8dcff6asi2664123qkd.437.2023.02.03.13.18.19 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Feb 2023 13:18:20 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YPv6OCOF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pO3Qb-0000KN-Tw; Fri, 03 Feb 2023 16:17:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pO3QE-0000EK-3u for qemu-devel@nongnu.org; Fri, 03 Feb 2023 16:16:45 -0500 Received: from mail-ej1-x636.google.com ([2a00:1450:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pO3QC-0006Ac-2H for qemu-devel@nongnu.org; Fri, 03 Feb 2023 16:16:37 -0500 Received: by mail-ej1-x636.google.com with SMTP id lu11so18899827ejb.3 for ; Fri, 03 Feb 2023 13:16:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hTCwlrhJCIZguZaGgCCFrwh716fRCo2CcQ01yatwjNM=; b=YPv6OCOFNmSqb9r3qVkITNmE1Qe3UrWL+M6ecJq0nPLVjhWsyRVlxRvpqMr/cqJHfl Lwee2uTqRg0JcPCDYAp9X1JgPx0Ez5L2qL5uUDt3nb90wQk5q/9ZvIom27mItRQ8A3Qn YNI+CgRoQL53Ej2UFnF+CttqMPbmKJPK4zVPwMlIEmHCf0+HfNSv13QQeqY2JxGkPECT W81zAALLn5fTjSyXY6R3qF8UD3EZ40XFwuhFv4M9ISUWVMF3GHWFXIkxnVkd2OZ5yMtH 4ILfusxe3w+ftE0h6qeor+eKwQlA1TU/LJRL7lscySQL294LkuxZjObV4wm7In9eKEJU TL6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hTCwlrhJCIZguZaGgCCFrwh716fRCo2CcQ01yatwjNM=; b=wFzVsDAkc8djXWN8BNIaOUcfdiRcaEq6mU+SDBigF54xnGpXT/QX3kHNtETsUbonT2 h1kswnR2f6n/1eO7K4X2I15AmSy8la6nMcrTAQLTihMbfy4Hkv3QhGE8VDyMmW86Y4Wa HHFg3BHRdH7FGebT0nPrZVlifhd10Z8F3tszTB5dhjXbJyRYvCshBA2S/CrGcjcK7aAQ 8HxkRcKC+lbnuG/kqexrnD8nuu2DU2am2hARjdg2uj186md+xjZcHOhqzVt/rZ616R3z d87fIv6AsNnclbVVj5dH5Cm+rcaaTP7gIJDVd/bAHwGE71VopOk5MdcHQzDvUgohuitl D+BA== X-Gm-Message-State: AO0yUKXeTUvqkdSfp6EN3D5aocvu7ENaOYOlAPF3vaftOpyhwyWllR/Y uMn1PNS50IkLtWatxjjcxk0iP3yPsTvbVpV2 X-Received: by 2002:a17:906:8e16:b0:88b:f26d:7b25 with SMTP id rx22-20020a1709068e1600b0088bf26d7b25mr3024678ejc.28.1675458994230; Fri, 03 Feb 2023 13:16:34 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id u11-20020a170906408b00b0088a694749f7sm1889419ejj.4.2023.02.03.13.16.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 03 Feb 2023 13:16:33 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: BALATON Zoltan , Mark Cave-Ayland , qemu-ppc@nongnu.org, =?utf-8?q?Herv=C3=A9_Poussineau?= , =?utf-8?q?C=C3=A9?= =?utf-8?q?dric_Le_Goater?= , Daniel Henrique Barboza , Markus Armbruster , David Gibson , Greg Kurz , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 1/5] hw/misc/macio: Set QDev properties using QDev API Date: Fri, 3 Feb 2023 22:16:19 +0100 Message-Id: <20230203211623.50930-2-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230203211623.50930-1-philmd@linaro.org> References: <20230203211623.50930-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=philmd@linaro.org; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org No need to use the low-level QOM API when an object inherits from QDev. Directly use the QDev API to set its properties. All calls use errp=&error_abort, so converting to the QDev API is a no-op (QDev API always uses &error_abort). Signed-off-by: Philippe Mathieu-Daudé --- hw/misc/macio/macio.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/hw/misc/macio/macio.c b/hw/misc/macio/macio.c index 08dbdd7fc0..66393280f1 100644 --- a/hw/misc/macio/macio.c +++ b/hw/misc/macio/macio.c @@ -128,8 +128,7 @@ static void macio_realize_ide(MacIOState *s, MACIOIDEState *ide, sysbus_connect_irq(sysbus_dev, 0, irq0); sysbus_connect_irq(sysbus_dev, 1, irq1); qdev_prop_set_uint32(DEVICE(ide), "channel", dmaid); - object_property_set_link(OBJECT(ide), "dbdma", OBJECT(&s->dbdma), - &error_abort); + qdev_prop_set_link(DEVICE(ide), "dbdma", OBJECT(&s->dbdma)); macio_ide_register_dma(ide); qdev_realize(DEVICE(ide), BUS(&s->macio_bus), errp); @@ -336,8 +335,7 @@ static void macio_newworld_realize(PCIDevice *d, Error **errp) /* PMU */ object_initialize_child(OBJECT(s), "pmu", &s->pmu, TYPE_VIA_PMU); - object_property_set_link(OBJECT(&s->pmu), "gpio", OBJECT(sysbus_dev), - &error_abort); + qdev_prop_set_link(DEVICE(&s->pmu), "gpio", OBJECT(sysbus_dev)); qdev_prop_set_bit(DEVICE(&s->pmu), "has-adb", ns->has_adb); if (!qdev_realize(DEVICE(&s->pmu), BUS(&s->macio_bus), errp)) { return; From patchwork Fri Feb 3 21:16:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 650110 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp1056916pva; Fri, 3 Feb 2023 13:17:37 -0800 (PST) X-Google-Smtp-Source: AK7set+FJfDs/920xZCbvSIEVcrutG330Fy30w3dCT9kx0mJ8iBfUbcJD4PBDMghLvTeGuDthlgG X-Received: by 2002:a05:6214:5442:b0:537:6bc5:6c3b with SMTP id kz2-20020a056214544200b005376bc56c3bmr20117242qvb.30.1675459056900; Fri, 03 Feb 2023 13:17:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675459056; cv=none; d=google.com; s=arc-20160816; b=QoonO2ZTxrwsoF9ZR6Q4dQa2ZjlWiOT37ONzR05UhHKGfpTU2zi/maWrBDBOYmGCLQ 4MffXpwiKiQGc9MoKZBStzNpOyALsp+EVRQAjUS5nLL+mjuBZ0spXXv6x2WgN47T4gpY Crlbpk0oPC6XHbTQyTfDioN2hayEjUFoMNLVwb6rNRW6ghryRyeG+hPRQPVH6cFK/iyH 86C3DvLcvKsGPr2iDodv/Moti/X3iCTizuraSXOgEIC07XJkSlk+M5kTIRO6WjMKXt0t lhV6iPOSArxePHkBY5FK94eglZAZBIDnZYqHkyCqdNjpAnfLZiYfvwf+xSG+Hn+OvCMU sZAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=OCe5fq1LEdCOCuZfIaOgrR1H22bGU2FTnkvkdNk/zEU=; b=fnxY9OhZOiCgERrk8127CIaMU9o4/NewDYgxA4wA5U2Dxvncr5IdJKBj0aiIQlYN6O zUsXn1tPez3QXNleBjHJEoHSNBCmJ/IMxQoitjUOKuNK47CZsoFZdOMKlmlWSL9ygip5 E6I5MNjri8drh5caMSV6mzaM8ZACwYbynR4+DhC4r9KIUsi1ZO9eGEVylSSfjz6dy+Yl 6MXSAo8IkIeB1cGlA/+yIsWWGb3AJFuZJCne5tcW00RqKC/iy4v4KhVMj+W2/D0w53Hl 0kKjs1nTrAlH4U5xnqm4KND2/RHv7RwGOXcB6/7b3eqrRnvrRo6k6KQgIZ8f2uqfaSVn Q1fA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sga5CwGk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Directly use the QDev API to set its properties. All calls use either errp=&error_fatal or NULL, so converting to the QDev API is almost a no-op (QDev API always uses &error_abort). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza --- hw/pci-host/raven.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c index cdfb62ac2e..2c842d2146 100644 --- a/hw/pci-host/raven.c +++ b/hw/pci-host/raven.c @@ -246,8 +246,7 @@ static void raven_pcihost_realizefn(DeviceState *d, Error **errp) /* According to PReP specification section 6.1.6 "System Interrupt * Assignments", all PCI interrupts are routed via IRQ 15 */ s->or_irq = OR_IRQ(object_new(TYPE_OR_IRQ)); - object_property_set_int(OBJECT(s->or_irq), "num-lines", PCI_NUM_PINS, - &error_fatal); + qdev_prop_set_uint16(DEVICE(s->or_irq), "num-lines", PCI_NUM_PINS); qdev_realize(DEVICE(s->or_irq), NULL, &error_fatal); sysbus_init_irq(dev, &s->or_irq->out_irq); @@ -319,8 +318,7 @@ static void raven_pcihost_initfn(Object *obj) object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_RAVEN_PCI_DEVICE); pci_dev = DEVICE(&s->pci_dev); - object_property_set_int(OBJECT(&s->pci_dev), "addr", PCI_DEVFN(0, 0), - NULL); + qdev_prop_set_int32(pci_dev, "addr", PCI_DEVFN(0, 0)); qdev_prop_set_bit(pci_dev, "multifunction", false); } From patchwork Fri Feb 3 21:16:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 650109 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp1056901pva; Fri, 3 Feb 2023 13:17:35 -0800 (PST) X-Google-Smtp-Source: AK7set8o1opSdZ6Szv+tc30bDVkBVEtBoBAIiN5tpPD1iU7+1gipw69Q+IGIXd1jedGgDKQITiZZ X-Received: by 2002:a05:622a:1d5:b0:3b8:5aa8:7d7a with SMTP id t21-20020a05622a01d500b003b85aa87d7amr20911239qtw.68.1675459055191; Fri, 03 Feb 2023 13:17:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675459055; cv=none; d=google.com; s=arc-20160816; b=wF9qeD/o9mvX/0D9EYX2qfUFYAjoRBNSGdUQV8NlpSoBWf/8nzLMKqFpDUf3zDjatL 3yJq/jPWAeo3awRMpjUGl0lDPLF4qwmS881mxmfO57W1O1AcWXttuu+Czd0bJnB0AjJj w6Q/k6PMJ/9Ba1gAjSe5QR7g3kq3ruuJC9cq+c2bT6IpO6/5AhSL8ewNxJ5QN8jm1Jov xUEZ8Nfn4LkpR/Grv0JVBKYz5z0S/5fTsNSwr3DxH3NtlhCVX5AcPUj1pwRtOi0qrrr1 ibnQId3ESeYGGvvfk7+Z7TfQi4CJUCz2OIve36ZciqnNuG5nA0qNpRQeXZpI2KlMK8Vs zn7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=9y7uNtLNirw+zlKhCFqLJUYA0wqOcSYOS5zDaJZAL3I=; b=0vdc/IYrksb5Y7/7grRV6HxOfhbev7QaClVpvbTj+Nf2bgU1dco2rtr5sZGSF1NHQz qrW9ZjpCl4l34Up6MndpGwyaT9J7L72d6HibVzzrlHKSnr4RgykICnbSxLfTKDl03+zq zkG3ii4ct6XDPcBPN0vXIhqSNWzJQBqBCqWP832ezkl4fMgSnoOydR0WqR017fca0RyZ 4QlVETNgQsKIL6GGQRj+zLsQG9O/GUreAiCtR6pkTqi25UThOs3KpG5ZWCU25pbBOC5C N74FMdGtmXPmz8wg/fCSQ3MXiZ0L+3fUsqOrBQV1sxf0FEGfeX+AH6RNaH8QYAJ15mvZ jgiw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fp5xuNSO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Directly use the QDev API to set its properties. All calls use either errp=&error_abort or &error_fatal, so converting to the QDev API is almost a no-op (QDev API always uses &error_abort). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: BALATON Zoltan Reviewed-by: Daniel Henrique Barboza --- hw/ppc/e500.c | 3 +-- hw/ppc/ppc405_boards.c | 6 ++---- hw/ppc/ppc405_uc.c | 6 +++--- hw/ppc/ppc440_bamboo.c | 3 +-- hw/ppc/ppc4xx_devs.c | 2 +- hw/ppc/sam460ex.c | 5 ++--- 6 files changed, 10 insertions(+), 15 deletions(-) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 9fa1f8e6cf..083961cef5 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -943,8 +943,7 @@ void ppce500_init(MachineState *machine) * Secondary CPU starts in halted state for now. Needs to change * when implementing non-kernel boot. */ - object_property_set_bool(OBJECT(cs), "start-powered-off", i != 0, - &error_fatal); + qdev_prop_set_bit(DEVICE(cs), "start-powered-off", i != 0); qdev_realize_and_unref(DEVICE(cs), NULL, &error_fatal); if (!firstenv) { diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index 4092ebc1ab..67eb9ac139 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -276,10 +276,8 @@ static void ppc405_init(MachineState *machine) object_initialize_child(OBJECT(machine), "soc", &ppc405->soc, TYPE_PPC405_SOC); - object_property_set_link(OBJECT(&ppc405->soc), "dram", - OBJECT(machine->ram), &error_abort); - object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333, - &error_abort); + qdev_prop_set_link(DEVICE(&ppc405->soc), "dram", OBJECT(machine->ram)); + qdev_prop_set_uint32(DEVICE(&ppc405->soc), "sys-clk", 33333333); qdev_realize(DEVICE(&ppc405->soc), NULL, &error_fatal); /* allocate and load BIOS */ diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index c973cfb04e..b7d5cfc548 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -1080,7 +1080,7 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp) * We use the 440 DDR SDRAM controller which has more regs and features * but it's compatible enough for now */ - object_property_set_int(OBJECT(&s->sdram), "nbanks", 2, &error_abort); + qdev_prop_set_uint32(DEVICE(&s->sdram), "nbanks", 2); if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->sdram), &s->cpu, errp)) { return; } @@ -1147,8 +1147,8 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp) } /* MAL */ - object_property_set_int(OBJECT(&s->mal), "txc-num", 4, &error_abort); - object_property_set_int(OBJECT(&s->mal), "rxc-num", 2, &error_abort); + qdev_prop_set_uint8(DEVICE(&s->mal), "txc-num", 4); + qdev_prop_set_uint8(DEVICE(&s->mal), "rxc-num", 2); if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->mal), &s->cpu, errp)) { return; } diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c index 81d71adf34..3612471990 100644 --- a/hw/ppc/ppc440_bamboo.c +++ b/hw/ppc/ppc440_bamboo.c @@ -200,8 +200,7 @@ static void bamboo_init(MachineState *machine) /* SDRAM controller */ dev = qdev_new(TYPE_PPC4xx_SDRAM_DDR); - object_property_set_link(OBJECT(dev), "dram", OBJECT(machine->ram), - &error_abort); + qdev_prop_set_link(dev, "dram", OBJECT(machine->ram)); ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal); object_unref(OBJECT(dev)); /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */ diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index c1d111465d..1848cf5d3c 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -535,7 +535,7 @@ void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque, bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu, Error **errp) { - object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort); + qdev_prop_set_link(DEVICE(dev), "cpu", OBJECT(cpu)); return sysbus_realize(SYS_BUS_DEVICE(dev), errp); } diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index cf065aae0e..cb828b6d4d 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -345,13 +345,12 @@ static void sam460ex_init(MachineState *machine) exit(1); } dev = qdev_new(TYPE_PPC4xx_SDRAM_DDR2); - object_property_set_link(OBJECT(dev), "dram", OBJECT(machine->ram), - &error_abort); + qdev_prop_set_link(dev, "dram", OBJECT(machine->ram)); /* * Put all RAM on first bank because board has one slot * and firmware only checks that */ - object_property_set_int(OBJECT(dev), "nbanks", 1, &error_abort); + qdev_prop_set_uint32(dev, "nbanks", 1); ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal); object_unref(OBJECT(dev)); /* FIXME: does 460EX have ECC interrupts? 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Directly use the QDev API to set its properties. All calls use either errp=&error_abort or &error_fatal, so converting to the QDev API is almost a no-op (QDev API always uses &error_abort). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza Reviewed-by: Cédric Le Goater --- hw/intc/spapr_xive.c | 11 ++++------- hw/intc/xics.c | 4 ++-- hw/intc/xive.c | 4 ++-- hw/ppc/spapr_irq.c | 8 +++----- 4 files changed, 11 insertions(+), 16 deletions(-) diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index dc641cc604..213c4cac44 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -310,9 +310,8 @@ static void spapr_xive_realize(DeviceState *dev, Error **errp) /* * Initialize the internal sources, for IPIs and virtual devices. */ - object_property_set_int(OBJECT(xsrc), "nr-irqs", xive->nr_irqs, - &error_fatal); - object_property_set_link(OBJECT(xsrc), "xive", OBJECT(xive), &error_abort); + qdev_prop_set_uint32(DEVICE(xsrc), "nr-irqs", xive->nr_irqs); + qdev_prop_set_link(DEVICE(xsrc), "xive", OBJECT(xive)); if (!qdev_realize(DEVICE(xsrc), NULL, errp)) { return; } @@ -321,10 +320,8 @@ static void spapr_xive_realize(DeviceState *dev, Error **errp) /* * Initialize the END ESB source */ - object_property_set_int(OBJECT(end_xsrc), "nr-ends", xive->nr_irqs, - &error_fatal); - object_property_set_link(OBJECT(end_xsrc), "xive", OBJECT(xive), - &error_abort); + qdev_prop_set_uint32(DEVICE(end_xsrc), "nr-ends", xive->nr_irqs); + qdev_prop_set_link(DEVICE(end_xsrc), "xive", OBJECT(xive)); if (!qdev_realize(DEVICE(end_xsrc), NULL, errp)) { return; } diff --git a/hw/intc/xics.c b/hw/intc/xics.c index c7f8abd71e..2fd1a15153 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -382,8 +382,8 @@ Object *icp_create(Object *cpu, const char *type, XICSFabric *xi, Error **errp) obj = object_new(type); object_property_add_child(cpu, type, obj); object_unref(obj); - object_property_set_link(obj, ICP_PROP_XICS, OBJECT(xi), &error_abort); - object_property_set_link(obj, ICP_PROP_CPU, cpu, &error_abort); + qdev_prop_set_link(DEVICE(obj), ICP_PROP_XICS, OBJECT(xi)); + qdev_prop_set_link(DEVICE(obj), ICP_PROP_CPU, cpu); if (!qdev_realize(DEVICE(obj), NULL, errp)) { object_unparent(obj); obj = NULL; diff --git a/hw/intc/xive.c b/hw/intc/xive.c index a986b96843..0e34035bc6 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -799,8 +799,8 @@ Object *xive_tctx_create(Object *cpu, XivePresenter *xptr, Error **errp) obj = object_new(TYPE_XIVE_TCTX); object_property_add_child(cpu, TYPE_XIVE_TCTX, obj); object_unref(obj); - object_property_set_link(obj, "cpu", cpu, &error_abort); - object_property_set_link(obj, "presenter", OBJECT(xptr), &error_abort); + qdev_prop_set_link(DEVICE(obj), "cpu", cpu); + qdev_prop_set_link(DEVICE(obj), "presenter", OBJECT(xptr)); if (!qdev_realize(DEVICE(obj), NULL, errp)) { object_unparent(obj); return NULL; diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index a0d1e1298e..283769c074 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -313,9 +313,8 @@ void spapr_irq_init(SpaprMachineState *spapr, Error **errp) obj = object_new(TYPE_ICS_SPAPR); object_property_add_child(OBJECT(spapr), "ics", obj); - object_property_set_link(obj, ICS_PROP_XICS, OBJECT(spapr), - &error_abort); - object_property_set_int(obj, "nr-irqs", smc->nr_xirqs, &error_abort); + qdev_prop_set_link(DEVICE(obj), ICS_PROP_XICS, OBJECT(spapr)); + qdev_prop_set_uint32(DEVICE(obj), "nr-irqs", smc->nr_xirqs); if (!qdev_realize(DEVICE(obj), NULL, errp)) { return; } @@ -335,8 +334,7 @@ void spapr_irq_init(SpaprMachineState *spapr, Error **errp) * priority */ qdev_prop_set_uint32(dev, "nr-ends", nr_servers << 3); - object_property_set_link(OBJECT(dev), "xive-fabric", OBJECT(spapr), - &error_abort); + qdev_prop_set_link(dev, "xive-fabric", OBJECT(spapr)); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); spapr->xive = SPAPR_XIVE(dev); From patchwork Fri Feb 3 21:16:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 650112 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp1057245pva; Fri, 3 Feb 2023 13:18:20 -0800 (PST) X-Google-Smtp-Source: AK7set+gexxplgClQ3APhDFY5nmFYZlbfrWUxelARshepG0ke4r/yLVeVJi/MvpKRgIXg+rMrKdC X-Received: by 2002:a05:6214:3009:b0:537:6cec:98e3 with SMTP id ke9-20020a056214300900b005376cec98e3mr22915062qvb.31.1675459100818; Fri, 03 Feb 2023 13:18:20 -0800 (PST) ARC-Seal: i=1; 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Directly use the QDev API to set its properties. One call in pnv_psi_power8_realize() propagate the Error* argument: if (!object_property_set_int(OBJECT(ics), "nr-irqs", PSI_NUM_INTERRUPTS, errp)) { return; } TYPE_ICS "nr-irqs" is declared in ics_properties[], itself always registered in ics_class_init(); so converting this errp to &error_abort is safe. All other calls use either errp=&error_abort or &error_fatal, so converting to the QDev API is almost a no-op (QDev API always uses &error_abort). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza Reviewed-by: Cédric Le Goater --- hw/intc/pnv_xive.c | 11 ++++------ hw/intc/pnv_xive2.c | 15 +++++--------- hw/pci-host/pnv_phb3.c | 9 +++------ hw/pci-host/pnv_phb4.c | 4 ++-- hw/pci-host/pnv_phb4_pec.c | 10 +++------- hw/ppc/pnv.c | 41 ++++++++++++++++---------------------- hw/ppc/pnv_psi.c | 10 +++------- 7 files changed, 37 insertions(+), 63 deletions(-) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 622f9d28b7..ccc1ea5380 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -1857,17 +1857,14 @@ static void pnv_xive_realize(DeviceState *dev, Error **errp) * resized dynamically when the controller is configured by the FW * to limit accesses to resources not provisioned. */ - object_property_set_int(OBJECT(xsrc), "nr-irqs", PNV_XIVE_NR_IRQS, - &error_fatal); - object_property_set_link(OBJECT(xsrc), "xive", OBJECT(xive), &error_abort); + qdev_prop_set_uint32(DEVICE(xsrc), "nr-irqs", PNV_XIVE_NR_IRQS); + qdev_prop_set_link(DEVICE(xsrc), "xive", OBJECT(xive)); if (!qdev_realize(DEVICE(xsrc), NULL, errp)) { return; } - object_property_set_int(OBJECT(end_xsrc), "nr-ends", PNV_XIVE_NR_ENDS, - &error_fatal); - object_property_set_link(OBJECT(end_xsrc), "xive", OBJECT(xive), - &error_abort); + qdev_prop_set_uint32(DEVICE(end_xsrc), "nr-ends", PNV_XIVE_NR_ENDS); + qdev_prop_set_link(DEVICE(end_xsrc), "xive", OBJECT(xive)); if (!qdev_realize(DEVICE(end_xsrc), NULL, errp)) { return; } diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c index 7176d70234..d7695f65e7 100644 --- a/hw/intc/pnv_xive2.c +++ b/hw/intc/pnv_xive2.c @@ -1821,22 +1821,17 @@ static void pnv_xive2_realize(DeviceState *dev, Error **errp) * resized dynamically when the controller is configured by the FW * to limit accesses to resources not provisioned. */ - object_property_set_int(OBJECT(xsrc), "flags", XIVE_SRC_STORE_EOI, - &error_fatal); - object_property_set_int(OBJECT(xsrc), "nr-irqs", PNV_XIVE2_NR_IRQS, - &error_fatal); - object_property_set_link(OBJECT(xsrc), "xive", OBJECT(xive), - &error_fatal); + qdev_prop_set_uint64(DEVICE(xsrc), "flags", XIVE_SRC_STORE_EOI); + qdev_prop_set_uint32(DEVICE(xsrc), "nr-irqs", PNV_XIVE2_NR_IRQS); + qdev_prop_set_link(DEVICE(xsrc), "xive", OBJECT(xive)); qdev_realize(DEVICE(xsrc), NULL, &local_err); if (local_err) { error_propagate(errp, local_err); return; } - object_property_set_int(OBJECT(end_xsrc), "nr-ends", PNV_XIVE2_NR_ENDS, - &error_fatal); - object_property_set_link(OBJECT(end_xsrc), "xive", OBJECT(xive), - &error_abort); + qdev_prop_set_uint32(DEVICE(end_xsrc), "nr-ends", PNV_XIVE2_NR_ENDS); + qdev_prop_set_link(DEVICE(end_xsrc), "xive", OBJECT(xive)); qdev_realize(DEVICE(end_xsrc), NULL, &local_err); if (local_err) { error_propagate(errp, local_err); diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c index 7a21497cf8..6da9053ffa 100644 --- a/hw/pci-host/pnv_phb3.c +++ b/hw/pci-host/pnv_phb3.c @@ -1029,8 +1029,7 @@ static void pnv_phb3_realize(DeviceState *dev, Error **errp) /* LSI sources */ object_property_set_link(OBJECT(&phb->lsis), "xics", OBJECT(pnv), &error_abort); - object_property_set_int(OBJECT(&phb->lsis), "nr-irqs", PNV_PHB3_NUM_LSI, - &error_abort); + qdev_prop_set_uint32(DEVICE(&phb->lsis), "nr-irqs", PNV_PHB3_NUM_LSI); if (!qdev_realize(DEVICE(&phb->lsis), NULL, errp)) { return; } @@ -1046,15 +1045,13 @@ static void pnv_phb3_realize(DeviceState *dev, Error **errp) &error_abort); object_property_set_link(OBJECT(&phb->msis), "xics", OBJECT(pnv), &error_abort); - object_property_set_int(OBJECT(&phb->msis), "nr-irqs", PHB3_MAX_MSI, - &error_abort); + qdev_prop_set_uint32(DEVICE(&phb->msis), "nr-irqs", PHB3_MAX_MSI); if (!qdev_realize(DEVICE(&phb->msis), NULL, errp)) { return; } /* Power Bus Common Queue */ - object_property_set_link(OBJECT(&phb->pbcq), "phb", OBJECT(phb), - &error_abort); + qdev_prop_set_link(DEVICE(&phb->pbcq), "phb", OBJECT(phb)); if (!qdev_realize(DEVICE(&phb->pbcq), NULL, errp)) { return; } diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index ccbde841fc..c4e7cb0efe 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -1583,8 +1583,8 @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp) } else { nr_irqs = PNV_PHB4_MAX_INTs >> 1; } - object_property_set_int(OBJECT(xsrc), "nr-irqs", nr_irqs, &error_fatal); - object_property_set_link(OBJECT(xsrc), "xive", OBJECT(phb), &error_fatal); + qdev_prop_set_uint32(DEVICE(xsrc), "nr-irqs", nr_irqs); + qdev_prop_set_link(DEVICE(xsrc), "xive", OBJECT(phb)); if (!qdev_realize(DEVICE(xsrc), NULL, errp)) { return; } diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index 43267a428f..9c21382330 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -120,13 +120,9 @@ static void pnv_pec_default_phb_realize(PnvPhb4PecState *pec, int phb_id = pnv_phb4_pec_get_phb_id(pec, stack_no); object_property_add_child(OBJECT(pec), "phb[*]", OBJECT(phb)); - object_property_set_link(OBJECT(phb), "pec", OBJECT(pec), - &error_abort); - object_property_set_int(OBJECT(phb), "chip-id", pec->chip_id, - &error_fatal); - object_property_set_int(OBJECT(phb), "index", phb_id, - &error_fatal); - + qdev_prop_set_link(DEVICE(phb), "pec", OBJECT(pec)); + qdev_prop_set_uint32(DEVICE(phb), "chip-id", pec->chip_id); + qdev_prop_set_uint32(DEVICE(phb), "index", phb_id); if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { return; } diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 44b1fbbc93..7c6d5e4320 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -954,35 +954,31 @@ static void pnv_init(MachineState *machine) pnv->chips = g_new0(PnvChip *, pnv->num_chips); for (i = 0; i < pnv->num_chips; i++) { char chip_name[32]; - Object *chip = OBJECT(qdev_new(chip_typename)); + DeviceState *chip = qdev_new(chip_typename); uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i); pnv->chips[i] = PNV_CHIP(chip); + snprintf(chip_name, sizeof(chip_name), "chip[%d]", i); + object_property_add_child(OBJECT(pnv), chip_name, OBJECT(chip)); + /* Distribute RAM among the chips */ - object_property_set_int(chip, "ram-start", chip_ram_start, - &error_fatal); - object_property_set_int(chip, "ram-size", chip_ram_size, - &error_fatal); + qdev_prop_set_uint64(chip, "ram-start", chip_ram_start); + qdev_prop_set_uint64(chip, "ram-size", chip_ram_size); chip_ram_start += chip_ram_size; - snprintf(chip_name, sizeof(chip_name), "chip[%d]", i); - object_property_add_child(OBJECT(pnv), chip_name, chip); - object_property_set_int(chip, "chip-id", i, &error_fatal); - object_property_set_int(chip, "nr-cores", machine->smp.cores, - &error_fatal); - object_property_set_int(chip, "nr-threads", machine->smp.threads, - &error_fatal); + qdev_prop_set_uint32(chip, "chip-id", i); + qdev_prop_set_uint32(chip, "nr-cores", machine->smp.cores); + qdev_prop_set_uint32(chip, "nr-threads", machine->smp.threads); /* * The POWER8 machine use the XICS interrupt interface. * Propagate the XICS fabric to the chip and its controllers. */ if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { - object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); + qdev_prop_set_link(chip, "xics", OBJECT(pnv)); } if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { - object_property_set_link(chip, "xive-fabric", OBJECT(pnv), - &error_abort); + qdev_prop_set_link(chip, "xive-fabric", OBJECT(pnv)); } sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); } @@ -1492,7 +1488,7 @@ static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq, sizeof(*eq), TYPE_PNV_QUAD, &error_fatal, NULL); - object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); + qdev_prop_set_uint32(DEVICE(eq), "quad-id", core_id); qdev_realize(DEVICE(eq), NULL, &error_fatal); } @@ -1969,16 +1965,13 @@ static void pnv_chip_core_realize(PnvChip *chip, Error **errp) snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); chip->cores[i] = pnv_core; - object_property_set_int(OBJECT(pnv_core), "nr-threads", - chip->nr_threads, &error_fatal); + qdev_prop_set_uint32(DEVICE(pnv_core), "nr-threads", chip->nr_threads); object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, core_hwid, &error_fatal); - object_property_set_int(OBJECT(pnv_core), "pir", - pcc->core_pir(chip, core_hwid), &error_fatal); - object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, - &error_fatal); - object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), - &error_abort); + qdev_prop_set_uint32(DEVICE(pnv_core), "pir", + pcc->core_pir(chip, core_hwid)); + qdev_prop_set_uint64(DEVICE(pnv_core), "hrmor", pnv->fw_load_addr); + qdev_prop_set_link(DEVICE(pnv_core), "chip", OBJECT(chip)); qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); /* Each core has an XSCOM MMIO region */ diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c index 8aa09ab26b..fb90d47138 100644 --- a/hw/ppc/pnv_psi.c +++ b/hw/ppc/pnv_psi.c @@ -492,10 +492,7 @@ static void pnv_psi_power8_realize(DeviceState *dev, Error **errp) unsigned int i; /* Create PSI interrupt control source */ - if (!object_property_set_int(OBJECT(ics), "nr-irqs", PSI_NUM_INTERRUPTS, - errp)) { - return; - } + qdev_prop_set_uint32(DEVICE(ics), "nr-irqs", PSI_NUM_INTERRUPTS); if (!qdev_realize(DEVICE(ics), NULL, errp)) { return; } @@ -849,9 +846,8 @@ static void pnv_psi_power9_realize(DeviceState *dev, Error **errp) XiveSource *xsrc = &PNV9_PSI(psi)->source; int i; - object_property_set_int(OBJECT(xsrc), "nr-irqs", PSIHB9_NUM_IRQS, - &error_fatal); - object_property_set_link(OBJECT(xsrc), "xive", OBJECT(psi), &error_abort); + qdev_prop_set_uint32(DEVICE(xsrc), "nr-irqs", PSIHB9_NUM_IRQS); + qdev_prop_set_link(DEVICE(xsrc), "xive", OBJECT(psi)); if (!qdev_realize(DEVICE(xsrc), NULL, errp)) { return; }