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Tsirkin" , Marcel Apfelbaum Subject: [PATCH 1/9] hw/i386/sgx: Do not open-code qdev_realize_and_unref() Date: Fri, 3 Feb 2023 12:36:42 +0100 Message-Id: <20230203113650.78146-2-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230203113650.78146-1-philmd@linaro.org> References: <20230203113650.78146-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Markus Armbruster --- hw/i386/sgx.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/i386/sgx.c b/hw/i386/sgx.c index db004d17a6..5ddc5d7ea2 100644 --- a/hw/i386/sgx.c +++ b/hw/i386/sgx.c @@ -299,7 +299,7 @@ void pc_machine_init_sgx_epc(PCMachineState *pcms) &sgx_epc->mr); for (list = x86ms->sgx_epc_list; list; list = list->next) { - obj = object_new("sgx-epc"); + obj = object_new(TYPE_SGX_EPC); /* set the memdev link with memory backend */ object_property_parse(obj, SGX_EPC_MEMDEV_PROP, list->value->memdev, @@ -307,8 +307,7 @@ void pc_machine_init_sgx_epc(PCMachineState *pcms) /* set the numa node property for sgx epc object */ object_property_set_uint(obj, SGX_EPC_NUMA_NODE_PROP, list->value->node, &error_fatal); - object_property_set_bool(obj, "realized", true, &error_fatal); - object_unref(obj); + qdev_realize_and_unref(DEVICE(obj), NULL, &error_fatal); } if ((sgx_epc->base + sgx_epc->size) < sgx_epc->base) { From patchwork Fri Feb 3 11:36:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 650023 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp765544pva; Fri, 3 Feb 2023 03:38:25 -0800 (PST) X-Google-Smtp-Source: AK7set+yfyvE+2Euey4/3U230TV0c7YxO0hZQjEaHuIybHYwFRVqlttmmjo3y2yFszlh+10oZEdr X-Received: by 2002:a0c:cc82:0:b0:567:fe96:85a7 with SMTP id f2-20020a0ccc82000000b00567fe9685a7mr3155328qvl.28.1675424305024; Fri, 03 Feb 2023 03:38:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675424305; cv=none; d=google.com; s=arc-20160816; b=0tW1YV0woWXLMF7KrYI/K1IwbppO1x1lEeImiDy+qFYjrFnY6seD1v9NYBCYW3sGuz oFy2KCWwDsh8wh91eWPYa7d/Z56HVBXOqTDzddrpZlzr51Eg1HbyMNPq2UwPhAPpdO5I 8HDG4L+14W6DB+VAUSj6BL2pP5cJmSj46bwCD6PCMCfqSI7SVn+d4i2ecIBdlNXWzvYt noIPznRJaOrJS9rFH1Pc6yEwSTxH7w8GJsTxNQAP1k/XrYmfkCxFJ2LrDjKnd5gCj1Lf yDXcls0cjwHOA4wq0glu8xRO2xclYrhvyrRFXHsTprGSjhi4RPcbSZ7Zxa0kcJ6mryrU eDuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=XruElQ/KqElMH5647D/y730I75puE5BeGIEjp7H7QEM=; b=PLJCnDMsFiJBqVWor53oMswL9LVsPUxre4b/AtuMazrMvY0EEuUjgkmtkuZxkGaTQ/ A4MP3wRPc1EXFav6lrb/yGS7Y+ZTgAhQ9JnAvjJoCQDxbKKKH+EIFVZtc5zHWaCtNvSx 7aMKwxNw/bS+C87QTCB93WCMzS1CZJcFGcR4ZpFltHUd8WsNqIx3X4CHH6gMdfEKrxpN 8PpRmSqBlxhXMxwXFhKtdy5z5RhF+atytAKo76vu8Ux49TfslHGfQm5HtBvs3eNFiivq YLEGdqNYtCUDxRnu686b/pljAr3hL70Mozg6yNtbiwZJgcpmo57/tfZ/VBUx4aoJoD7+ reoA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nocjyXie; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k2-20020a0cf582000000b00569b5d8716bsi616310qvm.182.2023.02.03.03.38.24 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Feb 2023 03:38:25 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nocjyXie; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNuNP-00080X-Ir; Fri, 03 Feb 2023 06:37:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNuNN-0007z6-V3 for qemu-devel@nongnu.org; Fri, 03 Feb 2023 06:37:05 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pNuNL-0001CZ-Ph for qemu-devel@nongnu.org; Fri, 03 Feb 2023 06:37:05 -0500 Received: by mail-wr1-x429.google.com with SMTP id a2so4102793wrd.6 for ; Fri, 03 Feb 2023 03:37:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XruElQ/KqElMH5647D/y730I75puE5BeGIEjp7H7QEM=; b=nocjyXieTrPivHs/s+PlPk/HgSfTlvK00jERJL/goaYJOO4/wb0GOEWMwESfoxe6W+ wT6dhwZu5OCof5DZpVD8Zn/28B1BUpynSYN3GYS8ewq7sHhx+LpIib9I+MMzGKlYOkdO pQigs7ujxKmhHTKCqcRUsYG7g5SZeGUiC0fe7/H8iBv7+ElXI5M5lJ4J+YzOgyLcLXgX Z7n6EcmEytjBfySSM9L6CeEIF/zwnWfzuh0JNwmPK4HxKEBkCqm2A7Vgg2puPf/u5xVk mcgtOYS/fZXnyPXXfsUiR3B+u2UH/mt4qJVlnlNO0PZkJsHvFhj8bOGMucnHPHTViO9X 5idQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XruElQ/KqElMH5647D/y730I75puE5BeGIEjp7H7QEM=; b=WE70dRTl5TBMas+8uE7WtH2RE2XflE8bJP2C5B3yhErqBxj7Y7Ky4JcUsi5ML6qG9D QYrv4n6QrhyTOgNy09BhQXxPZE1iIEIpv5YZdOOUPskkRlZl5G7dCWRRv3aT1jpN7Qde vlk0JLcpxzWKRRdCY69AFG05r3fl4U+ecFiO6ta0Lfr1NsFPd2CRtKCIR5r4n1utVEm6 ur1MdVoitB/FxwuWCHc8UF210y9/1bqw2x7t0bxoSKWFm+iYszS3zsoRcPWXul0kHMej bhrJLjhjNlT4R4zPpzE9soPDFpwTK260il26fA0OxXwtRPN2xFGmJ6jhAQX/kP2TsGGE CD/g== X-Gm-Message-State: AO0yUKVYZbQa1UwX4b+jECZt4NoP85h4HaErfN57sfvUG+saUHrptWaN HyE0Vti7Lj/DB83kQ33fzOYsDhIjyipkAMYD X-Received: by 2002:adf:ef85:0:b0:2bf:e443:ea70 with SMTP id d5-20020adfef85000000b002bfe443ea70mr8060231wro.1.1675424222405; Fri, 03 Feb 2023 03:37:02 -0800 (PST) Received: from localhost.localdomain ([81.0.6.76]) by smtp.gmail.com with ESMTPSA id y10-20020a05600015ca00b002bfd137ecddsm1885239wry.11.2023.02.03.03.37.01 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 03 Feb 2023 03:37:02 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Markus Armbruster , Eduardo Habkost , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , BALATON Zoltan Subject: [PATCH 2/9] hw/ppc/sam460ex: Correctly set MAL properties Date: Fri, 3 Feb 2023 12:36:43 +0100 Message-Id: <20230203113650.78146-3-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230203113650.78146-1-philmd@linaro.org> References: <20230203113650.78146-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org MAL properties are declared as uint8_t: static Property ppc4xx_mal_properties[] = { DEFINE_PROP_UINT8("txc-num", Ppc4xxMalState, txcnum, 0), DEFINE_PROP_UINT8("rxc-num", Ppc4xxMalState, rxcnum, 0), DEFINE_PROP_END_OF_LIST(), }; Set the property using qdev_prop_set_uint8(). Fixes: da116a8aab ("ppc/ppc405: QOM'ify MAL") Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: BALATON Zoltan --- hw/ppc/sam460ex.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index 4a22ce3761..cf065aae0e 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -389,8 +389,8 @@ static void sam460ex_init(MachineState *machine) /* MAL */ dev = qdev_new(TYPE_PPC4xx_MAL); - qdev_prop_set_uint32(dev, "txc-num", 4); - qdev_prop_set_uint32(dev, "rxc-num", 16); + qdev_prop_set_uint8(dev, "txc-num", 4); + qdev_prop_set_uint8(dev, "rxc-num", 16); ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal); object_unref(OBJECT(dev)); sbdev = SYS_BUS_DEVICE(dev); From patchwork Fri Feb 3 11:36:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 650026 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp765694pva; Fri, 3 Feb 2023 03:38:48 -0800 (PST) X-Google-Smtp-Source: AK7set/PQJUr0QER27npndFgaWp1cSBYFjE3+cxqtTh6QtRM3VBc/P3ubz6W8fVZBbTHdgvN8E8m X-Received: by 2002:a05:6214:1395:b0:53c:bfc9:73cc with SMTP id pp21-20020a056214139500b0053cbfc973ccmr14394235qvb.19.1675424328208; Fri, 03 Feb 2023 03:38:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675424328; cv=none; d=google.com; s=arc-20160816; b=UbeugS9z/v33crwz4MuvrguZFcPGpi1IsugiQicJoBQoqVsxLPIUthJyWO/93svFOg ID5J8IOLLEDXAYhiZTrVtwgN3IcoLWjH9ebZzsXGkg8GVTVdLG4XPJQBReDRJxeYLU90 /WIg+DJn6HMLfrUv6iLUFFj2+iF10R8+qfqAlPRzPSriKROmSv1WIOog3Q4rApiY5H7i oKuKR6yVoYwEMeHUbQ+J8h+HYJ3pmYPTuH3KqNFyK7jAyiAWuUQB5aZqJerO5BIUOock MdEUjzoAuscb/YC+7W/wpIFBE0q1j4+JY3vcVcbVWaXzfRhVE7LWpvBFsFXJFxFbwOhx CGNw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=T7gfeI3mnZ+Wy6rurWRcclNKo/AI2l33cgu5mda3V+c=; b=fJNafyyqEUOWdKCXZxRARPvh1Y0yAZH/pNhLjOySqsZTKz2urNq+lJK9gKKxHDli+D h2zPROsONXCsgHRA1WxwKWjmMkWr3hRpucZzcB39vTY9Bwb6n7on2ntzd4fIsUp87V5Y UiUFWGLfuUWYDD12lZcySYDGUFRqiu6f0emzYR8g92CtNCe8hbmHu2xthhwZXuxqV6tN a77OO3V4aOXeeE7H90iO/qflhVEvTz3h0aiMRJ69qrmZyimi/AayrX2XCTfyFpguTpTB NhGjQVpxcJffu8F0CO4Q3E3xy+6DACtKF3/YMqAqRuIcgmmBFM954yvk2kyHn2U+Iksx /C2g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="y0H+WM/0"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 8-20020a0562140cc800b004c74b9fbc58si1874113qvx.448.2023.02.03.03.38.48 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Feb 2023 03:38:48 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="y0H+WM/0"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNuNV-000844-LT; Fri, 03 Feb 2023 06:37:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNuNT-00082f-P4 for qemu-devel@nongnu.org; Fri, 03 Feb 2023 06:37:12 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pNuNR-0001EF-3W for qemu-devel@nongnu.org; Fri, 03 Feb 2023 06:37:11 -0500 Received: by mail-wm1-x32e.google.com with SMTP id bg13-20020a05600c3c8d00b003d9712b29d2so5807832wmb.2 for ; Fri, 03 Feb 2023 03:37:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=T7gfeI3mnZ+Wy6rurWRcclNKo/AI2l33cgu5mda3V+c=; b=y0H+WM/0RHQyjaSUvRiTy+/3im9WNQXEoc+hyue/zdwO841cTsyjcKxBjKK+5Y9ePH PfIZoPsBaCJ/c0aYPqXSI7fHtpS+sDaYyK3hZX2myB55QRvSPs/tHQcHQYV6DxvfBIfq B4FbtEWNE12zePp+BzYqpVY9zHrpVZq5I1MdqbpoTudSAzBH93H9o4pUp756NvY4Q0IU 5JOsru0y4GpfmFI9KcZLKNT9qdZxNw3uLyNKhEQYUVc5cwVc0nAMbSaSf6XU01ylIRDu +lFRcerS3xGOguQs4bOgmKSh51fFSWWU4e8KkvRVQX6ipGU9/LAdH+Ddmrj5evFa4Pu+ K+ag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=T7gfeI3mnZ+Wy6rurWRcclNKo/AI2l33cgu5mda3V+c=; b=y//ugFVOatM1dlu3WF+ysMV8FJp/BqgqYJ0u92rUpV4xIK1mzvePuQAzV4t2Y28BX3 lCq0niYcWW53CgoEtuGbbJylL3fgi7TLRSi6tHLnTyWABh+V8Q8uSJ/4r3aSzCNO7U3y iVQuccPKblSobcixdx/0Z/SrF5c3GHCo3PxmZXJ3JRK+/D29WtyjWf1tDNKDDg+oCNHj BkIGOlYHogFs2U8dUWDxKtHYORzPqsTr9M6dnPqzRj8wBjr9s2viG4Zx4pQxG5Eb8/vK dLa+/470/DLf4SCCJfeHDRc3xzq4TfbVs6T5EbEZyVX5xMUr4oliXl1Z7PQdMPGIOgLy 9QZQ== X-Gm-Message-State: AO0yUKWsO9iR529qJ0JnkfsWeBxz73tCK/GV2CwKwV4O81sD0LUH+E7Y XCF4llyvnN4q/ZrHlUvNNxoiupbDnOVHBHLY X-Received: by 2002:a05:600c:288:b0:3d3:513c:240b with SMTP id 8-20020a05600c028800b003d3513c240bmr8646952wmk.7.1675424227498; Fri, 03 Feb 2023 03:37:07 -0800 (PST) Received: from localhost.localdomain ([81.0.6.76]) by smtp.gmail.com with ESMTPSA id p30-20020a1c545e000000b003de2fc8214esm2531614wmi.20.2023.02.03.03.37.06 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 03 Feb 2023 03:37:07 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Markus Armbruster , Eduardo Habkost , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Joel Stanley , Peter Maydell Subject: [PATCH 3/9] hw/arm/nrf51: QOM-alias 'flash-size' property in SoC object Date: Fri, 3 Feb 2023 12:36:44 +0100 Message-Id: <20230203113650.78146-4-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230203113650.78146-1-philmd@linaro.org> References: <20230203113650.78146-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org No need to use an intermediate 'flash-size' property in the SoC object. Alias the property, so when the machine (here microbit) sets the value on the SoC, it is propagated to the flash object. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/microbit.c | 5 ++++- hw/arm/nrf51_soc.c | 10 +--------- hw/nvram/nrf51_nvm.c | 6 +++++- include/hw/arm/nrf51_soc.h | 1 - 4 files changed, 10 insertions(+), 12 deletions(-) diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c index 50df362088..79b5574884 100644 --- a/hw/arm/microbit.c +++ b/hw/arm/microbit.c @@ -36,6 +36,7 @@ static void microbit_init(MachineState *machine) MicrobitMachineState *s = MICROBIT_MACHINE(machine); MemoryRegion *system_memory = get_system_memory(); MemoryRegion *mr; + int64_t flash_size; object_initialize_child(OBJECT(machine), "nrf51", &s->nrf51, TYPE_NRF51_SOC); @@ -43,6 +44,8 @@ static void microbit_init(MachineState *machine) object_property_set_link(OBJECT(&s->nrf51), "memory", OBJECT(system_memory), &error_fatal); sysbus_realize(SYS_BUS_DEVICE(&s->nrf51), &error_fatal); + flash_size = object_property_get_int(OBJECT(&s->nrf51), + "flash-size", &error_abort); /* * Overlap the TWI stub device into the SoC. This is a microbit-specific @@ -57,7 +60,7 @@ static void microbit_init(MachineState *machine) mr, -1); armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, - 0, s->nrf51.flash_size); + 0, flash_size); } static void microbit_machine_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index 34da0d62f0..cc4a636c51 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -24,9 +24,7 @@ * are supported in the future, add a sub-class of NRF51SoC for * the specific variants */ -#define NRF51822_FLASH_PAGES 256 #define NRF51822_SRAM_PAGES 16 -#define NRF51822_FLASH_SIZE (NRF51822_FLASH_PAGES * NRF51_PAGE_SIZE) #define NRF51822_SRAM_SIZE (NRF51822_SRAM_PAGES * NRF51_PAGE_SIZE) #define BASE_TO_IRQ(base) ((base >> 12) & 0x1F) @@ -122,11 +120,6 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) BASE_TO_IRQ(NRF51_RNG_BASE))); /* UICR, FICR, NVMC, FLASH */ - if (!object_property_set_uint(OBJECT(&s->nvm), "flash-size", - s->flash_size, errp)) { - return; - } - if (!sysbus_realize(SYS_BUS_DEVICE(&s->nvm), errp)) { return; } @@ -199,6 +192,7 @@ static void nrf51_soc_init(Object *obj) object_initialize_child(obj, "rng", &s->rng, TYPE_NRF51_RNG); object_initialize_child(obj, "nvm", &s->nvm, TYPE_NRF51_NVM); + object_property_add_alias(obj, "flash-size", OBJECT(&s->nvm), "flash-size"); object_initialize_child(obj, "gpio", &s->gpio, TYPE_NRF51_GPIO); @@ -215,8 +209,6 @@ static Property nrf51_soc_properties[] = { DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_SIZE), - DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size, - NRF51822_FLASH_SIZE), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/nvram/nrf51_nvm.c b/hw/nvram/nrf51_nvm.c index 7f1db8c423..bfae028fcd 100644 --- a/hw/nvram/nrf51_nvm.c +++ b/hw/nvram/nrf51_nvm.c @@ -26,6 +26,9 @@ #include "hw/qdev-properties.h" #include "migration/vmstate.h" +#define NRF51822_FLASH_PAGES 256 +#define NRF51822_FLASH_SIZE (NRF51822_FLASH_PAGES * NRF51_PAGE_SIZE) + /* * FICR Registers Assignments * CODEPAGESIZE 0x010 @@ -358,7 +361,8 @@ static void nrf51_nvm_reset(DeviceState *dev) } static Property nrf51_nvm_properties[] = { - DEFINE_PROP_UINT32("flash-size", NRF51NVMState, flash_size, 0x40000), + DEFINE_PROP_UINT32("flash-size", NRF51NVMState, + flash_size, NRF51822_FLASH_SIZE), DEFINE_PROP_END_OF_LIST(), }; diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h index e52a56e75e..8cf0c21614 100644 --- a/include/hw/arm/nrf51_soc.h +++ b/include/hw/arm/nrf51_soc.h @@ -45,7 +45,6 @@ struct NRF51State { MemoryRegion twi; uint32_t sram_size; - uint32_t flash_size; MemoryRegion *board_memory; From patchwork Fri Feb 3 11:36:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 650028 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp765798pva; Fri, 3 Feb 2023 03:39:05 -0800 (PST) X-Google-Smtp-Source: AK7set85FbXUF5mhBs/QsQAhXHkBgK4xWklV6t1edVgIgbHluUrS77gZ6DETfRv08DenhxNpIQVH X-Received: by 2002:ac8:5f52:0:b0:3b9:bdb0:7aa1 with SMTP id y18-20020ac85f52000000b003b9bdb07aa1mr16427645qta.41.1675424345259; Fri, 03 Feb 2023 03:39:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675424345; cv=none; d=google.com; s=arc-20160816; b=loRv4B4NwlC2o5lGaESF+La0iu2+M4soC0Hdbv7gfu4RjFpagIw6SwgB1L7mHNH2Xg jLzjgZoIySvWRbMn8N5zo7c9HjRxeTAiYuSKsTixuVSXnBqsvE5/Qhd+8FVbwHhLIYes UJ0J4KGw49HWuzM6LMi/sdgF0vZDYZzoJqApsOKzhYyookyOAYSZVAhtGhL7+/IkFluy 80lAjXcF5JB8hhwXtF6/ZtEjCVa+HOQOidSVNMA/xeFcD3l8UDiGKmE9S+NJwEvtfJ23 4wGxpstJmdJRtfRDSrv8Mr/aK+hjRC///d+0N7/4rt0nrC5WpYiRzrO+PGZeiaW9GUZt Dn3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=f2kBLJKaVnGetSSqtxpfAhCXISkwd1yaz8QImmDemGM=; b=shVCf0VQUeVDNlURv52/mWt/nb4YGJGQ58r0NVXwqV5NqFs5eYpyVGo43J7Y68uoXk rgw58AUw9eHTGHDkdBFExrkvdAC1HpAl1PqI4NUSwPtruuUgRxV1kC721wTF6YPg9qO7 5+o11X11W0dbBh8b9aJfZbg5fl/eWYpQKxq5UWcMInSVxuMz7lS5rhoYpFZrH5mMs+Ad IaUD2FInc0NPshtXVYSP11b4fJcTVWmW5ORC3ByylsP7sNjDPkOR6cU//t6AuUq1hN2r Jx3dS1Grk7ns3r/d8glJttmzoH6ImQ33/JArVeWy2HbV3MJtrnod9aZAFOMJTVoiaZew gteg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=B2y5MLq9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Alias the properties, so when the machines set the value on the SoC, it is propagated to the network device object. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/fsl-imx25.c | 3 +-- hw/arm/fsl-imx6.c | 3 +-- hw/arm/fsl-imx6ul.c | 8 ++++---- hw/arm/fsl-imx7.c | 12 ++++++------ include/hw/arm/fsl-imx25.h | 1 - include/hw/arm/fsl-imx6.h | 1 - include/hw/arm/fsl-imx6ul.h | 2 -- include/hw/arm/fsl-imx7.h | 1 - 8 files changed, 12 insertions(+), 19 deletions(-) diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c index 24c4374590..eff58e1f7a 100644 --- a/hw/arm/fsl-imx25.c +++ b/hw/arm/fsl-imx25.c @@ -55,6 +55,7 @@ static void fsl_imx25_init(Object *obj) } object_initialize_child(obj, "fec", &s->fec, TYPE_IMX_FEC); + object_property_add_alias(obj, "fec-phy-num", OBJECT(&s->fec), "phy-num"); object_initialize_child(obj, "rngc", &s->rngc, TYPE_IMX_RNGC); @@ -169,7 +170,6 @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp) epit_table[i].irq)); } - object_property_set_uint(OBJECT(&s->fec), "phy-num", s->phy_num, &err); qdev_set_nic_properties(DEVICE(&s->fec), &nd_table[0]); if (!sysbus_realize(SYS_BUS_DEVICE(&s->fec), errp)) { @@ -315,7 +315,6 @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp) } static Property fsl_imx25_properties[] = { - DEFINE_PROP_UINT32("fec-phy-num", FslIMX25State, phy_num, 0), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c index 00dafe3f62..4f870c928c 100644 --- a/hw/arm/fsl-imx6.c +++ b/hw/arm/fsl-imx6.c @@ -100,6 +100,7 @@ static void fsl_imx6_init(Object *obj) object_initialize_child(obj, "eth", &s->eth, TYPE_IMX_ENET); + object_property_add_alias(obj, "fec-phy-num", OBJECT(&s->eth), "phy-num"); } static void fsl_imx6_realize(DeviceState *dev, Error **errp) @@ -377,7 +378,6 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp) spi_table[i].irq)); } - object_property_set_uint(OBJECT(&s->eth), "phy-num", s->phy_num, &err); qdev_set_nic_properties(DEVICE(&s->eth), &nd_table[0]); if (!sysbus_realize(SYS_BUS_DEVICE(&s->eth), errp)) { return; @@ -451,7 +451,6 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp) } static Property fsl_imx6_properties[] = { - DEFINE_PROP_UINT32("fec-phy-num", FslIMX6State, phy_num, 0), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c index d88d6cc1c5..8b3939e8c5 100644 --- a/hw/arm/fsl-imx6ul.c +++ b/hw/arm/fsl-imx6ul.c @@ -120,8 +120,12 @@ static void fsl_imx6ul_init(Object *obj) * Ethernet */ for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) { + g_autofree gchar *propname = g_strdup_printf("fec%d-phy-num", i + 1); snprintf(name, NAME_SIZE, "eth%d", i); object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET); + qdev_prop_set_uint32(DEVICE(&s->eth[i]), "phy-num", i); + object_property_add_alias(obj, propname, + OBJECT(&s->eth[i]), "phy-num"); } /* USB */ @@ -424,8 +428,6 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) FSL_IMX6UL_ENET2_TIMER_IRQ, }; - object_property_set_uint(OBJECT(&s->eth[i]), "phy-num", - s->phy_num[i], &error_abort); object_property_set_uint(OBJECT(&s->eth[i]), "tx-ring-num", FSL_IMX6UL_ETH_NUM_TX_RINGS, &error_abort); qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]); @@ -618,8 +620,6 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) } static Property fsl_imx6ul_properties[] = { - DEFINE_PROP_UINT32("fec1-phy-num", FslIMX6ULState, phy_num[0], 0), - DEFINE_PROP_UINT32("fec2-phy-num", FslIMX6ULState, phy_num[1], 1), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c index afc7480799..df035c9314 100644 --- a/hw/arm/fsl-imx7.c +++ b/hw/arm/fsl-imx7.c @@ -102,8 +102,12 @@ static void fsl_imx7_init(Object *obj) * Ethernet */ for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) { - snprintf(name, NAME_SIZE, "eth%d", i); - object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET); + g_autofree gchar *propname = g_strdup_printf("fec%d-phy-num", i + 1); + snprintf(name, NAME_SIZE, "eth%d", i); + object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET); + qdev_prop_set_uint32(DEVICE(&s->eth[i]), "phy-num", i); + object_property_add_alias(obj, propname, + OBJECT(&s->eth[i]), "phy-num"); } /* @@ -402,8 +406,6 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) FSL_IMX7_ENET2_ADDR, }; - object_property_set_uint(OBJECT(&s->eth[i]), "phy-num", - s->phy_num[i], &error_abort); object_property_set_uint(OBJECT(&s->eth[i]), "tx-ring-num", FSL_IMX7_ETH_NUM_TX_RINGS, &error_abort); qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]); @@ -599,8 +601,6 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) } static Property fsl_imx7_properties[] = { - DEFINE_PROP_UINT32("fec1-phy-num", FslIMX7State, phy_num[0], 0), - DEFINE_PROP_UINT32("fec2-phy-num", FslIMX7State, phy_num[1], 1), DEFINE_PROP_END_OF_LIST(), }; diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h index 1b1086e945..e377f8e79a 100644 --- a/include/hw/arm/fsl-imx25.h +++ b/include/hw/arm/fsl-imx25.h @@ -66,7 +66,6 @@ struct FslIMX25State { MemoryRegion rom[2]; MemoryRegion iram; MemoryRegion iram_alias; - uint32_t phy_num; }; /** diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h index 83291457cf..f7d1a94640 100644 --- a/include/hw/arm/fsl-imx6.h +++ b/include/hw/arm/fsl-imx6.h @@ -74,7 +74,6 @@ struct FslIMX6State { MemoryRegion caam; MemoryRegion ocram; MemoryRegion ocram_alias; - uint32_t phy_num; }; diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h index 7812e516a5..5217eeb8ff 100644 --- a/include/hw/arm/fsl-imx6ul.h +++ b/include/hw/arm/fsl-imx6ul.h @@ -88,8 +88,6 @@ struct FslIMX6ULState { MemoryRegion caam; MemoryRegion ocram; MemoryRegion ocram_alias; - - uint32_t phy_num[FSL_IMX6UL_NUM_ETHS]; }; enum FslIMX6ULMemoryMap { diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h index 4e5e071864..16c68a4937 100644 --- a/include/hw/arm/fsl-imx7.h +++ b/include/hw/arm/fsl-imx7.h @@ -82,7 +82,6 @@ struct FslIMX7State { IMX7GPRState gpr; ChipideaState usb[FSL_IMX7_NUM_USBS]; DesignwarePCIEHost pcie; - uint32_t phy_num[FSL_IMX7_NUM_ETHS]; }; enum FslIMX7MemoryMap { From patchwork Fri Feb 3 11:36:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 650027 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp765706pva; Fri, 3 Feb 2023 03:38:50 -0800 (PST) X-Google-Smtp-Source: AK7set8SNgjtZ6ElmvTmiFE893X2as4+mxDtifpZtX7SLTH/dBGcURr9peaglDeNktPB5yWtsES0 X-Received: by 2002:a05:622a:1648:b0:3b8:46f0:9904 with SMTP id y8-20020a05622a164800b003b846f09904mr19269238qtj.41.1675424330268; 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Fri, 03 Feb 2023 03:37:17 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Markus Armbruster , Eduardo Habkost , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Gerd Hoffmann Subject: [PATCH 5/9] hw/usb/hcd-ohci: Include missing 'sysbus.h' header Date: Fri, 3 Feb 2023 12:36:46 +0100 Message-Id: <20230203113650.78146-6-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230203113650.78146-1-philmd@linaro.org> References: <20230203113650.78146-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Avoid when including "hw/usb/hcd-ohci.h": hw/usb/hcd-ohci.h:100:5: error: unknown type name 'SysBusDevice' SysBusDevice parent_obj; ^ Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Markus Armbruster --- hw/usb/hcd-ohci.h | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/usb/hcd-ohci.h b/hw/usb/hcd-ohci.h index 11ac57058d..e5e6b434fd 100644 --- a/hw/usb/hcd-ohci.h +++ b/hw/usb/hcd-ohci.h @@ -21,6 +21,7 @@ #ifndef HCD_OHCI_H #define HCD_OHCI_H +#include "hw/sysbus.h" #include "sysemu/dma.h" #include "hw/usb.h" #include "qom/object.h" From patchwork Fri Feb 3 11:36:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 650024 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp765543pva; Fri, 3 Feb 2023 03:38:25 -0800 (PST) X-Google-Smtp-Source: AK7set9EVLoNXoTNckh8RIoYj8M63PiMMMZzNqJlK9rVPO95IDReCA5L/y5cz6j807vPaBVoj4cO X-Received: by 2002:a05:622a:1003:b0:3b8:6054:d41d with SMTP id d3-20020a05622a100300b003b86054d41dmr17513970qte.28.1675424305037; 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[209.51.188.17]) by mx.google.com with ESMTPS id w16-20020ac87e90000000b003b8559f2a03si1751858qtj.621.2023.02.03.03.38.24 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Feb 2023 03:38:25 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=joz2Q7NZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNuNj-0008D6-Is; Fri, 03 Feb 2023 06:37:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNuNi-0008At-1x for qemu-devel@nongnu.org; Fri, 03 Feb 2023 06:37:26 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pNuNf-0001GR-PW for qemu-devel@nongnu.org; Fri, 03 Feb 2023 06:37:25 -0500 Received: by mail-wm1-x333.google.com with SMTP id k8-20020a05600c1c8800b003dc57ea0dfeso5822822wms.0 for ; Fri, 03 Feb 2023 03:37:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=K+cjiRrUxf8pio68qBRhIQ1AivvB4oG5DvRMp0FNP4E=; b=joz2Q7NZy4LkvmEZpfE9ThGOiVfDAdi8oJL5jrAOgFOWlgGMpFnKpAsL0pFYk5yaRr YgsXnGUPddj0LkVytcsGSr5f8pNuMcMoqvTLANfyn1y1HfRkRHCsreTsXHAxun6QkHyG kRXq2v2IOfWAsrtEE9CefhygHGCBQjk8PaZCXr5glY6q6SFOojEbTm4aT1vwhkyR7MkK Q3IV0tDKzvoJ6/5ZLJmxpPsMz7DZbitKWjr0aYjcgLsCBh32bK5jTojYeAOadBujvc96 b9mlFZaBxuRE5LJtbUC4BCBS5I7ksYXytx2DgN5UPQsjq5w0UFluEm0rFgGjQZsKgAcq BYeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=K+cjiRrUxf8pio68qBRhIQ1AivvB4oG5DvRMp0FNP4E=; b=eAhP8ON7lReFaDkh7rMfI0Z1Fw0F73KUAzSU72fpN7roEOz4Nsr85KxbwaA+g3oevQ NcWZLGfhSxBqz5Jreba0xDHDcRXzOUhW3+z6sathgBZZd58pSqcU3zHg61LmdkLoOyFx y+/GYlaF4XDxtZsActu2EK4j0jhfA94BzbEym78dB64ytB4dO4v+eTXSJcUw4fJi9jW/ 0u1hdPn+m6o0BNycqtKIH/opb9W1fW1uDULue5uc+JJW+PLao1Rfw1C/pxo4e8m1mmak KD91jRDckX8vfdRoyGWFiby1qSbmlz7sEb7Zwxof/l2tR0qrAhZZSXvnnsGbRKs+TBmO akeQ== X-Gm-Message-State: AO0yUKV4FZ8LYDhOlN3VMvvdq8iyDhs/21IbmPiilHYHOoyAJ1Nx4O0O ztKHCiTBDc5GtOrKsdQcnZJDYp2Den4tgT3J X-Received: by 2002:a05:600c:210a:b0:3df:12db:2779 with SMTP id u10-20020a05600c210a00b003df12db2779mr8379657wml.3.1675424242406; Fri, 03 Feb 2023 03:37:22 -0800 (PST) Received: from localhost.localdomain ([81.0.6.76]) by smtp.gmail.com with ESMTPSA id i14-20020a1c540e000000b003db03725e86sm2517792wmb.8.2023.02.03.03.37.21 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 03 Feb 2023 03:37:22 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Markus Armbruster , Eduardo Habkost , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , BALATON Zoltan , Yoshinori Sato , Magnus Damm Subject: [PATCH 6/9] hw/display/sm501: QOM-alias 'dma-offset' property in chipset object Date: Fri, 3 Feb 2023 12:36:47 +0100 Message-Id: <20230203113650.78146-7-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230203113650.78146-1-philmd@linaro.org> References: <20230203113650.78146-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org No need to use an intermediate 'dma-offset' property in the chipset object. Alias the property, so when the machine (here r2d-plus) sets the value on the chipset, it is propagated to the OHCI object. Signed-off-by: Philippe Mathieu-Daudé --- hw/display/sm501.c | 22 +++++++++++----------- hw/sh4/r2d.c | 2 +- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/hw/display/sm501.c b/hw/display/sm501.c index 52e42585af..49a648e952 100644 --- a/hw/display/sm501.c +++ b/hw/display/sm501.c @@ -28,6 +28,7 @@ #include "qapi/error.h" #include "qemu/log.h" #include "qemu/module.h" +#include "hw/usb/hcd-ohci.h" #include "hw/char/serial.h" #include "ui/console.h" #include "hw/sysbus.h" @@ -1942,7 +1943,7 @@ struct SM501SysBusState { /*< public >*/ SM501State state; uint32_t vram_size; - uint32_t base; + OHCISysBusState ohci; SerialMM serial; }; @@ -1950,7 +1951,6 @@ static void sm501_realize_sysbus(DeviceState *dev, Error **errp) { SM501SysBusState *s = SYSBUS_SM501(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); - DeviceState *usb_dev; MemoryRegion *mr; sm501_init(&s->state, dev, s->vram_size); @@ -1963,13 +1963,10 @@ static void sm501_realize_sysbus(DeviceState *dev, Error **errp) sysbus_init_mmio(sbd, &s->state.mmio_region); /* bridge to usb host emulation module */ - usb_dev = qdev_new("sysbus-ohci"); - qdev_prop_set_uint32(usb_dev, "num-ports", 2); - qdev_prop_set_uint64(usb_dev, "dma-offset", s->base); - sysbus_realize_and_unref(SYS_BUS_DEVICE(usb_dev), &error_fatal); + sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->ohci), &error_fatal); memory_region_add_subregion(&s->state.mmio_region, SM501_USB_HOST, - sysbus_mmio_get_region(SYS_BUS_DEVICE(usb_dev), 0)); - sysbus_pass_irq(sbd, SYS_BUS_DEVICE(usb_dev)); + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ohci), 0)); + sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->ohci)); /* bridge to serial emulation module */ sysbus_realize(SYS_BUS_DEVICE(&s->serial), &error_fatal); @@ -1980,7 +1977,6 @@ static void sm501_realize_sysbus(DeviceState *dev, Error **errp) static Property sm501_sysbus_properties[] = { DEFINE_PROP_UINT32("vram-size", SM501SysBusState, vram_size, 0), - DEFINE_PROP_UINT32("base", SM501SysBusState, base, 0), DEFINE_PROP_END_OF_LIST(), }; @@ -2016,15 +2012,19 @@ static void sm501_sysbus_class_init(ObjectClass *klass, void *data) static void sm501_sysbus_init(Object *o) { SM501SysBusState *sm501 = SYSBUS_SM501(o); + OHCISysBusState *ohci = &sm501->ohci; SerialMM *smm = &sm501->serial; + object_initialize_child(o, "ohci", ohci, TYPE_SYSBUS_OHCI); + object_property_add_alias(o, "base", OBJECT(ohci), "dma-offset"); + qdev_prop_set_uint32(DEVICE(ohci), "num-ports", 2); + object_initialize_child(o, "serial", smm, TYPE_SERIAL_MM); qdev_set_legacy_instance_id(DEVICE(smm), SM501_UART0, 2); qdev_prop_set_uint8(DEVICE(smm), "regshift", 2); qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN); - object_property_add_alias(o, "chardev", - OBJECT(smm), "chardev"); + object_property_add_alias(o, "chardev", OBJECT(smm), "chardev"); } static const TypeInfo sm501_sysbus_info = { diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c index 39fc4f19d9..279724ffbb 100644 --- a/hw/sh4/r2d.c +++ b/hw/sh4/r2d.c @@ -274,7 +274,7 @@ static void r2d_init(MachineState *machine) dev = qdev_new("sysbus-sm501"); busdev = SYS_BUS_DEVICE(dev); qdev_prop_set_uint32(dev, "vram-size", SM501_VRAM_SIZE); - qdev_prop_set_uint32(dev, "base", 0x10000000); + qdev_prop_set_uint64(dev, "base", 0x10000000); qdev_prop_set_chr(dev, "chardev", serial_hd(2)); sysbus_realize_and_unref(busdev, &error_fatal); sysbus_mmio_map(busdev, 0, 0x10000000); From patchwork Fri Feb 3 11:36:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 650029 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp765993pva; Fri, 3 Feb 2023 03:39:39 -0800 (PST) X-Google-Smtp-Source: AK7set8eYKziPQRftjYEHwvwyr/NNuHEv9m7B8oqT7b+P1r70k1AXKmdZmpFRKPj5pIAFvaJ7VnB X-Received: by 2002:ad4:4e26:0:b0:536:85d1:1458 with SMTP id dm6-20020ad44e26000000b0053685d11458mr13870914qvb.19.1675424378850; Fri, 03 Feb 2023 03:39:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675424378; cv=none; d=google.com; s=arc-20160816; b=Gdk4Exb9QjS0hdM4UXFoy/zFLsAB+I467FyQh2uKEVK8/mvATEWAFyMbKk1EhR7RUz I03rTzCeiFevh87OANhOw8rGnIY2bYJC+QhbNL9YjCvgXjEcgUd+Mrz6h9zhEhnnwAu+ K4VpuQzopMD0SK/p1N9Dsw9WZm3l5qsP/mwLxpXJcTDbtsY9Ff9NQiawNCqQ2JSni4pi 914RWakwR9g8NRj0JGVZ+thI6yClnNoWnvoUx2TMOBsNjU0aGIAty3A/3LDxmrPEM2Fj GBcXoX77hccym1j8LapRE4wDUASFQEfYza57GdCxahr0bfgh5E6vI3JE1lAjF9uLMTmq yBRg== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id oo32-20020a056214452000b00535182acf77si1565452qvb.466.2023.02.03.03.39.38 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Feb 2023 03:39:38 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DMrWgame; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pNuNn-0008F2-TN; Fri, 03 Feb 2023 06:37:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pNuNm-0008ED-25 for qemu-devel@nongnu.org; Fri, 03 Feb 2023 06:37:30 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pNuNk-0001HC-J6 for qemu-devel@nongnu.org; Fri, 03 Feb 2023 06:37:29 -0500 Received: by mail-wr1-x432.google.com with SMTP id j25so847582wrc.4 for ; Fri, 03 Feb 2023 03:37:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=A0e0NEin6/qB1UWKlWtZ3V9I0KbRtGgK0QPchGtumd0=; b=DMrWgameUQbjcd64+jNpjO/Qc9YTZNVQ3swQhJPAqBtUV/EmghCwdKjgTj5CEKwj4y fRyHuxc7qWci9UnH0yaHbzbtaMWV1iMxTikpF0EmFGbb0bOgHS6VH4pk78Fp7CX+TxzQ HBNXOo8l7OivuOBEfps/QVSKdI5YnJWQcW3r+4El74ckF3cDG35H9R6/iDjvDMS+8QlE jqpxMpgGpr12J1TufqCTxhlPT8jhMH93Sa+mL76OuBCiJ4jqkaQeIcSqA6qd/uvEtbj6 c8v3J4AOIoTuDvneYP78cFFycmOtIj7/ApTV/HoEmxPmRa6zJeR7aMWT/5/JNvjamfoz P53A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=A0e0NEin6/qB1UWKlWtZ3V9I0KbRtGgK0QPchGtumd0=; b=1JlPR7o8KLw7spGd13SYTabzds/95e0fosrlgAp/OTBB56JmWXHhTN6z+EGT4GNAP+ j2JMw+yUUHbDtV+pL+Ppm7309ueKk60Zhp+TwBoo6w+0/xnhQgoMqSWJcCoqBO/k4nSj TER0DRT814phw7N7sVh+E1V4aNzzcP+G38EJCuw5g41UWGcHEmeFthg9DwcWLvEER6TB GPdu1pdJQlUyjBjiCFp/KMIoRAUHpdF49pOMK9YqURbrL+fIZ/YJW+BUfsj0Z0RzA8f6 I+/1PJl6ppxqubMWZIlMogK3qbHOXvAsaJHxshXi1/MlBdGNJoE50Pamk2Pu4xowfzzG 3oRQ== X-Gm-Message-State: AO0yUKWrJNkyYEkIATeTSbBSPht3ENTif8LNsQHKeTW+VLCbFTkKMmjU bVNtE9EIbIYVev+NlQsFLdb7g+hDoFmuTKQC X-Received: by 2002:adf:f68f:0:b0:2bf:ae17:bf58 with SMTP id v15-20020adff68f000000b002bfae17bf58mr9143116wrp.37.1675424247207; Fri, 03 Feb 2023 03:37:27 -0800 (PST) Received: from localhost.localdomain ([81.0.6.76]) by smtp.gmail.com with ESMTPSA id s7-20020adfeb07000000b002bff1de8d4bsm1791560wrn.49.2023.02.03.03.37.26 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 03 Feb 2023 03:37:26 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Markus Armbruster , Eduardo Habkost , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Gerd Hoffmann Subject: [PATCH 7/9] hw/qdev: Remove DEFINE_PROP_DMAADDR() and 'hw/qdev-dma.h' Date: Fri, 3 Feb 2023 12:36:48 +0100 Message-Id: <20230203113650.78146-8-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230203113650.78146-1-philmd@linaro.org> References: <20230203113650.78146-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philmd@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org DEFINE_PROP_DMAADDR() is only used once. Since it doesn't add much value, simply remove it, along with the header defining it. Signed-off-by: Philippe Mathieu-Daudé --- hw/usb/hcd-ohci-pci.c | 1 - hw/usb/hcd-ohci.c | 3 +-- include/hw/qdev-dma.h | 16 ---------------- 3 files changed, 1 insertion(+), 19 deletions(-) delete mode 100644 include/hw/qdev-dma.h diff --git a/hw/usb/hcd-ohci-pci.c b/hw/usb/hcd-ohci-pci.c index 6b630d35a7..92cc151264 100644 --- a/hw/usb/hcd-ohci-pci.c +++ b/hw/usb/hcd-ohci-pci.c @@ -25,7 +25,6 @@ #include "migration/vmstate.h" #include "hw/pci/pci_device.h" #include "hw/sysbus.h" -#include "hw/qdev-dma.h" #include "hw/qdev-properties.h" #include "trace.h" #include "hcd-ohci.h" diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c index 9d68036d23..26c377bf1b 100644 --- a/hw/usb/hcd-ohci.c +++ b/hw/usb/hcd-ohci.c @@ -33,7 +33,6 @@ #include "hw/usb.h" #include "migration/vmstate.h" #include "hw/sysbus.h" -#include "hw/qdev-dma.h" #include "hw/qdev-properties.h" #include "trace.h" #include "hcd-ohci.h" @@ -2008,7 +2007,7 @@ static Property ohci_sysbus_properties[] = { DEFINE_PROP_STRING("masterbus", OHCISysBusState, masterbus), DEFINE_PROP_UINT32("num-ports", OHCISysBusState, num_ports, 3), DEFINE_PROP_UINT32("firstport", OHCISysBusState, firstport, 0), - DEFINE_PROP_DMAADDR("dma-offset", OHCISysBusState, dma_offset, 0), + DEFINE_PROP_UINT64("dma-offset", OHCISysBusState, dma_offset, 0), DEFINE_PROP_END_OF_LIST(), }; diff --git a/include/hw/qdev-dma.h b/include/hw/qdev-dma.h deleted file mode 100644 index b00391aa0c..0000000000 --- a/include/hw/qdev-dma.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Support for dma_addr_t typed properties - * - * Copyright (C) 2012 David Gibson, IBM Corporation. - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#ifndef HW_QDEV_DMA_H -#define HW_QDEV_DMA_H - -#define DEFINE_PROP_DMAADDR(_n, _s, _f, _d) \ - DEFINE_PROP_UINT64(_n, _s, _f, _d) - -#endif From patchwork Fri Feb 3 11:36:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 650032 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp766204pva; Fri, 3 Feb 2023 03:40:12 -0800 (PST) X-Google-Smtp-Source: AK7set9Ng2nfyVfLIDQiskhZvZ2THbfe6b2GPvcwDkNOgQma2zQ8xR63wz10/ILQDhJmFUV53nSB X-Received: by 2002:a05:6214:4944:b0:531:8f76:3eeb with SMTP id pe4-20020a056214494400b005318f763eebmr6292717qvb.6.1675424412776; Fri, 03 Feb 2023 03:40:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675424412; cv=none; d=google.com; s=arc-20160816; b=uUTkYdDMQMIbV9r7gDfEPObyDCUHd7BYX9bSQ0lqrLFjRqz11mOJYXKbiyeRNp61p0 numSndnQ8lAcgqhuI8IRhYUvmvXLSQlichqConSaeXtxU9McAPnUvm3NhsbE9s999+cQ tKv23yGXtHo7htBINbnzQB7amf7fHs3in0lGhCt8+eHak3Xv8G49/aysCnyTLIYvNW2i HJDy3lZF9DrOqceQBm9suB17yrHli1uBirj6TetYYhP7h0TzV3iE2Cg4dy/RKG03B3GJ bFJnwb9ZPiJstknf+aaUowUtEAcgMWlJPJ2/fBStA7+ajxao0D+n1zMkSwHmWa2f2E03 3ilw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=EJd5TtZ9CjeRkTkoWKdyn/Q2ehPN6hId4MKx9NKONbE=; b=pjAvg6k2Rq6WRTDmyrfNXoVqFRQ046D9Ryh4wd0LHjUFJkDTVRzokS4cm7QudQvUdE WjtMR7GupWDwwzgW5mNhcLhnAwdGcHbGIgqYqOvKV/+hHeLANvXcoNWXPyqZHdCpmMjC 8sBNZza4r/MsZk+n3+Y0MZZdBoBTkSgwrf0VzzzgQ9oBOIz3P1vx7wa4ZI4tmqyo9hRc Ht04k1ijgbUhKVEotb300kfZURmGw1KKWOio6/5QctpC8wroagaDoUu5RyCOKYiQFR+t nxZ3jfzMEnoeCfoQQuauGnYjiZsT4/NtTNGce/3jmuInagmseHNiEx5oPTW9DVFd+0rQ FnVg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SkqyVkr9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Fri, 03 Feb 2023 03:37:31 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Markus Armbruster , Eduardo Habkost , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paul Burton , Aleksandar Rikalo , Aurelien Jarno , Jiaxun Yang Subject: [PATCH 8/9] hw/mips: Declare all length properties as unsigned Date: Fri, 3 Feb 2023 12:36:49 +0100 Message-Id: <20230203113650.78146-9-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230203113650.78146-1-philmd@linaro.org> References: <20230203113650.78146-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Some length properties are signed, other unsigned: hw/mips/cps.c:183: DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1), hw/mips/cps.c:184: DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 256), hw/misc/mips_cmgcr.c:215: DEFINE_PROP_INT32("num-vp", MIPSGCRState, num_vps, 1), hw/misc/mips_cpc.c:167: DEFINE_PROP_UINT32("num-vp", MIPSCPCState, num_vp, 0x1), hw/misc/mips_itu.c:552: DEFINE_PROP_INT32("num-fifo", MIPSITUState, num_fifo, hw/misc/mips_itu.c:554: DEFINE_PROP_INT32("num-semaphores", MIPSITUState, Since negative values are not used (the minimum is '0'), unify by declaring all properties as unsigned. Signed-off-by: Philippe Mathieu-Daudé --- hw/intc/mips_gic.c | 4 ++-- hw/mips/boston.c | 2 +- hw/mips/cps.c | 12 ++++++------ hw/mips/malta.c | 2 +- hw/misc/mips_cmgcr.c | 2 +- hw/misc/mips_itu.c | 4 ++-- include/hw/intc/mips_gic.h | 4 ++-- include/hw/misc/mips_cmgcr.h | 2 +- include/hw/misc/mips_itu.h | 4 ++-- 9 files changed, 18 insertions(+), 18 deletions(-) diff --git a/hw/intc/mips_gic.c b/hw/intc/mips_gic.c index bda4549925..4bdc3b1bd1 100644 --- a/hw/intc/mips_gic.c +++ b/hw/intc/mips_gic.c @@ -439,8 +439,8 @@ static void mips_gic_realize(DeviceState *dev, Error **errp) } static Property mips_gic_properties[] = { - DEFINE_PROP_INT32("num-vp", MIPSGICState, num_vps, 1), - DEFINE_PROP_INT32("num-irq", MIPSGICState, num_irq, 256), + DEFINE_PROP_UINT32("num-vp", MIPSGICState, num_vps, 1), + DEFINE_PROP_UINT32("num-irq", MIPSGICState, num_irq, 256), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/mips/boston.c b/hw/mips/boston.c index a9d87f3437..21ad844519 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -702,7 +702,7 @@ static void boston_mach_init(MachineState *machine) object_initialize_child(OBJECT(machine), "cps", &s->cps, TYPE_MIPS_CPS); object_property_set_str(OBJECT(&s->cps), "cpu-type", machine->cpu_type, &error_fatal); - object_property_set_int(OBJECT(&s->cps), "num-vp", machine->smp.cpus, + object_property_set_uint(OBJECT(&s->cps), "num-vp", machine->smp.cpus, &error_fatal); qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", qdev_get_clock_out(dev, "cpu-refclk")); diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 2b436700ce..38acc57468 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -114,9 +114,9 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) /* Inter-Thread Communication Unit */ if (itu_present) { object_initialize_child(OBJECT(dev), "itu", &s->itu, TYPE_MIPS_ITU); - object_property_set_int(OBJECT(&s->itu), "num-fifo", 16, + object_property_set_uint(OBJECT(&s->itu), "num-fifo", 16, &error_abort); - object_property_set_int(OBJECT(&s->itu), "num-semaphores", 16, + object_property_set_uint(OBJECT(&s->itu), "num-semaphores", 16, &error_abort); object_property_set_bool(OBJECT(&s->itu), "saar-present", saar_present, &error_abort); @@ -133,7 +133,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) /* Cluster Power Controller */ object_initialize_child(OBJECT(dev), "cpc", &s->cpc, TYPE_MIPS_CPC); - object_property_set_int(OBJECT(&s->cpc), "num-vp", s->num_vp, + object_property_set_uint(OBJECT(&s->cpc), "num-vp", s->num_vp, &error_abort); object_property_set_int(OBJECT(&s->cpc), "vp-start-running", 1, &error_abort); @@ -146,9 +146,9 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) /* Global Interrupt Controller */ object_initialize_child(OBJECT(dev), "gic", &s->gic, TYPE_MIPS_GIC); - object_property_set_int(OBJECT(&s->gic), "num-vp", s->num_vp, + object_property_set_uint(OBJECT(&s->gic), "num-vp", s->num_vp, &error_abort); - object_property_set_int(OBJECT(&s->gic), "num-irq", 128, + object_property_set_uint(OBJECT(&s->gic), "num-irq", 128, &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { return; @@ -161,7 +161,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) gcr_base = env->CP0_CMGCRBase << 4; object_initialize_child(OBJECT(dev), "gcr", &s->gcr, TYPE_MIPS_GCR); - object_property_set_int(OBJECT(&s->gcr), "num-vp", s->num_vp, + object_property_set_uint(OBJECT(&s->gcr), "num-vp", s->num_vp, &error_abort); object_property_set_int(OBJECT(&s->gcr), "gcr-rev", 0x800, &error_abort); diff --git a/hw/mips/malta.c b/hw/mips/malta.c index ec172b111a..af9021316d 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1066,7 +1066,7 @@ static void create_cps(MachineState *ms, MaltaState *s, object_initialize_child(OBJECT(s), "cps", &s->cps, TYPE_MIPS_CPS); object_property_set_str(OBJECT(&s->cps), "cpu-type", ms->cpu_type, &error_fatal); - object_property_set_int(OBJECT(&s->cps), "num-vp", ms->smp.cpus, + object_property_set_uint(OBJECT(&s->cps), "num-vp", ms->smp.cpus, &error_fatal); qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", s->cpuclk); sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal); diff --git a/hw/misc/mips_cmgcr.c b/hw/misc/mips_cmgcr.c index 3c8b37f700..66eb11662c 100644 --- a/hw/misc/mips_cmgcr.c +++ b/hw/misc/mips_cmgcr.c @@ -212,7 +212,7 @@ static const VMStateDescription vmstate_mips_gcr = { }; static Property mips_gcr_properties[] = { - DEFINE_PROP_INT32("num-vp", MIPSGCRState, num_vps, 1), + DEFINE_PROP_UINT32("num-vp", MIPSGCRState, num_vps, 1), DEFINE_PROP_INT32("gcr-rev", MIPSGCRState, gcr_rev, 0x800), DEFINE_PROP_UINT64("gcr-base", MIPSGCRState, gcr_base, GCR_BASE_ADDR), DEFINE_PROP_LINK("gic", MIPSGCRState, gic_mr, TYPE_MEMORY_REGION, diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index badef5c214..a06cdd10ea 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -549,9 +549,9 @@ static void mips_itu_reset(DeviceState *dev) } static Property mips_itu_properties[] = { - DEFINE_PROP_INT32("num-fifo", MIPSITUState, num_fifo, + DEFINE_PROP_UINT32("num-fifo", MIPSITUState, num_fifo, ITC_FIFO_NUM_MAX), - DEFINE_PROP_INT32("num-semaphores", MIPSITUState, num_semaphores, + DEFINE_PROP_UINT32("num-semaphores", MIPSITUState, num_semaphores, ITC_SEMAPH_NUM_MAX), DEFINE_PROP_BOOL("saar-present", MIPSITUState, saar_present, false), DEFINE_PROP_END_OF_LIST(), diff --git a/include/hw/intc/mips_gic.h b/include/hw/intc/mips_gic.h index eeb136e261..5e4c71edd4 100644 --- a/include/hw/intc/mips_gic.h +++ b/include/hw/intc/mips_gic.h @@ -211,8 +211,8 @@ struct MIPSGICState { /* GIC VP Timer */ MIPSGICTimerState *gic_timer; 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Signed-off-by: Philippe Mathieu-Daudé Tested-by: Jiaxun Yang Reviewed-by: Jiaxun Yang --- RFC because not tested. --- hw/mips/cps.c | 23 ++++++----------------- hw/misc/mips_itu.c | 26 ++++++++++++++++++-------- include/hw/misc/mips_itu.h | 5 ++--- 3 files changed, 26 insertions(+), 28 deletions(-) diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 38acc57468..2b5269ebf1 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -66,20 +66,17 @@ static bool cpu_mips_itu_supported(CPUMIPSState *env) static void mips_cps_realize(DeviceState *dev, Error **errp) { MIPSCPSState *s = MIPS_CPS(dev); - CPUMIPSState *env; - MIPSCPU *cpu; - int i; target_ulong gcr_base; bool itu_present = false; - bool saar_present = false; if (!clock_get(s->clock)) { error_setg(errp, "CPS input clock is not connected to an output clock"); return; } - for (i = 0; i < s->num_vp; i++) { - cpu = MIPS_CPU(object_new(s->cpu_type)); + for (int i = 0; i < s->num_vp; i++) { + MIPSCPU *cpu = MIPS_CPU(object_new(s->cpu_type)); + CPUMIPSState *env = &cpu->env; /* All VPs are halted on reset. Leave powering up to CPC. */ if (!object_property_set_bool(OBJECT(cpu), "start-powered-off", true, @@ -97,7 +94,6 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) cpu_mips_irq_init_cpu(cpu); cpu_mips_clock_init(cpu); - env = &cpu->env; if (cpu_mips_itu_supported(env)) { itu_present = true; /* Attach ITC Tag to the VP */ @@ -107,22 +103,15 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) qemu_register_reset(main_cpu_reset, cpu); } - cpu = MIPS_CPU(first_cpu); - env = &cpu->env; - saar_present = (bool)env->saarp; - /* Inter-Thread Communication Unit */ if (itu_present) { object_initialize_child(OBJECT(dev), "itu", &s->itu, TYPE_MIPS_ITU); + object_property_set_link(OBJECT(&s->itu), "cpu[0]", + OBJECT(first_cpu), &error_abort); object_property_set_uint(OBJECT(&s->itu), "num-fifo", 16, &error_abort); object_property_set_uint(OBJECT(&s->itu), "num-semaphores", 16, &error_abort); - object_property_set_bool(OBJECT(&s->itu), "saar-present", saar_present, - &error_abort); - if (saar_present) { - s->itu.saar = &env->CP0_SAAR; - } if (!sysbus_realize(SYS_BUS_DEVICE(&s->itu), errp)) { return; } @@ -158,7 +147,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic), 0)); /* Global Configuration Registers */ - gcr_base = env->CP0_CMGCRBase << 4; + gcr_base = MIPS_CPU(first_cpu)->env.CP0_CMGCRBase << 4; object_initialize_child(OBJECT(dev), "gcr", &s->gcr, TYPE_MIPS_GCR); object_property_set_uint(OBJECT(&s->gcr), "num-vp", s->num_vp, diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index a06cdd10ea..0eda302db4 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -93,10 +93,10 @@ void itc_reconfigure(MIPSITUState *tag) uint64_t size = (1 * KiB) + (am[1] & ITC_AM1_ADDR_MASK_MASK); bool is_enabled = (am[0] & ITC_AM0_EN_MASK) != 0; - if (tag->saar_present) { - address = ((*(uint64_t *) tag->saar) & 0xFFFFFFFFE000ULL) << 4; - size = 1ULL << ((*(uint64_t *) tag->saar >> 1) & 0x1f); - is_enabled = *(uint64_t *) tag->saar & 1; + if (tag->saar) { + address = (tag->saar[0] & 0xFFFFFFFFE000ULL) << 4; + size = 1ULL << ((tag->saar[0] >> 1) & 0x1f); + is_enabled = tag->saar[0] & 1; } memory_region_transaction_begin(); @@ -157,7 +157,7 @@ static inline ITCView get_itc_view(hwaddr addr) static inline int get_cell_stride_shift(const MIPSITUState *s) { /* Minimum interval (for EntryGain = 0) is 128 B */ - if (s->saar_present) { + if (s->saar) { return 7 + ((s->icr0 >> ITC_ICR0_BLK_GRAIN) & ITC_ICR0_BLK_GRAIN_MASK); } else { @@ -515,6 +515,7 @@ static void mips_itu_init(Object *obj) static void mips_itu_realize(DeviceState *dev, Error **errp) { MIPSITUState *s = MIPS_ITU(dev); + CPUMIPSState *env; if (s->num_fifo > ITC_FIFO_NUM_MAX) { error_setg(errp, "Exceed maximum number of FIFO cells: %d", @@ -526,6 +527,15 @@ static void mips_itu_realize(DeviceState *dev, Error **errp) s->num_semaphores); return; } + if (!s->cpu0) { + error_setg(errp, "Missing 'cpu[0]' property"); + return; + } + + env = &s->cpu0->env; + if (env->saarp) { + s->saar = env->CP0_SAAR; + } s->cell = g_new(ITCStorageCell, get_num_cells(s)); } @@ -534,8 +544,8 @@ static void mips_itu_reset(DeviceState *dev) { MIPSITUState *s = MIPS_ITU(dev); - if (s->saar_present) { - *(uint64_t *) s->saar = 0x11 << 1; + if (s->saar) { + s->saar[0] = 0x11 << 1; s->icr0 = get_num_cells(s) << ITC_ICR0_CELL_NUM; } else { s->ITCAddressMap[0] = 0; @@ -553,7 +563,7 @@ static Property mips_itu_properties[] = { ITC_FIFO_NUM_MAX), DEFINE_PROP_UINT32("num-semaphores", MIPSITUState, num_semaphores, ITC_SEMAPH_NUM_MAX), - DEFINE_PROP_BOOL("saar-present", MIPSITUState, saar_present, false), + DEFINE_PROP_LINK("cpu[0]", MIPSITUState, cpu0, TYPE_MIPS_CPU, MIPSCPU *), DEFINE_PROP_END_OF_LIST(), }; diff --git a/include/hw/misc/mips_itu.h b/include/hw/misc/mips_itu.h index ab6d286c38..35218b2d14 100644 --- a/include/hw/misc/mips_itu.h +++ b/include/hw/misc/mips_itu.h @@ -72,9 +72,8 @@ struct MIPSITUState { uint64_t icr0; /* SAAR */ - bool saar_present; - void *saar; - + uint64_t *saar; + MIPSCPU *cpu0; }; /* Get ITC Configuration Tag memory region. */