From patchwork Thu Feb 2 13:25:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 649830 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01C1BC61DA4 for ; Thu, 2 Feb 2023 13:25:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232145AbjBBNZ0 (ORCPT ); Thu, 2 Feb 2023 08:25:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54660 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232371AbjBBNZU (ORCPT ); Thu, 2 Feb 2023 08:25:20 -0500 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 726CD8C42C for ; Thu, 2 Feb 2023 05:25:18 -0800 (PST) Received: by mail-wm1-x332.google.com with SMTP id c10-20020a05600c0a4a00b003db0636ff84so1410705wmq.0 for ; Thu, 02 Feb 2023 05:25:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kLJ4DV7E0niWNy6tOT/hHjHASHjhkW4C34ZhSSnAdZg=; b=ofteobDsv40WYQLoQOlb8KFA9omA1BEgv6c/IhqVbAGa8eY3/YULcKLfHPI+Qmx8Fc KSPID2Ne1PuokQBCY+1qbyPc8bXhr1bNxG08zVR05jQDoyTSTcH0w6/3bbKiznWSTGD1 pSBsT2s6+gWi0+DE1ZasXkZgNIR3u/9+36pijZSXbdxnBcoTGFwTlDe54HlWToSdnSJK glWwMAY18K9Vm42k8SiV1lKC6rg78qQzm6JVSpO0elggE+dE/BikopgNIhgtbp5oY4GH KF/jjvmX/A+b9S+9FK8e1GE37KvMD8jKYf08LthFVdZ8QwsMhzAJXjIb6DEof1qLQJma gcwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kLJ4DV7E0niWNy6tOT/hHjHASHjhkW4C34ZhSSnAdZg=; b=gITJDHHdxOnLFTMOBGa5Axi+MsJriXJdwsoNdTk9o5BEPt0wV5PegiDVpaYbcSDv6l 9qlDfXYEsLOUeVANGjkouUEZRKAnIQ2dYm44V2orz89FUiNJhzsTx/ESaAOu+xPGXcpg CUz+fM1VdEkgHphJTCIi122rx73bTJuABSjM2hCOUZJi0w9qfY7T7c58tITHiL3YZgWG kEcR1AqbgzWB0qGxMzalQ/bX7iaNsTUVnVY+2dzfAZHCPkBSAZOEgBQun5n27bHzF56J gVgQnjaU4E/Go2geRNPwN7lId2MJFgmMNfoR0f0YjYP0jfgeP0Ssy8Xiw6Sv9/A5k7iC y0eg== X-Gm-Message-State: AO0yUKXKViYbgidOSXCbprcoeyf9LT8iVcwU2/vWjTNtA7nxsYMHifcZ JVkCCaDXhU1CM+3IXE08q6pjKg== X-Google-Smtp-Source: AK7set9DSvP7/QovInJVXQkn4RrV6sOo4/86oqVLztYB0oToBfJZ3aSbRacwvcnDXI+liFRiQ+fFvg== X-Received: by 2002:a05:600c:c1b:b0:3df:dea7:8e3 with SMTP id fm27-20020a05600c0c1b00b003dfdea708e3mr1663720wmb.21.1675344316884; Thu, 02 Feb 2023 05:25:16 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id e22-20020a05600c449600b003db06224953sm4690943wmo.41.2023.02.02.05.25.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Feb 2023 05:25:16 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , "vkoul@kernel.org" , Kishon Vijay Abraham I Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Linux Kernel Mailing List Subject: [PATCH v4 2/8] phy: qcom: Add QCOM SNPS eUSB2 driver Date: Thu, 2 Feb 2023 15:25:05 +0200 Message-Id: <20230202132511.3983095-3-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230202132511.3983095-1-abel.vesa@linaro.org> References: <20230202132511.3983095-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The SM8550 SoC uses Synopsis eUSB2 PHY for USB 2.0. Add a new driver for it. The driver is based on a downstream implementation. Signed-off-by: Abel Vesa --- The v3 version of this patch was here: https://lore.kernel.org/all/20230126131415.1453741-3-abel.vesa@linaro.org/ Changes since v3: * none Changes since v2: * this time actually dropped the qcom_snps_, which I missed in the v2 * this time actually added the new lines after break in switch clause, as Vinod suggested, which I missed in the v2 Changes since v1: * replaced qualcomm with qcom in subject line * dropped all unnecessary includes * dropped qcom_snps prefix from qcom_snps_eusb2_hsphy_vreg_names * properly aligned the arguments for qcom_snps_eusb2_hsphy_write_mask * added empty lines after break in switch clause, like Vinod suggested drivers/phy/qualcomm/Kconfig | 9 + drivers/phy/qualcomm/Makefile | 1 + drivers/phy/qualcomm/phy-qcom-snps-eusb2.c | 423 +++++++++++++++++++++ 3 files changed, 433 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-snps-eusb2.c diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig index eb9ddc685b38..27b5a2a3637d 100644 --- a/drivers/phy/qualcomm/Kconfig +++ b/drivers/phy/qualcomm/Kconfig @@ -70,6 +70,15 @@ config PHY_QCOM_QUSB2 PHY which is usually paired with either the ChipIdea or Synopsys DWC3 USB IPs on MSM SOCs. +config PHY_QCOM_SNPS_EUSB2 + tristate "Qualcomm SNPS eUSB2 PHY Driver" + depends on OF && (ARCH_QCOM || COMPILE_TEST) + select GENERIC_PHY + help + Enable support for the USB high-speed SNPS eUSB2 phy on Qualcomm + chipsets. The PHY is paired with a Synopsys DWC3 USB controller + on Qualcomm SOCs. + config PHY_QCOM_USB_HS tristate "Qualcomm USB HS PHY module" depends on USB_ULPI_BUS diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile index 65f6c30a3e93..3ee118f4dfc7 100644 --- a/drivers/phy/qualcomm/Makefile +++ b/drivers/phy/qualcomm/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_PHY_QCOM_QMP) += \ phy-qcom-qmp-usb.o obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o +obj-$(CONFIG_PHY_QCOM_SNPS_EUSB2) += phy-qcom-snps-eusb2.o obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o diff --git a/drivers/phy/qualcomm/phy-qcom-snps-eusb2.c b/drivers/phy/qualcomm/phy-qcom-snps-eusb2.c new file mode 100644 index 000000000000..23ec162cc3bd --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-snps-eusb2.c @@ -0,0 +1,423 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include + +#define USB_PHY_UTMI_CTRL0 (0x3c) +#define SLEEPM BIT(0) +#define OPMODE_MASK GENMASK(4, 3) +#define OPMODE_NONDRIVING BIT(3) + +#define USB_PHY_UTMI_CTRL5 (0x50) +#define POR BIT(1) + +#define USB_PHY_HS_PHY_CTRL_COMMON0 (0x54) +#define PHY_ENABLE BIT(0) +#define SIDDQ_SEL BIT(1) +#define SIDDQ BIT(2) +#define RETENABLEN BIT(3) +#define FSEL_MASK GENMASK(6, 4) +#define FSEL_19_2_MHZ_VAL (0x0) +#define FSEL_38_4_MHZ_VAL (0x4) + +#define USB_PHY_CFG_CTRL_1 (0x58) +#define PHY_CFG_PLL_CPBIAS_CNTRL_MASK GENMASK(7, 1) + +#define USB_PHY_CFG_CTRL_2 (0x5c) +#define PHY_CFG_PLL_FB_DIV_7_0_MASK GENMASK(7, 0) +#define DIV_7_0_19_2_MHZ_VAL (0x90) +#define DIV_7_0_38_4_MHZ_VAL (0xc8) + +#define USB_PHY_CFG_CTRL_3 (0x60) +#define PHY_CFG_PLL_FB_DIV_11_8_MASK GENMASK(3, 0) +#define DIV_11_8_19_2_MHZ_VAL (0x1) +#define DIV_11_8_38_4_MHZ_VAL (0x0) + +#define PHY_CFG_PLL_REF_DIV GENMASK(7, 4) +#define PLL_REF_DIV_VAL (0x0) + +#define USB_PHY_HS_PHY_CTRL2 (0x64) +#define VBUSVLDEXT0 BIT(0) +#define USB2_SUSPEND_N BIT(2) +#define USB2_SUSPEND_N_SEL BIT(3) +#define VBUS_DET_EXT_SEL BIT(4) + +#define USB_PHY_CFG_CTRL_4 (0x68) +#define PHY_CFG_PLL_GMP_CNTRL_MASK GENMASK(1, 0) +#define PHY_CFG_PLL_INT_CNTRL_MASK GENMASK(7, 2) + +#define USB_PHY_CFG_CTRL_5 (0x6c) +#define PHY_CFG_PLL_PROP_CNTRL_MASK GENMASK(4, 0) +#define PHY_CFG_PLL_VREF_TUNE_MASK GENMASK(7, 6) + +#define USB_PHY_CFG_CTRL_6 (0x70) +#define PHY_CFG_PLL_VCO_CNTRL_MASK GENMASK(2, 0) + +#define USB_PHY_CFG_CTRL_7 (0x74) + +#define USB_PHY_CFG_CTRL_8 (0x78) +#define PHY_CFG_TX_FSLS_VREF_TUNE_MASK GENMASK(1, 0) +#define PHY_CFG_TX_FSLS_VREG_BYPASS BIT(2) +#define PHY_CFG_TX_HS_VREF_TUNE_MASK GENMASK(5, 3) +#define PHY_CFG_TX_HS_XV_TUNE_MASK GENMASK(7, 6) + +#define USB_PHY_CFG_CTRL_9 (0x7c) +#define PHY_CFG_TX_PREEMP_TUNE_MASK GENMASK(2, 0) +#define PHY_CFG_TX_RES_TUNE_MASK GENMASK(4, 3) +#define PHY_CFG_TX_RISE_TUNE_MASK GENMASK(6, 5) +#define PHY_CFG_RCAL_BYPASS BIT(7) + +#define USB_PHY_CFG_CTRL_10 (0x80) + +#define USB_PHY_CFG0 (0x94) +#define DATAPATH_CTRL_OVERRIDE_EN BIT(0) +#define CMN_CTRL_OVERRIDE_EN BIT(1) + +#define UTMI_PHY_CMN_CTRL0 (0x98) +#define TESTBURNIN BIT(6) + +#define USB_PHY_FSEL_SEL (0xb8) +#define FSEL_SEL BIT(0) + +#define USB_PHY_APB_ACCESS_CMD (0x130) +#define RW_ACCESS BIT(0) +#define APB_START_CMD BIT(1) +#define APB_LOGIC_RESET BIT(2) + +#define USB_PHY_APB_ACCESS_STATUS (0x134) +#define ACCESS_DONE BIT(0) +#define TIMED_OUT BIT(1) +#define ACCESS_ERROR BIT(2) +#define ACCESS_IN_PROGRESS BIT(3) + +#define USB_PHY_APB_ADDRESS (0x138) +#define APB_REG_ADDR_MASK GENMASK(7, 0) + +#define USB_PHY_APB_WRDATA_LSB (0x13c) +#define APB_REG_WRDATA_7_0_MASK GENMASK(3, 0) + +#define USB_PHY_APB_WRDATA_MSB (0x140) +#define APB_REG_WRDATA_15_8_MASK GENMASK(7, 4) + +#define USB_PHY_APB_RDDATA_LSB (0x144) +#define APB_REG_RDDATA_7_0_MASK GENMASK(3, 0) + +#define USB_PHY_APB_RDDATA_MSB (0x148) +#define APB_REG_RDDATA_15_8_MASK GENMASK(7, 4) + +static const char * const eusb2_hsphy_vreg_names[] = { + "vdd", "vdda12", +}; + +#define EUSB2_NUM_VREGS ARRAY_SIZE(eusb2_hsphy_vreg_names) + +struct qcom_snps_eusb2_hsphy { + struct phy *phy; + void __iomem *base; + + struct clk *ref_clk; + struct reset_control *phy_reset; + + struct regulator_bulk_data vregs[EUSB2_NUM_VREGS]; + + enum phy_mode mode; +}; + +static int qcom_snps_eusb2_hsphy_set_mode(struct phy *p, enum phy_mode mode, int submode) +{ + struct qcom_snps_eusb2_hsphy *phy = phy_get_drvdata(p); + + phy->mode = mode; + + return 0; +} + +static void qcom_snps_eusb2_hsphy_write_mask(void __iomem *base, u32 offset, + u32 mask, u32 val) +{ + u32 reg; + + reg = readl_relaxed(base + offset); + reg &= ~mask; + reg |= val & mask; + writel_relaxed(reg, base + offset); + + /* Ensure above write is completed */ + readl_relaxed(base + offset); +} + +static void qcom_eusb2_default_parameters(struct qcom_snps_eusb2_hsphy *phy) +{ + /* default parameters: tx pre-emphasis */ + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_9, + PHY_CFG_TX_PREEMP_TUNE_MASK, + FIELD_PREP(PHY_CFG_TX_PREEMP_TUNE_MASK, 0)); + + /* tx rise/fall time */ + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_9, + PHY_CFG_TX_RISE_TUNE_MASK, + FIELD_PREP(PHY_CFG_TX_RISE_TUNE_MASK, 0x2)); + + /* source impedance adjustment */ + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_9, + PHY_CFG_TX_RES_TUNE_MASK, + FIELD_PREP(PHY_CFG_TX_RES_TUNE_MASK, 0x1)); + + /* dc voltage level adjustement */ + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_8, + PHY_CFG_TX_HS_VREF_TUNE_MASK, + FIELD_PREP(PHY_CFG_TX_HS_VREF_TUNE_MASK, 0x3)); + + /* transmitter HS crossover adjustement */ + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_8, + PHY_CFG_TX_HS_XV_TUNE_MASK, + FIELD_PREP(PHY_CFG_TX_HS_XV_TUNE_MASK, 0x0)); +} + +static int qcom_eusb2_ref_clk_init(struct qcom_snps_eusb2_hsphy *phy) +{ + unsigned long ref_clk_freq = clk_get_rate(phy->ref_clk); + + switch (ref_clk_freq) { + case 19200000: + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0, + FSEL_MASK, + FIELD_PREP(FSEL_MASK, FSEL_19_2_MHZ_VAL)); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_2, + PHY_CFG_PLL_FB_DIV_7_0_MASK, + DIV_7_0_19_2_MHZ_VAL); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_3, + PHY_CFG_PLL_FB_DIV_11_8_MASK, + DIV_11_8_19_2_MHZ_VAL); + break; + + case 38400000: + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0, + FSEL_MASK, + FIELD_PREP(FSEL_MASK, FSEL_38_4_MHZ_VAL)); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_2, + PHY_CFG_PLL_FB_DIV_7_0_MASK, + DIV_7_0_38_4_MHZ_VAL); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_3, + PHY_CFG_PLL_FB_DIV_11_8_MASK, + DIV_11_8_38_4_MHZ_VAL); + break; + + default: + dev_err(&phy->phy->dev, "unsupported ref_clk_freq:%lu\n", + ref_clk_freq); + return -EINVAL; + } + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_3, + PHY_CFG_PLL_REF_DIV, PLL_REF_DIV_VAL); + + return 0; +} + +static int qcom_snps_eusb2_hsphy_init(struct phy *p) +{ + struct qcom_snps_eusb2_hsphy *phy = phy_get_drvdata(p); + int ret; + + ret = regulator_bulk_enable(ARRAY_SIZE(phy->vregs), phy->vregs); + if (ret) + return ret; + + ret = clk_prepare_enable(phy->ref_clk); + if (ret) { + dev_err(&p->dev, "failed to enable ref clock, %d\n", ret); + goto disable_vreg; + } + + ret = reset_control_assert(phy->phy_reset); + if (ret) { + dev_err(&p->dev, "failed to assert phy_reset, %d\n", ret); + goto disable_ref_clk; + } + + usleep_range(100, 150); + + ret = reset_control_deassert(phy->phy_reset); + if (ret) { + dev_err(&p->dev, "failed to de-assert phy_reset, %d\n", ret); + goto disable_ref_clk; + } + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG0, + CMN_CTRL_OVERRIDE_EN, CMN_CTRL_OVERRIDE_EN); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_UTMI_CTRL5, POR, POR); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0, + PHY_ENABLE | RETENABLEN, PHY_ENABLE | RETENABLEN); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_APB_ACCESS_CMD, + APB_LOGIC_RESET, APB_LOGIC_RESET); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, UTMI_PHY_CMN_CTRL0, TESTBURNIN, 0); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_FSEL_SEL, + FSEL_SEL, FSEL_SEL); + + /* update ref_clk related registers */ + ret = qcom_eusb2_ref_clk_init(phy); + if (ret) + goto disable_ref_clk; + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_1, + PHY_CFG_PLL_CPBIAS_CNTRL_MASK, + FIELD_PREP(PHY_CFG_PLL_CPBIAS_CNTRL_MASK, 0x1)); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_4, + PHY_CFG_PLL_INT_CNTRL_MASK, + FIELD_PREP(PHY_CFG_PLL_INT_CNTRL_MASK, 0x8)); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_4, + PHY_CFG_PLL_GMP_CNTRL_MASK, + FIELD_PREP(PHY_CFG_PLL_GMP_CNTRL_MASK, 0x1)); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_5, + PHY_CFG_PLL_PROP_CNTRL_MASK, + FIELD_PREP(PHY_CFG_PLL_PROP_CNTRL_MASK, 0x10)); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_6, + PHY_CFG_PLL_VCO_CNTRL_MASK, + FIELD_PREP(PHY_CFG_PLL_VCO_CNTRL_MASK, 0x0)); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_5, + PHY_CFG_PLL_VREF_TUNE_MASK, + FIELD_PREP(PHY_CFG_PLL_VREF_TUNE_MASK, 0x1)); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL2, + VBUS_DET_EXT_SEL, VBUS_DET_EXT_SEL); + + /* set default parameters */ + qcom_eusb2_default_parameters(phy); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL2, + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N, + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_UTMI_CTRL0, SLEEPM, SLEEPM); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0, + SIDDQ_SEL, SIDDQ_SEL); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0, + SIDDQ, 0); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_UTMI_CTRL5, POR, 0); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL2, + USB2_SUSPEND_N_SEL, 0); + + return 0; + +disable_ref_clk: + clk_disable_unprepare(phy->ref_clk); + +disable_vreg: + regulator_bulk_disable(ARRAY_SIZE(phy->vregs), phy->vregs); + + return ret; +} + +static int qcom_snps_eusb2_hsphy_exit(struct phy *p) +{ + struct qcom_snps_eusb2_hsphy *phy = phy_get_drvdata(p); + + clk_disable_unprepare(phy->ref_clk); + + regulator_bulk_disable(ARRAY_SIZE(phy->vregs), phy->vregs); + + return 0; +} + +static const struct phy_ops qcom_snps_eusb2_hsphy_ops = { + .init = qcom_snps_eusb2_hsphy_init, + .exit = qcom_snps_eusb2_hsphy_exit, + .set_mode = qcom_snps_eusb2_hsphy_set_mode, + .owner = THIS_MODULE, +}; + +static int qcom_snps_eusb2_hsphy_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct qcom_snps_eusb2_hsphy *phy; + struct phy_provider *phy_provider; + struct phy *generic_phy; + int ret, i; + int num; + + phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); + if (!phy) + return -ENOMEM; + + phy->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(phy->base)) + return PTR_ERR(phy->base); + + phy->phy_reset = devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(phy->phy_reset)) + return PTR_ERR(phy->phy_reset); + + phy->ref_clk = devm_clk_get(dev, "ref"); + if (IS_ERR(phy->ref_clk)) + return dev_err_probe(dev, PTR_ERR(phy->ref_clk), + "failed to get ref clk\n"); + + num = ARRAY_SIZE(phy->vregs); + for (i = 0; i < num; i++) + phy->vregs[i].supply = eusb2_hsphy_vreg_names[i]; + + ret = devm_regulator_bulk_get(dev, num, phy->vregs); + if (ret) + return dev_err_probe(dev, ret, + "failed to get regulator supplies\n"); + generic_phy = devm_phy_create(dev, NULL, &qcom_snps_eusb2_hsphy_ops); + if (IS_ERR(generic_phy)) { + dev_err(dev, "failed to create phy %d\n", ret); + return PTR_ERR(generic_phy); + } + + dev_set_drvdata(dev, phy); + phy_set_drvdata(generic_phy, phy); + + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + if (IS_ERR(phy_provider)) + return PTR_ERR(phy_provider); + + dev_info(dev, "Registered Qcom-eUSB2 phy\n"); + + return 0; +} + +static const struct of_device_id qcom_snps_eusb2_hsphy_of_match_table[] = { + { .compatible = "qcom,sm8550-snps-eusb2-phy", }, + { }, +}; +MODULE_DEVICE_TABLE(of, qcom_snps_eusb2_hsphy_of_match_table); + +static struct platform_driver qcom_snps_eusb2_hsphy_driver = { + .probe = qcom_snps_eusb2_hsphy_probe, + .driver = { + .name = "qcom-snps-eusb2-hsphy", + .of_match_table = qcom_snps_eusb2_hsphy_of_match_table, + }, +}; + +module_platform_driver(qcom_snps_eusb2_hsphy_driver); +MODULE_DESCRIPTION("Qualcomm SNPS eUSB2 HS PHY driver"); +MODULE_LICENSE("GPL"); From patchwork Thu Feb 2 13:25:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 649829 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04DDEC64EC5 for ; Thu, 2 Feb 2023 13:25:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232475AbjBBNZ1 (ORCPT ); Thu, 2 Feb 2023 08:25:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54852 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232394AbjBBNZZ (ORCPT ); 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Thu, 02 Feb 2023 05:25:18 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , "vkoul@kernel.org" , Kishon Vijay Abraham I Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Linux Kernel Mailing List Subject: [PATCH v4 4/8] phy: qcom-qmp: pcs-usb: Add v6 register offsets Date: Thu, 2 Feb 2023 15:25:07 +0200 Message-Id: <20230202132511.3983095-5-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230202132511.3983095-1-abel.vesa@linaro.org> References: <20230202132511.3983095-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB. Add the new PCS USB specific offsets in a dedicated header file. Signed-off-by: Abel Vesa --- The v3 version of this patch was here: https://lore.kernel.org/all/20230126131415.1453741-5-abel.vesa@linaro.org/ Changes since v3: * none Changes since v2: * none Changes since v1: * split all the offsets into separate patches, like Vinod suggested drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 1 + .../phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h | 31 +++++++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c index 1f022e580407..86032dc4e24e 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -26,6 +26,7 @@ #include "phy-qcom-qmp-pcs-misc-v3.h" #include "phy-qcom-qmp-pcs-usb-v4.h" #include "phy-qcom-qmp-pcs-usb-v5.h" +#include "phy-qcom-qmp-pcs-usb-v6.h" /* QPHY_SW_RESET bit */ #define SW_RESET BIT(0) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h new file mode 100644 index 000000000000..9510e63ba9d8 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_USB_V6_H_ +#define QCOM_PHY_QMP_PCS_USB_V6_H_ + +/* Only for QMP V6 PHY - USB3 have different offsets than V5 */ +#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG1 0xc4 +#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG2 0xc8 +#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG3 0xcc +#define QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG6 0xd8 +#define QPHY_USB_V6_PCS_REFGEN_REQ_CONFIG1 0xdc +#define QPHY_USB_V6_PCS_USB3_POWER_STATE_CONFIG1 0x90 +#define QPHY_USB_V6_PCS_RX_SIGDET_LVL 0x188 +#define QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 +#define QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 +#define QPHY_USB_V6_PCS_CDR_RESET_TIME 0x1b0 +#define QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG1 0x1c0 +#define QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG2 0x1c4 +#define QPHY_USB_V6_PCS_PCS_TX_RX_CONFIG 0x1d0 +#define QPHY_USB_V6_PCS_EQ_CONFIG1 0x1dc +#define QPHY_USB_V6_PCS_EQ_CONFIG5 0x1ec + +#define QPHY_USB_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x18 +#define QPHY_USB_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x3c +#define QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40 +#define QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x44 + +#endif From patchwork Thu Feb 2 13:25:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 649828 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 398FFC636D6 for ; Thu, 2 Feb 2023 13:25:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232431AbjBBNZa (ORCPT ); Thu, 2 Feb 2023 08:25:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54858 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232390AbjBBNZ1 (ORCPT ); Thu, 2 Feb 2023 08:25:27 -0500 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9A6818F508 for ; Thu, 2 Feb 2023 05:25:23 -0800 (PST) Received: by mail-wm1-x332.google.com with SMTP id j29-20020a05600c1c1d00b003dc52fed235so1394199wms.1 for ; Thu, 02 Feb 2023 05:25:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IuSrh/aHOSE5N204zdrXun9rXbJUm4pY9kguGFMi0kc=; b=yy90TcgeT3mhGmCRfkVKt8tqKf3ktDl3EmwPoA87gp79LykqWwxmw9pZmy9Bw1PFyT 58+JAJfYkvwN4G6WWu2LSrG3iWXV1dIrkBnSfx0nh+A2XtC3giocFEF4iAdD7blWe+Hu oAw//rUnS+CvVQaOKTp4EM8h3iLvhM6LISEJDX6cynQV+df+FDW4PkDaahs3xptlU3Cx cBSjr6Ei7tE/OHWjEWHWfmNzxbnq4F3Ks8YKoHbyJHqnzh5W9NfxSocrDKzlD++fYid0 M6EGi6JBoQpUcP7fizWPQhtHB/P93ASefnhd/T+zhp6jGYy+Asns1+MZxNfSyAeK0VxC hDfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IuSrh/aHOSE5N204zdrXun9rXbJUm4pY9kguGFMi0kc=; b=O+RZ3xkvKNnyYkRuxjR2qafT3HfILjZd1bGhv8gOL3/Im11xGT7Iyngxo9o/zIibJw +QQmziYfpkFoM65iUpCGP+EXX06jFsUdIBf+l8DPeuj6OUXIPwb8U/o81bgI0Q3g4Aes T91QPObVmCFAC6HFvlJ0lfAtpXwJoMgkEegxkCx4Y8pK4eW/UNuN4SU12oZ98VRXoL3B FSwfCVUuKx2RAYWE96NTQnFRTCAn/kpUXgeAXw+nTqb0quSIZJxQ280lfNYLCLopvuDn KKXuz4euBrqK11grJUjqCOK/5oA7+8ciDHaFCGCmdgsdIO8zetuzT+GigdtxSE/x+UK7 +X9w== X-Gm-Message-State: AO0yUKUY6e1W4+Xr4hR15Ypcrodwr7curL9zQCnR5CgxRrhwKG2/9EmT VxWpwo9QPCeUNjr+kXHzUH/msA== X-Google-Smtp-Source: AK7set8QMVWQ4U5FU8+F4i5jUjMRtq/bTrtFeNmWqAHKQmb1to7WpUsR/5jVurQrMxqo8uAQ0P4NFA== X-Received: by 2002:a05:600c:3d8d:b0:3df:9858:c035 with SMTP id bi13-20020a05600c3d8d00b003df9858c035mr1774715wmb.10.1675344322061; Thu, 02 Feb 2023 05:25:22 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id e22-20020a05600c449600b003db06224953sm4690943wmo.41.2023.02.02.05.25.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Feb 2023 05:25:21 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , "vkoul@kernel.org" , Kishon Vijay Abraham I Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Linux Kernel Mailing List Subject: [PATCH v4 6/8] phy: qcom-qmp-combo: Add support for SM8550 Date: Thu, 2 Feb 2023 15:25:09 +0200 Message-Id: <20230202132511.3983095-7-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230202132511.3983095-1-abel.vesa@linaro.org> References: <20230202132511.3983095-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add SM8550 specific register layout and table configs. Signed-off-by: Abel Vesa --- The v3 version of this patch was here: https://lore.kernel.org/all/20230126131415.1453741-7-abel.vesa@linaro.org/ Changes since v3: * switched dp_tx and dp_tx2 to off->dp_tx0 and off->dp_tx1, like Neil suggested Changes since v2: * none Changes since v1: * switched from qmp-usb to qmp-combo as it will support DP also * changed all hex offset values to lowercase, like Vinod suggested drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 409 +++++++++++++++++++++- 1 file changed, 404 insertions(+), 5 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c index 86032dc4e24e..36c799fff416 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -493,6 +493,145 @@ static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), }; +static const struct qmp_phy_init_tbl sm8550_usb3_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x41), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x41), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x75), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x75), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c), +}; + +static const struct qmp_phy_init_tbl sm8550_usb3_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_TX, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_RX, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0xf5), + QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_3, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_5, 0x5f), + QMP_PHY_INIT_CFG(QSERDES_V6_TX_RCV_DETECT_LVL_2, 0x12), + QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x21, 1), + QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x05, 2), +}; + +static const struct qmp_phy_init_tbl sm8550_usb3_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_PI_CONTROLS, 0x99), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN2, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL1, 0x54), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x13), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CNTRL, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1d), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_EN_TIMER, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_DCC_CTRL1, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_VTH_CODE, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_CTRL1, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08), + + QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f, 1), + QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 1), + QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xff, 1), + QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 1), + QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xed, 1), + + QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0xbf, 2), + QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 2), + QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf, 2), + QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 2), + QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xfd, 2), +}; + +static const struct qmp_phy_init_tbl sm8550_usb3_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4), + QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG2, 0x89), + QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG3, 0x20), + QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG6, 0x13), + QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_REFGEN_REQ_CONFIG1, 0x21), + QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_RX_SIGDET_LVL, 0x99), + QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), + QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), + QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_CDR_RESET_TIME, 0x0a), + QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG1, 0x88), + QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG2, 0x13), + QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_PCS_TX_RX_CONFIG, 0x0c), + QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_EQ_CONFIG1, 0x4b), + QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_EQ_CONFIG5, 0x10), + QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_POWER_STATE_CONFIG1, 0x68), +}; + +static const struct qmp_phy_init_tbl sm8550_usb3_pcs_usb_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), + QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), + QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), + QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), +}; + static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), @@ -614,6 +753,91 @@ static const struct qmp_phy_init_tbl qmp_v5_5nm_dp_tx_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TX_BAND, 0x01), }; +static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x15), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x17), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x0f), +}; + +static const struct qmp_phy_init_tbl qmp_v6_dp_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_TX_VMODE_CTRL1, 0x40), + QMP_PHY_INIT_CFG(QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V6_TX_INTERFACE_SELECT, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V6_TX_CLKBUF_ENABLE, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V6_TX_RESET_TSYNC_EN, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V6_TX_TRAN_DRVR_EMP_EN, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_INTERFACE_MODE, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_BAND, 0x4), +}; + +static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_rbr[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x37), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), +}; + +static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), +}; + +static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr2[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x46), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x97), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x10), +}; + +static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr3[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x17), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x15), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), +}; + static const struct qmp_phy_init_tbl sc8280xp_usb43dp_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), @@ -795,6 +1019,13 @@ static const u8 qmp_dp_v5_voltage_swing_hbr_rbr[4][4] = { { 0x3f, 0xff, 0xff, 0xff } }; +static const u8 qmp_dp_v6_pre_emphasis_hbr_rbr[4][4] = { + { 0x20, 0x2d, 0x34, 0x3a }, + { 0x20, 0x2e, 0x35, 0xff }, + { 0x20, 0x2e, 0xff, 0xff }, + { 0x22, 0xff, 0xff, 0xff } +}; + struct qmp_combo; struct qmp_combo_offsets { @@ -808,6 +1039,8 @@ struct qmp_combo_offsets { u16 usb3_pcs; u16 usb3_pcs_usb; u16 dp_serdes; + u16 dp_tx0; + u16 dp_tx1; u16 dp_dp_phy; }; @@ -927,6 +1160,9 @@ static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp); static int qmp_v5_configure_dp_phy(struct qmp_combo *qmp); +static void qmp_v6_dp_aux_init(struct qmp_combo *qmp); +static int qmp_v6_configure_dp_phy(struct qmp_combo *qmp); + static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) { u32 reg; @@ -985,9 +1221,27 @@ static const struct qmp_combo_offsets qmp_combo_offsets_v5 = { .usb3_pcs = 0x1400, .usb3_pcs_usb = 0x1700, .dp_serdes = 0x2000, + .dp_tx0 = 0x2200, + .dp_tx1 = 0x2600, .dp_dp_phy = 0x2200, }; +static const struct qmp_combo_offsets qmp_combo_offsets_v6 = { + .com = 0x0000, + .txa = 0x1200, + .rxa = 0x1400, + .txb = 0x1600, + .rxb = 0x1800, + .usb3_serdes = 0x1000, + .usb3_pcs_misc = 0x1a00, + .usb3_pcs = 0x1c00, + .usb3_pcs_usb = 0x1f00, + .dp_serdes = 0x2000, + .dp_tx0 = 0x2200, + .dp_tx1 = 0x2600, + .dp_dp_phy = 0x2a00, +}; + static const struct qmp_phy_cfg sc7180_usb3dpphy_cfg = { .serdes_tbl = qmp_v3_usb3_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), @@ -1219,6 +1473,54 @@ static const struct qmp_phy_cfg sm8250_usb3dpphy_cfg = { .has_pwrdn_delay = true, }; +static const struct qmp_phy_cfg sm8550_usb3dpphy_cfg = { + .offsets = &qmp_combo_offsets_v6, + + .serdes_tbl = sm8550_usb3_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(sm8550_usb3_serdes_tbl), + .tx_tbl = sm8550_usb3_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(sm8550_usb3_tx_tbl), + .rx_tbl = sm8550_usb3_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(sm8550_usb3_rx_tbl), + .pcs_tbl = sm8550_usb3_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_tbl), + .pcs_usb_tbl = sm8550_usb3_pcs_usb_tbl, + .pcs_usb_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl), + + .dp_serdes_tbl = qmp_v6_dp_serdes_tbl, + .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl), + .dp_tx_tbl = qmp_v6_dp_tx_tbl, + .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl), + + .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr, + .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), + .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr, + .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), + .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2, + .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), + .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3, + .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), + + .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, + .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, + .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, + .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, + + .dp_aux_init = qmp_v6_dp_aux_init, + .configure_dp_tx = qmp_v4_configure_dp_tx, + .configure_dp_phy = qmp_v6_configure_dp_phy, + .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, + + .regs = qmp_v4_usb3phy_regs_layout, + .clk_list = qmp_v4_phy_clk_l, + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), + .reset_list = msm8996_usb3phy_reset_l, + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .pcs_usb_offset = 0x300, +}; + static void qmp_combo_configure_lane(void __iomem *base, const struct qmp_phy_init_tbl tbl[], int num, @@ -1529,6 +1831,33 @@ static void qmp_v4_dp_aux_init(struct qmp_combo *qmp) qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); } +static void qmp_v6_dp_aux_init(struct qmp_combo *qmp) +{ + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, + qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); + + /* Turn on BIAS current for PHY/PLL */ + writel(0x17, qmp->dp_serdes + QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN); + + writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); + writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); + writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); + writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); + writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); + writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); + writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); + writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); + writel(0xb7, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); + writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); + qmp->dp_aux_cfg = 0; + + writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | + PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | + PHY_AUX_REQ_ERR_MASK, + qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); +} + static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp) { /* Program default values before writing proper values */ @@ -1542,7 +1871,10 @@ static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp) QSERDES_V4_TX_TX_EMP_POST1_LVL); } -static int qmp_v45_configure_dp_phy(struct qmp_combo *qmp) +static int qmp_v456_configure_dp_phy(struct qmp_combo *qmp, + unsigned int com_resetm_ctrl_reg, + unsigned int com_c_ready_status_reg, + unsigned int dp_phy_status_reg) { const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; u32 phy_vco_div, status; @@ -1639,7 +1971,9 @@ static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp) u32 status; int ret; - ret = qmp_v45_configure_dp_phy(qmp); + ret = qmp_v456_configure_dp_phy(qmp, QSERDES_V4_COM_RESETSM_CNTRL, + QSERDES_V4_COM_C_READY_STATUS, + QSERDES_V4_DP_PHY_STATUS); if (ret < 0) return ret; @@ -1701,7 +2035,9 @@ static int qmp_v5_configure_dp_phy(struct qmp_combo *qmp) u32 status; int ret; - ret = qmp_v45_configure_dp_phy(qmp); + ret = qmp_v456_configure_dp_phy(qmp, QSERDES_V4_COM_RESETSM_CNTRL, + QSERDES_V4_COM_C_READY_STATUS, + QSERDES_V4_DP_PHY_STATUS); if (ret < 0) return ret; @@ -1750,6 +2086,65 @@ static int qmp_v5_configure_dp_phy(struct qmp_combo *qmp) return 0; } +static int qmp_v6_configure_dp_phy(struct qmp_combo *qmp) +{ + const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; + u32 bias0_en, drvr0_en, bias1_en, drvr1_en; + bool reverse = false; + u32 status; + int ret; + + ret = qmp_v456_configure_dp_phy(qmp, QSERDES_V6_COM_RESETSM_CNTRL, + QSERDES_V6_COM_C_READY_STATUS, + QSERDES_V6_DP_PHY_STATUS); + if (ret < 0) + return ret; + + if (dp_opts->lanes == 1) { + bias0_en = reverse ? 0x3e : 0x1a; + drvr0_en = reverse ? 0x13 : 0x10; + bias1_en = reverse ? 0x15 : 0x3e; + drvr1_en = reverse ? 0x10 : 0x13; + } else if (dp_opts->lanes == 2) { + bias0_en = reverse ? 0x3f : 0x15; + drvr0_en = 0x10; + bias1_en = reverse ? 0x15 : 0x3f; + drvr1_en = 0x10; + } else { + bias0_en = 0x3f; + bias1_en = 0x3f; + drvr0_en = 0x10; + drvr1_en = 0x10; + } + + writel(drvr0_en, qmp->dp_tx + QSERDES_V4_TX_HIGHZ_DRVR_EN); + writel(bias0_en, qmp->dp_tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); + writel(drvr1_en, qmp->dp_tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN); + writel(bias1_en, qmp->dp_tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); + + writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); + udelay(2000); + writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); + + if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V6_DP_PHY_STATUS, + status, + ((status & BIT(1)) > 0), + 500, + 10000)) + return -ETIMEDOUT; + + writel(0x0a, qmp->dp_tx + QSERDES_V4_TX_TX_POL_INV); + writel(0x0a, qmp->dp_tx2 + QSERDES_V4_TX_TX_POL_INV); + + writel(0x27, qmp->dp_tx + QSERDES_V4_TX_TX_DRV_LVL); + writel(0x27, qmp->dp_tx2 + QSERDES_V4_TX_TX_DRV_LVL); + + writel(0x20, qmp->dp_tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); + writel(0x20, qmp->dp_tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); + + return 0; +} + /* * We need to calibrate the aux setting here as many times * as the caller tries @@ -2640,8 +3035,8 @@ static int qmp_combo_parse_dt(struct qmp_combo *qmp) qmp->pcs_usb = base + offs->usb3_pcs_usb; qmp->dp_serdes = base + offs->dp_serdes; - qmp->dp_tx = base + offs->txa; - qmp->dp_tx2 = base + offs->txb; + qmp->dp_tx = base + offs->dp_tx0; + qmp->dp_tx2 = base + offs->dp_tx1; qmp->dp_dp_phy = base + offs->dp_dp_phy; qmp->pipe_clk = devm_clk_get(dev, "usb3_pipe"); @@ -2792,6 +3187,10 @@ static const struct of_device_id qmp_combo_of_match_table[] = { .compatible = "qcom,sm8250-qmp-usb3-dp-phy", .data = &sm8250_usb3dpphy_cfg, }, + { + .compatible = "qcom,sm8550-qmp-usb3-dp-phy", + .data = &sm8550_usb3dpphy_cfg, + }, { } }; MODULE_DEVICE_TABLE(of, qmp_combo_of_match_table); From patchwork Thu Feb 2 13:25:11 2023 Content-Type: text/plain; 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Thu, 02 Feb 2023 05:25:24 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id e22-20020a05600c449600b003db06224953sm4690943wmo.41.2023.02.02.05.25.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Feb 2023 05:25:24 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , "vkoul@kernel.org" , Kishon Vijay Abraham I Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Linux Kernel Mailing List Subject: [PATCH v4 8/8] arm64: dts: qcom: sm8550-mtp: Add USB PHYs and HC nodes Date: Thu, 2 Feb 2023 15:25:11 +0200 Message-Id: <20230202132511.3983095-9-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230202132511.3983095-1-abel.vesa@linaro.org> References: <20230202132511.3983095-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable USB HC and PHYs nodes on SM8550 MTP board. Signed-off-by: Abel Vesa --- Changes since v3: * none Changes since v2: * none NOTE: This patch has been already merged. It is here only to provide context for the rest of the patchset. There is a change with respect to the clocks, but that will be sent as a separate/individual fix patch. arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 265862d0e44f..03862132fe41 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -550,6 +550,28 @@ &ufs_mem_phy { status = "okay"; }; +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l1e_0p88>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3f_0p91>; + + status = "okay"; +}; + &xo_board { clock-frequency = <76800000>; };