From patchwork Wed Apr 24 12:02:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 162775 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp572123jan; Wed, 24 Apr 2019 05:03:24 -0700 (PDT) X-Google-Smtp-Source: APXvYqw/XlZeMIJgI6sCD6sJCzkGWHBvD7YQq6ZDi8GU69AXyPolirxjTm3OZtGEk3qOxZM80OG/ X-Received: by 2002:a17:902:20c9:: with SMTP id v9mr32055252plg.239.1556107404534; Wed, 24 Apr 2019 05:03:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556107404; cv=none; d=google.com; s=arc-20160816; b=DfZQgHpPUnVjbq+/CS0pBpLJnEgd26X58WlPfbfgYLtG6OZT6ifHpMon0QnnlPpDSQ MbOnZowfKgeoGGIVd0SUPXbJofhuoIjIFJtzPArAmt72/9qZaQASYOFIZDHZ6qEiDwYR rsIRm03ipf/CvJXBsE+XpcQaL5tCtHg5AZ6nIqkoFhnu3pV8wod3hylJYRAdQmpp61jl XRpQcKLYSiiLr5pGSWNm6779M+s9dsijAJgpD4RmHQQ1xH6ysM5KXWhIRKQVitzMa0NI 2VOjmHrVrZMG59GbT0bDlWj2lkzLZQ6H8TaG4B05zADuUTSiCZI0HDPND9q/HlG5C6r+ oTWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=o1BE+Lvm1P0Zy9V+X0g8sBTlpGL1gkXzWIVJDLVxgUQ=; b=mpwRrir6shMkzTEvyhaiYqbA76d6II2v4eic4wV0Eqqh6MGQKbZ3HFZ+fsE70wmUBW 9vFwMJIyi8dj7KO/MXqL44bLMWqNkNsooRVNl3rcYqf3/j+z/hV2k/BSXu2EDCww5r34 a2DglOsmdwQMvguVnev/uUehwr61H2R3ln2eazdTij+VVzWA1hWol8wYmNjhI55WuIty kng9T6c1SWvyJK8+AFlAQWKUlg8W662Tc3mHDnmzC5EQvdGTwBqyx+ndF3vLWgcY/eTN auByql7To8d26hfSqobF2bsLXRhf6yBG3kFkM9JFRlJfsR2B4mcgUKmUBGdn3y0zuRUX 7gwQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yrXSgBWH; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k8si18253512plt.354.2019.04.24.05.03.24; Wed, 24 Apr 2019 05:03:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yrXSgBWH; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726135AbfDXMDX (ORCPT + 7 others); Wed, 24 Apr 2019 08:03:23 -0400 Received: from mail-pg1-f195.google.com ([209.85.215.195]:46002 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726691AbfDXMDX (ORCPT ); Wed, 24 Apr 2019 08:03:23 -0400 Received: by mail-pg1-f195.google.com with SMTP id y3so9272662pgk.12 for ; Wed, 24 Apr 2019 05:03:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=o1BE+Lvm1P0Zy9V+X0g8sBTlpGL1gkXzWIVJDLVxgUQ=; b=yrXSgBWHOLW3k6sGjU2DzaPMuJetuFp9MxBNSr11uZR00yusCZ6RT4Sesrb31GncBR imlDBprVX2EJt6p8X8RrNW6/zzp5yhDm8skcyZSVYbZ3B7B97oPYXcg9thvmoVRsHV6U 9/YsOEDdhi3ZlOoCBe5P1NBIcZegIx3tqvHQWhhRM+UoMacTbfqD81z9bTLkDfHWjOMc RL8W9smTXXHsUvwdMNA2AL60L3pxwiySlnQ+4lnS+ux5yMpKO9urXui+3mB9BQWFT10T fvYhee1Wxs1H7F299tp5S9JpYWnvIUUGART0wNhtV6SRZ8D6M0/7lja6U8boLAUzovfw 51iA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=o1BE+Lvm1P0Zy9V+X0g8sBTlpGL1gkXzWIVJDLVxgUQ=; b=cYfKjlBYY41jx79RC8yNyf6Yn3g4MlTvHw5GA6QCgLviO9QW8e+69FCUZfU8Dfjea/ 3ml2QAFrRtipyGmA37WhXAisGSlszuF5v9OXt2727TIkBQXiu5ZoEyCEPC+XZ1IITGXQ Sgqj1HHpbb/koWmM6ErG7Qt1OUvq+Ky89MvnuKXtk7wmV4+CNcHILLDuR+UhhHwmk9Ek QItRrahu/9BlY3kIn8UqJfDz6KLahFwvJKeE4PgfmmwT3GAz+CE1SrcZSCpwh+hHzMWr ZVNeTzrXaQtVXoKXPntZtvHXiObRdeLedAMM20YhiXjBCM4AN/kOOeHTEs/lJ6qOCzl1 P+Ag== X-Gm-Message-State: APjAAAWr6MvrGQgTjNWwAqmfDAb9EvABTV0gT/z4zeP2mscdkUa8l/yc E+yUGIpVDyX5xfeEpKmAZLt4 X-Received: by 2002:a63:6988:: with SMTP id e130mr30616329pgc.150.1556107402644; Wed, 24 Apr 2019 05:03:22 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:711:bac8:7d48:1fca:4d86:743]) by smtp.gmail.com with ESMTPSA id j22sm25870840pfn.129.2019.04.24.05.03.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 24 Apr 2019 05:03:21 -0700 (PDT) From: Manivannan Sadhasivam To: linus.walleij@linaro.org, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, haitao.suo@bitmain.com, darren.tsao@bitmain.com, linux-gpio@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 1/5] dt-bindings: pinctrl: Add BM1880 pinctrl binding Date: Wed, 24 Apr 2019 17:32:20 +0530 Message-Id: <20190424120224.22660-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190424120224.22660-1-manivannan.sadhasivam@linaro.org> References: <20190424120224.22660-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add pinctrl binding for Bitmain BM1880 SoC. The SoC is not capable of handling pinconf, thereby supporting only pinmux and this limitation is documented. Signed-off-by: Manivannan Sadhasivam --- .../pinctrl/bitmain,bm1880-pinctrl.txt | 98 +++++++++++++++++++ 1 file changed, 98 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt new file mode 100644 index 000000000000..ed34bb1ee81c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt @@ -0,0 +1,98 @@ +Bitmain BM1880 Pin Controller + +This binding describes the pin controller found in the BM1880 SoC. + +Required Properties: + +- compatible: Should be "bitmain,bm1880-pinctrl" +- reg: Offset and length of pinctrl space in SCTRL. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +The pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration for BM1880 SoC +includes only pinmux as there is no pinconf support available in SoC. + +Each configuration node can consist of multiple nodes describing the pinmux +options. The name of each subnode is not important; all subnodes should be +enumerated and processed purely based on their content. + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pinmux subnode: + +Required Properties: + +- pins: An array of strings, each string containing the name of a pin. + Valid values for pins are: + + MIO0 - MIO111 + +- groups: An array of strings, each string containing the name of a pin + group. Valid values for groups are: + + nand_grp, spi_grp, emmc_grp, sdio_grp, eth0_grp, pwm0_grp, + pwm1_grp, pwm2_grp, pwm3_grp, pwm4_grp, pwm5_grp, pwm6_grp, + pwm7_grp, pwm8_grp, pwm9_grp, pwm10_grp, pwm11_grp, pwm12_grp, + pwm13_grp, pwm14_grp, pwm15_grp, pwm16_grp, pwm17_grp, + pwm18_grp, pwm19_grp, pwm20_grp, pwm21_grp, pwm22_grp, + pwm23_grp, pwm24_grp, pwm25_grp, pwm26_grp, pwm27_grp, + pwm28_grp, pwm29_grp, pwm30_grp, pwm31_grp, pwm32_grp, + pwm33_grp, pwm34_grp, pwm35_grp, pwm36_grp, i2c0_grp, + i2c1_grp, i2c2_grp, i2c3_grp, i2c4_grp, uart0_grp, uart1_grp, + uart2_grp, uart3_grp, uart4_grp, uart5_grp, uart6_grp, + uart7_grp, uart8_grp, uart9_grp, uart10_grp, uart11_grp, + uart12_grp, uart13_grp, uart14_grp, uart15_grp, gpio0_grp, + gpio1_grp, gpio2_grp, gpio3_grp, gpio4_grp, gpio5_grp, + gpio6_grp, gpio7_grp, gpio8_grp, gpio9_grp, gpio10_grp, + gpio11_grp, gpio12_grp, gpio13_grp, gpio14_grp, gpio15_grp, + gpio16_grp, gpio17_grp, gpio18_grp, gpio19_grp, gpio20_grp, + gpio21_grp, gpio22_grp, gpio23_grp, gpio24_grp, gpio25_grp, + gpio26_grp, gpio27_grp, gpio28_grp, gpio29_grp, gpio30_grp, + gpio31_grp, gpio32_grp, gpio33_grp, gpio34_grp, gpio35_grp, + gpio36_grp, gpio37_grp, gpio38_grp, gpio39_grp, gpio40_grp, + gpio41_grp, gpio42_grp, gpio43_grp, gpio44_grp, gpio45_grp, + gpio46_grp, gpio47_grp, gpio48_grp, gpio49_grp, gpio50_grp, + gpio51_grp, gpio52_grp, gpio53_grp, gpio54_grp, gpio55_grp, + gpio56_grp, gpio57_grp, gpio58_grp, gpio59_grp, gpio60_grp, + gpio61_grp, gpio62_grp, gpio63_grp, gpio64_grp, gpio65_grp, + gpio66_grp, gpio67_grp, eth1_grp, i2s0_grp, i2s0_mclkin_grp, + i2s1_grp, i2s1_mclkin_grp, spi0_grp + +- function: An array of strings, each string containing the name of the + pinmux functions. The following are the list of pinmux + functions available: + + nand, spi, emmc, sdio, eth0, pwm0, pwm1, pwm2, pwm3, pwm4, + pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11, pwm12, pwm13, + pwm14, pwm15, pwm16, pwm17, pwm18, pwm19, pwm20, pwm21, pwm22, + pwm23, pwm24, pwm25, pwm26, pwm27, pwm28, pwm29, pwm30, pwm31, + pwm32, pwm33, pwm34, pwm35, pwm36, i2c0, i2c1, i2c2, i2c3, + i2c4, uart0, uart1, uart2, uart3, uart4, uart5, uart6, uart7, + uart8, uart9, uart10, uart11, uart12, uart13, uart14, uart15, + gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, gpio8, + gpio9, gpio10, gpio11, gpio12, gpio13, gpio14, gpio15, gpio16, + gpio17, gpio18, gpio19, gpio20, gpio21, gpio22, gpio23, + gpio24, gpio25, gpio26, gpio27, gpio28, gpio29, gpio30, + gpio31, gpio32, gpio33, gpio34, gpio35, gpio36, gpio37, + gpio38, gpio39, gpio40, gpio41, gpio42, gpio43, gpio44, + gpio45, gpio46, gpio47, gpio48, gpio49, gpio50, gpio51, + gpio52, gpio53, gpio54, gpio55, gpio56, gpio57, gpio58, + gpio59, gpio60, gpio61, gpio62, gpio63, gpio64, gpio65, + gpio66, gpio67, eth1, i2s0, i2s0_mclkin, i2s1, i2s1_mclkin, + spi0 + +Example: + pinctrl: pinctrl@50 { + compatible = "bitmain,bm1880-pinctrl"; + reg = <0x50 0x4B0>; + + pinctrl_uart0_default: uart0-default { + pinmux { + groups = "uart0_grp"; + function = "uart0"; + }; + }; + }; From patchwork Wed Apr 24 12:02:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 162776 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp572217jan; Wed, 24 Apr 2019 05:03:29 -0700 (PDT) X-Google-Smtp-Source: APXvYqx5RUB0C9bCdr7IBjiI8r9RhPJ36f46D9UbhUKxRXkyamVg32u+s/wFnCng8mWvBgpsrM8v X-Received: by 2002:aa7:8694:: with SMTP id d20mr32468049pfo.81.1556107409444; Wed, 24 Apr 2019 05:03:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556107409; cv=none; d=google.com; s=arc-20160816; b=n5xuzFfjhtLxv1O8R6dKrYQLXpzxU4QaAo1hca5GlaP5SzQLzTnPos49xn6gKdKCVz /ANeQvNggv3k8iEqkU2o/PTwsH+5eNoaq2ikJA7UDHRFoTw/I/ZaUb2o9XnuvluXhWZw 7e9ba5DVTkZ/ruhBsh7oi/IqtboKmWkAj+935rlQK5vOAUNBFHwtezXo7UOKKqSCyjFr H5DqvvOnx1BK5W+7hz58D+wmV9VR7S0ys+6hMcEHGMB+uz6NzY99EOrvii5hNmiE3Cw9 1cOr9Cf7NY7x1bbbXnf3NqeAGBQ6dMvsqu1e7qsEAZMwLJcDkOkpLgyciW2OyukYApQ5 KL1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=K9GlpFCd2DOdgM3fSdxL4T71FjdIxk/5Xu8NSCGxtGQ=; b=qG3YW/n406O4wNGmPPgZjkBcCaqTjHKrmcdd+Xkqn4Zas5sR2u7Y2ilFh2cnGZ3Svv 5UhdrxIDHSkdN/pq3dxmnSzypmNsbewDAOACNk22t223WekwzY1zeSnFNMqLf27CNGrU MWDIA7A7ZNm5/vIvbFAvOJ7GrCv4vq8gZBVKPs5qBuRzjTnOzW44HFNNpvAwObrmwbJr UyvJnZnB7qlvdWwW43DeA06emeIOj3LV+Pskhqbd6kXyKcJsAzWUmARo1iYFQ4H1dibk MTHG+VEP9BSjgQmAkeYie88m+61vHZ/eonwNPcKdVVZpg01Iu7fs596WtUMJ/aEaY4E7 vdMQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KvImkMX1; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k12si18206336plt.28.2019.04.24.05.03.29; Wed, 24 Apr 2019 05:03:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KvImkMX1; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726211AbfDXMD2 (ORCPT + 7 others); Wed, 24 Apr 2019 08:03:28 -0400 Received: from mail-pl1-f195.google.com ([209.85.214.195]:37220 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729109AbfDXMD2 (ORCPT ); Wed, 24 Apr 2019 08:03:28 -0400 Received: by mail-pl1-f195.google.com with SMTP id w23so9213147ply.4 for ; Wed, 24 Apr 2019 05:03:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=K9GlpFCd2DOdgM3fSdxL4T71FjdIxk/5Xu8NSCGxtGQ=; b=KvImkMX1Rd5Ulv3d/JOyrloTLqwwyZOiJlUX4mmAACZGmD7mYS8uxB8mCwtaW8CcZS 6yMmf547hO97euAwcusstIgoAkMfssjQQTo69iNePnw7IqojK5QCFqAabbsyIKhjFUEE TdcyIfE8LctErMAzlfG/+q76vEW6LAEtJZaOnI2N29rw6gLxbn2zSVbeuoQxy+UPsz7H sxFBtgWaO0KGxOQ4DEw1Kjun0RC5kdkhQL7DinuYnWaQ+Yo83Wi6McZD6GZtr/BvKKga iWo0vhqv4rADc6Y/6qT7/pfuzNnScb//YcxNP+Zz0dd3GhGvJ5P3CW/Ow5AWR31LgnLI Oodg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=K9GlpFCd2DOdgM3fSdxL4T71FjdIxk/5Xu8NSCGxtGQ=; b=SlMT5/9rkK/zO8fLKH4rV/hymxtHRoNFNbrwKN9KRcup08M/SgRWM8BQHeL1z/UUfl S20dzsSNl2YgZQEH50bBiy/QXRj95mOQIzc3DYN2vZ62cDdKNteR60qrxufFkAgtj/SI yehdAW7IHbz59cnIw4LOY1LEOKqwP7sR38So4k7L9Jytxfey8Wf1FFwrqfxBFAD5QzFi TCOHtEyNwNofGTBPMWZte5HWb7M/oZ26yVjOLZVN3e4ywlLiwNDkheoM/pP64GbF2ewk 0EctgodnSu6Tck9AiViwAnttx+5VIJZ3k4vPnNRqheRc4V5hIJH/z0qixBzO9DlL7+m0 EgjA== X-Gm-Message-State: APjAAAXEqFZeRXwNncTTAjquHjid/3TLDIo0y/Vt7fyDj4FO2AkXWPhE pRFlsGdXVpEt7KY7HsJxmF7B X-Received: by 2002:a17:902:8349:: with SMTP id z9mr14427599pln.144.1556107407620; Wed, 24 Apr 2019 05:03:27 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:711:bac8:7d48:1fca:4d86:743]) by smtp.gmail.com with ESMTPSA id j22sm25870840pfn.129.2019.04.24.05.03.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 24 Apr 2019 05:03:26 -0700 (PDT) From: Manivannan Sadhasivam To: linus.walleij@linaro.org, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, haitao.suo@bitmain.com, darren.tsao@bitmain.com, linux-gpio@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 2/5] arm64: dts: bitmain: Add pinctrl support for BM1880 SoC Date: Wed, 24 Apr 2019 17:32:21 +0530 Message-Id: <20190424120224.22660-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190424120224.22660-1-manivannan.sadhasivam@linaro.org> References: <20190424120224.22660-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add pinctrl support for Bitmain BM1880 SoC. This SoC only supports pinmuxing and the pinctrl registers are part of the sctrl block. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/bitmain/bm1880.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/bitmain/bm1880.dtsi b/arch/arm64/boot/dts/bitmain/bm1880.dtsi index 55a4769e0de2..fdfdc65d29ef 100644 --- a/arch/arm64/boot/dts/bitmain/bm1880.dtsi +++ b/arch/arm64/boot/dts/bitmain/bm1880.dtsi @@ -80,6 +80,20 @@ #interrupt-cells = <3>; }; + sctrl: system-controller@50010000 { + compatible = "bitmain,bm1880-sctrl", "syscon", + "simple-mfd"; + reg = <0x0 0x50010000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x50010000 0x1000>; + + pinctrl: pinctrl@50 { + compatible = "bitmain,bm1880-pinctrl"; + reg = <0x50 0x4B0>; + }; + }; + uart0: serial@58018000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x58018000 0x0 0x2000>; From patchwork Wed Apr 24 12:02:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 162778 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp572445jan; Wed, 24 Apr 2019 05:03:41 -0700 (PDT) X-Google-Smtp-Source: APXvYqxT1xftanXEpQnkqL7MGBXdQnKmiYOrICB9DRODeDBa7f0ud+JzZ50gEZedt2Io4XjRHE1k X-Received: by 2002:a17:902:a5ca:: with SMTP id t10mr32425927plq.234.1556107421671; Wed, 24 Apr 2019 05:03:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556107421; cv=none; d=google.com; s=arc-20160816; b=uTHpwGprsbpiRk0DazSrL0qYqbZag/KEi8ZptbOdHA8CzF6edEqClNrfHANebkweB5 PKGd5MqygbgiMvUGBhk0VFEZJit1q1OtTuRdJdaUd+2fgXm6eJDlgsIe9OAUNg/HYAId x/gnzwL14FwdUs59ovLl8FMWykdAUIMUCw2od1DTYdfEDnb9B7sr/Dtl/zoXDlRBN67G 9MOpfdu+MGACtHlZKanu/IDRTYLUga8qKSLJ+adASMGgJeS+jJSSI3EZKIXFnle2ONO3 FWVfCc2H/hhGb8GRFF+DtJgQ1wc1ogsA6geh4e2PVD3JbveoFPSotk5wcr2QPGnoFx9+ Rvsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=RLYUge4zqzJB+u7+uZwXd+BLs4bko/xrbA6zAvL+P+k=; b=GZLLfQRD9IJEp2jTyAqDIf3N4p8V5ZbR+lE9bE8+baUqDqbh/dSRmRU2/XT+PGNGct dxdKi3iclFmvGGKV8YRbg8v0dLnTgiNcvHiDVZyCF//jW0vaATf/rJvu8pnWmo1ebfw9 Zp8FcP0rLTvWwWSJ/ODQccZ//oEB5uWvqy7c1fyr+z27snzMOtk3WPoaQgkoG/Gk8+eD 24ma29wyvJ1C74x6//+Fha9hRURWEivcwd2Nan4zuhIG4fLn5hQM4apdcOplY7z3mKD/ 7mwgBWQHe0Zt9jvQDL5GNdI4FPDdBYc9UL5KKWkBJDkjvGVWDRSSNhaqCGuuMq76/HDB /y2Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oqUwiV09; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k8si18254422plt.354.2019.04.24.05.03.40; Wed, 24 Apr 2019 05:03:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oqUwiV09; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729145AbfDXMDk (ORCPT + 7 others); Wed, 24 Apr 2019 08:03:40 -0400 Received: from mail-pl1-f196.google.com ([209.85.214.196]:35282 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729055AbfDXMDk (ORCPT ); Wed, 24 Apr 2019 08:03:40 -0400 Received: by mail-pl1-f196.google.com with SMTP id w24so9203931plp.2 for ; Wed, 24 Apr 2019 05:03:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RLYUge4zqzJB+u7+uZwXd+BLs4bko/xrbA6zAvL+P+k=; b=oqUwiV09nPJOQ4zX1ZHUIDYlgBu1wAMt7qIlMQH/h2hnFLiUgPmUwjY4JxDle0YW40 QM+61PzVRhUYp6Q6A5xbSMuGqbQ9hIrK+CAvUq2RItASSXKY22/Tjeg0aaQgwsgw0dqs P7SobgWPeMFP8g9SB8JZ+depJubTyNZyzU9xz7QrLX7zAtB5e2Mo0oWaNEaS3Ca3L8kO G9OhD/QowiOhyGThdMmDLQckTjD14o+XshK5DaQAq4QOph5To8hyOuOENmT7SEr7nph+ MRecqHjTKex8twPi0rCfLBGsNrByQDzpaiGb9IPPNHCs/2JaOEzP3F/cKcpNvvEzGxlS 0M/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RLYUge4zqzJB+u7+uZwXd+BLs4bko/xrbA6zAvL+P+k=; b=QpsYLFN5oEMQ2WucN8QwolR0Q5ny8DaE/PNJFPhVDO6rnYp8/caSXBNXo3vg0CDjdL l4rzMn2jAoJQZ0+0S3uRyg2mNTv4DvMVPlsASrSkWvCCfBusjtUl0uyitDDMo1wlIqdr 6gUZPpgA/NZKYxIYmv/guCbQ+2qJSXoDD+VDX+hC4KWPoPwdKQtQ83TL8okK0hdzJTQv s3zZG3fNKaEUhglqErxAlh/W4S3mA8588ktMLKnzwCl/S1/Hmjxmh4Bwc6eCO6fBKDWq F0JQzdpyw5pQY4HdhzKlYKZKEE1emnWhVv0qkUiPHejoGl2D7dLzrHz86BsI4ZOI33z6 vncA== X-Gm-Message-State: APjAAAWNl6Q0Bk9xkux2ytzXGW55Wh82YssUhOylxM5jRMi/vvt1clp/ eOGJx8YisK9MhV1vr5iVsmic X-Received: by 2002:a17:902:e683:: with SMTP id cn3mr32200739plb.115.1556107418545; Wed, 24 Apr 2019 05:03:38 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:711:bac8:7d48:1fca:4d86:743]) by smtp.gmail.com with ESMTPSA id j22sm25870840pfn.129.2019.04.24.05.03.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 24 Apr 2019 05:03:37 -0700 (PDT) From: Manivannan Sadhasivam To: linus.walleij@linaro.org, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, haitao.suo@bitmain.com, darren.tsao@bitmain.com, linux-gpio@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 4/5] pinctrl: Add pinctrl support for BM1880 SoC Date: Wed, 24 Apr 2019 17:32:23 +0530 Message-Id: <20190424120224.22660-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190424120224.22660-1-manivannan.sadhasivam@linaro.org> References: <20190424120224.22660-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add pinctrl support for Bitmain BM1880 SoC. The driver only handles pinmuxing as the SoC is not capable of handling pinconf. Signed-off-by: Manivannan Sadhasivam --- drivers/pinctrl/Kconfig | 7 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-bm1880.c | 965 +++++++++++++++++++++++++++++++ 3 files changed, 973 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-bm1880.c -- 2.17.1 diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 2764d713fea8..c4ac4bf1e1e4 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -108,6 +108,13 @@ config PINCTRL_AMD Requires ACPI/FDT device enumeration code to set up a platform device. +config PINCTRL_BM1880 + bool "Bitmain BM1880 Pinctrl driver" + depends on ARCH_BITMAIN + select PINMUX + help + Pinctrl driver for Bitmain BM1880 SoC. + config PINCTRL_DA850_PUPD tristate "TI DA850/OMAP-L138/AM18XX pullup/pulldown groups" depends on OF && (ARCH_DAVINCI_DA850 || COMPILE_TEST) diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 712184b74a5c..62df40647e02 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_PINCTRL_AXP209) += pinctrl-axp209.o obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o +obj-$(CONFIG_PINCTRL_BM1880) += pinctrl-bm1880.o obj-$(CONFIG_PINCTRL_DA850_PUPD) += pinctrl-da850-pupd.o obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o diff --git a/drivers/pinctrl/pinctrl-bm1880.c b/drivers/pinctrl/pinctrl-bm1880.c new file mode 100644 index 000000000000..446b07d8fbfc --- /dev/null +++ b/drivers/pinctrl/pinctrl-bm1880.c @@ -0,0 +1,965 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Bitmain BM1880 SoC Pinctrl driver + * + * Copyright (c) 2019 Linaro Ltd. + * Author: Manivannan Sadhasivam + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "core.h" +#include "pinctrl-utils.h" + +#define BM1880_REG_MUX 0x20 + +/** + * struct bm1880_pinctrl - driver data + * @base: Pinctrl base address + * @pctrl: Pinctrl device + * @groups: Pingroups + * @ngroups: Number of @groups + * @funcs: Pinmux functions + * @nfuncs: Number of @funcs + */ +struct bm1880_pinctrl { + void __iomem *base; + struct pinctrl_dev *pctrldev; + const struct bm1880_pctrl_group *groups; + unsigned int ngroups; + const struct bm1880_pinmux_function *funcs; + unsigned int nfuncs; +}; + +/** + * struct bm1880_pctrl_group - pinctrl group + * @name: Name of the group + * @pins: Array of pins belonging to this group + * @npins: Number of @pins + */ +struct bm1880_pctrl_group { + const char *name; + const unsigned int *pins; + const unsigned int npins; +}; + +/** + * struct bm1880_pinmux_function - a pinmux function + * @name: Name of the pinmux function. + * @groups: List of pingroups for this function. + * @ngroups: Number of entries in @groups. + * @mux_val: Selector for this function + * @mux_mask: Mask for function specific selector + * @mux: Offset of function specific mux + * @mux_shift: Shift for function specific selector + */ +struct bm1880_pinmux_function { + const char *name; + const char * const *groups; + unsigned int ngroups; + u32 mux_val; + u32 mux_mask; + u32 mux; + u8 mux_shift; +}; + +static const struct pinctrl_pin_desc bm1880_pins[] = { + PINCTRL_PIN(0, "MIO0"), + PINCTRL_PIN(1, "MIO1"), + PINCTRL_PIN(2, "MIO2"), + PINCTRL_PIN(3, "MIO3"), + PINCTRL_PIN(4, "MIO4"), + PINCTRL_PIN(5, "MIO5"), + PINCTRL_PIN(6, "MIO6"), + PINCTRL_PIN(7, "MIO7"), + PINCTRL_PIN(8, "MIO8"), + PINCTRL_PIN(9, "MIO9"), + PINCTRL_PIN(10, "MIO10"), + PINCTRL_PIN(11, "MIO11"), + PINCTRL_PIN(12, "MIO12"), + PINCTRL_PIN(13, "MIO13"), + PINCTRL_PIN(14, "MIO14"), + PINCTRL_PIN(15, "MIO15"), + PINCTRL_PIN(16, "MIO16"), + PINCTRL_PIN(17, "MIO17"), + PINCTRL_PIN(18, "MIO18"), + PINCTRL_PIN(19, "MIO19"), + PINCTRL_PIN(20, "MIO20"), + PINCTRL_PIN(21, "MIO21"), + PINCTRL_PIN(22, "MIO22"), + PINCTRL_PIN(23, "MIO23"), + PINCTRL_PIN(24, "MIO24"), + PINCTRL_PIN(25, "MIO25"), + PINCTRL_PIN(26, "MIO26"), + PINCTRL_PIN(27, "MIO27"), + PINCTRL_PIN(28, "MIO28"), + PINCTRL_PIN(29, "MIO29"), + PINCTRL_PIN(30, "MIO30"), + PINCTRL_PIN(31, "MIO31"), + PINCTRL_PIN(32, "MIO32"), + PINCTRL_PIN(33, "MIO33"), + PINCTRL_PIN(34, "MIO34"), + PINCTRL_PIN(35, "MIO35"), + PINCTRL_PIN(36, "MIO36"), + PINCTRL_PIN(37, "MIO37"), + PINCTRL_PIN(38, "MIO38"), + PINCTRL_PIN(39, "MIO39"), + PINCTRL_PIN(40, "MIO40"), + PINCTRL_PIN(41, "MIO41"), + PINCTRL_PIN(42, "MIO42"), + PINCTRL_PIN(43, "MIO43"), + PINCTRL_PIN(44, "MIO44"), + PINCTRL_PIN(45, "MIO45"), + PINCTRL_PIN(46, "MIO46"), + PINCTRL_PIN(47, "MIO47"), + PINCTRL_PIN(48, "MIO48"), + PINCTRL_PIN(49, "MIO49"), + PINCTRL_PIN(50, "MIO50"), + PINCTRL_PIN(51, "MIO51"), + PINCTRL_PIN(52, "MIO52"), + PINCTRL_PIN(53, "MIO53"), + PINCTRL_PIN(54, "MIO54"), + PINCTRL_PIN(55, "MIO55"), + PINCTRL_PIN(56, "MIO56"), + PINCTRL_PIN(57, "MIO57"), + PINCTRL_PIN(58, "MIO58"), + PINCTRL_PIN(59, "MIO59"), + PINCTRL_PIN(60, "MIO60"), + PINCTRL_PIN(61, "MIO61"), + PINCTRL_PIN(62, "MIO62"), + PINCTRL_PIN(63, "MIO63"), + PINCTRL_PIN(64, "MIO64"), + PINCTRL_PIN(65, "MIO65"), + PINCTRL_PIN(66, "MIO66"), + PINCTRL_PIN(67, "MIO67"), + PINCTRL_PIN(68, "MIO68"), + PINCTRL_PIN(69, "MIO69"), + PINCTRL_PIN(70, "MIO70"), + PINCTRL_PIN(71, "MIO71"), + PINCTRL_PIN(72, "MIO72"), + PINCTRL_PIN(73, "MIO73"), + PINCTRL_PIN(74, "MIO74"), + PINCTRL_PIN(75, "MIO75"), + PINCTRL_PIN(76, "MIO76"), + PINCTRL_PIN(77, "MIO77"), + PINCTRL_PIN(78, "MIO78"), + PINCTRL_PIN(79, "MIO79"), + PINCTRL_PIN(80, "MIO80"), + PINCTRL_PIN(81, "MIO81"), + PINCTRL_PIN(82, "MIO82"), + PINCTRL_PIN(83, "MIO83"), + PINCTRL_PIN(84, "MIO84"), + PINCTRL_PIN(85, "MIO85"), + PINCTRL_PIN(86, "MIO86"), + PINCTRL_PIN(87, "MIO87"), + PINCTRL_PIN(88, "MIO88"), + PINCTRL_PIN(89, "MIO89"), + PINCTRL_PIN(90, "MIO90"), + PINCTRL_PIN(91, "MIO91"), + PINCTRL_PIN(92, "MIO92"), + PINCTRL_PIN(93, "MIO93"), + PINCTRL_PIN(94, "MIO94"), + PINCTRL_PIN(95, "MIO95"), + PINCTRL_PIN(96, "MIO96"), + PINCTRL_PIN(97, "MIO97"), + PINCTRL_PIN(98, "MIO98"), + PINCTRL_PIN(99, "MIO99"), + PINCTRL_PIN(100, "MIO100"), + PINCTRL_PIN(101, "MIO101"), + PINCTRL_PIN(102, "MIO102"), + PINCTRL_PIN(103, "MIO103"), + PINCTRL_PIN(104, "MIO104"), + PINCTRL_PIN(105, "MIO105"), + PINCTRL_PIN(106, "MIO106"), + PINCTRL_PIN(107, "MIO107"), + PINCTRL_PIN(108, "MIO108"), + PINCTRL_PIN(109, "MIO109"), + PINCTRL_PIN(110, "MIO110"), + PINCTRL_PIN(111, "MIO111"), +}; + +enum bm1880_pinmux_functions { + F_nand, F_spi, F_emmc, F_sdio, F_eth0, F_pwm0, F_pwm1, F_pwm2, + F_pwm3, F_pwm4, F_pwm5, F_pwm6, F_pwm7, F_pwm8, F_pwm9, F_pwm10, + F_pwm11, F_pwm12, F_pwm13, F_pwm14, F_pwm15, F_pwm16, F_pwm17, + F_pwm18, F_pwm19, F_pwm20, F_pwm21, F_pwm22, F_pwm23, F_pwm24, + F_pwm25, F_pwm26, F_pwm27, F_pwm28, F_pwm29, F_pwm30, F_pwm31, + F_pwm32, F_pwm33, F_pwm34, F_pwm35, F_pwm36, F_pwm37, F_i2c0, F_i2c1, + F_i2c2, F_i2c3, F_i2c4, F_uart0, F_uart1, F_uart2, F_uart3, F_uart4, + F_uart5, F_uart6, F_uart7, F_uart8, F_uart9, F_uart10, F_uart11, + F_uart12, F_uart13, F_uart14, F_uart15, F_gpio0, F_gpio1, F_gpio2, + F_gpio3, F_gpio4, F_gpio5, F_gpio6, F_gpio7, F_gpio8, F_gpio9, F_gpio10, + F_gpio11, F_gpio12, F_gpio13, F_gpio14, F_gpio15, F_gpio16, F_gpio17, + F_gpio18, F_gpio19, F_gpio20, F_gpio21, F_gpio22, F_gpio23, F_gpio24, + F_gpio25, F_gpio26, F_gpio27, F_gpio28, F_gpio29, F_gpio30, F_gpio31, + F_gpio32, F_gpio33, F_gpio34, F_gpio35, F_gpio36, F_gpio37, F_gpio38, + F_gpio39, F_gpio40, F_gpio41, F_gpio42, F_gpio43, F_gpio44, F_gpio45, + F_gpio46, F_gpio47, F_gpio48, F_gpio49, F_gpio50, F_gpio51, F_gpio52, + F_gpio53, F_gpio54, F_gpio55, F_gpio56, F_gpio57, F_gpio58, F_gpio59, + F_gpio60, F_gpio61, F_gpio62, F_gpio63, F_gpio64, F_gpio65, F_gpio66, + F_gpio67, F_eth1, F_i2s0, F_i2s0_mclkin, F_i2s1, F_i2s1_mclkin, F_spi0, + F_max +}; + +static const unsigned int nand_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, + 10, 11, 12, 13, 14, 15, 16 }; +static const unsigned int spi_pins[] = { 0, 1, 8, 10, 11, 12, 13 }; +static const unsigned int emmc_pins[] = { 2, 3, 4, 5, 6, 7, 9, 14, 15, 16 }; +static const unsigned int sdio_pins[] = { 17, 18, 19, 20, 21, 22, 23, 24, + 25, 26 }; +static const unsigned int eth0_pins[] = { 27, 28, 29, 30, 31, 32, 33, 34, 35, + 36, 37, 38, 39, 40, 41, 42 }; +static const unsigned int pwm0_pins[] = { 29 }; +static const unsigned int pwm1_pins[] = { 30 }; +static const unsigned int pwm2_pins[] = { 34 }; +static const unsigned int pwm3_pins[] = { 35 }; +static const unsigned int pwm4_pins[] = { 43 }; +static const unsigned int pwm5_pins[] = { 44 }; +static const unsigned int pwm6_pins[] = { 45 }; +static const unsigned int pwm7_pins[] = { 46 }; +static const unsigned int pwm8_pins[] = { 47 }; +static const unsigned int pwm9_pins[] = { 48 }; +static const unsigned int pwm10_pins[] = { 49 }; +static const unsigned int pwm11_pins[] = { 50 }; +static const unsigned int pwm12_pins[] = { 51 }; +static const unsigned int pwm13_pins[] = { 52 }; +static const unsigned int pwm14_pins[] = { 53 }; +static const unsigned int pwm15_pins[] = { 54 }; +static const unsigned int pwm16_pins[] = { 55 }; +static const unsigned int pwm17_pins[] = { 56 }; +static const unsigned int pwm18_pins[] = { 57 }; +static const unsigned int pwm19_pins[] = { 58 }; +static const unsigned int pwm20_pins[] = { 59 }; +static const unsigned int pwm21_pins[] = { 60 }; +static const unsigned int pwm22_pins[] = { 61 }; +static const unsigned int pwm23_pins[] = { 62 }; +static const unsigned int pwm24_pins[] = { 97 }; +static const unsigned int pwm25_pins[] = { 98 }; +static const unsigned int pwm26_pins[] = { 99 }; +static const unsigned int pwm27_pins[] = { 100 }; +static const unsigned int pwm28_pins[] = { 101 }; +static const unsigned int pwm29_pins[] = { 102 }; +static const unsigned int pwm30_pins[] = { 103 }; +static const unsigned int pwm31_pins[] = { 104 }; +static const unsigned int pwm32_pins[] = { 105 }; +static const unsigned int pwm33_pins[] = { 106 }; +static const unsigned int pwm34_pins[] = { 107 }; +static const unsigned int pwm35_pins[] = { 108 }; +static const unsigned int pwm36_pins[] = { 109 }; +static const unsigned int pwm37_pins[] = { 110 }; +static const unsigned int i2c0_pins[] = { 63, 64 }; +static const unsigned int i2c1_pins[] = { 65, 66 }; +static const unsigned int i2c2_pins[] = { 67, 68 }; +static const unsigned int i2c3_pins[] = { 69, 70 }; +static const unsigned int i2c4_pins[] = { 71, 72 }; +static const unsigned int uart0_pins[] = { 73, 74 }; +static const unsigned int uart1_pins[] = { 75, 76 }; +static const unsigned int uart2_pins[] = { 77, 78 }; +static const unsigned int uart3_pins[] = { 79, 80 }; +static const unsigned int uart4_pins[] = { 81, 82 }; +static const unsigned int uart5_pins[] = { 83, 84 }; +static const unsigned int uart6_pins[] = { 85, 86 }; +static const unsigned int uart7_pins[] = { 87, 88 }; +static const unsigned int uart8_pins[] = { 89, 90 }; +static const unsigned int uart9_pins[] = { 91, 92 }; +static const unsigned int uart10_pins[] = { 93, 94 }; +static const unsigned int uart11_pins[] = { 95, 96 }; +static const unsigned int uart12_pins[] = { 73, 74, 75, 76 }; +static const unsigned int uart13_pins[] = { 77, 78, 83, 84 }; +static const unsigned int uart14_pins[] = { 79, 80, 85, 86 }; +static const unsigned int uart15_pins[] = { 81, 82, 87, 88 }; +static const unsigned int gpio0_pins[] = { 97 }; +static const unsigned int gpio1_pins[] = { 98 }; +static const unsigned int gpio2_pins[] = { 99 }; +static const unsigned int gpio3_pins[] = { 100 }; +static const unsigned int gpio4_pins[] = { 101 }; +static const unsigned int gpio5_pins[] = { 102 }; +static const unsigned int gpio6_pins[] = { 103 }; +static const unsigned int gpio7_pins[] = { 104 }; +static const unsigned int gpio8_pins[] = { 105 }; +static const unsigned int gpio9_pins[] = { 106 }; +static const unsigned int gpio10_pins[] = { 107 }; +static const unsigned int gpio11_pins[] = { 108 }; +static const unsigned int gpio12_pins[] = { 109 }; +static const unsigned int gpio13_pins[] = { 110 }; +static const unsigned int gpio14_pins[] = { 43 }; +static const unsigned int gpio15_pins[] = { 44 }; +static const unsigned int gpio16_pins[] = { 45 }; +static const unsigned int gpio17_pins[] = { 46 }; +static const unsigned int gpio18_pins[] = { 47 }; +static const unsigned int gpio19_pins[] = { 48 }; +static const unsigned int gpio20_pins[] = { 49 }; +static const unsigned int gpio21_pins[] = { 50 }; +static const unsigned int gpio22_pins[] = { 51 }; +static const unsigned int gpio23_pins[] = { 52 }; +static const unsigned int gpio24_pins[] = { 53 }; +static const unsigned int gpio25_pins[] = { 54 }; +static const unsigned int gpio26_pins[] = { 55 }; +static const unsigned int gpio27_pins[] = { 56 }; +static const unsigned int gpio28_pins[] = { 57 }; +static const unsigned int gpio29_pins[] = { 58 }; +static const unsigned int gpio30_pins[] = { 59 }; +static const unsigned int gpio31_pins[] = { 60 }; +static const unsigned int gpio32_pins[] = { 61 }; +static const unsigned int gpio33_pins[] = { 62 }; +static const unsigned int gpio34_pins[] = { 63 }; +static const unsigned int gpio35_pins[] = { 64 }; +static const unsigned int gpio36_pins[] = { 65 }; +static const unsigned int gpio37_pins[] = { 66 }; +static const unsigned int gpio38_pins[] = { 67 }; +static const unsigned int gpio39_pins[] = { 68 }; +static const unsigned int gpio40_pins[] = { 69 }; +static const unsigned int gpio41_pins[] = { 70 }; +static const unsigned int gpio42_pins[] = { 71 }; +static const unsigned int gpio43_pins[] = { 72 }; +static const unsigned int gpio44_pins[] = { 73 }; +static const unsigned int gpio45_pins[] = { 74 }; +static const unsigned int gpio46_pins[] = { 75 }; +static const unsigned int gpio47_pins[] = { 76 }; +static const unsigned int gpio48_pins[] = { 77 }; +static const unsigned int gpio49_pins[] = { 78 }; +static const unsigned int gpio50_pins[] = { 79 }; +static const unsigned int gpio51_pins[] = { 80 }; +static const unsigned int gpio52_pins[] = { 81 }; +static const unsigned int gpio53_pins[] = { 82 }; +static const unsigned int gpio54_pins[] = { 83 }; +static const unsigned int gpio55_pins[] = { 84 }; +static const unsigned int gpio56_pins[] = { 85 }; +static const unsigned int gpio57_pins[] = { 86 }; +static const unsigned int gpio58_pins[] = { 87 }; +static const unsigned int gpio59_pins[] = { 88 }; +static const unsigned int gpio60_pins[] = { 89 }; +static const unsigned int gpio61_pins[] = { 90 }; +static const unsigned int gpio62_pins[] = { 91 }; +static const unsigned int gpio63_pins[] = { 92 }; +static const unsigned int gpio64_pins[] = { 93 }; +static const unsigned int gpio65_pins[] = { 94 }; +static const unsigned int gpio66_pins[] = { 95 }; +static const unsigned int gpio67_pins[] = { 96 }; +static const unsigned int eth1_pins[] = { 43, 44, 45, 46, 47, 48, 49, 50, 51, + 52, 53, 54, 55, 56, 57, 58 }; +static const unsigned int i2s0_pins[] = { 87, 88, 89, 90, 91 }; +static const unsigned int i2s0_mclkin_pins[] = { 97 }; +static const unsigned int i2s1_pins[] = { 92, 93, 94, 95, 96 }; +static const unsigned int i2s1_mclkin_pins[] = { 98 }; +static const unsigned int spi0_pins[] = { 59, 60, 61, 62 }; + +#define BM1880_PINCTRL_GRP(nm) \ + { \ + .name = #nm "_grp", \ + .pins = nm ## _pins, \ + .npins = ARRAY_SIZE(nm ## _pins), \ + } + +static const struct bm1880_pctrl_group bm1880_pctrl_groups[] = { + BM1880_PINCTRL_GRP(nand), + BM1880_PINCTRL_GRP(spi), + BM1880_PINCTRL_GRP(emmc), + BM1880_PINCTRL_GRP(sdio), + BM1880_PINCTRL_GRP(eth0), + BM1880_PINCTRL_GRP(pwm0), + BM1880_PINCTRL_GRP(pwm1), + BM1880_PINCTRL_GRP(pwm2), + BM1880_PINCTRL_GRP(pwm3), + BM1880_PINCTRL_GRP(pwm4), + BM1880_PINCTRL_GRP(pwm5), + BM1880_PINCTRL_GRP(pwm6), + BM1880_PINCTRL_GRP(pwm7), + BM1880_PINCTRL_GRP(pwm8), + BM1880_PINCTRL_GRP(pwm9), + BM1880_PINCTRL_GRP(pwm10), + BM1880_PINCTRL_GRP(pwm11), + BM1880_PINCTRL_GRP(pwm12), + BM1880_PINCTRL_GRP(pwm13), + BM1880_PINCTRL_GRP(pwm14), + BM1880_PINCTRL_GRP(pwm15), + BM1880_PINCTRL_GRP(pwm16), + BM1880_PINCTRL_GRP(pwm17), + BM1880_PINCTRL_GRP(pwm18), + BM1880_PINCTRL_GRP(pwm19), + BM1880_PINCTRL_GRP(pwm20), + BM1880_PINCTRL_GRP(pwm21), + BM1880_PINCTRL_GRP(pwm22), + BM1880_PINCTRL_GRP(pwm23), + BM1880_PINCTRL_GRP(pwm24), + BM1880_PINCTRL_GRP(pwm25), + BM1880_PINCTRL_GRP(pwm26), + BM1880_PINCTRL_GRP(pwm27), + BM1880_PINCTRL_GRP(pwm28), + BM1880_PINCTRL_GRP(pwm29), + BM1880_PINCTRL_GRP(pwm30), + BM1880_PINCTRL_GRP(pwm31), + BM1880_PINCTRL_GRP(pwm32), + BM1880_PINCTRL_GRP(pwm33), + BM1880_PINCTRL_GRP(pwm34), + BM1880_PINCTRL_GRP(pwm35), + BM1880_PINCTRL_GRP(pwm36), + BM1880_PINCTRL_GRP(i2c0), + BM1880_PINCTRL_GRP(i2c1), + BM1880_PINCTRL_GRP(i2c2), + BM1880_PINCTRL_GRP(i2c3), + BM1880_PINCTRL_GRP(i2c4), + BM1880_PINCTRL_GRP(uart0), + BM1880_PINCTRL_GRP(uart1), + BM1880_PINCTRL_GRP(uart2), + BM1880_PINCTRL_GRP(uart3), + BM1880_PINCTRL_GRP(uart4), + BM1880_PINCTRL_GRP(uart5), + BM1880_PINCTRL_GRP(uart6), + BM1880_PINCTRL_GRP(uart7), + BM1880_PINCTRL_GRP(uart8), + BM1880_PINCTRL_GRP(uart9), + BM1880_PINCTRL_GRP(uart10), + BM1880_PINCTRL_GRP(uart11), + BM1880_PINCTRL_GRP(uart12), + BM1880_PINCTRL_GRP(uart13), + BM1880_PINCTRL_GRP(uart14), + BM1880_PINCTRL_GRP(uart15), + BM1880_PINCTRL_GRP(gpio0), + BM1880_PINCTRL_GRP(gpio1), + BM1880_PINCTRL_GRP(gpio2), + BM1880_PINCTRL_GRP(gpio3), + BM1880_PINCTRL_GRP(gpio4), + BM1880_PINCTRL_GRP(gpio5), + BM1880_PINCTRL_GRP(gpio6), + BM1880_PINCTRL_GRP(gpio7), + BM1880_PINCTRL_GRP(gpio8), + BM1880_PINCTRL_GRP(gpio9), + BM1880_PINCTRL_GRP(gpio10), + BM1880_PINCTRL_GRP(gpio11), + BM1880_PINCTRL_GRP(gpio12), + BM1880_PINCTRL_GRP(gpio13), + BM1880_PINCTRL_GRP(gpio14), + BM1880_PINCTRL_GRP(gpio15), + BM1880_PINCTRL_GRP(gpio16), + BM1880_PINCTRL_GRP(gpio17), + BM1880_PINCTRL_GRP(gpio18), + BM1880_PINCTRL_GRP(gpio19), + BM1880_PINCTRL_GRP(gpio20), + BM1880_PINCTRL_GRP(gpio21), + BM1880_PINCTRL_GRP(gpio22), + BM1880_PINCTRL_GRP(gpio23), + BM1880_PINCTRL_GRP(gpio24), + BM1880_PINCTRL_GRP(gpio25), + BM1880_PINCTRL_GRP(gpio26), + BM1880_PINCTRL_GRP(gpio27), + BM1880_PINCTRL_GRP(gpio28), + BM1880_PINCTRL_GRP(gpio29), + BM1880_PINCTRL_GRP(gpio30), + BM1880_PINCTRL_GRP(gpio31), + BM1880_PINCTRL_GRP(gpio32), + BM1880_PINCTRL_GRP(gpio33), + BM1880_PINCTRL_GRP(gpio34), + BM1880_PINCTRL_GRP(gpio35), + BM1880_PINCTRL_GRP(gpio36), + BM1880_PINCTRL_GRP(gpio37), + BM1880_PINCTRL_GRP(gpio38), + BM1880_PINCTRL_GRP(gpio39), + BM1880_PINCTRL_GRP(gpio40), + BM1880_PINCTRL_GRP(gpio41), + BM1880_PINCTRL_GRP(gpio42), + BM1880_PINCTRL_GRP(gpio43), + BM1880_PINCTRL_GRP(gpio44), + BM1880_PINCTRL_GRP(gpio45), + BM1880_PINCTRL_GRP(gpio46), + BM1880_PINCTRL_GRP(gpio47), + BM1880_PINCTRL_GRP(gpio48), + BM1880_PINCTRL_GRP(gpio49), + BM1880_PINCTRL_GRP(gpio50), + BM1880_PINCTRL_GRP(gpio51), + BM1880_PINCTRL_GRP(gpio52), + BM1880_PINCTRL_GRP(gpio53), + BM1880_PINCTRL_GRP(gpio54), + BM1880_PINCTRL_GRP(gpio55), + BM1880_PINCTRL_GRP(gpio56), + BM1880_PINCTRL_GRP(gpio57), + BM1880_PINCTRL_GRP(gpio58), + BM1880_PINCTRL_GRP(gpio59), + BM1880_PINCTRL_GRP(gpio60), + BM1880_PINCTRL_GRP(gpio61), + BM1880_PINCTRL_GRP(gpio62), + BM1880_PINCTRL_GRP(gpio63), + BM1880_PINCTRL_GRP(gpio64), + BM1880_PINCTRL_GRP(gpio65), + BM1880_PINCTRL_GRP(gpio66), + BM1880_PINCTRL_GRP(gpio67), + BM1880_PINCTRL_GRP(eth1), + BM1880_PINCTRL_GRP(i2s0), + BM1880_PINCTRL_GRP(i2s0_mclkin), + BM1880_PINCTRL_GRP(i2s1), + BM1880_PINCTRL_GRP(i2s1_mclkin), + BM1880_PINCTRL_GRP(spi0), +}; + +static const char * const nand_group[] = { "nand_grp" }; +static const char * const spi_group[] = { "spi_grp" }; +static const char * const emmc_group[] = { "emmc_grp" }; +static const char * const sdio_group[] = { "sdio_grp" }; +static const char * const eth0_group[] = { "eth0_grp" }; +static const char * const pwm0_group[] = { "pwm0_grp" }; +static const char * const pwm1_group[] = { "pwm1_grp" }; +static const char * const pwm2_group[] = { "pwm2_grp" }; +static const char * const pwm3_group[] = { "pwm3_grp" }; +static const char * const pwm4_group[] = { "pwm4_grp" }; +static const char * const pwm5_group[] = { "pwm5_grp" }; +static const char * const pwm6_group[] = { "pwm6_grp" }; +static const char * const pwm7_group[] = { "pwm7_grp" }; +static const char * const pwm8_group[] = { "pwm8_grp" }; +static const char * const pwm9_group[] = { "pwm9_grp" }; +static const char * const pwm10_group[] = { "pwm10_grp" }; +static const char * const pwm11_group[] = { "pwm11_grp" }; +static const char * const pwm12_group[] = { "pwm12_grp" }; +static const char * const pwm13_group[] = { "pwm13_grp" }; +static const char * const pwm14_group[] = { "pwm14_grp" }; +static const char * const pwm15_group[] = { "pwm15_grp" }; +static const char * const pwm16_group[] = { "pwm16_grp" }; +static const char * const pwm17_group[] = { "pwm17_grp" }; +static const char * const pwm18_group[] = { "pwm18_grp" }; +static const char * const pwm19_group[] = { "pwm19_grp" }; +static const char * const pwm20_group[] = { "pwm20_grp" }; +static const char * const pwm21_group[] = { "pwm21_grp" }; +static const char * const pwm22_group[] = { "pwm22_grp" }; +static const char * const pwm23_group[] = { "pwm23_grp" }; +static const char * const pwm24_group[] = { "pwm24_grp" }; +static const char * const pwm25_group[] = { "pwm25_grp" }; +static const char * const pwm26_group[] = { "pwm26_grp" }; +static const char * const pwm27_group[] = { "pwm27_grp" }; +static const char * const pwm28_group[] = { "pwm28_grp" }; +static const char * const pwm29_group[] = { "pwm29_grp" }; +static const char * const pwm30_group[] = { "pwm30_grp" }; +static const char * const pwm31_group[] = { "pwm31_grp" }; +static const char * const pwm32_group[] = { "pwm32_grp" }; +static const char * const pwm33_group[] = { "pwm33_grp" }; +static const char * const pwm34_group[] = { "pwm34_grp" }; +static const char * const pwm35_group[] = { "pwm35_grp" }; +static const char * const pwm36_group[] = { "pwm36_grp" }; +static const char * const pwm37_group[] = { "pwm37_grp" }; +static const char * const i2c0_group[] = { "i2c0_grp" }; +static const char * const i2c1_group[] = { "i2c1_grp" }; +static const char * const i2c2_group[] = { "i2c2_grp" }; +static const char * const i2c3_group[] = { "i2c3_grp" }; +static const char * const i2c4_group[] = { "i2c4_grp" }; +static const char * const uart0_group[] = { "uart0_grp" }; +static const char * const uart1_group[] = { "uart1_grp" }; +static const char * const uart2_group[] = { "uart2_grp" }; +static const char * const uart3_group[] = { "uart3_grp" }; +static const char * const uart4_group[] = { "uart4_grp" }; +static const char * const uart5_group[] = { "uart5_grp" }; +static const char * const uart6_group[] = { "uart6_grp" }; +static const char * const uart7_group[] = { "uart7_grp" }; +static const char * const uart8_group[] = { "uart8_grp" }; +static const char * const uart9_group[] = { "uart9_grp" }; +static const char * const uart10_group[] = { "uart10_grp" }; +static const char * const uart11_group[] = { "uart11_grp" }; +static const char * const uart12_group[] = { "uart12_grp" }; +static const char * const uart13_group[] = { "uart13_grp" }; +static const char * const uart14_group[] = { "uart14_grp" }; +static const char * const uart15_group[] = { "uart15_grp" }; +static const char * const gpio0_group[] = { "gpio0_grp" }; +static const char * const gpio1_group[] = { "gpio1_grp" }; +static const char * const gpio2_group[] = { "gpio2_grp" }; +static const char * const gpio3_group[] = { "gpio3_grp" }; +static const char * const gpio4_group[] = { "gpio4_grp" }; +static const char * const gpio5_group[] = { "gpio5_grp" }; +static const char * const gpio6_group[] = { "gpio6_grp" }; +static const char * const gpio7_group[] = { "gpio7_grp" }; +static const char * const gpio8_group[] = { "gpio8_grp" }; +static const char * const gpio9_group[] = { "gpio9_grp" }; +static const char * const gpio10_group[] = { "gpio10_grp" }; +static const char * const gpio11_group[] = { "gpio11_grp" }; +static const char * const gpio12_group[] = { "gpio12_grp" }; +static const char * const gpio13_group[] = { "gpio13_grp" }; +static const char * const gpio14_group[] = { "gpio14_grp" }; +static const char * const gpio15_group[] = { "gpio15_grp" }; +static const char * const gpio16_group[] = { "gpio16_grp" }; +static const char * const gpio17_group[] = { "gpio17_grp" }; +static const char * const gpio18_group[] = { "gpio18_grp" }; +static const char * const gpio19_group[] = { "gpio19_grp" }; +static const char * const gpio20_group[] = { "gpio20_grp" }; +static const char * const gpio21_group[] = { "gpio21_grp" }; +static const char * const gpio22_group[] = { "gpio22_grp" }; +static const char * const gpio23_group[] = { "gpio23_grp" }; +static const char * const gpio24_group[] = { "gpio24_grp" }; +static const char * const gpio25_group[] = { "gpio25_grp" }; +static const char * const gpio26_group[] = { "gpio26_grp" }; +static const char * const gpio27_group[] = { "gpio27_grp" }; +static const char * const gpio28_group[] = { "gpio28_grp" }; +static const char * const gpio29_group[] = { "gpio29_grp" }; +static const char * const gpio30_group[] = { "gpio30_grp" }; +static const char * const gpio31_group[] = { "gpio31_grp" }; +static const char * const gpio32_group[] = { "gpio32_grp" }; +static const char * const gpio33_group[] = { "gpio33_grp" }; +static const char * const gpio34_group[] = { "gpio34_grp" }; +static const char * const gpio35_group[] = { "gpio35_grp" }; +static const char * const gpio36_group[] = { "gpio36_grp" }; +static const char * const gpio37_group[] = { "gpio37_grp" }; +static const char * const gpio38_group[] = { "gpio38_grp" }; +static const char * const gpio39_group[] = { "gpio39_grp" }; +static const char * const gpio40_group[] = { "gpio40_grp" }; +static const char * const gpio41_group[] = { "gpio41_grp" }; +static const char * const gpio42_group[] = { "gpio42_grp" }; +static const char * const gpio43_group[] = { "gpio43_grp" }; +static const char * const gpio44_group[] = { "gpio44_grp" }; +static const char * const gpio45_group[] = { "gpio45_grp" }; +static const char * const gpio46_group[] = { "gpio46_grp" }; +static const char * const gpio47_group[] = { "gpio47_grp" }; +static const char * const gpio48_group[] = { "gpio48_grp" }; +static const char * const gpio49_group[] = { "gpio49_grp" }; +static const char * const gpio50_group[] = { "gpio50_grp" }; +static const char * const gpio51_group[] = { "gpio51_grp" }; +static const char * const gpio52_group[] = { "gpio52_grp" }; +static const char * const gpio53_group[] = { "gpio53_grp" }; +static const char * const gpio54_group[] = { "gpio54_grp" }; +static const char * const gpio55_group[] = { "gpio55_grp" }; +static const char * const gpio56_group[] = { "gpio56_grp" }; +static const char * const gpio57_group[] = { "gpio57_grp" }; +static const char * const gpio58_group[] = { "gpio58_grp" }; +static const char * const gpio59_group[] = { "gpio59_grp" }; +static const char * const gpio60_group[] = { "gpio60_grp" }; +static const char * const gpio61_group[] = { "gpio61_grp" }; +static const char * const gpio62_group[] = { "gpio62_grp" }; +static const char * const gpio63_group[] = { "gpio63_grp" }; +static const char * const gpio64_group[] = { "gpio64_grp" }; +static const char * const gpio65_group[] = { "gpio65_grp" }; +static const char * const gpio66_group[] = { "gpio66_grp" }; +static const char * const gpio67_group[] = { "gpio67_grp" }; +static const char * const eth1_group[] = { "eth1_grp" }; +static const char * const i2s0_group[] = { "i2s0_grp" }; +static const char * const i2s0_mclkin_group[] = { "i2s0_mclkin_grp" }; +static const char * const i2s1_group[] = { "i2s1_grp" }; +static const char * const i2s1_mclkin_group[] = { "i2s1_mclkin_grp" }; +static const char * const spi0_group[] = { "spi0_grp" }; + +#define BM1880_PINMUX_FUNCTION(fname, mval, mask) \ + [F_##fname] = { \ + .name = #fname, \ + .groups = fname##_group, \ + .ngroups = ARRAY_SIZE(fname##_group), \ + .mux_val = mval, \ + .mux_mask = mask, \ + } + +#define BM1880_PINMUX_FUNCTION_MUX(fname, mval, mask, offset, shift)\ + [F_##fname] = { \ + .name = #fname, \ + .groups = fname##_group, \ + .ngroups = ARRAY_SIZE(fname##_group), \ + .mux_val = mval, \ + .mux_mask = mask, \ + .mux = offset, \ + .mux_shift = shift, \ + } + +static const struct bm1880_pinmux_function bm1880_pmux_functions[] = { + BM1880_PINMUX_FUNCTION(nand, 2, 0x03), + BM1880_PINMUX_FUNCTION(spi, 0, 0x03), + BM1880_PINMUX_FUNCTION(emmc, 1, 0x03), + BM1880_PINMUX_FUNCTION(sdio, 0, 0x03), + BM1880_PINMUX_FUNCTION(eth0, 0, 0x03), + BM1880_PINMUX_FUNCTION_MUX(pwm0, 2, 0x0F, 0x50, 0x00), + BM1880_PINMUX_FUNCTION_MUX(pwm1, 2, 0x0F, 0x50, 0x04), + BM1880_PINMUX_FUNCTION_MUX(pwm2, 2, 0x0F, 0x50, 0x08), + BM1880_PINMUX_FUNCTION_MUX(pwm3, 2, 0x0F, 0x50, 0x0C), + BM1880_PINMUX_FUNCTION_MUX(pwm4, 2, 0x0F, 0x50, 0x10), + BM1880_PINMUX_FUNCTION_MUX(pwm5, 2, 0x0F, 0x50, 0x14), + BM1880_PINMUX_FUNCTION_MUX(pwm6, 2, 0x0F, 0x50, 0x18), + BM1880_PINMUX_FUNCTION_MUX(pwm7, 2, 0x0F, 0x50, 0x1C), + BM1880_PINMUX_FUNCTION_MUX(pwm8, 2, 0x0F, 0x54, 0x00), + BM1880_PINMUX_FUNCTION_MUX(pwm9, 2, 0x0F, 0x54, 0x04), + BM1880_PINMUX_FUNCTION_MUX(pwm10, 2, 0x0F, 0x54, 0x08), + BM1880_PINMUX_FUNCTION_MUX(pwm11, 2, 0x0F, 0x54, 0x0C), + BM1880_PINMUX_FUNCTION_MUX(pwm12, 2, 0x0F, 0x54, 0x10), + BM1880_PINMUX_FUNCTION_MUX(pwm13, 2, 0x0F, 0x54, 0x14), + BM1880_PINMUX_FUNCTION_MUX(pwm14, 2, 0x0F, 0x54, 0x18), + BM1880_PINMUX_FUNCTION_MUX(pwm15, 2, 0x0F, 0x54, 0x1C), + BM1880_PINMUX_FUNCTION_MUX(pwm16, 2, 0x0F, 0x58, 0x00), + BM1880_PINMUX_FUNCTION_MUX(pwm17, 2, 0x0F, 0x58, 0x04), + BM1880_PINMUX_FUNCTION_MUX(pwm18, 2, 0x0F, 0x58, 0x08), + BM1880_PINMUX_FUNCTION_MUX(pwm19, 2, 0x0F, 0x58, 0x0C), + BM1880_PINMUX_FUNCTION_MUX(pwm20, 2, 0x0F, 0x58, 0x10), + BM1880_PINMUX_FUNCTION_MUX(pwm21, 2, 0x0F, 0x58, 0x14), + BM1880_PINMUX_FUNCTION_MUX(pwm22, 2, 0x0F, 0x58, 0x18), + BM1880_PINMUX_FUNCTION_MUX(pwm23, 2, 0x0F, 0x58, 0x1C), + BM1880_PINMUX_FUNCTION_MUX(pwm24, 2, 0x0F, 0x5C, 0x00), + BM1880_PINMUX_FUNCTION_MUX(pwm25, 2, 0x0F, 0x5C, 0x04), + BM1880_PINMUX_FUNCTION_MUX(pwm26, 2, 0x0F, 0x5C, 0x08), + BM1880_PINMUX_FUNCTION_MUX(pwm27, 2, 0x0F, 0x5C, 0x0C), + BM1880_PINMUX_FUNCTION_MUX(pwm28, 2, 0x0F, 0x5C, 0x10), + BM1880_PINMUX_FUNCTION_MUX(pwm29, 2, 0x0F, 0x5C, 0x14), + BM1880_PINMUX_FUNCTION_MUX(pwm30, 2, 0x0F, 0x5C, 0x18), + BM1880_PINMUX_FUNCTION_MUX(pwm31, 2, 0x0F, 0x5C, 0x1C), + BM1880_PINMUX_FUNCTION_MUX(pwm32, 2, 0x0F, 0x60, 0x00), + BM1880_PINMUX_FUNCTION_MUX(pwm33, 2, 0x0F, 0x60, 0x04), + BM1880_PINMUX_FUNCTION_MUX(pwm34, 2, 0x0F, 0x60, 0x08), + BM1880_PINMUX_FUNCTION_MUX(pwm35, 2, 0x0F, 0x60, 0x0C), + BM1880_PINMUX_FUNCTION_MUX(pwm36, 2, 0x0F, 0x60, 0x10), + BM1880_PINMUX_FUNCTION_MUX(pwm37, 2, 0x0F, 0x60, 0x1C), + BM1880_PINMUX_FUNCTION(i2c0, 1, 0x03), + BM1880_PINMUX_FUNCTION(i2c1, 1, 0x03), + BM1880_PINMUX_FUNCTION(i2c2, 1, 0x03), + BM1880_PINMUX_FUNCTION(i2c3, 1, 0x03), + BM1880_PINMUX_FUNCTION(i2c4, 1, 0x03), + BM1880_PINMUX_FUNCTION(uart0, 1, 0x03), + BM1880_PINMUX_FUNCTION(uart1, 1, 0x03), + BM1880_PINMUX_FUNCTION(uart2, 1, 0x03), + BM1880_PINMUX_FUNCTION(uart3, 1, 0x03), + BM1880_PINMUX_FUNCTION(uart4, 1, 0x03), + BM1880_PINMUX_FUNCTION(uart5, 1, 0x03), + BM1880_PINMUX_FUNCTION(uart6, 1, 0x03), + BM1880_PINMUX_FUNCTION(uart7, 1, 0x03), + BM1880_PINMUX_FUNCTION(uart8, 1, 0x03), + BM1880_PINMUX_FUNCTION(uart9, 1, 0x03), + BM1880_PINMUX_FUNCTION(uart10, 1, 0x03), + BM1880_PINMUX_FUNCTION(uart11, 1, 0x03), + BM1880_PINMUX_FUNCTION(uart12, 3, 0x03), + BM1880_PINMUX_FUNCTION(uart13, 3, 0x03), + BM1880_PINMUX_FUNCTION(uart14, 3, 0x03), + BM1880_PINMUX_FUNCTION(uart15, 3, 0x03), + BM1880_PINMUX_FUNCTION_MUX(gpio0, 0, 0x03, 0x4E0, 0x14), + BM1880_PINMUX_FUNCTION_MUX(gpio1, 0, 0x03, 0x4E4, 0x04), + BM1880_PINMUX_FUNCTION_MUX(gpio2, 0, 0x03, 0x4E4, 0x14), + BM1880_PINMUX_FUNCTION_MUX(gpio3, 0, 0x03, 0x4E8, 0x04), + BM1880_PINMUX_FUNCTION_MUX(gpio4, 0, 0x03, 0x4E8, 0x14), + BM1880_PINMUX_FUNCTION_MUX(gpio5, 0, 0x03, 0x4EC, 0x04), + BM1880_PINMUX_FUNCTION_MUX(gpio6, 0, 0x03, 0x4EC, 0x14), + BM1880_PINMUX_FUNCTION_MUX(gpio7, 0, 0x03, 0x4F0, 0x04), + BM1880_PINMUX_FUNCTION_MUX(gpio8, 0, 0x03, 0x4F0, 0x14), + BM1880_PINMUX_FUNCTION_MUX(gpio9, 0, 0x03, 0x4F4, 0x04), + BM1880_PINMUX_FUNCTION_MUX(gpio10, 0, 0x03, 0x4F4, 0x14), + BM1880_PINMUX_FUNCTION_MUX(gpio11, 0, 0x03, 0x4F8, 0x04), + BM1880_PINMUX_FUNCTION_MUX(gpio12, 1, 0x03, 0x4F8, 0x14), + BM1880_PINMUX_FUNCTION_MUX(gpio13, 1, 0x03, 0x4FC, 0x04), + BM1880_PINMUX_FUNCTION_MUX(gpio14, 0, 0x03, 0x474, 0x14), + BM1880_PINMUX_FUNCTION_MUX(gpio15, 0, 0x03, 0x478, 0x04), + BM1880_PINMUX_FUNCTION_MUX(gpio16, 0, 0x03, 0x478, 0x14), + BM1880_PINMUX_FUNCTION_MUX(gpio17, 0, 0x03, 0x47C, 0x04), + BM1880_PINMUX_FUNCTION_MUX(gpio18, 0, 0x03, 0x47C, 0x14), + BM1880_PINMUX_FUNCTION_MUX(gpio19, 0, 0x03, 0x480, 0x04), + BM1880_PINMUX_FUNCTION_MUX(gpio20, 0, 0x03, 0x480, 0x14), + BM1880_PINMUX_FUNCTION_MUX(gpio21, 0, 0x03, 0x484, 0x04), + BM1880_PINMUX_FUNCTION_MUX(gpio22, 0, 0x03, 0x484, 0x14), + BM1880_PINMUX_FUNCTION_MUX(gpio23, 0, 0x03, 0x488, 0x04), + BM1880_PINMUX_FUNCTION_MUX(gpio24, 0, 0x03, 0x488, 0x14), + BM1880_PINMUX_FUNCTION_MUX(gpio25, 0, 0x03, 0x48C, 0x04), + BM1880_PINMUX_FUNCTION_MUX(gpio26, 0, 0x03, 0x48C, 0x14), + BM1880_PINMUX_FUNCTION_MUX(gpio27, 0, 0x03, 0x490, 0x04), + BM1880_PINMUX_FUNCTION_MUX(gpio28, 0, 0x03, 0x490, 0x14), + BM1880_PINMUX_FUNCTION_MUX(gpio29, 0, 0x03, 0x494, 0x04), + BM1880_PINMUX_FUNCTION_MUX(gpio30, 0, 0x03, 0x494, 0x14), + BM1880_PINMUX_FUNCTION_MUX(gpio31, 0, 0x03, 0x498, 0x04), + BM1880_PINMUX_FUNCTION_MUX(gpio32, 0, 0x03, 0x498, 0x14), + BM1880_PINMUX_FUNCTION_MUX(gpio33, 0, 0x03, 0x49C, 0x04), + BM1880_PINMUX_FUNCTION_MUX(gpio34, 0, 0x03, 0x49C, 0x14), + BM1880_PINMUX_FUNCTION_MUX(gpio35, 0, 0x03, 0x4A0, 0x04), + BM1880_PINMUX_FUNCTION_MUX(gpio36, 0, 0x03, 0x4A0, 0x14), + BM1880_PINMUX_FUNCTION_MUX(gpio37, 0, 0x03, 0x4A4, 0x04), + BM1880_PINMUX_FUNCTION_MUX(gpio38, 0, 0x03, 0x4A4, 0x14), + BM1880_PINMUX_FUNCTION_MUX(gpio39, 0, 0x03, 0x4A8, 0x04), + BM1880_PINMUX_FUNCTION_MUX(gpio40, 0, 0x03, 0x4A8, 0x14), + BM1880_PINMUX_FUNCTION_MUX(gpio41, 0, 0x03, 0x4AC, 0x04), + BM1880_PINMUX_FUNCTION_MUX(gpio42, 0, 0x03, 0x4AC, 0x14), + BM1880_PINMUX_FUNCTION_MUX(gpio43, 0, 0x03, 0x4B0, 0x04), + BM1880_PINMUX_FUNCTION_MUX(gpio44, 0, 0x03, 0x4B0, 0x14), + BM1880_PINMUX_FUNCTION_MUX(gpio45, 0, 0x03, 0x4B4, 0x04), + BM1880_PINMUX_FUNCTION_MUX(gpio46, 0, 0x03, 0x4B4, 0x14), + BM1880_PINMUX_FUNCTION_MUX(gpio47, 0, 0x03, 0x4B8, 0x04), + BM1880_PINMUX_FUNCTION_MUX(gpio48, 0, 0x03, 0x4B8, 0x14), + BM1880_PINMUX_FUNCTION_MUX(gpio49, 0, 0x03, 0x4BC, 0x04), + BM1880_PINMUX_FUNCTION_MUX(gpio50, 0, 0x03, 0x4BC, 0x14), + BM1880_PINMUX_FUNCTION_MUX(gpio51, 0, 0x03, 0x4C0, 0x04), + BM1880_PINMUX_FUNCTION_MUX(gpio52, 0, 0x03, 0x4C0, 0x14), + BM1880_PINMUX_FUNCTION_MUX(gpio53, 0, 0x03, 0x4C4, 0x04), + BM1880_PINMUX_FUNCTION_MUX(gpio54, 0, 0x03, 0x4C4, 0x14), + BM1880_PINMUX_FUNCTION_MUX(gpio55, 0, 0x03, 0x4C8, 0x04), + BM1880_PINMUX_FUNCTION_MUX(gpio56, 0, 0x03, 0x4C8, 0x14), + BM1880_PINMUX_FUNCTION_MUX(gpio57, 0, 0x03, 0x4CC, 0x04), + BM1880_PINMUX_FUNCTION_MUX(gpio58, 0, 0x03, 0x4CC, 0x14), + BM1880_PINMUX_FUNCTION_MUX(gpio59, 0, 0x03, 0x4D0, 0x04), + BM1880_PINMUX_FUNCTION_MUX(gpio60, 0, 0x03, 0x4D0, 0x14), + BM1880_PINMUX_FUNCTION_MUX(gpio61, 0, 0x03, 0x4D4, 0x04), + BM1880_PINMUX_FUNCTION_MUX(gpio62, 0, 0x03, 0x4D4, 0x14), + BM1880_PINMUX_FUNCTION_MUX(gpio63, 0, 0x03, 0x4D8, 0x04), + BM1880_PINMUX_FUNCTION_MUX(gpio64, 0, 0x03, 0x4D8, 0x14), + BM1880_PINMUX_FUNCTION_MUX(gpio65, 0, 0x03, 0x4DC, 0x04), + BM1880_PINMUX_FUNCTION_MUX(gpio66, 0, 0x03, 0x4DC, 0x14), + BM1880_PINMUX_FUNCTION_MUX(gpio67, 0, 0x03, 0x4E0, 0x04), + BM1880_PINMUX_FUNCTION(eth1, 1, 0x03), + BM1880_PINMUX_FUNCTION(i2s0, 2, 0x03), + BM1880_PINMUX_FUNCTION(i2s0_mclkin, 1, 0x03), + BM1880_PINMUX_FUNCTION(i2s1, 2, 0x03), + BM1880_PINMUX_FUNCTION(i2s1_mclkin, 1, 0x03), + BM1880_PINMUX_FUNCTION(spi0, 1, 0x03), +}; + +static int bm1880_pctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->ngroups; +} + +static const char *bm1880_pctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->groups[selector].name; +} + +static int bm1880_pctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int selector, + const unsigned int **pins, + unsigned int *num_pins) +{ + struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + *pins = pctrl->groups[selector].pins; + *num_pins = pctrl->groups[selector].npins; + + return 0; +} + +static const struct pinctrl_ops bm1880_pctrl_ops = { + .get_groups_count = bm1880_pctrl_get_groups_count, + .get_group_name = bm1880_pctrl_get_group_name, + .get_group_pins = bm1880_pctrl_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_all, + .dt_free_map = pinctrl_utils_free_map, +}; + +/* pinmux */ +static int bm1880_pmux_get_functions_count(struct pinctrl_dev *pctldev) +{ + struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->nfuncs; +} + +static const char *bm1880_pmux_get_function_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->funcs[selector].name; +} + +static int bm1880_pmux_get_function_groups(struct pinctrl_dev *pctldev, + unsigned int selector, + const char * const **groups, + unsigned * const num_groups) +{ + struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + *groups = pctrl->funcs[selector].groups; + *num_groups = pctrl->funcs[selector].ngroups; + return 0; +} + +static int bm1880_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned int function, + unsigned int group) +{ + struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct bm1880_pctrl_group *pgrp = &pctrl->groups[group]; + const struct bm1880_pinmux_function *func = &pctrl->funcs[function]; + int i; + + if (func->mux) { + u32 regval = readl_relaxed(pctrl->base + BM1880_REG_MUX + + func->mux); + + regval &= ~(func->mux_mask << func->mux_shift); + regval |= func->mux_val << func->mux_shift; + writel_relaxed(regval, pctrl->base + BM1880_REG_MUX + + func->mux); + } else { + for (i = 0; i < pgrp->npins; i++) { + unsigned int pin = pgrp->pins[i]; + u32 offset = (pin >> 1) << 2; + u32 mux_offset = ((!((pin + 1) & 1) << 4) + 4); + u32 regval = readl_relaxed(pctrl->base + + BM1880_REG_MUX + offset); + + regval &= ~(func->mux_mask << mux_offset); + regval |= func->mux_val << mux_offset; + + writel_relaxed(regval, pctrl->base + + BM1880_REG_MUX + offset); + } + } + + return 0; +} + +static const struct pinmux_ops bm1880_pinmux_ops = { + .get_functions_count = bm1880_pmux_get_functions_count, + .get_function_name = bm1880_pmux_get_function_name, + .get_function_groups = bm1880_pmux_get_function_groups, + .set_mux = bm1880_pinmux_set_mux, +}; + +static struct pinctrl_desc bm1880_desc = { + .name = "bm1880_pinctrl", + .pins = bm1880_pins, + .npins = ARRAY_SIZE(bm1880_pins), + .pctlops = &bm1880_pctrl_ops, + .pmxops = &bm1880_pinmux_ops, + .owner = THIS_MODULE, +}; + +static int bm1880_pinctrl_probe(struct platform_device *pdev) + +{ + struct resource *res; + struct bm1880_pinctrl *pctrl; + + pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pctrl->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pctrl->base)) + return PTR_ERR(pctrl->base); + + pctrl->groups = bm1880_pctrl_groups; + pctrl->ngroups = ARRAY_SIZE(bm1880_pctrl_groups); + pctrl->funcs = bm1880_pmux_functions; + pctrl->nfuncs = ARRAY_SIZE(bm1880_pmux_functions); + + pctrl->pctrldev = devm_pinctrl_register(&pdev->dev, &bm1880_desc, + pctrl); + if (IS_ERR(pctrl->pctrldev)) + return PTR_ERR(pctrl->pctrldev); + + platform_set_drvdata(pdev, pctrl); + + dev_info(&pdev->dev, "BM1880 pinctrl driver initialized\n"); + + return 0; +} + +static const struct of_device_id bm1880_pinctrl_of_match[] = { + { .compatible = "bitmain,bm1880-pinctrl" }, + { } +}; + +static struct platform_driver bm1880_pinctrl_driver = { + .driver = { + .name = "pinctrl-bm1880", + .of_match_table = of_match_ptr(bm1880_pinctrl_of_match), + }, + .probe = bm1880_pinctrl_probe, +}; + +static int __init bm1880_pinctrl_init(void) +{ + return platform_driver_register(&bm1880_pinctrl_driver); +} +arch_initcall(bm1880_pinctrl_init); From patchwork Wed Apr 24 12:02:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 162779 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp572586jan; Wed, 24 Apr 2019 05:03:47 -0700 (PDT) X-Google-Smtp-Source: APXvYqwv4yy1kosYCnQ3mUK1t+ZJfrCJhYGpDFINNKfP/TuALGUk0fhpT4GzoFKq+DtgF87Ek52F X-Received: by 2002:a17:902:f212:: with SMTP id gn18mr18534114plb.126.1556107427835; Wed, 24 Apr 2019 05:03:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556107427; cv=none; d=google.com; s=arc-20160816; b=nx4TTH4L93acZA4XeFtkkAaK05NsE0P/xikBDrtUBkVxyJk9ddLzFAKFbtI2ZC8fYp ObwK2Ku5Lzv8hHdc6mGsIFnivMe1I07lKJCKW/Y+QOO/cEiJqkR1zSOk9n9BIcjKzrqz 3VqNXpzsJ8i3UW3OV0dGSku/3Ed0jCLFmx92Q84tsoPrcopqrJNV4/6QQselEN/o+0AE 1FLFpFpOMno9ZAOK0Nc9qYHLJXafgoav9J6pZ3L3XL2mIgDje4ewTzFf+/Vs74mZWw1P t6zQhPdPf45D/mNlxmCZrN2JR7Hc4O1wL9RH4lQ0WpUhOK2ecfDHulZ7yHPc/mUqEp85 kqvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=W9bSn0OqpP5RdzN44itrr4Bd4P8/I8xsjoaJwybVMyw=; b=n8kfMRj1empuvJSayNifmSSb0E0BFhRASZn4hqgGwogjbY406XoldQuU3cYC5zUYQX 6RsynS0U6Zzavwp3qAUJQli8rmERXRrsGMQU+2e0n4hR1GLiu1IUXbouVYr5axITV/Zy EkyDUvi8ZqwRtNNpVmOtBs99tAaoRGxOa35ZFUiEKIk3j7JZL+YNoTiHzF6HWpEvmS9p ELFVmeg3tNkDG3Rk28a/awcbZQb2QeDPT3R/hj7hWlnnSU1J7MbIooKbwY6dh3j7jUVi 0TPx76xGYAv+qQzwbu6HW8sRAliCYzMZ5tuAXqR7Fek65HvzEJ4Yqi8n76hWGP3V2SfH 1daA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oUWcHKtg; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d2si18248008pgh.499.2019.04.24.05.03.47; Wed, 24 Apr 2019 05:03:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oUWcHKtg; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728463AbfDXMDr (ORCPT + 7 others); Wed, 24 Apr 2019 08:03:47 -0400 Received: from mail-pf1-f194.google.com ([209.85.210.194]:45579 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729644AbfDXMDn (ORCPT ); Wed, 24 Apr 2019 08:03:43 -0400 Received: by mail-pf1-f194.google.com with SMTP id e24so9186950pfi.12 for ; Wed, 24 Apr 2019 05:03:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=W9bSn0OqpP5RdzN44itrr4Bd4P8/I8xsjoaJwybVMyw=; b=oUWcHKtglfevDr79ibcbnHC0CQACs+X1fLjHBpqiw0pRgA1ncsIVM/hVxcQoC05Fls SPZHMA+jf8R0hUYlXc9C1NSO7/k9y9B5ru13VCWmcghib+sIDuxHxNx0WA8X0pHdFnUn e3BDPQct1ny0LsPKy5nyn3UK+1F3vxyEU/EuoLwYvE52r0BAAmC0sI+jwwfqXHDCUZYm U61l5XmrtfOXSaU+VSQOOXpmlaijyI1tg/3mtNkHnZhmDmoFQecGVTq9XsplP6xbhI6Y ZBKcvMXPuxFGsTVqMnKVjiJ2CLa5R0NGnwXyP1dO3yKqYXb92cQyCHa8mlDEE38NnCv0 mDyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=W9bSn0OqpP5RdzN44itrr4Bd4P8/I8xsjoaJwybVMyw=; b=Psix+GfarAIZXsHDErB9cL8UsL7sa8S1KTvTCxXGta9+iGscWQsYrCxGQbMbiboEYg fg7NRAXHB0TRJwRBgqf+AkW5FNmHndHuA5fwbOrG7js9Sa2NLoZgSsmBCteB76+MmRdl 0XgjCJpTapBl+VTsIgPWNXV5SbaIxxByZhHGqX/hO5XlkCpUqEC2ocGrQpYXAFKIVibz HphIsKkfWEb8aOfer4y/4gjnQ0TBBqXWPS6JuShOn1EsCELqnFkmE1MGi8nulfK4vRBF DCcoBLkyFcFg6MAHf+ROz/aLUj2GoagwVS3GAQLTiQflS1SCcK+cEAWD/Q1aU/Btd08Y tYRg== X-Gm-Message-State: APjAAAXVR92ci3Y2zm8Lcmv5zSXjo+HccAtFaAT8qC0Avzy0faSBsZA9 iQV0V91PtVYzg7prTgBLAaUc X-Received: by 2002:aa7:920b:: with SMTP id 11mr32005423pfo.3.1556107422940; Wed, 24 Apr 2019 05:03:42 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:711:bac8:7d48:1fca:4d86:743]) by smtp.gmail.com with ESMTPSA id j22sm25870840pfn.129.2019.04.24.05.03.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 24 Apr 2019 05:03:42 -0700 (PDT) From: Manivannan Sadhasivam To: linus.walleij@linaro.org, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, haitao.suo@bitmain.com, darren.tsao@bitmain.com, linux-gpio@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 5/5] MAINTAINERS: Add entry for BM1880 pinctrl Date: Wed, 24 Apr 2019 17:32:24 +0530 Message-Id: <20190424120224.22660-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190424120224.22660-1-manivannan.sadhasivam@linaro.org> References: <20190424120224.22660-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add MAINTAINERS entry for Bitmain BM1880 SoC pinctrl. Signed-off-by: Manivannan Sadhasivam --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) -- 2.17.1 diff --git a/MAINTAINERS b/MAINTAINERS index 3671fdea5010..8b5fcb89a8a4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1416,7 +1416,9 @@ M: Manivannan Sadhasivam L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm64/boot/dts/bitmain/ +F: drivers/pinctrl/pinctrl-bm1880.c F: Documentation/devicetree/bindings/arm/bitmain.yaml +F: Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt ARM/CALXEDA HIGHBANK ARCHITECTURE M: Rob Herring