From patchwork Mon Jan 30 23:59:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 648779 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E4BBC636D3 for ; Mon, 30 Jan 2023 23:59:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231331AbjA3X76 (ORCPT ); Mon, 30 Jan 2023 18:59:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42432 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231414AbjA3X7r (ORCPT ); Mon, 30 Jan 2023 18:59:47 -0500 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AB68827D54 for ; Mon, 30 Jan 2023 15:59:44 -0800 (PST) Received: by mail-ej1-x632.google.com with SMTP id hx15so17375008ejc.11 for ; Mon, 30 Jan 2023 15:59:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MjPN7pBI5UqQh3zYwpXxa2DpIw4tZgUWZdbUG7h3884=; b=OLrdnLOzIkECvzt95wsqIhyo24/uSrgDF8q5Bvv0vkVC1f8PcjmrnFHpJtSjG161ih 7H7+bgvKNhypgoAMtLTsK2oLxVamvl7BQqDrfXflzsBCdCFo/z7KN2O2nmTysf3IRjNs M2yzxS5WCXSYDIIt9wZiPWwJsoFjrrWSzMAeJ1UM7v9k8WToNvIoRREBeannx2TJneYr ++nv61VGF6ibNoItFTJcxOoyjLcJUXRv0yT/9rfkDMhF3o9uridjDBxPqf4xag8rgwGB DprbW5I4P6weCnbKNnmNtQFLokJ3WhiWVSGu6lFMCGBtqO2g0D0wQ/v98OwKTCvdrJCo p+fQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MjPN7pBI5UqQh3zYwpXxa2DpIw4tZgUWZdbUG7h3884=; b=KgbPY7k3xKNm7j4UXTZ41nPWd+Z3OGuX/h/Autb5mDXw3IKpNZTd6YR6Q34zil3GkQ 3O5IWWN0+HNScdAOUtR+jLhFcFsVRGuiXjHJeQAe22EgHmcbDeVZPf69Rk5+o59dtbww wxCxHQ/O6J3HrB2N8YKUy0vDD2syjVU/RygYeOy56ZPxqV7pCtonHoZUaBqwRxbPO8we DQ/ZwW/ghXYkC0Z8waWsS86b0KMLxSZgD6ZWbFRrBg7BilKDcMBFkKtQTiNA/qE4MsMJ aYDKI1cNASNTHRYx/q5v58cf0+IuDuEaefG4/riE8OqwCQHIHMgFU1Mrn+UeIac4PzER SKuA== X-Gm-Message-State: AFqh2kr8czQHnlQOazO7pWbhF9eyqdkBE6uLtI0oJEMFm7IRWdDGiOoO KcDztZ1pjL/FF4lypSA9NnpuHQ== X-Google-Smtp-Source: AMrXdXshBq2A+aG9X2v+nQs+pC5yo4FtU1/Zkj/YtJ/chHsF2tTwAoGKEfKxDX+wCZAwXqGx7kQdIA== X-Received: by 2002:a17:906:3741:b0:861:eb6e:8019 with SMTP id e1-20020a170906374100b00861eb6e8019mr49525879ejc.69.1675123183202; Mon, 30 Jan 2023 15:59:43 -0800 (PST) Received: from localhost.localdomain (abyl20.neoplus.adsl.tpnet.pl. [83.9.31.20]) by smtp.gmail.com with ESMTPSA id jr23-20020a170906515700b0086f4b8f9e42sm7577751ejc.65.2023.01.30.15.59.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 15:59:42 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 5/8] dt-bindings: clock: Add Qcom SM6375 GPUCC Date: Tue, 31 Jan 2023 00:59:23 +0100 Message-Id: <20230130235926.2419776-6-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230130235926.2419776-1-konrad.dybcio@linaro.org> References: <20230130235926.2419776-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM6375 SoCs. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- .../bindings/clock/qcom,sm6375-gpucc.yaml | 60 +++++++++++++++++++ include/dt-bindings/clock/qcom,sm6375-gpucc.h | 36 +++++++++++ 2 files changed, 96 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml create mode 100644 include/dt-bindings/clock/qcom,sm6375-gpucc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml new file mode 100644 index 000000000000..b480ead5bd69 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm6375-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on SM6375 + +maintainers: + - Konrad Dybcio + +description: | + Qualcomm graphics clock control module provides clocks, resets and power + domains on Qualcomm SoCs. + + See also:: include/dt-bindings/clock/qcom,sm6375-gpucc.h + +properties: + compatible: + enum: + - qcom,sm6375-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 div branch source + - description: SNoC DVM GFX source + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@5990000 { + compatible = "qcom,sm6375-gpucc"; + reg = <0 0x05990000 0 0x9000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,sm6375-gpucc.h b/include/dt-bindings/clock/qcom,sm6375-gpucc.h new file mode 100644 index 000000000000..0887ac03825e --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm6375-gpucc.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_BLAIR_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_BLAIR_H + +/* GPU CC clocks */ +#define GPU_CC_PLL0 0 +#define GPU_CC_PLL1 1 +#define GPU_CC_AHB_CLK 2 +#define GPU_CC_CX_GFX3D_CLK 3 +#define GPU_CC_CX_GFX3D_SLV_CLK 4 +#define GPU_CC_CX_GMU_CLK 5 +#define GPU_CC_CX_SNOC_DVM_CLK 6 +#define GPU_CC_CXO_AON_CLK 7 +#define GPU_CC_CXO_CLK 8 +#define GPU_CC_GMU_CLK_SRC 9 +#define GPU_CC_GX_CXO_CLK 10 +#define GPU_CC_GX_GFX3D_CLK 11 +#define GPU_CC_GX_GFX3D_CLK_SRC 12 +#define GPU_CC_GX_GMU_CLK 13 +#define GPU_CC_SLEEP_CLK 14 + +/* GDSCs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +/* Resets */ +#define GPU_GX_BCR 0 +#define GPU_ACD_BCR 1 +#define GPU_GX_ACD_MISC_BCR 2 + +#endif From patchwork Mon Jan 30 23:59:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 648778 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4CEEFC64EC4 for ; Tue, 31 Jan 2023 00:00:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231360AbjAaAAA (ORCPT ); Mon, 30 Jan 2023 19:00:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42548 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231530AbjA3X7x (ORCPT ); Mon, 30 Jan 2023 18:59:53 -0500 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B1F7523DA2 for ; Mon, 30 Jan 2023 15:59:48 -0800 (PST) Received: by mail-ej1-x630.google.com with SMTP id me3so36897401ejb.7 for ; Mon, 30 Jan 2023 15:59:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CDoOdjfsWKmLJAB94hSuPuVJscqgiA2qYQ0HfGwlM14=; b=zoyMpp6Mw+IHu+8pRT4ByKS6CEL8Oce2qDWrBO8hJwrcv/2e8dYzGpI15NGI82Thps dCmxAy30En9Rd3j3SiAtYVC+TdAs7V1E0IRG4t0WL6SbwIvMNZPOKOOy982SQLYdCvVv KYiKAc72zusfWG7C6QPKS6y/rrXrDM0wxtDyiPztjRNlfcoSzY/VYcchuTZ71q0N/66y yX/YkTlj1+Ts6UUaTW7/bSnLC6WTm/99flXNYicRVsa64lRZKd7TqEUPFKEuwbKjjTy8 D+cc3DMM5Yp3d+LvZkhZkAF+Ufb3R+0axI1ObSghkxANaKCcoCEWPx9aCq1L/zJeN+7X tC/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CDoOdjfsWKmLJAB94hSuPuVJscqgiA2qYQ0HfGwlM14=; b=AhEsk85DC5kvTKWJJzdJX/tODo9qnXDxlqdng3jxKO4tV5cOa7kJNqaryTH57u24LO /nWVq4+Y9sDoKQvip70ac+RpQBJK4O09sJ7LOkrZRUdA8IMvDOGdbtPaCMNclkUVVAfw Z6mDXxEgQYe9fT4U+NdWo7mWr5zDb1LeuV2yRbEcYNbl8SIIlCof1tpsmFPvr1EpsXwD wVw+8Kg9lVoETlpuzZlQI9VrzfxkUF0I3XmZXg5yh+fBpC015NqVZMK5v3IMjT5a/+63 HpZPNX67CMO40fpffpYoYyEtjyITyzgwxD6nXZJ4yjWShxp5+HZuQ5fCKHs1iiUiiXWz AQxw== X-Gm-Message-State: AO0yUKXdrM1beApMh/jmofgZTISnTbsgKmjReLbWcoM1RiTxRUFGMe5K OV2EYckB2veaVYsR2nOSAHFFRQ== X-Google-Smtp-Source: AK7set8Ozk7kadx6GKeokKjGlVdmDRVF4XNjXDE/8Bmt3bcgkElGINLh5+oEVFJ5gIQ+6239+tWBDQ== X-Received: by 2002:a17:907:a0d2:b0:871:dd2:4afb with SMTP id hw18-20020a170907a0d200b008710dd24afbmr1421405ejc.42.1675123187287; Mon, 30 Jan 2023 15:59:47 -0800 (PST) Received: from localhost.localdomain (abyl20.neoplus.adsl.tpnet.pl. [83.9.31.20]) by smtp.gmail.com with ESMTPSA id jr23-20020a170906515700b0086f4b8f9e42sm7577751ejc.65.2023.01.30.15.59.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 15:59:47 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 7/8] dt-bindings: clock: Add Qcom SM6115 GPUCC Date: Tue, 31 Jan 2023 00:59:25 +0100 Message-Id: <20230130235926.2419776-8-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230130235926.2419776-1-konrad.dybcio@linaro.org> References: <20230130235926.2419776-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM6115 SoCs. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski --- v3 -> v4: - Use unevaluatedProperties instead of additionalProperties .../bindings/clock/qcom,sm6115-gpucc.yaml | 58 +++++++++++++++++++ include/dt-bindings/clock/qcom,sm6115-gpucc.h | 36 ++++++++++++ 2 files changed, 94 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml create mode 100644 include/dt-bindings/clock/qcom,sm6115-gpucc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml new file mode 100644 index 000000000000..cf19f44af774 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm6115-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on SM6115 + +maintainers: + - Konrad Dybcio + +description: | + Qualcomm graphics clock control module provides clocks, resets and power + domains on Qualcomm SoCs. + + See also:: include/dt-bindings/clock/qcom,sm6115-gpucc.h + +properties: + compatible: + enum: + - qcom,sm6115-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 main div source + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <1>; + #size-cells = <1>; + + clock-controller@5990000 { + compatible = "qcom,sm6115-gpucc"; + reg = <0x05990000 0x9000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,sm6115-gpucc.h b/include/dt-bindings/clock/qcom,sm6115-gpucc.h new file mode 100644 index 000000000000..945f21a7d745 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm6115-gpucc.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6115_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6115_H + +/* GPU_CC clocks */ +#define GPU_CC_PLL0 0 +#define GPU_CC_PLL0_OUT_AUX2 1 +#define GPU_CC_PLL1 2 +#define GPU_CC_PLL1_OUT_AUX 3 +#define GPU_CC_AHB_CLK 4 +#define GPU_CC_CRC_AHB_CLK 5 +#define GPU_CC_CX_GFX3D_CLK 6 +#define GPU_CC_CX_GMU_CLK 7 +#define GPU_CC_CX_SNOC_DVM_CLK 8 +#define GPU_CC_CXO_AON_CLK 9 +#define GPU_CC_CXO_CLK 10 +#define GPU_CC_GMU_CLK_SRC 11 +#define GPU_CC_GX_CXO_CLK 12 +#define GPU_CC_GX_GFX3D_CLK 13 +#define GPU_CC_GX_GFX3D_CLK_SRC 14 +#define GPU_CC_SLEEP_CLK 15 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 16 + +/* Resets */ +#define GPU_GX_BCR 0 + +/* GDSCs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif