From patchwork Mon Jan 30 11:46:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 648726 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F0A9C636D0 for ; Mon, 30 Jan 2023 11:47:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236585AbjA3Lr5 (ORCPT ); Mon, 30 Jan 2023 06:47:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44314 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236409AbjA3Lrv (ORCPT ); Mon, 30 Jan 2023 06:47:51 -0500 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 713EB2B0BA; Mon, 30 Jan 2023 03:47:49 -0800 (PST) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 30UBXQw2018578; Mon, 30 Jan 2023 11:47:31 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=ebXnmWAKQ+AfsBaIpQ8igehv8pSTf2dOgM7d7mihQzA=; b=irSRTAqGVCDlcX/nCxWtUAYXUXSekr3pBBYHdeaayfZPR7Lv8aPUtGCdyz6e3fgU90mA BKB9wakg10wBCVUwAe3OXJVPzAEgVACOzJRatQ+22wGDAvs96M47/unG/H6RrHRKJKLi 5zCQ9XHXFNwaXajuB0MuF2dW6hMYXfCFSPq9jlev8VLRiMHhNkstbCLUpH+MvGY4yW1C qoQCPKCR1ZVirZpa7GaZJiCCJCiZ+7hOebtYu8CAdzNW/mDvtGOSaau/lITmZyP7Dmne jF1p3tiBftnbbIZOl7S0AS2eFYo3qB9D454Zo/6kjMpei8PKNTe0ElEE1QrS2lKELO91 yg== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3ncvvu3c0d-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 30 Jan 2023 11:47:30 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 30UBlU70032521 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 30 Jan 2023 11:47:30 GMT Received: from kathirav-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Mon, 30 Jan 2023 03:47:23 -0800 From: Kathiravan Thirumoorthy To: , , , , , , , , , , , , , , , , , , , , , , CC: Kathiravan T Subject: [PATCH V2 1/9] dt-bindings: pinctrl: qcom: add IPQ5332 pinctrl Date: Mon, 30 Jan 2023 17:16:54 +0530 Message-ID: <20230130114702.20606-2-quic_kathirav@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230130114702.20606-1-quic_kathirav@quicinc.com> References: <20230130114702.20606-1-quic_kathirav@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: XrSNreKC3pIrqEyX_QtkFAqytesSK91T X-Proofpoint-ORIG-GUID: XrSNreKC3pIrqEyX_QtkFAqytesSK91T X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-01-30_10,2023-01-30_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxlogscore=999 suspectscore=0 spamscore=0 mlxscore=0 phishscore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 bulkscore=0 adultscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2301300113 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Kathiravan T Add device tree bindings for IPQ5332 TLMM block. Signed-off-by: Kathiravan T Reviewed-by: Krzysztof Kozlowski --- Changes in V2: - Renamed the file name to match with compatible - Added 'maxItems' for 'interrupt' property - Fixed the gpio pattern to 0 to 52 GPIOs instead of 0 to 53 GPIOs - Converted the function names to lowercase and sort it .../bindings/pinctrl/qcom,ipq5332-tlmm.yaml | 136 ++++++++++++++++++ 1 file changed, 136 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-tlmm.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-tlmm.yaml new file mode 100644 index 000000000000..9a943d613afa --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-tlmm.yaml @@ -0,0 +1,136 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5332-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ5332 TLMM pin controller + +maintainers: + - Bjorn Andersson + - Krzysztof Kozlowski + +description: | + Top Level Mode Multiplexer pin controller in Qualcomm IPQ5332 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,ipq5332-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + "#interrupt-cells": true + gpio-controller: true + "#gpio-cells": true + gpio-ranges: true + wakeup-parent: true + + gpio-reserved-ranges: + minItems: 1 + maxItems: 27 + + gpio-line-names: + maxItems: 53 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-ipq5332-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-ipq5332-tlmm-state" + additionalProperties: false + +$defs: + qcom-ipq5332-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|[1-4][0-9]|5[0-2])$" + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ atest_char, atest_char0, atest_char1, atest_char2, atest_char3, + atest_tic, audio_pri, audio_pri0, audio_pri1, audio_sec, + audio_sec0, audio_sec1, blsp0_i2c, blsp0_spi, blsp0_uart0, + blsp0_uart1, blsp1_i2c0, blsp1_i2c1, blsp1_spi0, blsp1_spi1, + blsp1_uart0, blsp1_uart1, blsp1_uart2, blsp2_i2c0, blsp2_i2c1, + blsp2_spi, blsp2_spi0, blsp2_spi1, core_voltage, cri_trng0, + cri_trng1, cri_trng2, cri_trng3, cxc_clk, cxc_data, dbg_out, + gcc_plltest, gcc_tlmm, gpio, lock_det, mac0, mac1, mdc0, mdc1, + mdio0, mdio1, pc, pcie0_clk, pcie0_wake, pcie1_clk, pcie1_wake, + pcie2_clk, pcie2_wake, pll_test, prng_rosc0, prng_rosc1, + prng_rosc2, prng_rosc3, pta_0, pta_2, pta_1, pwm0, pwm1, pwm2, + pwm3, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, + qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_a0, + qdss_cti_trig_out_a1, qdss_cti_trig_out_b0, + qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_traceclk_b, + qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a, + qdss_tracedata_b, qspi_data, qspi_clk, qspi_cs, resout, rx0, + rx1, sdc_data, sdc_clk, sdc_cmd, tsens_max, wci0, wci1, wci10, + wci11, wci2, wci3, wci4, wci5, wci6, wci7, wci8, wci9, wsi_clk, + wsi_clk3, wsi_data, wsi_data3, wsis_reset, xfem0, xfem1, xfem2, + xfem3, xfem4, xfem5, xfem6, xfem7 ] + + bias-pull-down: true + bias-pull-up: true + bias-disable: true + drive-strength: true + input-enable: true + output-high: true + output-low: true + + required: + - pins + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq5332-tlmm"; + reg = <0x01000000 0x300000>; + gpio-controller; + #gpio-cells = <0x2>; + gpio-ranges = <&tlmm 0 0 53>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <0x2>; + + serial0-state { + pins = "gpio18", "gpio19"; + function = "blsp0_uart0"; + drive-strength = <8>; + bias-pull-up; + }; + }; From patchwork Mon Jan 30 11:46:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 648725 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8E7FC61DA4 for ; Mon, 30 Jan 2023 11:48:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236640AbjA3LsG (ORCPT ); Mon, 30 Jan 2023 06:48:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44614 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236641AbjA3LsA (ORCPT ); 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Mon, 30 Jan 2023 11:47:38 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 30UBlbjX032588 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 30 Jan 2023 11:47:37 GMT Received: from kathirav-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Mon, 30 Jan 2023 03:47:30 -0800 From: Kathiravan Thirumoorthy To: , , , , , , , , , , , , , , , , , , , , , , CC: Kathiravan T Subject: [PATCH V2 2/9] pinctrl: qcom: Introduce IPQ5332 TLMM driver Date: Mon, 30 Jan 2023 17:16:55 +0530 Message-ID: <20230130114702.20606-3-quic_kathirav@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230130114702.20606-1-quic_kathirav@quicinc.com> References: <20230130114702.20606-1-quic_kathirav@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: CF-0HEaG-Uc4sbSMEE3C5Y4QKqoEXrZY X-Proofpoint-ORIG-GUID: CF-0HEaG-Uc4sbSMEE3C5Y4QKqoEXrZY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-01-30_10,2023-01-30_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 bulkscore=0 phishscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 spamscore=0 suspectscore=0 mlxlogscore=999 impostorscore=0 priorityscore=1501 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2301300113 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Kathiravan T The IPQ5332 SoC comes with a TLMM block, like all other Qualcomm platforms, so add a driver for it. Signed-off-by: Kathiravan T --- Changes in V2: - Converted the function names to lowercase and sort it drivers/pinctrl/qcom/Kconfig | 10 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-ipq5332.c | 1008 ++++++++++++++++++++++++ 3 files changed, 1019 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq5332.c diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 2a517775a61e..787dfe4f2363 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -48,6 +48,16 @@ config PINCTRL_IPQ8064 This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm IPQ8064 platform. +config PINCTRL_IPQ5332 + tristate "Qualcomm Technologies Inc IPQ5332 pin controller driver" + depends on OF + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc IPQ5332 platform. + config PINCTRL_IPQ8074 tristate "Qualcomm Technologies, Inc. IPQ8074 pin controller driver" depends on OF diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 952f784d0888..314feaf242be 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o +obj-$(CONFIG_PINCTRL_IPQ5332) += pinctrl-ipq5332.o obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o obj-$(CONFIG_PINCTRL_IPQ6018) += pinctrl-ipq6018.o obj-$(CONFIG_PINCTRL_MSM8226) += pinctrl-msm8226.o diff --git a/drivers/pinctrl/qcom/pinctrl-ipq5332.c b/drivers/pinctrl/qcom/pinctrl-ipq5332.c new file mode 100644 index 000000000000..57f628d5cff5 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-ipq5332.c @@ -0,0 +1,1008 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include + +#include "pinctrl-msm.h" + +#define FUNCTION(fname) \ + [msm_mux_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .intr_target_reg = 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +static const struct pinctrl_pin_desc ipq5332_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); + +enum ipq5332_functions { + msm_mux_atest_char, + msm_mux_atest_char0, + msm_mux_atest_char1, + msm_mux_atest_char2, + msm_mux_atest_char3, + msm_mux_atest_tic, + msm_mux_audio_pri, + msm_mux_audio_pri0, + msm_mux_audio_pri1, + msm_mux_audio_sec, + msm_mux_audio_sec0, + msm_mux_audio_sec1, + msm_mux_blsp0_i2c, + msm_mux_blsp0_spi, + msm_mux_blsp0_uart0, + msm_mux_blsp0_uart1, + msm_mux_blsp1_i2c0, + msm_mux_blsp1_i2c1, + msm_mux_blsp1_spi0, + msm_mux_blsp1_spi1, + msm_mux_blsp1_uart0, + msm_mux_blsp1_uart1, + msm_mux_blsp1_uart2, + msm_mux_blsp2_i2c0, + msm_mux_blsp2_i2c1, + msm_mux_blsp2_spi, + msm_mux_blsp2_spi0, + msm_mux_blsp2_spi1, + msm_mux_core_voltage, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_cri_trng2, + msm_mux_cri_trng3, + msm_mux_cxc_clk, + msm_mux_cxc_data, + msm_mux_dbg_out, + msm_mux_gcc_plltest, + msm_mux_gcc_tlmm, + msm_mux_gpio, + msm_mux_lock_det, + msm_mux_mac0, + msm_mux_mac1, + msm_mux_mdc0, + msm_mux_mdc1, + msm_mux_mdio0, + msm_mux_mdio1, + msm_mux_pc, + msm_mux_pcie0_clk, + msm_mux_pcie0_wake, + msm_mux_pcie1_clk, + msm_mux_pcie1_wake, + msm_mux_pcie2_clk, + msm_mux_pcie2_wake, + msm_mux_pll_test, + msm_mux_prng_rosc0, + msm_mux_prng_rosc1, + msm_mux_prng_rosc2, + msm_mux_prng_rosc3, + msm_mux_pta_0, + msm_mux_pta_1, + msm_mux_pta_2, + msm_mux_pwm0, + msm_mux_pwm1, + msm_mux_pwm2, + msm_mux_pwm3, + msm_mux_qdss_cti_trig_in_a0, + msm_mux_qdss_cti_trig_in_a1, + msm_mux_qdss_cti_trig_in_b0, + msm_mux_qdss_cti_trig_in_b1, + msm_mux_qdss_cti_trig_out_a0, + msm_mux_qdss_cti_trig_out_a1, + msm_mux_qdss_cti_trig_out_b0, + msm_mux_qdss_cti_trig_out_b1, + msm_mux_qdss_traceclk_a, + msm_mux_qdss_traceclk_b, + msm_mux_qdss_tracectl_a, + msm_mux_qdss_tracectl_b, + msm_mux_qdss_tracedata_a, + msm_mux_qdss_tracedata_b, + msm_mux_qspi_data, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_resout, + msm_mux_rx0, + msm_mux_rx1, + msm_mux_sdc_data, + msm_mux_sdc_clk, + msm_mux_sdc_cmd, + msm_mux_tsens_max, + msm_mux_wci0, + msm_mux_wci1, + msm_mux_wci10, + msm_mux_wci11, + msm_mux_wci2, + msm_mux_wci3, + msm_mux_wci4, + msm_mux_wci5, + msm_mux_wci6, + msm_mux_wci7, + msm_mux_wci8, + msm_mux_wci9, + msm_mux_wsi_clk, + msm_mux_wsi_clk3, + msm_mux_wsi_data, + msm_mux_wsi_data3, + msm_mux_wsis_reset, + msm_mux_xfem0, + msm_mux_xfem1, + msm_mux_xfem2, + msm_mux_xfem3, + msm_mux_xfem4, + msm_mux_xfem5, + msm_mux_xfem6, + msm_mux_xfem7, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", +}; + +static const char * const atest_char_groups[] = { + "gpio46", +}; + +static const char * const atest_char0_groups[] = { + "gpio0", +}; + +static const char * const atest_char1_groups[] = { + "gpio1", +}; + +static const char * const atest_char2_groups[] = { + "gpio2", +}; + +static const char * const atest_char3_groups[] = { + "gpio3", +}; + +static const char * const atest_tic_groups[] = { + "gpio9", +}; + +static const char * const audio_pri_groups[] = { + "gpio29", "gpio30", "gpio31", "gpio32", +}; + +static const char * const audio_pri0_groups[] = { + "gpio34", "gpio34", +}; + +static const char * const audio_pri1_groups[] = { + "gpio43", "gpio43", +}; + +static const char * const audio_sec_groups[] = { + "gpio33", "gpio34", "gpio35", "gpio36", +}; + +static const char * const audio_sec0_groups[] = { + "gpio30", "gpio30", +}; + +static const char * const audio_sec1_groups[] = { + "gpio45", "gpio45", +}; + +static const char * const blsp0_i2c_groups[] = { + "gpio16", "gpio17", +}; + +static const char * const blsp0_spi_groups[] = { + "gpio14", "gpio15", "gpio16", "gpio17", +}; + +static const char * const blsp0_uart0_groups[] = { + "gpio18", "gpio19", +}; + +static const char * const blsp0_uart1_groups[] = { + "gpio27", "gpio28", +}; + +static const char * const blsp1_i2c0_groups[] = { + "gpio29", "gpio30", +}; + +static const char * const blsp1_i2c1_groups[] = { + "gpio40", "gpio41", +}; + +static const char * const blsp1_spi0_groups[] = { + "gpio29", "gpio30", "gpio31", "gpio32", +}; + +static const char * const blsp1_spi1_groups[] = { + "gpio25", "gpio26", "gpio27", "gpio28", +}; + +static const char * const blsp1_uart0_groups[] = { + "gpio14", "gpio15", "gpio16", "gpio17", +}; + +static const char * const blsp1_uart1_groups[] = { + "gpio25", "gpio26", "gpio27", "gpio28", +}; + +static const char * const blsp1_uart2_groups[] = { + "gpio33", "gpio34", "gpio35", "gpio36", +}; + +static const char * const blsp2_i2c0_groups[] = { + "gpio43", "gpio45", +}; + +static const char * const blsp2_i2c1_groups[] = { + "gpio33", "gpio34", +}; + +static const char * const blsp2_spi_groups[] = { + "gpio37", +}; + +static const char * const blsp2_spi0_groups[] = { + "gpio33", "gpio34", "gpio35", "gpio36", +}; + +static const char * const blsp2_spi1_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio52", +}; + +static const char * const core_voltage_groups[] = { + "gpio21", "gpio23", +}; + +static const char * const cri_trng0_groups[] = { + "gpio17", +}; + +static const char * const cri_trng1_groups[] = { + "gpio18", +}; + +static const char * const cri_trng2_groups[] = { + "gpio19", +}; + +static const char * const cri_trng3_groups[] = { + "gpio20", +}; + +static const char * const cxc_clk_groups[] = { + "gpio49", +}; + +static const char * const cxc_data_groups[] = { + "gpio50", +}; + +static const char * const dbg_out_groups[] = { + "gpio48", +}; + +static const char * const gcc_plltest_groups[] = { + "gpio43", "gpio45", +}; + +static const char * const gcc_tlmm_groups[] = { + "gpio44", +}; + +static const char * const lock_det_groups[] = { + "gpio51", +}; + +static const char * const mac0_groups[] = { + "gpio18", +}; + +static const char * const mac1_groups[] = { + "gpio19", +}; + +static const char * const mdc0_groups[] = { + "gpio25", +}; + +static const char * const mdc1_groups[] = { + "gpio27", +}; + +static const char * const mdio0_groups[] = { + "gpio26", +}; + +static const char * const mdio1_groups[] = { + "gpio28", +}; + +static const char * const pc_groups[] = { + "gpio35", +}; + +static const char * const pcie0_clk_groups[] = { + "gpio37", +}; + +static const char * const pcie0_wake_groups[] = { + "gpio39", +}; + +static const char * const pcie1_clk_groups[] = { + "gpio46", +}; + +static const char * const pcie1_wake_groups[] = { + "gpio48", +}; + +static const char * const pcie2_clk_groups[] = { + "gpio43", +}; + +static const char * const pcie2_wake_groups[] = { + "gpio45", +}; + +static const char * const pll_test_groups[] = { + "gpio49", +}; + +static const char * const prng_rosc0_groups[] = { + "gpio22", +}; + +static const char * const prng_rosc1_groups[] = { + "gpio24", +}; + +static const char * const prng_rosc2_groups[] = { + "gpio25", +}; + +static const char * const prng_rosc3_groups[] = { + "gpio26", +}; + +static const char * const pta_0_groups[] = { + "gpio49", +}; + +static const char * const pta_1_groups[] = { + "gpio50", +}; + +static const char * const pta_2_groups[] = { + "gpio51", +}; + +static const char * const pwm0_groups[] = { + "gpio43", "gpio44", "gpio45", "gpio46", +}; + +static const char * const pwm1_groups[] = { + "gpio29", "gpio30", "gpio31", "gpio32", +}; + +static const char * const pwm2_groups[] = { + "gpio25", "gpio26", "gpio27", "gpio28", +}; + +static const char * const pwm3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; + +static const char * const qdss_cti_trig_in_a0_groups[] = { + "gpio5", +}; + +static const char * const qdss_cti_trig_in_a1_groups[] = { + "gpio7", +}; + +static const char * const qdss_cti_trig_in_b0_groups[] = { + "gpio47", +}; + +static const char * const qdss_cti_trig_in_b1_groups[] = { + "gpio49", +}; + +static const char * const qdss_cti_trig_out_a0_groups[] = { + "gpio4", +}; + +static const char * const qdss_cti_trig_out_a1_groups[] = { + "gpio6", +}; + +static const char * const qdss_cti_trig_out_b0_groups[] = { + "gpio46", +}; + +static const char * const qdss_cti_trig_out_b1_groups[] = { + "gpio48", +}; + +static const char * const qdss_traceclk_a_groups[] = { + "gpio8", +}; + +static const char * const qdss_traceclk_b_groups[] = { + "gpio45", +}; + +static const char * const qdss_tracectl_a_groups[] = { + "gpio9", +}; + +static const char * const qdss_tracectl_b_groups[] = { + "gpio44", +}; + +static const char * const qdss_tracedata_a_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", + "gpio17", "gpio18", "gpio19", "gpio20", "gpio22", "gpio24", "gpio25", + "gpio26", "gpio27", +}; + +static const char * const qdss_tracedata_b_groups[] = { + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio52", +}; + +static const char * const qspi_clk_groups[] = { + "gpio13", +}; + +static const char * const qspi_cs_groups[] = { + "gpio12", +}; + +static const char * const qspi_data_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; + +static const char * const resout_groups[] = { + "gpio20", +}; + +static const char * const rx0_groups[] = { + "gpio48", +}; + +static const char * const rx1_groups[] = { + "gpio45", +}; + +static const char * const sdc_clk_groups[] = { + "gpio13", +}; + +static const char * const sdc_cmd_groups[] = { + "gpio12", +}; + +static const char * const sdc_data_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; + +static const char * const tsens_max_groups[] = { + "gpio28", +}; + +static const char * const wci0_groups[] = { + "gpio0", "gpio0", +}; + +static const char * const wci1_groups[] = { + "gpio1", "gpio1", +}; + +static const char * const wci10_groups[] = { + "gpio35", +}; + +static const char * const wci11_groups[] = { + "gpio36", "gpio36", +}; + +static const char * const wci2_groups[] = { + "gpio2", "gpio2", +}; + +static const char * const wci3_groups[] = { + "gpio3", "gpio3", +}; + +static const char * const wci4_groups[] = { + "gpio4", "gpio4", +}; + +static const char * const wci5_groups[] = { + "gpio5", "gpio5", +}; + +static const char * const wci6_groups[] = { + "gpio6", "gpio6", +}; + +static const char * const wci7_groups[] = { + "gpio7", "gpio7", +}; + +static const char * const wci8_groups[] = { + "gpio43", "gpio43", +}; + +static const char * const wci9_groups[] = { + "gpio45", "gpio45", +}; + +static const char * const wsi_clk_groups[] = { + "gpio40", "gpio42", +}; + +static const char * const wsi_clk3_groups[] = { + "gpio43", +}; + +static const char * const wsi_data_groups[] = { + "gpio41", "gpio52", +}; + +static const char * const wsi_data3_groups[] = { + "gpio44", +}; + +static const char * const wsis_reset_groups[] = { + "gpio41", +}; + +static const char * const xfem0_groups[] = { + "gpio0", +}; + +static const char * const xfem1_groups[] = { + "gpio1", +}; + +static const char * const xfem2_groups[] = { + "gpio2", +}; + +static const char * const xfem3_groups[] = { + "gpio3", +}; + +static const char * const xfem4_groups[] = { + "gpio4", +}; + +static const char * const xfem5_groups[] = { + "gpio5", +}; + +static const char * const xfem6_groups[] = { + "gpio6", +}; + +static const char * const xfem7_groups[] = { + "gpio7", +}; + +static const struct msm_function ipq5332_functions[] = { + FUNCTION(atest_char), + FUNCTION(atest_char0), + FUNCTION(atest_char1), + FUNCTION(atest_char2), + FUNCTION(atest_char3), + FUNCTION(atest_tic), + FUNCTION(audio_pri), + FUNCTION(audio_pri0), + FUNCTION(audio_pri1), + FUNCTION(audio_sec), + FUNCTION(audio_sec0), + FUNCTION(audio_sec1), + FUNCTION(blsp0_i2c), + FUNCTION(blsp0_spi), + FUNCTION(blsp0_uart0), + FUNCTION(blsp0_uart1), + FUNCTION(blsp1_i2c0), + FUNCTION(blsp1_i2c1), + FUNCTION(blsp1_spi0), + FUNCTION(blsp1_spi1), + FUNCTION(blsp1_uart0), + FUNCTION(blsp1_uart1), + FUNCTION(blsp1_uart2), + FUNCTION(blsp2_i2c0), + FUNCTION(blsp2_i2c1), + FUNCTION(blsp2_spi), + FUNCTION(blsp2_spi0), + FUNCTION(blsp2_spi1), + FUNCTION(core_voltage), + FUNCTION(cri_trng0), + FUNCTION(cri_trng1), + FUNCTION(cri_trng2), + FUNCTION(cri_trng3), + FUNCTION(cxc_clk), + FUNCTION(cxc_data), + FUNCTION(dbg_out), + FUNCTION(gcc_plltest), + FUNCTION(gcc_tlmm), + FUNCTION(gpio), + FUNCTION(lock_det), + FUNCTION(mac0), + FUNCTION(mac1), + FUNCTION(mdc0), + FUNCTION(mdc1), + FUNCTION(mdio0), + FUNCTION(mdio1), + FUNCTION(pc), + FUNCTION(pcie0_clk), + FUNCTION(pcie0_wake), + FUNCTION(pcie1_clk), + FUNCTION(pcie1_wake), + FUNCTION(pcie2_clk), + FUNCTION(pcie2_wake), + FUNCTION(pll_test), + FUNCTION(prng_rosc0), + FUNCTION(prng_rosc1), + FUNCTION(prng_rosc2), + FUNCTION(prng_rosc3), + FUNCTION(pta_0), + FUNCTION(pta_1), + FUNCTION(pta_2), + FUNCTION(pwm0), + FUNCTION(pwm1), + FUNCTION(pwm2), + FUNCTION(pwm3), + FUNCTION(qdss_cti_trig_in_a0), + FUNCTION(qdss_cti_trig_in_a1), + FUNCTION(qdss_cti_trig_in_b0), + FUNCTION(qdss_cti_trig_in_b1), + FUNCTION(qdss_cti_trig_out_a0), + FUNCTION(qdss_cti_trig_out_a1), + FUNCTION(qdss_cti_trig_out_b0), + FUNCTION(qdss_cti_trig_out_b1), + FUNCTION(qdss_traceclk_a), + FUNCTION(qdss_traceclk_b), + FUNCTION(qdss_tracectl_a), + FUNCTION(qdss_tracectl_b), + FUNCTION(qdss_tracedata_a), + FUNCTION(qdss_tracedata_b), + FUNCTION(qspi_data), + FUNCTION(qspi_clk), + FUNCTION(qspi_cs), + FUNCTION(resout), + FUNCTION(rx0), + FUNCTION(rx1), + FUNCTION(sdc_data), + FUNCTION(sdc_clk), + FUNCTION(sdc_cmd), + FUNCTION(tsens_max), + FUNCTION(wci0), + FUNCTION(wci1), + FUNCTION(wci10), + FUNCTION(wci11), + FUNCTION(wci2), + FUNCTION(wci3), + FUNCTION(wci4), + FUNCTION(wci5), + FUNCTION(wci6), + FUNCTION(wci7), + FUNCTION(wci8), + FUNCTION(wci9), + FUNCTION(wsi_clk), + FUNCTION(wsi_clk3), + FUNCTION(wsi_data), + FUNCTION(wsi_data3), + FUNCTION(wsis_reset), + FUNCTION(xfem0), + FUNCTION(xfem1), + FUNCTION(xfem2), + FUNCTION(xfem3), + FUNCTION(xfem4), + FUNCTION(xfem5), + FUNCTION(xfem6), + FUNCTION(xfem7), +}; + +static const struct msm_pingroup ipq5332_groups[] = { + PINGROUP(0, atest_char0, wci0, wci0, xfem0, _, _, _, _, _), + PINGROUP(1, atest_char1, wci1, wci1, xfem1, _, _, _, _, _), + PINGROUP(2, atest_char2, wci2, wci2, xfem2, _, _, _, _, _), + PINGROUP(3, atest_char3, wci3, wci3, xfem3, _, _, _, _, _), + PINGROUP(4, qdss_cti_trig_out_a0, wci4, wci4, xfem4, _, _, _, _, + _), + PINGROUP(5, qdss_cti_trig_in_a0, wci5, wci5, xfem5, _, _, _, _, _), + PINGROUP(6, qdss_cti_trig_out_a1, wci6, wci6, xfem6, _, _, _, _, + _), + PINGROUP(7, qdss_cti_trig_in_a1, wci7, wci7, xfem7, _, _, _, _, _), + PINGROUP(8, sdc_data, qspi_data, pwm3, qdss_traceclk_a, _, _, _, _, _), + PINGROUP(9, sdc_data, qspi_data, pwm3, qdss_tracectl_a, _, atest_tic, _, _, + _), + PINGROUP(10, sdc_data, qspi_data, pwm3, qdss_tracedata_a, _, _, _, _, _), + PINGROUP(11, sdc_data, qspi_data, pwm3, qdss_tracedata_a, _, _, _, _, _), + PINGROUP(12, sdc_cmd, qspi_cs, qdss_tracedata_a, _, _, _, _, _, + _), + PINGROUP(13, sdc_clk, qspi_clk, qdss_tracedata_a, _, _, _, _, _, + _), + PINGROUP(14, blsp0_spi, blsp1_uart0, qdss_tracedata_a, _, _, _, _, + _, _), + PINGROUP(15, blsp0_spi, blsp1_uart0, qdss_tracedata_a, _, _, _, _, + _, _), + PINGROUP(16, blsp0_spi, blsp0_i2c, blsp1_uart0, _, qdss_tracedata_a, + _, _, _, _), + PINGROUP(17, blsp0_spi, blsp0_i2c, blsp1_uart0, _, cri_trng0, + qdss_tracedata_a, _, _, _), + PINGROUP(18, blsp0_uart0, mac0, _, cri_trng1, qdss_tracedata_a, _, + _, _, _), + PINGROUP(19, blsp0_uart0, mac1, _, cri_trng2, qdss_tracedata_a, _, + _, _, _), + PINGROUP(20, resout, _, cri_trng3, qdss_tracedata_a, _, _, _, _, + _), + PINGROUP(21, core_voltage, _, _, _, _, _, _, _, _), + PINGROUP(22, _, prng_rosc0, qdss_tracedata_a, _, _, _, _, _, _), + PINGROUP(23, core_voltage, _, _, _, _, _, _, _, _), + PINGROUP(24, _, prng_rosc1, qdss_tracedata_a, _, _, _, _, _, _), + PINGROUP(25, mdc0, blsp1_uart1, blsp1_spi1, pwm2, _, _, prng_rosc2, + qdss_tracedata_a, _), + PINGROUP(26, mdio0, blsp1_uart1, blsp1_spi1, pwm2, _, _, prng_rosc3, + qdss_tracedata_a, _), + PINGROUP(27, mdc1, blsp0_uart1, blsp1_uart1, blsp1_spi1, pwm2, _, _, + qdss_tracedata_a, _), + PINGROUP(28, mdio1, blsp0_uart1, blsp1_uart1, blsp1_spi1, pwm2, _, + tsens_max, _, _), + PINGROUP(29, audio_pri, blsp1_spi0, blsp1_i2c0, pwm1, _, + qdss_tracedata_b, _, _, _), + PINGROUP(30, audio_pri, blsp1_spi0, blsp1_i2c0, pwm1, audio_sec0, + audio_sec0, _, qdss_tracedata_b, _), + PINGROUP(31, audio_pri, blsp1_spi0, pwm1, _, qdss_tracedata_b, _, _, + _, _), + PINGROUP(32, audio_pri, blsp1_spi0, pwm1, _, qdss_tracedata_b, _, _, + _, _), + PINGROUP(33, audio_sec, blsp1_uart2, blsp2_i2c1, blsp2_spi0, _, + qdss_tracedata_b, _, _, _), + PINGROUP(34, audio_sec, blsp1_uart2, blsp2_i2c1, blsp2_spi0, + audio_pri0, audio_pri0, _, qdss_tracedata_b, _), + PINGROUP(35, audio_sec, blsp1_uart2, pc, wci10, blsp2_spi0, + _, qdss_tracedata_b, _, _), + PINGROUP(36, audio_sec, blsp1_uart2, wci11, wci11, blsp2_spi0, + _, qdss_tracedata_b, _, _), + PINGROUP(37, pcie0_clk, blsp2_spi, _, qdss_tracedata_b, _, _, _, + _, _), + PINGROUP(38, _, qdss_tracedata_b, _, _, _, _, _, _, _), + PINGROUP(39, pcie0_wake, _, qdss_tracedata_b, _, _, _, _, _, _), + PINGROUP(40, wsi_clk, blsp1_i2c1, blsp2_spi1, _, _, qdss_tracedata_b, + _, _, _), + PINGROUP(41, wsi_data, blsp1_i2c1, blsp2_spi1, _, _, + qdss_tracedata_b, _, wsis_reset, _), + PINGROUP(42, wsi_clk, blsp2_spi1, _, qdss_tracedata_b, _, _, _, _, + _), + PINGROUP(43, pcie2_clk, wci8, wci8, blsp2_i2c0, pwm0, audio_pri1, + audio_pri1, _, gcc_plltest), + PINGROUP(44, pwm0, _, gcc_tlmm, qdss_tracectl_b, _, wsi_data3, _, + _, _), + PINGROUP(45, pcie2_wake, wci9, wci9, blsp2_i2c0, rx1, pwm0, audio_sec1, + audio_sec1, _), + PINGROUP(46, pcie1_clk, atest_char, pwm0, _, qdss_cti_trig_out_b0, _, + _, _, _), + PINGROUP(47, _, qdss_cti_trig_in_b0, _, _, _, _, _, _, _), + PINGROUP(48, pcie1_wake, rx0, dbg_out, qdss_cti_trig_out_b1, _, _, + _, _, _), + PINGROUP(49, pta_0, cxc_clk, pll_test, _, qdss_cti_trig_in_b1, _, _, + _, _), + PINGROUP(50, pta_1, cxc_data, _, _, _, _, _, _, _), + PINGROUP(51, pta_2, lock_det, _, _, _, _, _, _, _), + PINGROUP(52, wsi_data, blsp2_spi1, _, qdss_tracedata_b, _, _, _, + _, _), +}; + +static const struct msm_pinctrl_soc_data ipq5332_pinctrl = { + .pins = ipq5332_pins, + .npins = ARRAY_SIZE(ipq5332_pins), + .functions = ipq5332_functions, + .nfunctions = ARRAY_SIZE(ipq5332_functions), + .groups = ipq5332_groups, + .ngroups = ARRAY_SIZE(ipq5332_groups), + .ngpios = 53, +}; + +static int ipq5332_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &ipq5332_pinctrl); +} + +static const struct of_device_id ipq5332_pinctrl_of_match[] = { + { .compatible = "qcom,ipq5332-tlmm", }, + { }, +}; +MODULE_DEVICE_TABLE(of, ipq5332_pinctrl_of_match); + +static struct platform_driver ipq5332_pinctrl_driver = { + .driver = { + .name = "ipq5332-tlmm", + .of_match_table = ipq5332_pinctrl_of_match, + }, + .probe = ipq5332_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init ipq5332_pinctrl_init(void) +{ + return platform_driver_register(&ipq5332_pinctrl_driver); +} +arch_initcall(ipq5332_pinctrl_init); + +static void __exit ipq5332_pinctrl_exit(void) +{ + platform_driver_unregister(&ipq5332_pinctrl_driver); +} +module_exit(ipq5332_pinctrl_exit); + +MODULE_DESCRIPTION("QTI IPQ5332 TLMM driver"); +MODULE_LICENSE("GPL"); From patchwork Mon Jan 30 11:46:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 648996 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D05EC636CD for ; Mon, 30 Jan 2023 11:48:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236663AbjA3LsH (ORCPT ); Mon, 30 Jan 2023 06:48:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44506 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236648AbjA3LsA (ORCPT ); Mon, 30 Jan 2023 06:48:00 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE850B773; 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Mon, 30 Jan 2023 11:47:45 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 30UBli3K012219 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 30 Jan 2023 11:47:44 GMT Received: from kathirav-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Mon, 30 Jan 2023 03:47:37 -0800 From: Kathiravan Thirumoorthy To: , , , , , , , , , , , , , , , , , , , , , , CC: Kathiravan T Subject: [PATCH V2 3/9] clk: qcom: Add STROMER PLUS PLL type for IPQ5332 Date: Mon, 30 Jan 2023 17:16:56 +0530 Message-ID: <20230130114702.20606-4-quic_kathirav@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230130114702.20606-1-quic_kathirav@quicinc.com> References: <20230130114702.20606-1-quic_kathirav@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: DXDbv08AU9U2aoqgTXW3g4DNVLXjK5qD X-Proofpoint-ORIG-GUID: DXDbv08AU9U2aoqgTXW3g4DNVLXjK5qD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-01-30_10,2023-01-30_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 bulkscore=0 phishscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 spamscore=0 suspectscore=0 mlxlogscore=828 impostorscore=0 priorityscore=1501 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2301300113 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Kathiravan T Add the support for stromer plus pll, which is found on the IPQ5332 SoCs. Programming sequence is same as the stromer pll, so we can re-use the same. Reviewed-by: Stephen Boyd Signed-off-by: Kathiravan T --- Changes in V2: - Added the Reviewed-by tag. drivers/clk/qcom/clk-alpha-pll.c | 11 +++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 1 + 2 files changed, 12 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 14f9436b62fc..b9f6535a7ba7 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -216,6 +216,17 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { [PLL_OFF_TEST_CTL_U] = 0x34, [PLL_OFF_STATUS] = 0x28, }, + [CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = { + [PLL_OFF_L_VAL] = 0x04, + [PLL_OFF_USER_CTL] = 0x08, + [PLL_OFF_USER_CTL_U] = 0x0c, + [PLL_OFF_CONFIG_CTL] = 0x10, + [PLL_OFF_TEST_CTL] = 0x14, + [PLL_OFF_TEST_CTL_U] = 0x18, + [PLL_OFF_STATUS] = 0x1c, + [PLL_OFF_ALPHA_VAL] = 0x24, + [PLL_OFF_ALPHA_VAL_U] = 0x28, + }, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index ff25c7f7b43e..d07b17186b90 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -27,6 +27,7 @@ enum { CLK_ALPHA_PLL_TYPE_DEFAULT_EVO, CLK_ALPHA_PLL_TYPE_BRAMMO_EVO, CLK_ALPHA_PLL_TYPE_STROMER, + CLK_ALPHA_PLL_TYPE_STROMER_PLUS, CLK_ALPHA_PLL_TYPE_MAX, }; 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Mon, 30 Jan 2023 11:47:52 GMT Received: from kathirav-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Mon, 30 Jan 2023 03:47:44 -0800 From: Kathiravan Thirumoorthy To: , , , , , , , , , , , , , , , , , , , , , , CC: Kathiravan T Subject: [PATCH V2 4/9] dt-bindings: clock: Add Qualcomm IPQ5332 GCC Date: Mon, 30 Jan 2023 17:16:57 +0530 Message-ID: <20230130114702.20606-5-quic_kathirav@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230130114702.20606-1-quic_kathirav@quicinc.com> References: <20230130114702.20606-1-quic_kathirav@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 21dZ5LiwvizVjq2XpRkFh1erXyv8BAV8 X-Proofpoint-GUID: 21dZ5LiwvizVjq2XpRkFh1erXyv8BAV8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-01-30_10,2023-01-30_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 malwarescore=0 bulkscore=0 clxscore=1015 priorityscore=1501 adultscore=0 lowpriorityscore=0 mlxlogscore=999 impostorscore=0 phishscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2301300113 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Kathiravan T Add binding for the Qualcomm IPQ5332 Global Clock Controller. Signed-off-by: Kathiravan T --- Changes in V2: - property 'clocks' is marked required - Renamed the include file name to match with compatible .../bindings/clock/qcom,ipq5332-gcc.yaml | 61 +++ include/dt-bindings/clock/qcom,ipq5332-gcc.h | 359 ++++++++++++++++++ 2 files changed, 420 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml create mode 100644 include/dt-bindings/clock/qcom,ipq5332-gcc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml new file mode 100644 index 000000000000..961311af400c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on IPQ5332 + +maintainers: + - Stephen Boyd + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on IPQ5332. + + See also:: include/dt-bindings/clock/qcom,gcc-ipq5332.h + +allOf: + - $ref: qcom,gcc.yaml# + +properties: + compatible: + const: qcom,ipq5332-gcc + + clocks: + items: + - description: Board XO clock source + - description: Sleep clock source + - description: PCIE 2lane PHY pipe clock source + - description: PCIE 2lane x1 PHY pipe clock source (For second lane) + - description: USB PCIE wrapper pipe clock source + + clock-names: + items: + - const: xo + - const: sleep_clk + - const: pcie_2lane_phy_pipe_clk + - const: pcie_2lane_phy_pipe_clk_x1 + - const: usb_pcie_wrapper_pipe_clk + +required: + - compatible + - clocks + +unevaluatedProperties: false + +examples: + - | + clock-controller@1800000 { + compatible = "qcom,ipq5332-gcc"; + reg = <0x01800000 0x80000>; + clocks = <&xo_board>, + <&sleep_clk>, + <&pcie_2lane_phy_pipe_clk>, + <&pcie_2lane_phy_pipe_clk_x1>, + <&usb_pcie_wrapper_pipe_clk>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,ipq5332-gcc.h b/include/dt-bindings/clock/qcom,ipq5332-gcc.h new file mode 100644 index 000000000000..a305c648b724 --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq5332-gcc.h @@ -0,0 +1,359 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_IPQ5332_H +#define _DT_BINDINGS_CLK_QCOM_GCC_IPQ5332_H + +#define GPLL0_MAIN 0 +#define GPLL0 1 +#define GPLL2_MAIN 2 +#define GPLL2 3 +#define GPLL4_MAIN 4 +#define GPLL4 5 +#define GCC_ADSS_PWM_CLK 6 +#define GCC_ADSS_PWM_CLK_SRC 7 +#define GCC_AHB_CLK 8 +#define GCC_APSS_AHB_CLK 9 +#define GCC_APSS_AHB_CLK_SRC 10 +#define GCC_APSS_AXI_CLK 11 +#define GCC_APSS_AXI_CLK_SRC 12 +#define GCC_BLSP1_AHB_CLK 13 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 14 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 15 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 16 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 17 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 18 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 19 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 20 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 21 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 22 +#define GCC_BLSP1_SLEEP_CLK 23 +#define GCC_BLSP1_UART1_APPS_CLK 24 +#define GCC_BLSP1_UART1_APPS_CLK_SRC 25 +#define GCC_BLSP1_UART2_APPS_CLK 26 +#define GCC_BLSP1_UART2_APPS_CLK_SRC 27 +#define GCC_BLSP1_UART3_APPS_CLK 28 +#define GCC_BLSP1_UART3_APPS_CLK_SRC 29 +#define GCC_CE_AHB_CLK 30 +#define GCC_CE_AXI_CLK 31 +#define GCC_CE_PCNOC_AHB_CLK 32 +#define GCC_CMN_12GPLL_AHB_CLK 33 +#define GCC_CMN_12GPLL_APU_CLK 34 +#define GCC_CMN_12GPLL_SYS_CLK 35 +#define GCC_GP1_CLK 36 +#define GCC_GP1_CLK_SRC 37 +#define GCC_GP2_CLK 38 +#define GCC_GP2_CLK_SRC 39 +#define GCC_LPASS_CORE_AXIM_CLK 40 +#define GCC_LPASS_SWAY_CLK 41 +#define GCC_LPASS_SWAY_CLK_SRC 42 +#define GCC_MDIO_AHB_CLK 43 +#define GCC_MDIO_SLAVE_AHB_CLK 44 +#define GCC_MEM_NOC_Q6_AXI_CLK 45 +#define GCC_MEM_NOC_TS_CLK 46 +#define GCC_NSS_TS_CLK 47 +#define GCC_NSS_TS_CLK_SRC 48 +#define GCC_NSSCC_CLK 49 +#define GCC_NSSCFG_CLK 50 +#define GCC_NSSNOC_ATB_CLK 51 +#define GCC_NSSNOC_NSSCC_CLK 52 +#define GCC_NSSNOC_QOSGEN_REF_CLK 53 +#define GCC_NSSNOC_SNOC_1_CLK 54 +#define GCC_NSSNOC_SNOC_CLK 55 +#define GCC_NSSNOC_TIMEOUT_REF_CLK 56 +#define GCC_NSSNOC_XO_DCD_CLK 57 +#define GCC_PCIE3X1_0_AHB_CLK 58 +#define GCC_PCIE3X1_0_AUX_CLK 59 +#define GCC_PCIE3X1_0_AXI_CLK_SRC 60 +#define GCC_PCIE3X1_0_AXI_M_CLK 61 +#define GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK 62 +#define GCC_PCIE3X1_0_AXI_S_CLK 63 +#define GCC_PCIE3X1_0_PIPE_CLK 64 +#define GCC_PCIE3X1_0_RCHG_CLK 65 +#define GCC_PCIE3X1_0_RCHG_CLK_SRC 66 +#define GCC_PCIE3X1_1_AHB_CLK 67 +#define GCC_PCIE3X1_1_AUX_CLK 68 +#define GCC_PCIE3X1_1_AXI_CLK_SRC 69 +#define GCC_PCIE3X1_1_AXI_M_CLK 70 +#define GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK 71 +#define GCC_PCIE3X1_1_AXI_S_CLK 72 +#define GCC_PCIE3X1_1_PIPE_CLK 73 +#define GCC_PCIE3X1_1_RCHG_CLK 74 +#define GCC_PCIE3X1_1_RCHG_CLK_SRC 75 +#define GCC_PCIE3X1_PHY_AHB_CLK 76 +#define GCC_PCIE3X2_AHB_CLK 77 +#define GCC_PCIE3X2_AUX_CLK 78 +#define GCC_PCIE3X2_AXI_M_CLK 79 +#define GCC_PCIE3X2_AXI_M_CLK_SRC 80 +#define GCC_PCIE3X2_AXI_S_BRIDGE_CLK 81 +#define GCC_PCIE3X2_AXI_S_CLK 82 +#define GCC_PCIE3X2_AXI_S_CLK_SRC 83 +#define GCC_PCIE3X2_PHY_AHB_CLK 84 +#define GCC_PCIE3X2_PIPE_CLK 85 +#define GCC_PCIE3X2_RCHG_CLK 86 +#define GCC_PCIE3X2_RCHG_CLK_SRC 87 +#define GCC_PCIE_AUX_CLK_SRC 88 +#define GCC_PCNOC_AT_CLK 89 +#define GCC_PCNOC_BFDCD_CLK_SRC 90 +#define GCC_PCNOC_LPASS_CLK 91 +#define GCC_PRNG_AHB_CLK 92 +#define GCC_Q6_AHB_CLK 93 +#define GCC_Q6_AHB_S_CLK 94 +#define GCC_Q6_AXIM_CLK 95 +#define GCC_Q6_AXIM_CLK_SRC 96 +#define GCC_Q6_AXIS_CLK 97 +#define GCC_Q6_TSCTR_1TO2_CLK 98 +#define GCC_Q6SS_ATBM_CLK 99 +#define GCC_Q6SS_PCLKDBG_CLK 100 +#define GCC_Q6SS_TRIG_CLK 101 +#define GCC_QDSS_AT_CLK 102 +#define GCC_QDSS_AT_CLK_SRC 103 +#define GCC_QDSS_CFG_AHB_CLK 104 +#define GCC_QDSS_DAP_AHB_CLK 105 +#define GCC_QDSS_DAP_CLK 106 +#define GCC_QDSS_DAP_DIV_CLK_SRC 107 +#define GCC_QDSS_ETR_USB_CLK 108 +#define GCC_QDSS_EUD_AT_CLK 109 +#define GCC_QDSS_TSCTR_CLK_SRC 110 +#define GCC_QPIC_AHB_CLK 111 +#define GCC_QPIC_CLK 112 +#define GCC_QPIC_IO_MACRO_CLK 113 +#define GCC_QPIC_IO_MACRO_CLK_SRC 114 +#define GCC_QPIC_SLEEP_CLK 115 +#define GCC_SDCC1_AHB_CLK 116 +#define GCC_SDCC1_APPS_CLK 117 +#define GCC_SDCC1_APPS_CLK_SRC 118 +#define GCC_SLEEP_CLK_SRC 119 +#define GCC_SNOC_LPASS_CFG_CLK 120 +#define GCC_SNOC_NSSNOC_1_CLK 121 +#define GCC_SNOC_NSSNOC_CLK 122 +#define GCC_SNOC_PCIE3_1LANE_1_M_CLK 123 +#define GCC_SNOC_PCIE3_1LANE_1_S_CLK 124 +#define GCC_SNOC_PCIE3_1LANE_M_CLK 125 +#define GCC_SNOC_PCIE3_1LANE_S_CLK 126 +#define GCC_SNOC_PCIE3_2LANE_M_CLK 127 +#define GCC_SNOC_PCIE3_2LANE_S_CLK 128 +#define GCC_SNOC_USB_CLK 129 +#define GCC_SYS_NOC_AT_CLK 130 +#define GCC_SYS_NOC_WCSS_AHB_CLK 131 +#define GCC_SYSTEM_NOC_BFDCD_CLK_SRC 132 +#define GCC_UNIPHY0_AHB_CLK 133 +#define GCC_UNIPHY0_SYS_CLK 134 +#define GCC_UNIPHY1_AHB_CLK 135 +#define GCC_UNIPHY1_SYS_CLK 136 +#define GCC_UNIPHY_SYS_CLK_SRC 137 +#define GCC_USB0_AUX_CLK 138 +#define GCC_USB0_AUX_CLK_SRC 139 +#define GCC_USB0_EUD_AT_CLK 140 +#define GCC_USB0_LFPS_CLK 141 +#define GCC_USB0_LFPS_CLK_SRC 142 +#define GCC_USB0_MASTER_CLK 143 +#define GCC_USB0_MASTER_CLK_SRC 144 +#define GCC_USB0_MOCK_UTMI_CLK 145 +#define GCC_USB0_MOCK_UTMI_CLK_SRC 146 +#define GCC_USB0_MOCK_UTMI_DIV_CLK_SRC 147 +#define GCC_USB0_PHY_CFG_AHB_CLK 148 +#define GCC_USB0_PIPE_CLK 149 +#define GCC_USB0_SLEEP_CLK 150 +#define GCC_WCSS_AHB_CLK_SRC 151 +#define GCC_WCSS_AXIM_CLK 152 +#define GCC_WCSS_AXIS_CLK 153 +#define GCC_WCSS_DBG_IFC_APB_BDG_CLK 154 +#define GCC_WCSS_DBG_IFC_APB_CLK 155 +#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK 156 +#define GCC_WCSS_DBG_IFC_ATB_CLK 157 +#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK 158 +#define GCC_WCSS_DBG_IFC_NTS_CLK 159 +#define GCC_WCSS_ECAHB_CLK 160 +#define GCC_WCSS_MST_ASYNC_BDG_CLK 161 +#define GCC_WCSS_SLV_ASYNC_BDG_CLK 162 +#define GCC_XO_CLK 163 +#define GCC_XO_CLK_SRC 164 +#define GCC_XO_DIV4_CLK 165 +#define GCC_IM_SLEEP_CLK 166 +#define GCC_NSSNOC_PCNOC_1_CLK 167 +#define GCC_MEM_NOC_AHB_CLK 168 +#define GCC_MEM_NOC_APSS_AXI_CLK 169 +#define GCC_SNOC_QOSGEN_EXTREF_DIV_CLK_SRC 170 +#define GCC_MEM_NOC_QOSGEN_EXTREF_CLK 171 +#define GCC_PCIE3X2_PIPE_CLK_SRC 172 +#define GCC_PCIE3X1_0_PIPE_CLK_SRC 173 +#define GCC_PCIE3X1_1_PIPE_CLK_SRC 174 +#define GCC_USB0_PIPE_CLK_SRC 175 + +#define GCC_ADSS_BCR 0 +#define GCC_ADSS_PWM_CLK_ARES 1 +#define GCC_AHB_CLK_ARES 2 +#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 3 +#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_CLK_ARES 4 +#define GCC_APSS_AHB_CLK_ARES 5 +#define GCC_APSS_AXI_CLK_ARES 6 +#define GCC_BLSP1_AHB_CLK_ARES 7 +#define GCC_BLSP1_BCR 8 +#define GCC_BLSP1_QUP1_BCR 9 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK_ARES 10 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK_ARES 11 +#define GCC_BLSP1_QUP2_BCR 12 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK_ARES 13 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK_ARES 14 +#define GCC_BLSP1_QUP3_BCR 15 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK_ARES 16 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK_ARES 17 +#define GCC_BLSP1_SLEEP_CLK_ARES 18 +#define GCC_BLSP1_UART1_APPS_CLK_ARES 19 +#define GCC_BLSP1_UART1_BCR 20 +#define GCC_BLSP1_UART2_APPS_CLK_ARES 21 +#define GCC_BLSP1_UART2_BCR 22 +#define GCC_BLSP1_UART3_APPS_CLK_ARES 23 +#define GCC_BLSP1_UART3_BCR 24 +#define GCC_CE_BCR 25 +#define GCC_CMN_BLK_BCR 26 +#define GCC_CMN_LDO0_BCR 27 +#define GCC_CMN_LDO1_BCR 28 +#define GCC_DCC_BCR 29 +#define GCC_GP1_CLK_ARES 30 +#define GCC_GP2_CLK_ARES 31 +#define GCC_LPASS_BCR 32 +#define GCC_LPASS_CORE_AXIM_CLK_ARES 33 +#define GCC_LPASS_SWAY_CLK_ARES 34 +#define GCC_MDIOM_BCR 35 +#define GCC_MDIOS_BCR 36 +#define GCC_NSS_BCR 37 +#define GCC_NSS_TS_CLK_ARES 38 +#define GCC_NSSCC_CLK_ARES 39 +#define GCC_NSSCFG_CLK_ARES 40 +#define GCC_NSSNOC_ATB_CLK_ARES 41 +#define GCC_NSSNOC_NSSCC_CLK_ARES 42 +#define GCC_NSSNOC_QOSGEN_REF_CLK_ARES 43 +#define GCC_NSSNOC_SNOC_1_CLK_ARES 44 +#define GCC_NSSNOC_SNOC_CLK_ARES 45 +#define GCC_NSSNOC_TIMEOUT_REF_CLK_ARES 46 +#define GCC_NSSNOC_XO_DCD_CLK_ARES 47 +#define GCC_PCIE3X1_0_AHB_CLK_ARES 48 +#define GCC_PCIE3X1_0_AUX_CLK_ARES 49 +#define GCC_PCIE3X1_0_AXI_M_CLK_ARES 50 +#define GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK_ARES 51 +#define GCC_PCIE3X1_0_AXI_S_CLK_ARES 52 +#define GCC_PCIE3X1_0_BCR 53 +#define GCC_PCIE3X1_0_LINK_DOWN_BCR 54 +#define GCC_PCIE3X1_0_PHY_BCR 55 +#define GCC_PCIE3X1_0_PHY_PHY_BCR 56 +#define GCC_PCIE3X1_1_AHB_CLK_ARES 57 +#define GCC_PCIE3X1_1_AUX_CLK_ARES 58 +#define GCC_PCIE3X1_1_AXI_M_CLK_ARES 59 +#define GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK_ARES 60 +#define GCC_PCIE3X1_1_AXI_S_CLK_ARES 61 +#define GCC_PCIE3X1_1_BCR 62 +#define GCC_PCIE3X1_1_LINK_DOWN_BCR 63 +#define GCC_PCIE3X1_1_PHY_BCR 64 +#define GCC_PCIE3X1_1_PHY_PHY_BCR 65 +#define GCC_PCIE3X1_PHY_AHB_CLK_ARES 66 +#define GCC_PCIE3X2_AHB_CLK_ARES 67 +#define GCC_PCIE3X2_AUX_CLK_ARES 68 +#define GCC_PCIE3X2_AXI_M_CLK_ARES 69 +#define GCC_PCIE3X2_AXI_S_BRIDGE_CLK_ARES 70 +#define GCC_PCIE3X2_AXI_S_CLK_ARES 71 +#define GCC_PCIE3X2_BCR 72 +#define GCC_PCIE3X2_LINK_DOWN_BCR 73 +#define GCC_PCIE3X2_PHY_AHB_CLK_ARES 74 +#define GCC_PCIE3X2_PHY_BCR 75 +#define GCC_PCIE3X2PHY_PHY_BCR 76 +#define GCC_PCNOC_BCR 77 +#define GCC_PCNOC_LPASS_CLK_ARES 78 +#define GCC_PRNG_AHB_CLK_ARES 79 +#define GCC_PRNG_BCR 80 +#define GCC_Q6_AHB_CLK_ARES 81 +#define GCC_Q6_AHB_S_CLK_ARES 82 +#define GCC_Q6_AXIM_CLK_ARES 83 +#define GCC_Q6_AXIS_CLK_ARES 84 +#define GCC_Q6_TSCTR_1TO2_CLK_ARES 85 +#define GCC_Q6SS_ATBM_CLK_ARES 86 +#define GCC_Q6SS_PCLKDBG_CLK_ARES 87 +#define GCC_Q6SS_TRIG_CLK_ARES 88 +#define GCC_QDSS_APB2JTAG_CLK_ARES 89 +#define GCC_QDSS_AT_CLK_ARES 90 +#define GCC_QDSS_BCR 91 +#define GCC_QDSS_CFG_AHB_CLK_ARES 92 +#define GCC_QDSS_DAP_AHB_CLK_ARES 93 +#define GCC_QDSS_DAP_CLK_ARES 94 +#define GCC_QDSS_ETR_USB_CLK_ARES 95 +#define GCC_QDSS_EUD_AT_CLK_ARES 96 +#define GCC_QDSS_STM_CLK_ARES 97 +#define GCC_QDSS_TRACECLKIN_CLK_ARES 98 +#define GCC_QDSS_TS_CLK_ARES 99 +#define GCC_QDSS_TSCTR_DIV16_CLK_ARES 100 +#define GCC_QDSS_TSCTR_DIV2_CLK_ARES 101 +#define GCC_QDSS_TSCTR_DIV3_CLK_ARES 102 +#define GCC_QDSS_TSCTR_DIV4_CLK_ARES 103 +#define GCC_QDSS_TSCTR_DIV8_CLK_ARES 104 +#define GCC_QPIC_AHB_CLK_ARES 105 +#define GCC_QPIC_CLK_ARES 106 +#define GCC_QPIC_BCR 107 +#define GCC_QPIC_IO_MACRO_CLK_ARES 108 +#define GCC_QPIC_SLEEP_CLK_ARES 109 +#define GCC_QUSB2_0_PHY_BCR 110 +#define GCC_SDCC1_AHB_CLK_ARES 111 +#define GCC_SDCC1_APPS_CLK_ARES 112 +#define GCC_SDCC_BCR 113 +#define GCC_SNOC_BCR 114 +#define GCC_SNOC_LPASS_CFG_CLK_ARES 115 +#define GCC_SNOC_NSSNOC_1_CLK_ARES 116 +#define GCC_SNOC_NSSNOC_CLK_ARES 117 +#define GCC_SYS_NOC_QDSS_STM_AXI_CLK_ARES 118 +#define GCC_SYS_NOC_WCSS_AHB_CLK_ARES 119 +#define GCC_UNIPHY0_AHB_CLK_ARES 120 +#define GCC_UNIPHY0_BCR 121 +#define GCC_UNIPHY0_SYS_CLK_ARES 122 +#define GCC_UNIPHY1_AHB_CLK_ARES 123 +#define GCC_UNIPHY1_BCR 124 +#define GCC_UNIPHY1_SYS_CLK_ARES 125 +#define GCC_USB0_AUX_CLK_ARES 126 +#define GCC_USB0_EUD_AT_CLK_ARES 127 +#define GCC_USB0_LFPS_CLK_ARES 128 +#define GCC_USB0_MASTER_CLK_ARES 129 +#define GCC_USB0_MOCK_UTMI_CLK_ARES 130 +#define GCC_USB0_PHY_BCR 131 +#define GCC_USB0_PHY_CFG_AHB_CLK_ARES 132 +#define GCC_USB0_SLEEP_CLK_ARES 133 +#define GCC_USB3PHY_0_PHY_BCR 134 +#define GCC_USB_BCR 135 +#define GCC_WCSS_AXIM_CLK_ARES 136 +#define GCC_WCSS_AXIS_CLK_ARES 137 +#define GCC_WCSS_BCR 138 +#define GCC_WCSS_DBG_IFC_APB_BDG_CLK_ARES 139 +#define GCC_WCSS_DBG_IFC_APB_CLK_ARES 140 +#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK_ARES 141 +#define GCC_WCSS_DBG_IFC_ATB_CLK_ARES 142 +#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK_ARES 143 +#define GCC_WCSS_DBG_IFC_NTS_CLK_ARES 144 +#define GCC_WCSS_ECAHB_CLK_ARES 145 +#define GCC_WCSS_MST_ASYNC_BDG_CLK_ARES 146 +#define GCC_WCSS_Q6_BCR 147 +#define GCC_WCSS_SLV_ASYNC_BDG_CLK_ARES 148 +#define GCC_XO_CLK_ARES 149 +#define GCC_XO_DIV4_CLK_ARES 150 +#define GCC_Q6SS_DBG_ARES 151 +#define GCC_WCSS_DBG_BDG_ARES 152 +#define GCC_WCSS_DBG_ARES 153 +#define GCC_WCSS_AXI_S_ARES 154 +#define GCC_WCSS_AXI_M_ARES 155 +#define GCC_WCSSAON_ARES 156 +#define GCC_PCIE3X2_PIPE_ARES 157 +#define GCC_PCIE3X2_CORE_STICKY_ARES 158 +#define GCC_PCIE3X2_AXI_S_STICKY_ARES 159 +#define GCC_PCIE3X2_AXI_M_STICKY_ARES 160 +#define GCC_PCIE3X1_0_PIPE_ARES 161 +#define GCC_PCIE3X1_0_CORE_STICKY_ARES 162 +#define GCC_PCIE3X1_0_AXI_S_STICKY_ARES 163 +#define GCC_PCIE3X1_0_AXI_M_STICKY_ARES 164 +#define GCC_PCIE3X1_1_PIPE_ARES 165 +#define GCC_PCIE3X1_1_CORE_STICKY_ARES 166 +#define GCC_PCIE3X1_1_AXI_S_STICKY_ARES 167 +#define GCC_PCIE3X1_1_AXI_M_STICKY_ARES 168 +#define GCC_IM_SLEEP_CLK_ARES 169 +#define GCC_NSSNOC_PCNOC_1_CLK_ARES 170 +#define GCC_UNIPHY0_XPCS_ARES 171 +#define GCC_UNIPHY1_XPCS_ARES 172 +#endif From patchwork Mon Jan 30 11:46:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 648724 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP 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vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-01-30_10,2023-01-30_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 lowpriorityscore=0 phishscore=0 mlxscore=0 adultscore=0 malwarescore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2301300113 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Kathiravan T Document the new ipq5332 SoC/board device tree bindings Signed-off-by: Kathiravan T --- Changes in V2: - No changes Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 22553637c519..0a339b8d2319 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -30,6 +30,7 @@ description: | apq8084 apq8096 ipq4018 + ipq5332 ipq6018 ipq8074 mdm9615 @@ -87,6 +88,7 @@ description: | hk10-c2 idp liquid + ap-mi01.2 mtp qrd sbc @@ -316,6 +318,11 @@ properties: - qcom,ipq4019-dk04.1-c1 - const: qcom,ipq4019 + - items: + - enum: + - qcom,ipq5332-ap-mi01.2 + - const: qcom,ipq5332 + - items: - enum: - mikrotik,rb3011 From patchwork Mon Jan 30 11:47:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 648994 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02211C61DA4 for ; Mon, 30 Jan 2023 11:49:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236683AbjA3Lta (ORCPT ); Mon, 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Thirumoorthy To: , , , , , , , , , , , , , , , , , , , , , , CC: Kathiravan T Subject: [PATCH V2 7/9] dt-bindings: firmware: qcom,scm: document IPQ5332 SCM Date: Mon, 30 Jan 2023 17:17:00 +0530 Message-ID: <20230130114702.20606-8-quic_kathirav@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230130114702.20606-1-quic_kathirav@quicinc.com> References: <20230130114702.20606-1-quic_kathirav@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Dguc3slqHozMz7sPYnuMiA99LFO3PVaM X-Proofpoint-ORIG-GUID: Dguc3slqHozMz7sPYnuMiA99LFO3PVaM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-01-30_10,2023-01-30_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 lowpriorityscore=0 phishscore=0 mlxscore=0 adultscore=0 malwarescore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2301300113 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Kathiravan T Document the compatible for IPQ5332 SCM. Acked-by: Krzysztof Kozlowski Signed-off-by: Kathiravan T --- Changes in V2: - Added the 'Acked-by' tag Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index 4193492ba73e..02354d06e054 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -24,6 +24,7 @@ properties: - qcom,scm-apq8064 - qcom,scm-apq8084 - qcom,scm-ipq4019 + - qcom,scm-ipq5332 - qcom,scm-ipq6018 - qcom,scm-ipq806x - qcom,scm-ipq8074 From patchwork Mon Jan 30 11:47:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 648723 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C5DBC61DA4 for ; Mon, 30 Jan 2023 11:49:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236715AbjA3Ltg (ORCPT ); Mon, 30 Jan 2023 06:49:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45790 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235814AbjA3Lt2 (ORCPT ); Mon, 30 Jan 2023 06:49:28 -0500 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D89936091; Mon, 30 Jan 2023 03:48:57 -0800 (PST) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 30UBSJOO004058; Mon, 30 Jan 2023 11:48:21 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=5OvxXUZipzWCBpFvVa5CogcV4T+VJf33YDyCncG4jXs=; b=jCjP6gJGCFt00VMrWPoiRLL4NO+zWHkQVbYtMTOHdxwvZHyotsI0BzI2COPP5ST3COoq 8BfK7N/RiipQ8m7llj0eMQPWZh9ZHHMzS43fT4F0I00ZfA23u+oVR0quETYSslUGFmDc XZmaNWA6xHoiS/O8gee/ItXoELRzxiFNZ+/STpxTaqecfAmUU+O/DitGNAF7WKaCv0rl zi4VCyKVJV8OYf8zDpQqfCpjcal8WpVIruG9D3Ez57YogPXsF57wLZxU1ns4v0a06P0Y 1hZ6HAuXPhGVq6VAr6jiZVsKtC2y4jyQXmvH7Ex9jFPtBi/okb2jbklyNtpT+igf6Lqt yA== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3ncvvu3c1p-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 30 Jan 2023 11:48:21 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 30UBmK9Y014622 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 30 Jan 2023 11:48:20 GMT Received: from kathirav-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Mon, 30 Jan 2023 03:48:13 -0800 From: Kathiravan Thirumoorthy To: , , , , , , , , , , , , , , , , , , , , , , CC: Kathiravan T Subject: [PATCH V2 8/9] arm64: dts: qcom: add IPQ5332 SoC and MI01.2 board support Date: Mon, 30 Jan 2023 17:17:01 +0530 Message-ID: <20230130114702.20606-9-quic_kathirav@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230130114702.20606-1-quic_kathirav@quicinc.com> References: <20230130114702.20606-1-quic_kathirav@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: JqOSio1xCjcT2I4E_7m3CEvjYOdqNYHY X-Proofpoint-ORIG-GUID: JqOSio1xCjcT2I4E_7m3CEvjYOdqNYHY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-01-30_10,2023-01-30_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxlogscore=999 suspectscore=0 spamscore=0 mlxscore=0 phishscore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 bulkscore=0 adultscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2301300113 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Kathiravan T Add initial device tree support for the Qualcomm IPQ5332 SoC and MI01.2 board. Signed-off-by: Kathiravan T --- Changes in V2: - Changed the license to BSD3 in the file ipq5332-mi01.2.dts - Updated the model name, not to include the foundry ID - Used the decimal notation instead of hex for 'cache-level' property - Dropped the blank line - Updated the node name for the TZ reserved region - Moved the 'compatible' property as first one in the node, wherever applicable - Used the decimal notation for *-cells property insrtead of hex - Reorganised the properties of memory mapped timer node as below - reg - interrupts - frame-number - Fixed the indentation in timer node arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts | 71 +++++ arch/arm64/boot/dts/qcom/ipq5332.dtsi | 272 ++++++++++++++++++++ 3 files changed, 344 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts create mode 100644 arch/arm64/boot/dts/qcom/ipq5332.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index b0423ca3e79f..28d0587b8991 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq5332-mi01.2.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts b/arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts new file mode 100644 index 000000000000..e86ae14e5613 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * IPQ5332 AP-MI01.2 board device tree source + * + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ipq5332.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ5332 MI01.2"; + compatible = "qcom,ipq5332-ap-mi01.2", "qcom,ipq5332"; + + aliases { + serial0 = &blsp1_uart0; + }; + + chosen { + stdout-path = "serial0"; + }; +}; + +&blsp1_uart0 { + pinctrl-0 = <&serial_0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdhc { + pinctrl-0 = <&sdc_default_state>; + pinctrl-names = "default"; + non-removable; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&xo_board { + clock-frequency = <24000000>; +}; + +/* PINCTRL */ + +&tlmm { + sdc_default_state: sdc-default-state { + clk-pins { + pins = "gpio13"; + function = "sdc_clk"; + drive-strength = <8>; + bias-disable; + }; + + cmd-pins { + pins = "gpio12"; + function = "sdc_cmd"; + drive-strength = <8>; + bias-pull-up; + }; + + data-pins { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "sdc_data"; + drive-strength = <8>; + bias-pull-up; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi new file mode 100644 index 000000000000..7f0ba2ec339c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -0,0 +1,272 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * IPQ5332 device tree source + * + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +/ { + interrupt-parent = <&intc>; + #address-cells = <2>; + #size-cells = <2>; + + clocks { + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + xo_board: xo-board-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-ipq5332", "qcom,scm"; + }; + }; + + memory@40000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0x40000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + tz_mem: tz@4a600000 { + no-map; + reg = <0x0 0x4a600000 0x0 0x200000>; + }; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq5332-tlmm"; + reg = <0x01000000 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 53>; + interrupt-controller; + #interrupt-cells = <2>; + + serial_0_pins: serial0-state { + pins = "gpio18", "gpio19"; + function = "blsp0_uart0"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + gcc: clock-controller@1800000 { + compatible = "qcom,ipq5332-gcc"; + reg = <0x01800000 0x80000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clock-names = "xo", + "sleep_clk", + "pcie_2lane_phy_pipe_clk", + "pcie_2lane_phy_pipe_clk_x1", + "usb_pcie_wrapper_pipe_clk"; + clocks = <&xo_board>, + <&sleep_clk>, + <0>, + <0>, + <0>; + }; + + sdhc: mmc@7804000 { + compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x07804000 0x1000>, <0x07805000 0x1000>; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board>; + clock-names = "iface", "core", "xo"; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + max-frequency = <192000000>; + bus-width = <4>; + status = "disabled"; + }; + + blsp1_uart0: serial@78af000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078af000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + reg = <0x0b000000 0x1000>, /* GICD */ + <0x0b002000 0x1000>, /* GICC */ + <0x0b001000 0x1000>, /* GICH */ + <0x0b004000 0x1000>; /* GICV */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0b00c000 0x3000>; + + v2m0: v2m@0 { + compatible = "arm,gic-v2m-frame"; + reg = <0x00000000 0xffd>; + msi-controller; + }; + + v2m1: v2m@1 { + compatible = "arm,gic-v2m-frame"; + reg = <0x00001000 0xffd>; + msi-controller; + }; + + v2m2: v2m@2 { + compatible = "arm,gic-v2m-frame"; + reg = <0x00002000 0xffd>; + msi-controller; + }; + }; + + timer@b120000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0b120000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + frame@b120000 { + reg = <0x0b121000 0x1000>, + <0x0b122000 0x1000>; + interrupts = , + ; + frame-number = <0>; + }; + + frame@b123000 { + reg = <0x0b123000 0x1000>; + interrupts = ; + frame-number = <1>; + status = "disabled"; + }; + + frame@b124000 { + reg = <0x0b124000 0x1000>; + interrupts = ; + frame-number = <2>; + status = "disabled"; + }; + + frame@b125000 { + reg = <0x0b125000 0x1000>; + interrupts = ; + frame-number = <3>; + status = "disabled"; + }; + + frame@b126000 { + reg = <0x0b126000 0x1000>; + interrupts = ; + frame-number = <4>; + status = "disabled"; + }; + + frame@b127000 { + reg = <0x0b127000 0x1000>; + interrupts = ; + frame-number = <5>; + status = "disabled"; + }; + + frame@b128000 { + reg = <0x0b128000 0x1000>; + interrupts = ; + frame-number = <6>; + status = "disabled"; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; From patchwork Mon Jan 30 11:47:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 648993 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1B1EC6379F for ; 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Mon, 30 Jan 2023 11:48:28 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 30UBmRYV014696 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 30 Jan 2023 11:48:27 GMT Received: from kathirav-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Mon, 30 Jan 2023 03:48:20 -0800 From: Kathiravan Thirumoorthy To: , , , , , , , , , , , , , , , , , , , , , , CC: Kathiravan T Subject: [PATCH V2 9/9] arm64: defconfig: Enable IPQ5332 SoC base configs Date: Mon, 30 Jan 2023 17:17:02 +0530 Message-ID: <20230130114702.20606-10-quic_kathirav@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230130114702.20606-1-quic_kathirav@quicinc.com> References: <20230130114702.20606-1-quic_kathirav@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: giEXvMFJOUaUabDtFpI2TMf1lFYsJ08D X-Proofpoint-ORIG-GUID: giEXvMFJOUaUabDtFpI2TMf1lFYsJ08D X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-01-30_10,2023-01-30_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxlogscore=794 suspectscore=0 spamscore=0 mlxscore=0 phishscore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 bulkscore=0 adultscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2301300113 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Kathiravan T Enable the clock and pinctrl related configs which are required for the bootup. Signed-off-by: Kathiravan T --- Changed in V2: - No changes arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 984553d55e17..4a18ea596b32 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -549,6 +549,7 @@ CONFIG_PINCTRL_IMX8ULP=y CONFIG_PINCTRL_IMX93=y CONFIG_PINCTRL_MSM=y CONFIG_PINCTRL_IPQ8074=y +CONFIG_PINCTRL_IPQ5332=y CONFIG_PINCTRL_IPQ6018=y CONFIG_PINCTRL_MSM8916=y CONFIG_PINCTRL_MSM8953=y @@ -1105,6 +1106,7 @@ CONFIG_QCOM_CLK_APCS_MSM8916=y CONFIG_QCOM_CLK_APCC_MSM8996=y CONFIG_QCOM_CLK_SMD_RPM=y CONFIG_QCOM_CLK_RPMH=y +CONFIG_IPQ_GCC_5332=y CONFIG_IPQ_GCC_6018=y CONFIG_IPQ_GCC_8074=y CONFIG_MSM_GCC_8916=y