From patchwork Thu Jan 26 13:14:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 648267 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8BFAC61DA3 for ; Thu, 26 Jan 2023 13:14:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232760AbjAZNOr (ORCPT ); Thu, 26 Jan 2023 08:14:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50202 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230273AbjAZNOq (ORCPT ); Thu, 26 Jan 2023 08:14:46 -0500 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 085CB69519 for ; Thu, 26 Jan 2023 05:14:22 -0800 (PST) Received: by mail-wm1-x32b.google.com with SMTP id d4-20020a05600c3ac400b003db1de2aef0so1089265wms.2 for ; Thu, 26 Jan 2023 05:14:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=u8aVTxzWn1UixQJuXT/p8bVFkzgfvSz7e0kUvSVzVNM=; b=vfa+Wv47xDD5N44ame85qOABQIuhcW5F6QP8QrJVUDCzOXjS7fnancY0ojaFM+x14O ANOMRqi1TIMikABYJ+TzRiJH8wbYr70H3w7so0uKeJqCWH4UKZOo/PYzC3Bfdko07C+Y I9DL1//vT7BKAu0l/1uVrCV7rpolV7Qc8TMig+WFJRqEWekWrfmhDU6Bu4g4NL1LPq66 G7g4gGn5F98htr4u1IP17rTn85Ur4VrAUzIWDm15Dz5X9WxIQVzepoSb5BEaFwZktDBW 9qDx94sRBMvLKSQMcvGi1hBvqLSxJzUChalshlngotbOZwQnQRLq0F5prQaFZfbkptXJ 2NKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=u8aVTxzWn1UixQJuXT/p8bVFkzgfvSz7e0kUvSVzVNM=; b=pLIzyXYDU1pzh29Vv4oDxTTllsNHhKHMOIpEsGBynKbgO+tAf5v0bq2AK6/9Ze70wG VCYTebH9WudgMqK3LqSPJKhN/7B8AdGoABpNW5NQq9/LLtlJVz1yVz8pSY46koEeGEl8 XuiI89u1eCURPWohp0JZ+P/mJEHvdExrwXiPlq4EBQ6mNX+ZwUQNGZ+Th5St3oJAakNT 0V661RpuRaWHnZVvFhMulomEtjz3SpwNXBju24gbr4Jj7hqESZttB6anaIyuNO7cL+uC htuRnq+0aRiFt0GI7ppZSHmZZx8uzi81wT1QqvfW2WSvXxLaPynVjI7/8cSLwIJGMnSy 4noQ== X-Gm-Message-State: AFqh2kolJcKYUGtJLqE2Q242I32TZTL4ikjgMDd3CLoJ1amwlGELNIRr MC1uYyFTssQotLiQf4X0lfM1hQ== X-Google-Smtp-Source: AMrXdXtzde+unOWbFn9P6rtGSe12ZvQaPKTxAXxHHcUapQ+Y63I46+FycM+w1q/FD9AFNMEClsL8Vg== X-Received: by 2002:a05:600c:43d3:b0:3da:fbcd:cdd2 with SMTP id f19-20020a05600c43d300b003dafbcdcdd2mr35942889wmn.9.1674738860450; Thu, 26 Jan 2023 05:14:20 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id 18-20020a05600c26d200b003da28dfdedcsm1719804wmv.5.2023.01.26.05.14.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Jan 2023 05:14:20 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , "vkoul@kernel.org" , Kishon Vijay Abraham I , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Linux Kernel Mailing List , linux-phy@lists.infradead.org Subject: [PATCH v3 1/8] dt-bindings: phy: Add qcom,snps-eusb2-phy schema file Date: Thu, 26 Jan 2023 15:14:08 +0200 Message-Id: <20230126131415.1453741-2-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230126131415.1453741-1-abel.vesa@linaro.org> References: <20230126131415.1453741-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The SM8550 SoC uses Synopsis eUSB2 PHY. Add a dt-binding schema for the new driver. Signed-off-by: Abel Vesa --- The v2 version of this patch was here: https://lore.kernel.org/all/20230126124651.1362533-2-abel.vesa@linaro.org/ Changes since v2: * none Changes since v1: * dropped the "ref src" clock * dropped the usb-repeater property .../bindings/phy/qcom,snps-eusb2-phy.yaml | 78 +++++++++++++++++++ 1 file changed, 78 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml new file mode 100644 index 000000000000..49a5dad486c2 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/qcom,snps-eusb2-phy.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm SNPS eUSB2 phy controller + +maintainers: + - Abel Vesa + +description: + eUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets. + +properties: + compatible: + const: qcom,sm8550-snps-eusb2-phy + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + clocks: + items: + - description: ref + + clock-names: + items: + - const: ref + + resets: + maxItems: 1 + description: + Phandle to reset to phy block. + + vdd-supply: + description: + Phandle to 0.88V regulator supply to PHY digital circuit. + + vdda12-supply: + description: + Phandle to 1.2V regulator supply to PHY refclk pll block. + +required: + - compatible + - reg + - "#phy-cells" + - clocks + - clock-names + - vdd-supply + - vdda12-supply + - resets + +additionalProperties: false + +examples: + - | + #include + #include + #include + + usb_1_hsphy: phy@88e3000 { + compatible = "qcom,sm8550-snps-eusb2-phy"; + reg = <0x88e3000 0x154>; + #phy-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_PAD_CLK>, + <&tcsrcc TCSR_USB2_CLKREF_EN>; + clock-names = "ref_src", "ref"; + + vdd-supply = <&vreg_l1e_0p88>; + vdda12-supply = <&vreg_l3e_1p2>; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + }; From patchwork Thu Jan 26 13:14:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 648266 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4335FC54E94 for ; Thu, 26 Jan 2023 13:14:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236540AbjAZNOv (ORCPT ); Thu, 26 Jan 2023 08:14:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50256 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236482AbjAZNOr (ORCPT ); Thu, 26 Jan 2023 08:14:47 -0500 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 69E3467792 for ; Thu, 26 Jan 2023 05:14:23 -0800 (PST) Received: by mail-wm1-x32f.google.com with SMTP id c4-20020a1c3504000000b003d9e2f72093so3224060wma.1 for ; Thu, 26 Jan 2023 05:14:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KuIQE6AhVFPCdsWHInYpexugm6+/PIPyWE1P1sCXHyw=; b=mex+DaEg/Y4izZfI6reu6agjqlcmZAXI73l8d0QiccLBa1tL4/OWcVkmCXy2DUX794 dS59hVTKalvmJ37yPNSduILsRO4SOt0wfsxtXRM6pv75wA5cHl+vZwgF/xVjO+8r9psy DBEPB1pd/fUGJPpxXrmxwxvdHhcQ5bIOWEt5RYIaSCqSEUy58dxP1PRJ47EBblzYZXtD ikeIxUOzcJJ8BkUCIx4tvcvUH+BYNbwTWqY78bXXCyoRcdDcr2tq/BjVQylH2I1m4n17 8oKHHonYK08auq+rtprFOjmXx4vgjyYxCdVhUw4GZhNQ6BQ1GstpHXHh3L537EjNoI2S +sKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KuIQE6AhVFPCdsWHInYpexugm6+/PIPyWE1P1sCXHyw=; b=Nk5+9zALHF3vA1L1ULMgVtgYx4BRZTTLBUWkVwjF5xLh+Cw+yPE2fF5CwuJZmOy9I1 roCFYo0OeR+3OJMWcTDYWiB9h0WvrKOk/uA9rfTDKUd/HFnqm0SCMI8TFlduVip+THlF Ol53XZoouwen5yQZtuPxmy5HONWM/4fEdwAb1s5GPpMuKz8WtjBI/rWReWhY2jJAKj/j R0tqz1BG7lqQcp8hVYUyUbNQRjs9+L4hsVPFlEXLtfSIbVaQzN8U+sxlNAEWoq8vgcSi UYPB3J6rJkbBRYC6iKEFIirVU27XTmkpdcaXr6Z18euMgrVZaSo5fJwW1RZnEhDwdt6t T6LA== X-Gm-Message-State: AFqh2kpjOOWmTSdtXwAAki3qVmiX3OJU00jKeHIuonES8epAlrFhbt3W 26afXXfjterMYSH0mSZyASmLtQ== X-Google-Smtp-Source: AMrXdXtTZfx9CjXw9rlf6Ig074Tjd1J7fi3zNguu7wV5fp0/hm41DrE3oFw0fNX1MhrzwEZBKgFk9w== X-Received: by 2002:a7b:cb88:0:b0:3d9:f801:73bf with SMTP id m8-20020a7bcb88000000b003d9f80173bfmr34940247wmi.12.1674738861758; Thu, 26 Jan 2023 05:14:21 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id 18-20020a05600c26d200b003da28dfdedcsm1719804wmv.5.2023.01.26.05.14.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Jan 2023 05:14:21 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , "vkoul@kernel.org" , Kishon Vijay Abraham I , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Linux Kernel Mailing List , linux-phy@lists.infradead.org Subject: [PATCH v3 2/8] phy: qcom: Add QCOM SNPS eUSB2 driver Date: Thu, 26 Jan 2023 15:14:09 +0200 Message-Id: <20230126131415.1453741-3-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230126131415.1453741-1-abel.vesa@linaro.org> References: <20230126131415.1453741-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The SM8550 SoC uses Synopsis eUSB2 PHY for USB 2.0. Add a new driver for it. The driver is based on a downstream implementation. Signed-off-by: Abel Vesa --- The v2 version of this patch was here: https://lore.kernel.org/all/20230126124651.1362533-3-abel.vesa@linaro.org/ Changes since v2: * this time actually dropped the qcom_snps_, which I missed in the v2 * this time actually added the new lines after break in switch clause, as Vinod suggested, which I missed in the v2 Changes since v1: * replaced qualcomm with qcom in subject line * dropped all unnecessary includes * dropped qcom_snps prefix from qcom_snps_eusb2_hsphy_vreg_names * properly aligned the arguments for qcom_snps_eusb2_hsphy_write_mask * added empty lines after break in switch clause, like Vinod suggested drivers/phy/qualcomm/Kconfig | 9 + drivers/phy/qualcomm/Makefile | 1 + drivers/phy/qualcomm/phy-qcom-snps-eusb2.c | 423 +++++++++++++++++++++ 3 files changed, 433 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-snps-eusb2.c diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig index eb9ddc685b38..27b5a2a3637d 100644 --- a/drivers/phy/qualcomm/Kconfig +++ b/drivers/phy/qualcomm/Kconfig @@ -70,6 +70,15 @@ config PHY_QCOM_QUSB2 PHY which is usually paired with either the ChipIdea or Synopsys DWC3 USB IPs on MSM SOCs. +config PHY_QCOM_SNPS_EUSB2 + tristate "Qualcomm SNPS eUSB2 PHY Driver" + depends on OF && (ARCH_QCOM || COMPILE_TEST) + select GENERIC_PHY + help + Enable support for the USB high-speed SNPS eUSB2 phy on Qualcomm + chipsets. The PHY is paired with a Synopsys DWC3 USB controller + on Qualcomm SOCs. + config PHY_QCOM_USB_HS tristate "Qualcomm USB HS PHY module" depends on USB_ULPI_BUS diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile index 65f6c30a3e93..3ee118f4dfc7 100644 --- a/drivers/phy/qualcomm/Makefile +++ b/drivers/phy/qualcomm/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_PHY_QCOM_QMP) += \ phy-qcom-qmp-usb.o obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o +obj-$(CONFIG_PHY_QCOM_SNPS_EUSB2) += phy-qcom-snps-eusb2.o obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o diff --git a/drivers/phy/qualcomm/phy-qcom-snps-eusb2.c b/drivers/phy/qualcomm/phy-qcom-snps-eusb2.c new file mode 100644 index 000000000000..23ec162cc3bd --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-snps-eusb2.c @@ -0,0 +1,423 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include + +#define USB_PHY_UTMI_CTRL0 (0x3c) +#define SLEEPM BIT(0) +#define OPMODE_MASK GENMASK(4, 3) +#define OPMODE_NONDRIVING BIT(3) + +#define USB_PHY_UTMI_CTRL5 (0x50) +#define POR BIT(1) + +#define USB_PHY_HS_PHY_CTRL_COMMON0 (0x54) +#define PHY_ENABLE BIT(0) +#define SIDDQ_SEL BIT(1) +#define SIDDQ BIT(2) +#define RETENABLEN BIT(3) +#define FSEL_MASK GENMASK(6, 4) +#define FSEL_19_2_MHZ_VAL (0x0) +#define FSEL_38_4_MHZ_VAL (0x4) + +#define USB_PHY_CFG_CTRL_1 (0x58) +#define PHY_CFG_PLL_CPBIAS_CNTRL_MASK GENMASK(7, 1) + +#define USB_PHY_CFG_CTRL_2 (0x5c) +#define PHY_CFG_PLL_FB_DIV_7_0_MASK GENMASK(7, 0) +#define DIV_7_0_19_2_MHZ_VAL (0x90) +#define DIV_7_0_38_4_MHZ_VAL (0xc8) + +#define USB_PHY_CFG_CTRL_3 (0x60) +#define PHY_CFG_PLL_FB_DIV_11_8_MASK GENMASK(3, 0) +#define DIV_11_8_19_2_MHZ_VAL (0x1) +#define DIV_11_8_38_4_MHZ_VAL (0x0) + +#define PHY_CFG_PLL_REF_DIV GENMASK(7, 4) +#define PLL_REF_DIV_VAL (0x0) + +#define USB_PHY_HS_PHY_CTRL2 (0x64) +#define VBUSVLDEXT0 BIT(0) +#define USB2_SUSPEND_N BIT(2) +#define USB2_SUSPEND_N_SEL BIT(3) +#define VBUS_DET_EXT_SEL BIT(4) + +#define USB_PHY_CFG_CTRL_4 (0x68) +#define PHY_CFG_PLL_GMP_CNTRL_MASK GENMASK(1, 0) +#define PHY_CFG_PLL_INT_CNTRL_MASK GENMASK(7, 2) + +#define USB_PHY_CFG_CTRL_5 (0x6c) +#define PHY_CFG_PLL_PROP_CNTRL_MASK GENMASK(4, 0) +#define PHY_CFG_PLL_VREF_TUNE_MASK GENMASK(7, 6) + +#define USB_PHY_CFG_CTRL_6 (0x70) +#define PHY_CFG_PLL_VCO_CNTRL_MASK GENMASK(2, 0) + +#define USB_PHY_CFG_CTRL_7 (0x74) + +#define USB_PHY_CFG_CTRL_8 (0x78) +#define PHY_CFG_TX_FSLS_VREF_TUNE_MASK GENMASK(1, 0) +#define PHY_CFG_TX_FSLS_VREG_BYPASS BIT(2) +#define PHY_CFG_TX_HS_VREF_TUNE_MASK GENMASK(5, 3) +#define PHY_CFG_TX_HS_XV_TUNE_MASK GENMASK(7, 6) + +#define USB_PHY_CFG_CTRL_9 (0x7c) +#define PHY_CFG_TX_PREEMP_TUNE_MASK GENMASK(2, 0) +#define PHY_CFG_TX_RES_TUNE_MASK GENMASK(4, 3) +#define PHY_CFG_TX_RISE_TUNE_MASK GENMASK(6, 5) +#define PHY_CFG_RCAL_BYPASS BIT(7) + +#define USB_PHY_CFG_CTRL_10 (0x80) + +#define USB_PHY_CFG0 (0x94) +#define DATAPATH_CTRL_OVERRIDE_EN BIT(0) +#define CMN_CTRL_OVERRIDE_EN BIT(1) + +#define UTMI_PHY_CMN_CTRL0 (0x98) +#define TESTBURNIN BIT(6) + +#define USB_PHY_FSEL_SEL (0xb8) +#define FSEL_SEL BIT(0) + +#define USB_PHY_APB_ACCESS_CMD (0x130) +#define RW_ACCESS BIT(0) +#define APB_START_CMD BIT(1) +#define APB_LOGIC_RESET BIT(2) + +#define USB_PHY_APB_ACCESS_STATUS (0x134) +#define ACCESS_DONE BIT(0) +#define TIMED_OUT BIT(1) +#define ACCESS_ERROR BIT(2) +#define ACCESS_IN_PROGRESS BIT(3) + +#define USB_PHY_APB_ADDRESS (0x138) +#define APB_REG_ADDR_MASK GENMASK(7, 0) + +#define USB_PHY_APB_WRDATA_LSB (0x13c) +#define APB_REG_WRDATA_7_0_MASK GENMASK(3, 0) + +#define USB_PHY_APB_WRDATA_MSB (0x140) +#define APB_REG_WRDATA_15_8_MASK GENMASK(7, 4) + +#define USB_PHY_APB_RDDATA_LSB (0x144) +#define APB_REG_RDDATA_7_0_MASK GENMASK(3, 0) + +#define USB_PHY_APB_RDDATA_MSB (0x148) +#define APB_REG_RDDATA_15_8_MASK GENMASK(7, 4) + +static const char * const eusb2_hsphy_vreg_names[] = { + "vdd", "vdda12", +}; + +#define EUSB2_NUM_VREGS ARRAY_SIZE(eusb2_hsphy_vreg_names) + +struct qcom_snps_eusb2_hsphy { + struct phy *phy; + void __iomem *base; + + struct clk *ref_clk; + struct reset_control *phy_reset; + + struct regulator_bulk_data vregs[EUSB2_NUM_VREGS]; + + enum phy_mode mode; +}; + +static int qcom_snps_eusb2_hsphy_set_mode(struct phy *p, enum phy_mode mode, int submode) +{ + struct qcom_snps_eusb2_hsphy *phy = phy_get_drvdata(p); + + phy->mode = mode; + + return 0; +} + +static void qcom_snps_eusb2_hsphy_write_mask(void __iomem *base, u32 offset, + u32 mask, u32 val) +{ + u32 reg; + + reg = readl_relaxed(base + offset); + reg &= ~mask; + reg |= val & mask; + writel_relaxed(reg, base + offset); + + /* Ensure above write is completed */ + readl_relaxed(base + offset); +} + +static void qcom_eusb2_default_parameters(struct qcom_snps_eusb2_hsphy *phy) +{ + /* default parameters: tx pre-emphasis */ + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_9, + PHY_CFG_TX_PREEMP_TUNE_MASK, + FIELD_PREP(PHY_CFG_TX_PREEMP_TUNE_MASK, 0)); + + /* tx rise/fall time */ + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_9, + PHY_CFG_TX_RISE_TUNE_MASK, + FIELD_PREP(PHY_CFG_TX_RISE_TUNE_MASK, 0x2)); + + /* source impedance adjustment */ + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_9, + PHY_CFG_TX_RES_TUNE_MASK, + FIELD_PREP(PHY_CFG_TX_RES_TUNE_MASK, 0x1)); + + /* dc voltage level adjustement */ + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_8, + PHY_CFG_TX_HS_VREF_TUNE_MASK, + FIELD_PREP(PHY_CFG_TX_HS_VREF_TUNE_MASK, 0x3)); + + /* transmitter HS crossover adjustement */ + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_8, + PHY_CFG_TX_HS_XV_TUNE_MASK, + FIELD_PREP(PHY_CFG_TX_HS_XV_TUNE_MASK, 0x0)); +} + +static int qcom_eusb2_ref_clk_init(struct qcom_snps_eusb2_hsphy *phy) +{ + unsigned long ref_clk_freq = clk_get_rate(phy->ref_clk); + + switch (ref_clk_freq) { + case 19200000: + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0, + FSEL_MASK, + FIELD_PREP(FSEL_MASK, FSEL_19_2_MHZ_VAL)); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_2, + PHY_CFG_PLL_FB_DIV_7_0_MASK, + DIV_7_0_19_2_MHZ_VAL); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_3, + PHY_CFG_PLL_FB_DIV_11_8_MASK, + DIV_11_8_19_2_MHZ_VAL); + break; + + case 38400000: + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0, + FSEL_MASK, + FIELD_PREP(FSEL_MASK, FSEL_38_4_MHZ_VAL)); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_2, + PHY_CFG_PLL_FB_DIV_7_0_MASK, + DIV_7_0_38_4_MHZ_VAL); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_3, + PHY_CFG_PLL_FB_DIV_11_8_MASK, + DIV_11_8_38_4_MHZ_VAL); + break; + + default: + dev_err(&phy->phy->dev, "unsupported ref_clk_freq:%lu\n", + ref_clk_freq); + return -EINVAL; + } + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_3, + PHY_CFG_PLL_REF_DIV, PLL_REF_DIV_VAL); + + return 0; +} + +static int qcom_snps_eusb2_hsphy_init(struct phy *p) +{ + struct qcom_snps_eusb2_hsphy *phy = phy_get_drvdata(p); + int ret; + + ret = regulator_bulk_enable(ARRAY_SIZE(phy->vregs), phy->vregs); + if (ret) + return ret; + + ret = clk_prepare_enable(phy->ref_clk); + if (ret) { + dev_err(&p->dev, "failed to enable ref clock, %d\n", ret); + goto disable_vreg; + } + + ret = reset_control_assert(phy->phy_reset); + if (ret) { + dev_err(&p->dev, "failed to assert phy_reset, %d\n", ret); + goto disable_ref_clk; + } + + usleep_range(100, 150); + + ret = reset_control_deassert(phy->phy_reset); + if (ret) { + dev_err(&p->dev, "failed to de-assert phy_reset, %d\n", ret); + goto disable_ref_clk; + } + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG0, + CMN_CTRL_OVERRIDE_EN, CMN_CTRL_OVERRIDE_EN); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_UTMI_CTRL5, POR, POR); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0, + PHY_ENABLE | RETENABLEN, PHY_ENABLE | RETENABLEN); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_APB_ACCESS_CMD, + APB_LOGIC_RESET, APB_LOGIC_RESET); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, UTMI_PHY_CMN_CTRL0, TESTBURNIN, 0); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_FSEL_SEL, + FSEL_SEL, FSEL_SEL); + + /* update ref_clk related registers */ + ret = qcom_eusb2_ref_clk_init(phy); + if (ret) + goto disable_ref_clk; + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_1, + PHY_CFG_PLL_CPBIAS_CNTRL_MASK, + FIELD_PREP(PHY_CFG_PLL_CPBIAS_CNTRL_MASK, 0x1)); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_4, + PHY_CFG_PLL_INT_CNTRL_MASK, + FIELD_PREP(PHY_CFG_PLL_INT_CNTRL_MASK, 0x8)); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_4, + PHY_CFG_PLL_GMP_CNTRL_MASK, + FIELD_PREP(PHY_CFG_PLL_GMP_CNTRL_MASK, 0x1)); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_5, + PHY_CFG_PLL_PROP_CNTRL_MASK, + FIELD_PREP(PHY_CFG_PLL_PROP_CNTRL_MASK, 0x10)); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_6, + PHY_CFG_PLL_VCO_CNTRL_MASK, + FIELD_PREP(PHY_CFG_PLL_VCO_CNTRL_MASK, 0x0)); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_5, + PHY_CFG_PLL_VREF_TUNE_MASK, + FIELD_PREP(PHY_CFG_PLL_VREF_TUNE_MASK, 0x1)); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL2, + VBUS_DET_EXT_SEL, VBUS_DET_EXT_SEL); + + /* set default parameters */ + qcom_eusb2_default_parameters(phy); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL2, + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N, + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_UTMI_CTRL0, SLEEPM, SLEEPM); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0, + SIDDQ_SEL, SIDDQ_SEL); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0, + SIDDQ, 0); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_UTMI_CTRL5, POR, 0); + + qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL2, + USB2_SUSPEND_N_SEL, 0); + + return 0; + +disable_ref_clk: + clk_disable_unprepare(phy->ref_clk); + +disable_vreg: + regulator_bulk_disable(ARRAY_SIZE(phy->vregs), phy->vregs); + + return ret; +} + +static int qcom_snps_eusb2_hsphy_exit(struct phy *p) +{ + struct qcom_snps_eusb2_hsphy *phy = phy_get_drvdata(p); + + clk_disable_unprepare(phy->ref_clk); + + regulator_bulk_disable(ARRAY_SIZE(phy->vregs), phy->vregs); + + return 0; +} + +static const struct phy_ops qcom_snps_eusb2_hsphy_ops = { + .init = qcom_snps_eusb2_hsphy_init, + .exit = qcom_snps_eusb2_hsphy_exit, + .set_mode = qcom_snps_eusb2_hsphy_set_mode, + .owner = THIS_MODULE, +}; + +static int qcom_snps_eusb2_hsphy_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct qcom_snps_eusb2_hsphy *phy; + struct phy_provider *phy_provider; + struct phy *generic_phy; + int ret, i; + int num; + + phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); + if (!phy) + return -ENOMEM; + + phy->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(phy->base)) + return PTR_ERR(phy->base); + + phy->phy_reset = devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(phy->phy_reset)) + return PTR_ERR(phy->phy_reset); + + phy->ref_clk = devm_clk_get(dev, "ref"); + if (IS_ERR(phy->ref_clk)) + return dev_err_probe(dev, PTR_ERR(phy->ref_clk), + "failed to get ref clk\n"); + + num = ARRAY_SIZE(phy->vregs); + for (i = 0; i < num; i++) + phy->vregs[i].supply = eusb2_hsphy_vreg_names[i]; + + ret = devm_regulator_bulk_get(dev, num, phy->vregs); + if (ret) + return dev_err_probe(dev, ret, + "failed to get regulator supplies\n"); + generic_phy = devm_phy_create(dev, NULL, &qcom_snps_eusb2_hsphy_ops); + if (IS_ERR(generic_phy)) { + dev_err(dev, "failed to create phy %d\n", ret); + return PTR_ERR(generic_phy); + } + + dev_set_drvdata(dev, phy); + phy_set_drvdata(generic_phy, phy); + + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + if (IS_ERR(phy_provider)) + return PTR_ERR(phy_provider); + + dev_info(dev, "Registered Qcom-eUSB2 phy\n"); + + return 0; +} + +static const struct of_device_id qcom_snps_eusb2_hsphy_of_match_table[] = { + { .compatible = "qcom,sm8550-snps-eusb2-phy", }, + { }, +}; +MODULE_DEVICE_TABLE(of, qcom_snps_eusb2_hsphy_of_match_table); + +static struct platform_driver qcom_snps_eusb2_hsphy_driver = { + .probe = qcom_snps_eusb2_hsphy_probe, + .driver = { + .name = "qcom-snps-eusb2-hsphy", + .of_match_table = qcom_snps_eusb2_hsphy_of_match_table, + }, +}; + +module_platform_driver(qcom_snps_eusb2_hsphy_driver); +MODULE_DESCRIPTION("Qualcomm SNPS eUSB2 HS PHY driver"); +MODULE_LICENSE("GPL"); From patchwork Thu Jan 26 13:14:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 648265 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88C9DC54E94 for ; Thu, 26 Jan 2023 13:14:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236676AbjAZNO5 (ORCPT ); Thu, 26 Jan 2023 08:14:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50300 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236419AbjAZNOv (ORCPT ); Thu, 26 Jan 2023 08:14:51 -0500 Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 91D6A611C9 for ; Thu, 26 Jan 2023 05:14:27 -0800 (PST) Received: by mail-wm1-x32a.google.com with SMTP id f25-20020a1c6a19000000b003da221fbf48so1096011wmc.1 for ; Thu, 26 Jan 2023 05:14:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=L8S/k5EZmNceNC6Mb6iquS22SFOybuz/c5edVTjpSWQ=; b=jbUFuQbr46utCUyThNoFkNjZt0H9yAQO8Dsi5ZT1Oz4vwUbod+B+DYeXw1mMuIW8yk 2T2KB525Cb1YDINUCh1d/8VpAggbNU2f7sjpKNV+3Zcdio4kcojcA5ByVaUI9svZtYH/ JR4aoPaqYDP9qgM3n4YToJywCnVh8ki3bhQte/sZrcVMf7dAe9AlrGFJ+VfKGq+p9o3k 7artgLWuj85uQVV1G6GRsE6x4PSxQrXs79hOWX0cu3A04xAyYccVP8n0gSaow9WXZFVK x0r0iuznEfWpAC9govDHAET72/UDWqBSHF4fAMaWR5xvZPcJBRDBnatQ8hjoB7+efUDp Sd7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=L8S/k5EZmNceNC6Mb6iquS22SFOybuz/c5edVTjpSWQ=; b=O5xW8cFb/zdyCDJcozDAmj7bTGdgACxXrsSIXFavAyDZ484h9bWMVi5mvb8DnVqUOD PUwrskF9GhrI/VnnkXUzryK6CWADliB52umDt0EqDKVvT4E+zmmk+sgv//LFy7fD+cZj pgesNkwXHhTwUsEGtifZwVxOk59drbXshNTX8/7RDTWfhb+FhK1PkEPVcVe3j5NEb643 zT9HBuHjeva5fsm0r8r3uGlbrUI3W87nhYJTlHm1AoqrmIYj2+34hnlNZv7Qyc68fQpr 0ik7JX4vRJLqNLsYuo827CKuAeNyTMrey4H1MtsPEGRVME0kQUudZwuGrboIrRCI3tgc zmJg== X-Gm-Message-State: AO0yUKUBZBMjEF1K6+5hrwMbGXiq8eBCxvKxl/ZwLQOR6mR3lDPjj7Vr gqEAMLQX4cSwOCITLqSy4n44YA== X-Google-Smtp-Source: AK7set9Mipn93fBan5Mm1jnzFa/ECppqiDj0Cy/gwDUPPO3En4NlVsc+jfJJDQwJX7brzeHc8Ky7+w== X-Received: by 2002:a05:600c:a42:b0:3dc:1050:5553 with SMTP id c2-20020a05600c0a4200b003dc10505553mr9772874wmq.23.1674738865812; Thu, 26 Jan 2023 05:14:25 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id 18-20020a05600c26d200b003da28dfdedcsm1719804wmv.5.2023.01.26.05.14.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Jan 2023 05:14:25 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , "vkoul@kernel.org" , Kishon Vijay Abraham I , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Linux Kernel Mailing List , linux-phy@lists.infradead.org Subject: [PATCH v3 5/8] phy: qcom-qmp: Add v6 DP register offsets Date: Thu, 26 Jan 2023 15:14:12 +0200 Message-Id: <20230126131415.1453741-6-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230126131415.1453741-1-abel.vesa@linaro.org> References: <20230126131415.1453741-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The new SM8550 SoC bumps up the HW version of QMP phy to v6. Add the new DP specific offsets in the generic qmp header file. Signed-off-by: Abel Vesa --- The v2 version of this patch was here: https://lore.kernel.org/all/20230126124651.1362533-6-abel.vesa@linaro.org/ Changes since v2: * none This patch did not exist in v1. Since then, the DP support has been added. drivers/phy/qualcomm/phy-qcom-qmp.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h index 148663ee713a..7ee4b0e07d11 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -134,4 +134,8 @@ #define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10 #define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14 +/* Only for QMP V6 PHY - DP PHY registers */ +#define QSERDES_V6_DP_PHY_AUX_INTERRUPT_STATUS 0x0e0 +#define QSERDES_V6_DP_PHY_STATUS 0x0e4 + #endif From patchwork Thu Jan 26 13:14:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 648264 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E22EEC61DB3 for ; Thu, 26 Jan 2023 13:14:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236680AbjAZNO6 (ORCPT ); Thu, 26 Jan 2023 08:14:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50332 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236607AbjAZNOw (ORCPT ); Thu, 26 Jan 2023 08:14:52 -0500 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 529BD6952F for ; Thu, 26 Jan 2023 05:14:31 -0800 (PST) Received: by mail-wm1-x335.google.com with SMTP id fl11-20020a05600c0b8b00b003daf72fc844so3239654wmb.0 for ; Thu, 26 Jan 2023 05:14:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KLiIzuhLPj2W8HRLu1RLddTMjBu2HLYaLu88JyklILs=; b=f4SkERW1RtNf5h/pePShnuCAaC/+L+ggulKbVjRVcKvjaKAz8ktOCH4I1JsRHP4ccG 0G/esHNAzMByXZz0ihwO2e0THIFZsG5Dr2p5ohi20RtAW0c+BGc7MirXpOwWShacxFtR /3gJQ937eIPpFdNAU9UVHwWnIq1KwnOGh1Mb8Tnr67CxruNqXabVsSr/HX4qWACTgVj4 urj3wCGmlv76QtW/yWu7lsTnhSeg36W2cU8tb3nQHAgKgQ/Y4Zk4x1NBL+8cG5iIttJV Gt126Wa82Xv1u5tg9sL3wrsl7yFFWJM0Pb0yUTbJs5B4arXCD5zKOovkf2qgDIo1O24L 3nQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KLiIzuhLPj2W8HRLu1RLddTMjBu2HLYaLu88JyklILs=; b=SZMkwQtgQ5ksLa9CHBze5Y4n9t2R/285Dg87TqPyDh9tMDi+iHZXhNFVGTEJZLosG2 g0J9cNTbMq0ChY+3GSB6a0m56VtTdgFd3aksduN4kUfv8cf2zX7Sq3H/Q8YWMwk6JbvY qPZZlCK/JPQ83XQXUi/wy2oGWOyBu81HJ9RhGsBjwFL58MUwdH8ssClcBxti8SJ3JvKP STvzVIrRubf6vEW48VCG3PQ6cgRT5aSVOqyWUqED7cFMeRMvSUfgOzGelzbwTSH84HYS pT6Ze7HdYbJ2ccCcr/U3xmamn38h2npCyTAaoR0nHtSc21de2aGNaKNzxDYhnd+I4Ggs sV4Q== X-Gm-Message-State: AO0yUKVNGO0k3X8yKg43ZkM9DqXQRr8m3o5PkucfPYT4mTY0P6js63x0 B1b0j/NINgiWUpnZlpFYk2xaAQ== X-Google-Smtp-Source: AK7set97mUdUoUStPMzspZ1HBJa/ogA3H8+v0Skr3C4OKz7dz2a1AIG2oDCQ2nZPfoElAUoUg76n1w== X-Received: by 2002:a05:600c:3ca3:b0:3dc:1687:9ba2 with SMTP id bg35-20020a05600c3ca300b003dc16879ba2mr9293190wmb.35.1674738869713; Thu, 26 Jan 2023 05:14:29 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id 18-20020a05600c26d200b003da28dfdedcsm1719804wmv.5.2023.01.26.05.14.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Jan 2023 05:14:29 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , "vkoul@kernel.org" , Kishon Vijay Abraham I , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Linux Kernel Mailing List , linux-phy@lists.infradead.org Subject: [PATCH v3 8/8] arm64: dts: qcom: sm8550-mtp: Add USB PHYs and HC nodes Date: Thu, 26 Jan 2023 15:14:15 +0200 Message-Id: <20230126131415.1453741-9-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230126131415.1453741-1-abel.vesa@linaro.org> References: <20230126131415.1453741-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable USB HC and PHYs nodes on SM8550 MTP board. Signed-off-by: Abel Vesa --- Changes since v2: * none NOTE: This patch has been already merged. It is here only to provide context for the rest of the patchset. There is a change with respect to the clocks, but that will be sent as a separate/individual fix patch. arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 31e039f10a1b..cea1f12ce294 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -455,6 +455,28 @@ &ufs_mem_phy { status = "okay"; }; +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l1e_0p88>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3f_0p91>; + + status = "okay"; +}; + &xo_board { clock-frequency = <76800000>; };