From patchwork Thu Jan 26 18:13:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 647373 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA8EEC61DA7 for ; Thu, 26 Jan 2023 18:13:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229459AbjAZSNp (ORCPT ); Thu, 26 Jan 2023 13:13:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230404AbjAZSNo (ORCPT ); Thu, 26 Jan 2023 13:13:44 -0500 Received: from mail-ed1-x535.google.com (mail-ed1-x535.google.com [IPv6:2a00:1450:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E9F2F5A350 for ; Thu, 26 Jan 2023 10:13:42 -0800 (PST) Received: by mail-ed1-x535.google.com with SMTP id y19so2657057edc.2 for ; Thu, 26 Jan 2023 10:13:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mwu7GIxD7xZjN0XvP9+6NJsNqcMUvGhwmupilA4s3ZQ=; b=N+wIuEMYwj32c8Uc2Qea8UbDHNBhImfFs96fuCgkP1HLNQEdtxpPfi7MnXxKO8GpTq wMapf2Il83YjJx7C1o9yWayCoSpgGTcxrM8G1efEYp+m/D6qoA1LVwc5d7AQ0D3zC+UK ct1UCLqnku/Dg61Zgp02FDggTPRF6b94xWHh9gY1zQRErMjH8EzwXIsL5BqY6GHkqvWd AvCQqk2/xHr3jkyHu1+F8KrpVWAxrHOYvwj3ThrxxeQHNbMe0GU4ScO9fPNZzQo3I1Y7 vYP/+rzFTGm/F0IBgI2EOHfLjhSDFJstYX0kEFG4Icbq8NdHrqnlEVAZxxzPz+DQYbdM nTCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mwu7GIxD7xZjN0XvP9+6NJsNqcMUvGhwmupilA4s3ZQ=; b=5CZu0yNZnZTGBDUH3/wVfwvH4yIfhmKHk91KVCbR5JLoh0+/Y+lbASBt6mgrYYH+KX y5hg23soiIAEiEyjqsb9Tqq/ga0+pV+RdRwkXuLiJyNI/LgdyZ5sgL4KihIsNq17mrF2 XRg0xMnIG46k0TPpQPaN5Divst8fLT015y0RiaxOxlOxXdf0m4+aw3BmdBBT5Tn6LfP9 ck3cuh7OjrZj6ak6Ds/NuLR69w/ZOCcwkdqwG7uyn7L6O1gW7PvUM2fnEdFmeFrY04Sn Z1u+POkQMA2mSCYCMGZ6HRAaUIpsYnkiI8rfaeXp60TqgXDv67zyQsf63iEEOFO+4Ypg TGXw== X-Gm-Message-State: AFqh2kq8OBLiGOuqRnTqmACj1FqxSpwEMW20+NDcEv1FkBBogDWyEOHQ Td1IKOEDkqDtHYmY1jCWaLXZ0Q== X-Google-Smtp-Source: AMrXdXsEMIbaMwrQUMl0SmoFRJGzPWPhc+YB69S1VB2LhKyir4OEiC7XTqPUcj2J1fQaLTAWlB9AZw== X-Received: by 2002:a05:6402:400a:b0:496:bdb5:572f with SMTP id d10-20020a056402400a00b00496bdb5572fmr44047344eda.31.1674756821499; Thu, 26 Jan 2023 10:13:41 -0800 (PST) Received: from localhost.localdomain (abyl20.neoplus.adsl.tpnet.pl. [83.9.31.20]) by smtp.gmail.com with ESMTPSA id k6-20020aa7d8c6000000b00487fc51c532sm1100416eds.33.2023.01.26.10.13.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Jan 2023 10:13:41 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/6] dt-bindings: clock: Add Qcom SM6125 GPUCC Date: Thu, 26 Jan 2023 19:13:30 +0100 Message-Id: <20230126181335.12970-2-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230126181335.12970-1-konrad.dybcio@linaro.org> References: <20230126181335.12970-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM6125 SoCs. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski --- v1 -> v2: No changes .../bindings/clock/qcom,sm6125-gpucc.yaml | 64 +++++++++++++++++++ include/dt-bindings/clock/qcom,sm6125-gpucc.h | 31 +++++++++ 2 files changed, 95 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml create mode 100644 include/dt-bindings/clock/qcom,sm6125-gpucc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml new file mode 100644 index 000000000000..374a1844a159 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm6125-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on SM6125 + +maintainers: + - Konrad Dybcio + +description: | + Qualcomm graphics clock control module provides clocks and power domains on + Qualcomm SoCs. + + See also:: include/dt-bindings/clock/qcom,sm6125-gpucc.h + +properties: + compatible: + enum: + - qcom,sm6125-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + + '#clock-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <1>; + #size-cells = <1>; + + clock-controller@5990000 { + compatible = "qcom,sm6125-gpucc"; + reg = <0x05990000 0x9000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,sm6125-gpucc.h b/include/dt-bindings/clock/qcom,sm6125-gpucc.h new file mode 100644 index 000000000000..ce5bd920f2c4 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm6125-gpucc.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6125_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6125_H + +/* Clocks */ +#define GPU_CC_PLL0_OUT_AUX2 0 +#define GPU_CC_PLL1_OUT_AUX2 1 +#define GPU_CC_CRC_AHB_CLK 2 +#define GPU_CC_CX_APB_CLK 3 +#define GPU_CC_CX_GFX3D_CLK 4 +#define GPU_CC_CX_GMU_CLK 5 +#define GPU_CC_CX_SNOC_DVM_CLK 6 +#define GPU_CC_CXO_AON_CLK 7 +#define GPU_CC_CXO_CLK 8 +#define GPU_CC_GMU_CLK_SRC 9 +#define GPU_CC_SLEEP_CLK 10 +#define GPU_CC_GX_GFX3D_CLK 11 +#define GPU_CC_GX_GFX3D_CLK_SRC 12 +#define GPU_CC_AHB_CLK 13 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 14 + +/* GDSCs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif From patchwork Thu Jan 26 18:13:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 648230 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 897C3C61DA4 for ; Thu, 26 Jan 2023 18:13:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231837AbjAZSNt (ORCPT ); Thu, 26 Jan 2023 13:13:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33770 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231745AbjAZSNs (ORCPT ); Thu, 26 Jan 2023 13:13:48 -0500 Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [IPv6:2a00:1450:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 653B35CFFC for ; Thu, 26 Jan 2023 10:13:46 -0800 (PST) Received: by mail-ed1-x52d.google.com with SMTP id x10so2631841edd.10 for ; Thu, 26 Jan 2023 10:13:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dW3sC3ktDpdZxd0icwPexqyi6yhFwBIKGDsOHiNFRKo=; b=yz3O3ypV2TVaUHW5VBMM7xDR7DdZE8dHjVeQ5ob+7UhLWnQZZAw5QFTIxZvFjctOhs OasGcBDndNOUlnr3C2BTSGesNvTNei0dXzKlDZNKXhKjzegu1qOVA3K7NCMYYYyRTZSJ gH9ZOMtSMOfz5Xtumf824rzFbe9/bv9HAU7JrUkcYhT7W0B+xXJAnCoB1mPK+H3oPMI+ mTOHuQYvn2VerRH8wInqlm6h7ZtFKv4UdL1lsOaBqdMuOUv3OEiNdMzykRJ5mjQQ3t4o rS5K8HF17GAVCz6Oz3jD768JkA10pFalntnuPo+tRtYCFjpITN9NTODCjLiBlt3zs2CH co6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dW3sC3ktDpdZxd0icwPexqyi6yhFwBIKGDsOHiNFRKo=; b=WvFyNzceBM1PNQ0SIhRV+HVLcJj2UKeWJOkp3uSb1JhIxFBCp5J4S+AB0WkcQZctfq X0QDy+aZE9n5SZ3B3blhS8l7Q5lioaun5j3DG8zsjTZ3/vwo4JAJIesUSPk69mhOpoP9 XcIYXXDqgiMWhO8VxFwj/ybnVgS3cjLhiDCa39mCJLx9OQNSY7fGThVRUiVO9bUI7B3D oClUEXD16pWRSgYVFBAQm4OdtdNcKgCmx7bEajOuy+m1Wg+7lYt2c0rAaXDfpZRO1iPR CJ5by2ompXp62Po9H5wb4gFOVLCYR1Ti3IK4lxQKXomMUo1k8QItJV0IUUSIcnThLE4y XOFg== X-Gm-Message-State: AFqh2kpg52vioMFtkkrS9gYroWfb91UvrmXHUIwLPZhlaPsAuFKPWE+n SUNg6Cl7H7jWNlXh1w+AqlTCtQ== X-Google-Smtp-Source: AMrXdXsxw2tOad0R4RGEE1aVfIzjU2DsTarFDs9uMXTGTUwd4VhmYWeFFnMb8nW6gPs1BxwvLqs2mA== X-Received: by 2002:a05:6402:1002:b0:49b:63ea:b5d8 with SMTP id c2-20020a056402100200b0049b63eab5d8mr38863609edu.4.1674756826042; Thu, 26 Jan 2023 10:13:46 -0800 (PST) Received: from localhost.localdomain (abyl20.neoplus.adsl.tpnet.pl. [83.9.31.20]) by smtp.gmail.com with ESMTPSA id k6-20020aa7d8c6000000b00487fc51c532sm1100416eds.33.2023.01.26.10.13.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Jan 2023 10:13:45 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/6] dt-bindings: clock: Add Qcom SM6375 GPUCC Date: Thu, 26 Jan 2023 19:13:32 +0100 Message-Id: <20230126181335.12970-4-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230126181335.12970-1-konrad.dybcio@linaro.org> References: <20230126181335.12970-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM6375 SoCs. Signed-off-by: Konrad Dybcio --- v1 -> v2: No changes .../bindings/clock/qcom,sm6375-gpucc.yaml | 60 +++++++++++++++++++ include/dt-bindings/clock/qcom,sm6375-gpucc.h | 36 +++++++++++ 2 files changed, 96 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml create mode 100644 include/dt-bindings/clock/qcom,sm6375-gpucc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml new file mode 100644 index 000000000000..b480ead5bd69 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm6375-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on SM6375 + +maintainers: + - Konrad Dybcio + +description: | + Qualcomm graphics clock control module provides clocks, resets and power + domains on Qualcomm SoCs. + + See also:: include/dt-bindings/clock/qcom,sm6375-gpucc.h + +properties: + compatible: + enum: + - qcom,sm6375-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 div branch source + - description: SNoC DVM GFX source + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@5990000 { + compatible = "qcom,sm6375-gpucc"; + reg = <0 0x05990000 0 0x9000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,sm6375-gpucc.h b/include/dt-bindings/clock/qcom,sm6375-gpucc.h new file mode 100644 index 000000000000..0887ac03825e --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm6375-gpucc.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_BLAIR_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_BLAIR_H + +/* GPU CC clocks */ +#define GPU_CC_PLL0 0 +#define GPU_CC_PLL1 1 +#define GPU_CC_AHB_CLK 2 +#define GPU_CC_CX_GFX3D_CLK 3 +#define GPU_CC_CX_GFX3D_SLV_CLK 4 +#define GPU_CC_CX_GMU_CLK 5 +#define GPU_CC_CX_SNOC_DVM_CLK 6 +#define GPU_CC_CXO_AON_CLK 7 +#define GPU_CC_CXO_CLK 8 +#define GPU_CC_GMU_CLK_SRC 9 +#define GPU_CC_GX_CXO_CLK 10 +#define GPU_CC_GX_GFX3D_CLK 11 +#define GPU_CC_GX_GFX3D_CLK_SRC 12 +#define GPU_CC_GX_GMU_CLK 13 +#define GPU_CC_SLEEP_CLK 14 + +/* GDSCs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +/* Resets */ +#define GPU_GX_BCR 0 +#define GPU_ACD_BCR 1 +#define GPU_GX_ACD_MISC_BCR 2 + +#endif From patchwork Thu Jan 26 18:13:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 647372 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79320C61DB3 for ; Thu, 26 Jan 2023 18:14:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231956AbjAZSOE (ORCPT ); Thu, 26 Jan 2023 13:14:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34402 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231989AbjAZSOC (ORCPT ); Thu, 26 Jan 2023 13:14:02 -0500 Received: from mail-ed1-x536.google.com (mail-ed1-x536.google.com [IPv6:2a00:1450:4864:20::536]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 02C1D5E530 for ; Thu, 26 Jan 2023 10:13:52 -0800 (PST) Received: by mail-ed1-x536.google.com with SMTP id v10so2639877edi.8 for ; Thu, 26 Jan 2023 10:13:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3pTb5wpNdthCuVjgjcUKylwdCIsqRo5OGcUFbMgOJow=; b=b/A8K/0tYlSS0dzWC+tB/RqdwpPxJXEihggNaF6GullWU5syq3Hgbv9Sqy2Q/zo5zo DILtSrp7DIyEhN++LlXvGI45zUC943muS31OZga42jy4htt3HcvuKeVvgZQXvfqbNtuK a4Bnb1Gm1/FU0NkF6E+zPJUX90Y0STM/sdP0CyejIdwDDeo2RjIXKpUSKhdGfWhDOoIn 7yULdOSUY5z8O5SMkFsXzyRX7VD/LZCRjXsOToBe0aB32u/qMsGzwj5daM6+qPOe6n0r Z4O02Nmyeh1gieAXM5yXNhvW/urssJI9AOKVVWr700WFbzci0NgKQrXqZIF3Oj2/fL0g qIZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3pTb5wpNdthCuVjgjcUKylwdCIsqRo5OGcUFbMgOJow=; b=x4Z/aDNZWk0InJOqalp4qHcgqD3qY8zHVprB3BsBppQJ7KUO0m58cyOiVc3UH/4U+d RCxOUTJcE/97yfMqkKpMCuzsis0KbJL4kZ8cE63s8OqAzsdC/psuETVmWbRisSLSWGQv 8ja5+e+YDpoQ5DKLeJOTb7HPvBfg/ynnCNFC+cR70SiZhArZEV5a3HrH6e3p9GlULJkC 7RabGDf7aXsuI/OKvQFkcgE5SjqwraTSca9yfT8m3ndA74brNgZmUI4ABYRhbWV2qhOt eJhMGR/1NnbROeRR9FD0gCOldT25CK75sKB4+BuuKfW6f1RSLczod4FleaNDfyU/RRpT GWTQ== X-Gm-Message-State: AFqh2kqhucHFjHhFk/LkpfBbIY5LIWUX33cH3UCaCzsN9UAIhg9SiNeW S7jqac/ciwShFIB9HTJbLMziKw== X-Google-Smtp-Source: AMrXdXstychLZTmlwRBia5qU3U7DVyHSAhRd5pnfGzhcUcXurvOsOVxTpLQWqdSxdcrrdV1kJEMk0Q== X-Received: by 2002:a05:6402:43c4:b0:49e:8425:6033 with SMTP id p4-20020a05640243c400b0049e84256033mr29415893edc.28.1674756832243; Thu, 26 Jan 2023 10:13:52 -0800 (PST) Received: from localhost.localdomain (abyl20.neoplus.adsl.tpnet.pl. [83.9.31.20]) by smtp.gmail.com with ESMTPSA id k6-20020aa7d8c6000000b00487fc51c532sm1100416eds.33.2023.01.26.10.13.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Jan 2023 10:13:51 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/6] dt-bindings: clock: Add Qcom SM6115 GPUCC Date: Thu, 26 Jan 2023 19:13:34 +0100 Message-Id: <20230126181335.12970-6-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230126181335.12970-1-konrad.dybcio@linaro.org> References: <20230126181335.12970-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM6115 SoCs. Signed-off-by: Konrad Dybcio --- v1 -> v2: No changes .../bindings/clock/qcom,sm6115-gpucc.yaml | 71 +++++++++++++++++++ include/dt-bindings/clock/qcom,sm6115-gpucc.h | 36 ++++++++++ 2 files changed, 107 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml create mode 100644 include/dt-bindings/clock/qcom,sm6115-gpucc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml new file mode 100644 index 000000000000..abf4e87359a3 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm6115-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on SM6115 + +maintainers: + - Konrad Dybcio + +description: | + Qualcomm graphics clock control module provides clocks and power domains on + Qualcomm SoCs. + + See also:: include/dt-bindings/clock/qcom,sm6115-gpucc.h + +properties: + compatible: + enum: + - qcom,sm6115-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 main div source + + '#clock-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + '#reset-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <1>; + #size-cells = <1>; + + clock-controller@5990000 { + compatible = "qcom,sm6115-gpucc"; + reg = <0x05990000 0x9000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,sm6115-gpucc.h b/include/dt-bindings/clock/qcom,sm6115-gpucc.h new file mode 100644 index 000000000000..945f21a7d745 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm6115-gpucc.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6115_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6115_H + +/* GPU_CC clocks */ +#define GPU_CC_PLL0 0 +#define GPU_CC_PLL0_OUT_AUX2 1 +#define GPU_CC_PLL1 2 +#define GPU_CC_PLL1_OUT_AUX 3 +#define GPU_CC_AHB_CLK 4 +#define GPU_CC_CRC_AHB_CLK 5 +#define GPU_CC_CX_GFX3D_CLK 6 +#define GPU_CC_CX_GMU_CLK 7 +#define GPU_CC_CX_SNOC_DVM_CLK 8 +#define GPU_CC_CXO_AON_CLK 9 +#define GPU_CC_CXO_CLK 10 +#define GPU_CC_GMU_CLK_SRC 11 +#define GPU_CC_GX_CXO_CLK 12 +#define GPU_CC_GX_GFX3D_CLK 13 +#define GPU_CC_GX_GFX3D_CLK_SRC 14 +#define GPU_CC_SLEEP_CLK 15 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 16 + +/* Resets */ +#define GPU_GX_BCR 0 + +/* GDSCs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif