From patchwork Wed Jan 18 15:08:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 643746 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06326C32793 for ; Wed, 18 Jan 2023 15:09:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230083AbjARPJi (ORCPT ); Wed, 18 Jan 2023 10:09:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41302 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231556AbjARPJV (ORCPT ); Wed, 18 Jan 2023 10:09:21 -0500 Received: from mail-pf1-x432.google.com (mail-pf1-x432.google.com [IPv6:2607:f8b0:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1921022782 for ; Wed, 18 Jan 2023 07:09:20 -0800 (PST) Received: by mail-pf1-x432.google.com with SMTP id w2so11006258pfc.11 for ; Wed, 18 Jan 2023 07:09:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5b3A1ENOut7aNsWCrE1p0bbYMaJf6g4gCfGrBW3niiU=; b=V0GP2xZ9ALQYbIs2LpKz6ECcKJ0MwWRBh+9tbtdCd69NptGSqFuVgnCHV6YB3wnpcS Ed4f0BxPWm19o496hKKuim/EzFn0+HVy31f4wVz1JbLRVw6wAgA4t/o+fidVDwn5TJO8 S5i8dxfc8PolN013w5Vza0OsMLzqhRD/kd9NE32WHFrbj7JBlFfWJ6LEja8cHUCw5oKK kl2Rq9EWsPy8u1s5Ok5LBK01d7Txsy+Ue6ahfFK7M26noXN8L0OVCxszE9sfOJ7iB1/g Ac3KKs+4TNRxLrq7WylSVABz0FipAs6S7Z6vN070gKKBNuaGiD/A2gbwWd5k7NLmoFEr Uazg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5b3A1ENOut7aNsWCrE1p0bbYMaJf6g4gCfGrBW3niiU=; b=XNIrodw6O02TkYejHIx6hEFKJUZZ57y6i1cydWb8WvvrVOb+Vym4lThX/D264NrPV3 YWLKnnvqCJWgB6EX/CWW1QUvKf3SXblZvrX2tv8gMYkiBk3tY+uDlpeNFR1tqYRREzhZ +xKy4P6XxlczU6hnHzJfY+QyNMMoqp4sMauzSTvL/Ji9mjv4IBdk2wJZh8mcKYo7f4qJ To3ukSfDdztnQNmIsG7rxPvXtKd+hY/W9zqOyv42y3aCE2SetAY36gcWPg+4F+bYyJyu yOSWbf1lQ6XJT7jGMmmJnWUVbf0NAkqUlTgxZyLpMFm1yQYVnWhqeCHh2X4Y6k/fI5XG DGrA== X-Gm-Message-State: AFqh2kpaKY4kdrirUtMwWZ3IBnFmPDCQO3KaVOo8JBSLsyVe18/TFVFk 3j8ocVztFH2RL55IzwmGQ9Hs X-Google-Smtp-Source: AMrXdXsLTWywF4NbchUpZhySfS8ietOm7jmmeDUYkw4BmqGHBpj3Pb/+0uYWijxasklhMlDHCZX1FQ== X-Received: by 2002:aa7:8d11:0:b0:587:f436:6ea8 with SMTP id j17-20020aa78d11000000b00587f4366ea8mr6651438pfe.16.1674054559488; Wed, 18 Jan 2023 07:09:19 -0800 (PST) Received: from localhost.localdomain ([27.111.75.61]) by smtp.gmail.com with ESMTPSA id i15-20020aa796ef000000b0058d9623e7f1sm6721544pfq.73.2023.01.18.07.09.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jan 2023 07:09:18 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH v6 01/17] EDAC/device: Respect any driver-supplied workqueue polling value Date: Wed, 18 Jan 2023 20:38:48 +0530 Message-Id: <20230118150904.26913-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230118150904.26913-1-manivannan.sadhasivam@linaro.org> References: <20230118150904.26913-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The EDAC drivers may optionally pass the poll_msec value. Use that value if available, else fall back to 1000ms. [ bp: Touchups. ] Fixes: e27e3dac6517 ("drivers/edac: add edac_device class") Reported-by: Luca Weiss Signed-off-by: Manivannan Sadhasivam Signed-off-by: Borislav Petkov (AMD) Tested-by: Steev Klimaszewski # Thinkpad X13s Tested-by: Andrew Halaney # sa8540p-ride Cc: # 4.9 Link: https://lore.kernel.org/r/COZYL8MWN97H.MROQ391BGA09@otso --- drivers/edac/edac_device.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/edac/edac_device.c b/drivers/edac/edac_device.c index 19522c568aa5..a50b7bcfb731 100644 --- a/drivers/edac/edac_device.c +++ b/drivers/edac/edac_device.c @@ -34,6 +34,9 @@ static DEFINE_MUTEX(device_ctls_mutex); static LIST_HEAD(edac_device_list); +/* Default workqueue processing interval on this instance, in msecs */ +#define DEFAULT_POLL_INTERVAL 1000 + #ifdef CONFIG_EDAC_DEBUG static void edac_device_dump_device(struct edac_device_ctl_info *edac_dev) { @@ -336,7 +339,7 @@ static void edac_device_workq_function(struct work_struct *work_req) * whole one second to save timers firing all over the period * between integral seconds */ - if (edac_dev->poll_msec == 1000) + if (edac_dev->poll_msec == DEFAULT_POLL_INTERVAL) edac_queue_work(&edac_dev->work, round_jiffies_relative(edac_dev->delay)); else edac_queue_work(&edac_dev->work, edac_dev->delay); @@ -366,7 +369,7 @@ static void edac_device_workq_setup(struct edac_device_ctl_info *edac_dev, * timers firing on sub-second basis, while they are happy * to fire together on the 1 second exactly */ - if (edac_dev->poll_msec == 1000) + if (edac_dev->poll_msec == DEFAULT_POLL_INTERVAL) edac_queue_work(&edac_dev->work, round_jiffies_relative(edac_dev->delay)); else edac_queue_work(&edac_dev->work, edac_dev->delay); @@ -398,7 +401,7 @@ void edac_device_reset_delay_period(struct edac_device_ctl_info *edac_dev, { unsigned long jiffs = msecs_to_jiffies(value); - if (value == 1000) + if (value == DEFAULT_POLL_INTERVAL) jiffs = round_jiffies_relative(value); edac_dev->poll_msec = value; @@ -443,11 +446,7 @@ int edac_device_add_device(struct edac_device_ctl_info *edac_dev) /* This instance is NOW RUNNING */ edac_dev->op_state = OP_RUNNING_POLL; - /* - * enable workq processing on this instance, - * default = 1000 msec - */ - edac_device_workq_setup(edac_dev, 1000); + edac_device_workq_setup(edac_dev, edac_dev->poll_msec ?: DEFAULT_POLL_INTERVAL); } else { edac_dev->op_state = OP_RUNNING_INTERRUPT; } From patchwork Wed Jan 18 15:08:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 644234 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 791B0C38147 for ; Wed, 18 Jan 2023 15:09:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231594AbjARPJm (ORCPT ); Wed, 18 Jan 2023 10:09:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41160 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231570AbjARPJ0 (ORCPT ); Wed, 18 Jan 2023 10:09:26 -0500 Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5906523C56 for ; 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Tested-by: Steev Klimaszewski # Thinkpad X13s Tested-by: Andrew Halaney # sa8540p-ride Reported-by: Andrew Halaney Signed-off-by: Manivannan Sadhasivam --- drivers/edac/qcom_edac.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c index 97a27e42dd61..9e77fa84e84f 100644 --- a/drivers/edac/qcom_edac.c +++ b/drivers/edac/qcom_edac.c @@ -397,12 +397,19 @@ static int qcom_llcc_edac_remove(struct platform_device *pdev) return 0; } +static const struct platform_device_id qcom_llcc_edac_id_table[] = { + { .name = "qcom_llcc_edac" }, + {} +}; +MODULE_DEVICE_TABLE(platform, qcom_llcc_edac_id_table); + static struct platform_driver qcom_llcc_edac_driver = { .probe = qcom_llcc_edac_probe, .remove = qcom_llcc_edac_remove, .driver = { .name = "qcom_llcc_edac", }, + .id_table = qcom_llcc_edac_id_table, }; module_platform_driver(qcom_llcc_edac_driver); From patchwork Wed Jan 18 15:08:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 644233 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C848C677F1 for ; Wed, 18 Jan 2023 15:09:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231628AbjARPJq (ORCPT ); Wed, 18 Jan 2023 10:09:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41346 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231585AbjARPJb (ORCPT ); Wed, 18 Jan 2023 10:09:31 -0500 Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 015C3233D9 for ; Wed, 18 Jan 2023 07:09:31 -0800 (PST) Received: by mail-pf1-x436.google.com with SMTP id 200so20238945pfx.7 for ; Wed, 18 Jan 2023 07:09:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9g1r2YkbrCTL06JBn8TcdxJnLCnZpZqC+qdq6jkkxOk=; b=rmGHhTlj8O6W1yPAhd3uk2Ho8WDQV2ls8DgNFrQvHO8xa5RrlA6ALv/tHMw3UtegjW uqKI8SSb5ozUimyYj7w3LSV61Kuk7og8suQrm1s2/uBYGWx1E8e8+UTZWwXFYUkb9eEL lo4+CJxoKxTh9NmrYfhJ8cQFpyT9/yvaUSXXInOg50ZEnzW3wCzXGWjkf/N2pSJxrcnx O2lXZ3BPh1lMOkLCDCqNEQTA5yPe7iKk5Q2QO7A1+syXPfPEX9xHDqByGpjF2QPNeACx NJKYI778puEQkLpRby0cQlida5hNSZRwwTyoxlUd4xBBmwuL+76wvu9c/ou2wdGNsAkc q7vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9g1r2YkbrCTL06JBn8TcdxJnLCnZpZqC+qdq6jkkxOk=; b=vAkHemEIKACB/i8c8ARa8XVpABYZpwjaqWbCi/GO68rDoRsXW/6sTl9RGxCq9c7IYE 2Mm+9REwX39R49V9lFnbkOs4ZznsTXML28LULdbV8qeOWzLxVi9rASgmHh2xMH+upxMp yO1/yWJT9pgJlg6ntLniLe6k6XS0/DCfDj0lTDpEQymMB53ARExlOrP/Uca+37z60+2R zIsoXuWrTCGQKg66e73frqgJQb7ZoKutxXgK+kp1kVW5xIl+I2P3WBhNzyE+CHGUA6Zm M028Kjd17RxCzvqtrYRPTkv3P5yIO1z5e+6Dbv6eG0CxOVlOy95M2t44pvObc4dLyfDK kmgg== X-Gm-Message-State: AFqh2kqlR9TQS475iwCk7oO/O7v1/yoiZ7SE5KJ4Rbz8odeVcOBEyWpS HtscZshj0Dvp+TiNMVn8xJ/B X-Google-Smtp-Source: AMrXdXvZOMcQB/ZBoqS+3k2rADk7d3DCLX6WFNCx/MxVUn82xQIrp1DOK76Vvu1vLwsXnqn861Rddg== X-Received: by 2002:aa7:9a50:0:b0:589:b85:1e32 with SMTP id x16-20020aa79a50000000b005890b851e32mr7763285pfj.16.1674054570482; Wed, 18 Jan 2023 07:09:30 -0800 (PST) Received: from localhost.localdomain ([27.111.75.61]) by smtp.gmail.com with ESMTPSA id i15-20020aa796ef000000b0058d9623e7f1sm6721544pfq.73.2023.01.18.07.09.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jan 2023 07:09:29 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH v6 03/17] EDAC/qcom: Do not pass llcc_driv_data as edac_device_ctl_info's pvt_info Date: Wed, 18 Jan 2023 20:38:50 +0530 Message-Id: <20230118150904.26913-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230118150904.26913-1-manivannan.sadhasivam@linaro.org> References: <20230118150904.26913-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The memory for "llcc_driv_data" is allocated by the LLCC driver. But when it is passed as "pvt_info" to the EDAC core, it will get freed during the qcom_edac driver release. So when the qcom_edac driver gets probed again, it will try to use the freed data leading to the use-after-free bug. Hence, do not pass "llcc_driv_data" as pvt_info but rather reference it using the "platform_data" in the qcom_edac driver. Cc: # 4.20 Fixes: 27450653f1db ("drivers: edac: Add EDAC driver support for QCOM SoCs") Tested-by: Steev Klimaszewski # Thinkpad X13s Tested-by: Andrew Halaney # sa8540p-ride Reported-by: Steev Klimaszewski Reviewed-by: Borislav Petkov (AMD) Signed-off-by: Manivannan Sadhasivam --- drivers/edac/qcom_edac.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c index 9e77fa84e84f..3256254c3722 100644 --- a/drivers/edac/qcom_edac.c +++ b/drivers/edac/qcom_edac.c @@ -252,7 +252,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type) static int dump_syn_reg(struct edac_device_ctl_info *edev_ctl, int err_type, u32 bank) { - struct llcc_drv_data *drv = edev_ctl->pvt_info; + struct llcc_drv_data *drv = edev_ctl->dev->platform_data; int ret; ret = dump_syn_reg_values(drv, bank, err_type); @@ -289,7 +289,7 @@ static irqreturn_t llcc_ecc_irq_handler(int irq, void *edev_ctl) { struct edac_device_ctl_info *edac_dev_ctl = edev_ctl; - struct llcc_drv_data *drv = edac_dev_ctl->pvt_info; + struct llcc_drv_data *drv = edac_dev_ctl->dev->platform_data; irqreturn_t irq_rc = IRQ_NONE; u32 drp_error, trp_error, i; int ret; @@ -358,7 +358,6 @@ static int qcom_llcc_edac_probe(struct platform_device *pdev) edev_ctl->dev_name = dev_name(dev); edev_ctl->ctl_name = "llcc"; edev_ctl->panic_on_ue = LLCC_ERP_PANIC_ON_UE; - edev_ctl->pvt_info = llcc_driv_data; rc = edac_device_add_device(edev_ctl); if (rc) From patchwork Wed Jan 18 15:08:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 643745 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53D2DC46467 for ; Wed, 18 Jan 2023 15:09:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231515AbjARPJr (ORCPT ); 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Wed, 18 Jan 2023 07:09:35 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam , Krzysztof Kozlowski Subject: [PATCH v6 04/17] dt-bindings: arm: msm: Update the maintainers for LLCC Date: Wed, 18 Jan 2023 20:38:51 +0530 Message-Id: <20230118150904.26913-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230118150904.26913-1-manivannan.sadhasivam@linaro.org> References: <20230118150904.26913-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Rishabh Bhatnagar has left Qualcomm, and there is no evidence of him maintaining with a new identity. So his entry needs to be removed. Also, Sai Prakash Ranjan's email address should be updated to use quicinc domain. Cc: Sai Prakash Ranjan Acked-by: Sai Prakash Ranjan Acked-by: Krzysztof Kozlowski Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index 38efcad56dbd..d1df49ffcc1b 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -7,8 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Last Level Cache Controller maintainers: - - Rishabh Bhatnagar - - Sai Prakash Ranjan + - Sai Prakash Ranjan description: | LLCC (Last Level Cache Controller) provides last level of cache memory in SoC, From patchwork Wed Jan 18 15:08:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 643744 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81A6FC38147 for ; Wed, 18 Jan 2023 15:10:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231651AbjARPJu (ORCPT ); Wed, 18 Jan 2023 10:09:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41488 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231618AbjARPJn (ORCPT ); Wed, 18 Jan 2023 10:09:43 -0500 Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2EBAA1554D for ; Wed, 18 Jan 2023 07:09:42 -0800 (PST) Received: by mail-pf1-x436.google.com with SMTP id s3so23880952pfd.12 for ; Wed, 18 Jan 2023 07:09:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jXuVNaTN8VlggSdcrqnxpaEGm5VyBVkNPNZuLm2UVUQ=; b=eXeh3yGVsH9ffM3jicbIsyf8jsrDa5kqR1E3UQGIGTQKTitp9gSaGd/JMuK3t0iLYV KkFtkPPrZx/r5KylQPaS0s9oAh/m3W3HdLeoW8VFxGfXHDRQdsmTCFO0av+fur/vi1TX RLqXV/qF4sBk0DEHhysTXbZ/LYRTl9CkwQEGhiOaZCVbohgbfATxUbeeJxB2Xnl7hban d7yprmgPtYXdFxIhx8pJQ9fhGzxuyFtIj4Rk9lB/bi1hhoZGyNvW8ijm3c2fwvLk25jF PeDCF6M0So7AyXvaNw0N9vI/Khm4ATbMS/SKqzlIzWvh/eUTxDR/zJ8VJ5EDM7Z5Opjx VjSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jXuVNaTN8VlggSdcrqnxpaEGm5VyBVkNPNZuLm2UVUQ=; b=MMkLNvV903p7sxwCIEIz9w03FRjJwDzoVHqfbSqoOTWBz9tzWa2e6Q8h8wg1AmhJhE XrXce8AAmz+h65YvsgroUqEQJEbFiB49srAz46v+zJSJYI2rFoYVvLqzmAzaCD8R/qvU WoBRAh18rxkjBb8PbMLFtmT9aFecIMA7Zu8OWarHGa6gMLNPNhPLV6YYzRPNH3nuE/3E vahsPwaq7jbhEi7KeInmF7HiJhOSs/2L2E9sOTtJfzrYWsd6oOqyQCy81TZtPNxJ7v0D XdHufs0jeYqSUpxIZUOq2M6qd91DFzLjb7FQuTVmmSlO50bPLIh/3ls0DeT3OIzzB22J wRCA== X-Gm-Message-State: AFqh2kqUDQ0/T9IdRVKaRkuUsbruVu/SULaeeuvbN3U2UjY2VWGHV/1Y hgztGkDfrhqDjwm6eJXAs0p1 X-Google-Smtp-Source: AMrXdXupg+FJU9gCGZn0pA4MSvTGTZj/iNGqwm+Tn9dHNYuSRVGDFJsSd2WJPflryOxKI2zn2RlM1w== X-Received: by 2002:a05:6a00:3390:b0:58c:6ba1:58dd with SMTP id cm16-20020a056a00339000b0058c6ba158ddmr8010503pfb.11.1674054581652; Wed, 18 Jan 2023 07:09:41 -0800 (PST) Received: from localhost.localdomain ([27.111.75.61]) by smtp.gmail.com with ESMTPSA id i15-20020aa796ef000000b0058d9623e7f1sm6721544pfq.73.2023.01.18.07.09.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jan 2023 07:09:40 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam , Krzysztof Kozlowski Subject: [PATCH v6 05/17] dt-bindings: arm: msm: Fix register regions used for LLCC banks Date: Wed, 18 Jan 2023 20:38:52 +0530 Message-Id: <20230118150904.26913-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230118150904.26913-1-manivannan.sadhasivam@linaro.org> References: <20230118150904.26913-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Register regions of the LLCC banks are located at different addresses. Currently, the binding just lists the LLCC0 base address and tries to cover all the banks using a single size. This is entirely wrong as there are other register regions that happen to lie inside the size covered by the binding such as the memory controller and holes. So this needs to be fixed by specifying the base address of individual LLCC banks. This approach will break the existing users of this binding as the register regions are split and the drivers now cannot use LLCC0 register region for accessing rest of the banks (which is wrong anyway). But considering the fact that the binding was wrong from the day one and also the device drivers going wrong by the binding, this breakage is acceptable. Reported-by: Parikshit Pareek Reviewed-by: Krzysztof Kozlowski Signed-off-by: Manivannan Sadhasivam --- .../bindings/arm/msm/qcom,llcc.yaml | 125 ++++++++++++++++-- 1 file changed, 114 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index d1df49ffcc1b..050e21d4a03e 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -33,14 +33,12 @@ properties: - qcom,sm8550-llcc reg: - items: - - description: LLCC base register region - - description: LLCC broadcast base register region + minItems: 2 + maxItems: 9 reg-names: - items: - - const: llcc_base - - const: llcc_broadcast_base + minItems: 2 + maxItems: 9 interrupts: maxItems: 1 @@ -50,15 +48,120 @@ required: - reg - reg-names +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7180-llcc + - qcom,sm6350-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7280-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8180x-llcc + - qcom,sc8280xp-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC2 base register region + - description: LLCC3 base register region + - description: LLCC4 base register region + - description: LLCC5 base register region + - description: LLCC6 base register region + - description: LLCC7 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc2_base + - const: llcc3_base + - const: llcc4_base + - const: llcc5_base + - const: llcc6_base + - const: llcc7_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: + - qcom,sdm845-llcc + - qcom,sm8150-llcc + - qcom,sm8250-llcc + - qcom,sm8350-llcc + - qcom,sm8450-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC2 base register region + - description: LLCC3 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc2_base + - const: llcc3_base + - const: llcc_broadcast_base + additionalProperties: false examples: - | #include - system-cache-controller@1100000 { - compatible = "qcom,sdm845-llcc"; - reg = <0x1100000 0x200000>, <0x1300000 0x50000> ; - reg-names = "llcc_base", "llcc_broadcast_base"; - interrupts = ; + soc { + #address-cells = <2>; + #size-cells = <2>; + + system-cache-controller@1100000 { + compatible = "qcom,sdm845-llcc"; + reg = <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>, + <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, + <0 0x01300000 0 0x50000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; + interrupts = ; + }; }; From patchwork Wed Jan 18 15:08:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 643743 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21771C38159 for ; Wed, 18 Jan 2023 15:10:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231618AbjARPKO (ORCPT ); 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Wed, 18 Jan 2023 07:09:46 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v6 06/17] arm64: dts: qcom: sdm845: Fix the base addresses of LLCC banks Date: Wed, 18 Jan 2023 20:38:53 +0530 Message-Id: <20230118150904.26913-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230118150904.26913-1-manivannan.sadhasivam@linaro.org> References: <20230118150904.26913-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. On SDM845, the size of the LLCC bank 0 needs to be reduced to 0x4500 as there are LLCC BWMON registers located after this range. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 65032b94b46d..4db68d4d78df 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2132,8 +2132,11 @@ uart15: serial@a9c000 { llcc: system-cache-controller@1100000 { compatible = "qcom,sdm845-llcc"; - reg = <0 0x01100000 0 0x31000>, <0 0x01300000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x01100000 0 0x45000>, <0 0x01180000 0 0x50000>, + <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, + <0 0x01300000 0 0x50000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; interrupts = ; }; From patchwork Wed Jan 18 15:08:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 644232 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66F1BC678D4 for ; Wed, 18 Jan 2023 15:10:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231235AbjARPKR (ORCPT ); Wed, 18 Jan 2023 10:10:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41752 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231704AbjARPJ7 (ORCPT ); Wed, 18 Jan 2023 10:09:59 -0500 Received: from mail-pf1-x42f.google.com (mail-pf1-x42f.google.com [IPv6:2607:f8b0:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C450A3457A for ; Wed, 18 Jan 2023 07:09:52 -0800 (PST) Received: by mail-pf1-x42f.google.com with SMTP id a184so26406899pfa.9 for ; Wed, 18 Jan 2023 07:09:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4GFA6I79C1YmmOYQX1BIX7MOGuUjMMgmSjlJ7uhFCjc=; b=F9kKv6buxOU5Im8R6aHB0PFWZ/FXExIZ8ZaDgwt5k8VDOOIwtnBfmZxGR0TZxcjTpL /DKUIVp96tTBZyYFeFB2+XfArqK9Ugu+5xmH1COagG0gyhsE9F8Dx4NlHHujD0k0X7dY oGDLCyLiVcLdlHDIQJYjGId2jV9TBZ9o3yiJ1XIgN5xTnazav+/UJHdo6FlVAuMni/l3 8C4b4AK+H/bcqH711QjPXaLPLL0FZBz44KVSWz8Nq2tR4e1FMN46U8MWlFDAupu8R2rv PbvGbNeMfDiqcAaIRCvMAQwzCIzR8Ms3CnQ1WoRmfH5oN1yTQ4PBEsqEHsrmBE5OG6x/ 3N0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4GFA6I79C1YmmOYQX1BIX7MOGuUjMMgmSjlJ7uhFCjc=; b=rzQp3SvFsFxtVfomNDDqF3Y766i6ZvjdfAZWwSgSI5w1kuIc6dr54ufL9bZ/8hRGk0 DkB4xwF0K7FfUyfK121qspqjFZzNPZ6jQfJdnIpqoJ4wG6DdGVT+oMVvyaFvG6O6JtlO +xJZ5aR1waoL1ZjnttFaHaoj3Q45myudNoJlDQJEal5gJ0hambMsYftqRkE+xHSonBfF dby9srPgEUomZkOGJxiVLt2pvIyh/Oae7e7ScPAnZdHxI0nwsHjoidB/aSCT66jyNzdr cBYk2RJTQ+QTAdqoH3CxNXNB9SxqtKKWse+zx7jQmHp5Q7tVpgrVWhiaI+Kc7+I8kj7S gyxA== X-Gm-Message-State: AFqh2kp051TyiZ1BB7CghjmDaILCylVGAR/lzsHckPdP04s6EEVV5nP1 ZqtX7qWGYGWa3OwrKj9YU6XW X-Google-Smtp-Source: AMrXdXt+3Qs7UO8zkUQYgy7ddY4gAvvWByLhnlOSea+JmBNYxQsNPuuqGkF9FiQWd9ELlXUqUO+9iQ== X-Received: by 2002:aa7:8a0e:0:b0:58d:9850:d55f with SMTP id m14-20020aa78a0e000000b0058d9850d55fmr7381028pfa.21.1674054592431; Wed, 18 Jan 2023 07:09:52 -0800 (PST) Received: from localhost.localdomain ([27.111.75.61]) by smtp.gmail.com with ESMTPSA id i15-20020aa796ef000000b0058d9623e7f1sm6721544pfq.73.2023.01.18.07.09.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jan 2023 07:09:51 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v6 07/17] arm64: dts: qcom: sc7180: Fix the base addresses of LLCC banks Date: Wed, 18 Jan 2023 20:38:54 +0530 Message-Id: <20230118150904.26913-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230118150904.26913-1-manivannan.sadhasivam@linaro.org> References: <20230118150904.26913-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. On SC7180, there is only one LLCC bank available. So let's just pass that as "llcc0_base". Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index f71cf21a8dd8..f861f692c9b1 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2759,7 +2759,7 @@ dc_noc: interconnect@9160000 { system-cache-controller@9200000 { compatible = "qcom,sc7180-llcc"; reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg-names = "llcc0_base", "llcc_broadcast_base"; interrupts = ; }; From patchwork Wed Jan 18 15:08:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 644231 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18E38C38147 for ; Wed, 18 Jan 2023 15:10:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231694AbjARPKU (ORCPT ); Wed, 18 Jan 2023 10:10:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41940 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231749AbjARPKD (ORCPT ); Wed, 18 Jan 2023 10:10:03 -0500 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9B353366BF for ; Wed, 18 Jan 2023 07:09:58 -0800 (PST) Received: by mail-pl1-x62e.google.com with SMTP id r21so5084822plg.13 for ; Wed, 18 Jan 2023 07:09:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=u3b0H9FlwI0cHeu/QvvhJdFruV0iaHa3piiWtATy1Lw=; b=fuZe+rBBF8dNZgZ166UGWALWEqUi/EqjxyiDbf3I2knIvjilvd+rFGnFFZbeNtbshq dJCEoglW9mMo3fczTSmNcEo/eVJ6qwrHZdlvzCSH/FMGYGITVltBgcQB4mWqotbS6Rnv Km18GSOD/QKLSMmGSpr1GwoyMNukZc2JlXm/5lWpyKsud00rDKYHwbCcgC0SYvvfs980 /CviqcY5RUCvSW2Bb7+pQf/oahJWOH77BTMEuRAAuQo7MQQWYSxCSeKOgGYLL++yVkHl +iqT0Zw7pB9HueGu6tr2mBEr3w68OdmwTgdcJYO2PiFzS/O4Llcs44sUq08cysL17/OD VpHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=u3b0H9FlwI0cHeu/QvvhJdFruV0iaHa3piiWtATy1Lw=; b=vihkwE6Qk2Vd9eJRCfOs9a2ECwM6t7GV5zeks+HYHZhCcBeiiKLUSwZP7vPhUEEj3i xlSZhDGJREkkeydtVSwgXnzv2Kc603pZkiyM8B3qyJx2PYb4x+/mf49l4LafycGvqBM/ AxiIB/GG3bcY2MYxO3skHQC/xV2dwgUMyUZDMBDvMf3mbQJxjNIgy62Sv3DXHI2Staiz X5Mhq84m6NYJa0MxmQRFfXLIjrvWMx0WHl1iPyqKzktbsUu+t9wzgDvf0/tcA34c8o7g k0cxifmEIlM7DqV+GJYtL7S60TkIdlxOrvC2Wr8nbfjoklkluGKkCghQUrzOWK9FBGRc t9cg== X-Gm-Message-State: AFqh2kpY+mUszeGtNG/qtGdssIZGAN+9itAcRhbgWIqnK2py2bNGrPKn C0iQtgF+bOt+EgsJDHZHOJ6K X-Google-Smtp-Source: AMrXdXtzc0ScrQ4oiKZQSUbvx3A62txQrmHbGeMTTVpTLslEN8WG1ZhVA5Pm07yH/XqGthynf1nYxQ== X-Received: by 2002:a05:6a20:6d19:b0:b8:4978:cde8 with SMTP id fv25-20020a056a206d1900b000b84978cde8mr6918596pzb.18.1674054598025; Wed, 18 Jan 2023 07:09:58 -0800 (PST) Received: from localhost.localdomain ([27.111.75.61]) by smtp.gmail.com with ESMTPSA id i15-20020aa796ef000000b0058d9623e7f1sm6721544pfq.73.2023.01.18.07.09.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jan 2023 07:09:56 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v6 08/17] arm64: dts: qcom: sc7280: Fix the base addresses of LLCC banks Date: Wed, 18 Jan 2023 20:38:55 +0530 Message-Id: <20230118150904.26913-9-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230118150904.26913-1-manivannan.sadhasivam@linaro.org> References: <20230118150904.26913-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. While at it, let's also fix the size of the llcc_broadcast_base to cover the whole region. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 0adf13399e64..6c6eb6f4f650 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3579,8 +3579,9 @@ gem_noc: interconnect@9100000 { system-cache-controller@9200000 { compatible = "qcom,sc7280-llcc"; - reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, + <0 0x09600000 0 0x58000>; + reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base"; interrupts = ; }; From patchwork Wed Jan 18 15:08:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 643742 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7C2FC32793 for ; Wed, 18 Jan 2023 15:10:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231735AbjARPK6 (ORCPT ); Wed, 18 Jan 2023 10:10:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42162 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231787AbjARPKH (ORCPT ); Wed, 18 Jan 2023 10:10:07 -0500 Received: from mail-pf1-x42b.google.com (mail-pf1-x42b.google.com [IPv6:2607:f8b0:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E9BCC3527D for ; Wed, 18 Jan 2023 07:10:03 -0800 (PST) Received: by mail-pf1-x42b.google.com with SMTP id 200so20240313pfx.7 for ; Wed, 18 Jan 2023 07:10:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cEcc2ZZg4+/rCWO8lF+EBDL5HIag6zFEZ6LhCeBUUxo=; b=SF0jnonDRV3kMcVclflOD2iajoDlCgYs+7RCBsuEuTbAUtPpOd051QxBH225nYEe0j Wk7K28q+az5tsoheuC4aGX0bgSFN7k0Vtt0G0ChpVLhfmHZbdK8w84laJV+yrBSNmswB XI6NZgoKeBfDSIef82be5y5+3HHpwTFwN9Xoi1nUaUwR81eOGaxpFfsoMAZ5tGhYDRPN qWhPD5MUhGK7waGozSvl5VJg1U4LsL2YiMOwEFoMZFDIR1bUIN0XXezUVKTZUTH1tH5m O4OIz6PnAzQXZkm7m0GIvKtjNOOPzoLBRjfuaj2hFbmYUm8SjMfS2H5/0/t2IWkXuG6l OJXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cEcc2ZZg4+/rCWO8lF+EBDL5HIag6zFEZ6LhCeBUUxo=; b=1Vq4yYAdmD2/1vNARp8TYTVD9Yg0IoNECsu1ddwjh3pxVU9EtYOg/Y+pQxiJzxCr6+ I9579FkaDwBBxqjUJ3gAfE3xS5kclkGJD4nvDAjyzsQde6McEkVWJ1sgZHdo4JnG2hGZ QD4k2xNp02DvnZ3NpNT76oEv4hYotaoxSQWakuLOM/lwqI7jMNeJsesJcnxkaESATDUD uO07VwcR7kiLta/j3ga0+CP8lZitTDv2khySxWabjAZ4QxAG3soG/OhUWrWMsHqwUjq/ 8aP9M2dpXGZ5Zsizu1IX0fVSAY1IbnpoGSIfy+CRBV48M+rEsTgIPiQMT5ojYladUE+R hohw== X-Gm-Message-State: AFqh2koXwn7IhiFHfY/j7oTVkjJNw/cyvE9R/0uuz8zEWCRGgHunwDPg 28G7xCDEO2Z2GlZsvlnYMG0m X-Google-Smtp-Source: AMrXdXsQHYRmOryPXtwWfuYEySKTMiOyDnNTqUQWNw+ESAAg1dOAhAWgoXvMEjompjkzgvz9mP7Jpw== X-Received: by 2002:a05:6a00:3691:b0:580:d409:396c with SMTP id dw17-20020a056a00369100b00580d409396cmr8995745pfb.6.1674054603390; Wed, 18 Jan 2023 07:10:03 -0800 (PST) Received: from localhost.localdomain ([27.111.75.61]) by smtp.gmail.com with ESMTPSA id i15-20020aa796ef000000b0058d9623e7f1sm6721544pfq.73.2023.01.18.07.09.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jan 2023 07:10:02 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v6 09/17] arm64: dts: qcom: sc8280xp: Fix the base addresses of LLCC banks Date: Wed, 18 Jan 2023 20:38:56 +0530 Message-Id: <20230118150904.26913-10-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230118150904.26913-1-manivannan.sadhasivam@linaro.org> References: <20230118150904.26913-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Tested-by: Steev Klimaszewski # Thinkpad X13s Tested-by: Andrew Halaney # sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 109c9d2b684d..0510a5d510e7 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1856,8 +1856,14 @@ opp-6 { system-cache-controller@9200000 { compatible = "qcom,sc8280xp-llcc"; - reg = <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, + <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, + <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>, + <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>, + <0 0x09600000 0 0x58000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc4_base", "llcc5_base", + "llcc6_base", "llcc7_base", "llcc_broadcast_base"; interrupts = ; }; From patchwork Wed Jan 18 15:08:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 644230 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51420C32793 for ; Wed, 18 Jan 2023 15:11:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231536AbjARPLa (ORCPT ); Wed, 18 Jan 2023 10:11:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42304 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231816AbjARPKM (ORCPT ); Wed, 18 Jan 2023 10:10:12 -0500 Received: from mail-pg1-x534.google.com (mail-pg1-x534.google.com [IPv6:2607:f8b0:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 79D8534C21 for ; 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bh=7WUljA05hxjrMgWInu+aANTEuP2TXhzChwqlFzG2wks=; b=opLtO8S1CS/9GPnaDzi32AK6IIl+mCWX6nByTdbOKFGi+TkUDCxeSCZw1Zro8mr+aD PMZ4jZDm5hFEmIZfQ5SldfGBfbpE6JcCWjQXPw7d0KooO9+9AgTzIEdvYxL6JF7a3bqy ve7AG/dwNGhdgYPLp3phTU2N0cLWEXalsO8jb7nctUECw/l/M9qTa4CGkTNjTKJBsTtn GxgGKfAegpRZOcBV5BLL2zP/TH2IarYChk6vScci78VCdBH1NRcmJ/ZnVP19KLNZ1XFG ZrcLI6YSY//M4vbTZzShsUy+c5DWzxN0yITKqEtasP/GejC7i0szlkPDZm4z63gkfSRb spag== X-Gm-Message-State: AFqh2krXugXjKigti5i+Pu0AuXZJuck9dXLdEiAD6QLQI9AtStFefm74 rHdmr1RJLe0bsA53ABpvsjE0 X-Google-Smtp-Source: AMrXdXv4dGbRz48I94C4u/f36GkYSgZxv9G7FxDH7O/TUGN1UplLnGQ9KRzYws3OjzOyks7e9vROfQ== X-Received: by 2002:aa7:81d4:0:b0:581:b3b3:7717 with SMTP id c20-20020aa781d4000000b00581b3b37717mr7424491pfn.26.1674054608907; Wed, 18 Jan 2023 07:10:08 -0800 (PST) Received: from localhost.localdomain ([27.111.75.61]) by smtp.gmail.com with ESMTPSA id i15-20020aa796ef000000b0058d9623e7f1sm6721544pfq.73.2023.01.18.07.10.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jan 2023 07:10:08 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v6 10/17] arm64: dts: qcom: sm8150: Fix the base addresses of LLCC banks Date: Wed, 18 Jan 2023 20:38:57 +0530 Message-Id: <20230118150904.26913-11-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230118150904.26913-1-manivannan.sadhasivam@linaro.org> References: <20230118150904.26913-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index a0c57fb798d3..7fd2291b2638 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1762,8 +1762,11 @@ mmss_noc: interconnect@1740000 { system-cache-controller@9200000 { compatible = "qcom,sm8150-llcc"; - reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, + <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, + <0 0x09600000 0 0x50000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; interrupts = ; }; From patchwork Wed Jan 18 15:08:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 643741 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AAAF9C32793 for ; Wed, 18 Jan 2023 15:11:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231665AbjARPLj (ORCPT ); Wed, 18 Jan 2023 10:11:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42078 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231684AbjARPKU (ORCPT ); Wed, 18 Jan 2023 10:10:20 -0500 Received: from mail-pf1-x42b.google.com (mail-pf1-x42b.google.com [IPv6:2607:f8b0:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D3F2538EA5 for ; Wed, 18 Jan 2023 07:10:14 -0800 (PST) Received: by mail-pf1-x42b.google.com with SMTP id 207so10316178pfv.5 for ; Wed, 18 Jan 2023 07:10:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WYoJy3okzdnngL6TcLmeGykcAQcBXE1fb+mKXu1bB1c=; b=IQPIE/eXydmZ3f4OORjsxJU3PrDJNNWBD5X3faQZsETILHHrwW+fCkgS9LGofsk6L/ kg6ThppKwQ38Dzy095MzkDh+hzytj8rp1hLOn7YhbnwP2m0bvwGPlvIWRLeiJWTF+ElK M1vkwKc9Y8KjPB5l5yb7XrOATb3dnn1SQW9GiMqfT0oyqpOAPJywOh2sHvRp5ioG2yn9 1HjXoIpsY+WlRaTlSMwyT0RZoqtJIPrNUAkwWhfZ7Xtv0DaRmC+p44YjD+u90EvxQiXJ vNRv1cI+M7q6kgKfypF16XBMAE22IG0NHKKTDJX5zGJNuuA2N/IGN7JaIbkaWobi9Z3G RbHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WYoJy3okzdnngL6TcLmeGykcAQcBXE1fb+mKXu1bB1c=; b=3Isux/2/8t1hyTBkg+lEyPU4XAP5QF3m5j7CQ0umE/qOflMUmpQAru7aH+WNltDYHD PlN730ZZxF7EnCxQwrHAB1nS+3lwHqsOnvIfVNaAt2G8fUgmeMkSue+vAUE6zIy5yXc8 Nw/Wd6Z2FcxJhTxa7N7eX9FvT2rXRiKzMMnwQs8IPQIKaOBrMuhafIyu+fN9ltL+CBUk qYpPdsjsS6T5IHEcFMfdphhQ5dqcK4b3faQK7XaBNQ1/JumAnyJj9sphOXfB56PQ3nCO 3+pYbd9Q+c9irlq9Koh5FHmy/nLhNRZYbPf9gr67inXUEG1TMntitTIyD2WYI4tvcve4 mD0A== X-Gm-Message-State: AFqh2kqbfAVBjAt/AfeMXltwDzOVYM4f5pSmz2Xn9DLy72PrVhWy1GDR eSetpBR/Mq4lkyTrphwz8gMu X-Google-Smtp-Source: AMrXdXtgMsSHESMDsUTy6/2cPHBnkiBlkcscfB2U0QnjfKoDHaYmD4yfNA3PHoAYHvrGI8x9va/LFQ== X-Received: by 2002:a05:6a00:1887:b0:588:cb81:9274 with SMTP id x7-20020a056a00188700b00588cb819274mr11486900pfh.32.1674054614292; Wed, 18 Jan 2023 07:10:14 -0800 (PST) Received: from localhost.localdomain ([27.111.75.61]) by smtp.gmail.com with ESMTPSA id i15-20020aa796ef000000b0058d9623e7f1sm6721544pfq.73.2023.01.18.07.10.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jan 2023 07:10:13 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v6 11/17] arm64: dts: qcom: sm8250: Fix the base addresses of LLCC banks Date: Wed, 18 Jan 2023 20:38:58 +0530 Message-Id: <20230118150904.26913-12-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230118150904.26913-1-manivannan.sadhasivam@linaro.org> References: <20230118150904.26913-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index dab5579946f3..d1b65fb3f3f3 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3545,8 +3545,11 @@ usb_1_dwc3: usb@a600000 { system-cache-controller@9200000 { compatible = "qcom,sm8250-llcc"; - reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, + <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, + <0 0x09600000 0 0x50000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; }; usb_2: usb@a8f8800 { From patchwork Wed Jan 18 15:08:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 644229 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AEA70C32793 for ; Wed, 18 Jan 2023 15:12:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230323AbjARPMV (ORCPT ); Wed, 18 Jan 2023 10:12:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41920 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231740AbjARPK6 (ORCPT ); Wed, 18 Jan 2023 10:10:58 -0500 Received: from mail-pf1-x432.google.com (mail-pf1-x432.google.com [IPv6:2607:f8b0:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D37DC3A842 for ; Wed, 18 Jan 2023 07:10:20 -0800 (PST) Received: by mail-pf1-x432.google.com with SMTP id s3so23882651pfd.12 for ; Wed, 18 Jan 2023 07:10:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sMev9I+ZdryrTBjzJ8tiTgJp1UwzDLK7UbgCFoQvzyA=; b=M2Zt7BwlCbRUyzUpY0C8uW6kOyIgROzdxl18/wJqi7ZDLkX8RZyNuAyr+YNA3ksmio V45R3WJ5eJrllVq6ApMZjda0bSw3tD3wK6HWZ2YOkFwfbSwap/oi0+tjnQOpbws9b84P XxBbET5BM0uVyeJB4pbjHmmN1JN8ldeexZqyh3g1n+EpBLbf/Rtf3AvWCMwb+XJ++4X2 MTLNoIRkwKiq1ODJtjklt4MMK2b5tbZlG+L86DYsUUxS+zy+dbr62voqspwteMG95K9X qNg7bp0EGJbjZoBNwKeQ150qgHrqHEk8776bDe31wTK27B1x3Ko3iA3c5WQ/NDi2TZ/5 dhGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sMev9I+ZdryrTBjzJ8tiTgJp1UwzDLK7UbgCFoQvzyA=; b=S9wQZj3onVR47IfsfrILR4XYRuccKT+4lULRsriLVSXIpp5GCLN6B5agqGtFj/++8l jxbz1U3ezb0J+iWNK/1+eCQwUQRJ757Y79rAcOWVtcO625d88r8NWk+Ib60+qoE1sltz wfD4v7onAO22i6gY4f5+DoZ+ekjqi4Hn2tC4OC3rh2GlIzhz4bvo5LlFbuDIl7xFRJyW QkvW7bqwLYpZa5hXPbV8GzVjUwsftTequ1QXO5LTQV3CZigsEQTcY+v21JZaJ1M5wVAo wpUGNupGYcKghturibSb0Zxz+rNajidv7VpNdDZ/lUYA/TCZxiOIwgUrqKcVirFa4QvG Z+rA== X-Gm-Message-State: AFqh2kqFJTL+1eZ1XRNYTVc09LygRLmirE1Oj5FOrvXDpl9oO/syfT32 F70RAxGOioewfH4HEWYbbeNb X-Google-Smtp-Source: AMrXdXs4K3MwS+YLPgiGAPQ6/UgN+AoTZaYfW9Gxgyu1BTNK4z3gwlkRja+p8IA0kytToAo81UjcEg== X-Received: by 2002:a05:6a00:a27:b0:566:900d:a1de with SMTP id p39-20020a056a000a2700b00566900da1demr9592363pfh.26.1674054620187; Wed, 18 Jan 2023 07:10:20 -0800 (PST) Received: from localhost.localdomain ([27.111.75.61]) by smtp.gmail.com with ESMTPSA id i15-20020aa796ef000000b0058d9623e7f1sm6721544pfq.73.2023.01.18.07.10.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jan 2023 07:10:18 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v6 12/17] arm64: dts: qcom: sm8350: Fix the base addresses of LLCC banks Date: Wed, 18 Jan 2023 20:38:59 +0530 Message-Id: <20230118150904.26913-13-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230118150904.26913-1-manivannan.sadhasivam@linaro.org> References: <20230118150904.26913-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 245dce24ec59..836732d16635 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2513,8 +2513,11 @@ gem_noc: interconnect@9100000 { system-cache-controller@9200000 { compatible = "qcom,sm8350-llcc"; - reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, + <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, + <0 0x09600000 0 0x58000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; }; usb_1: usb@a6f8800 { From patchwork Wed Jan 18 15:09:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 643740 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5091AC38147 for ; Wed, 18 Jan 2023 15:12:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231782AbjARPMv (ORCPT ); Wed, 18 Jan 2023 10:12:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42076 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231791AbjARPLh (ORCPT ); Wed, 18 Jan 2023 10:11:37 -0500 Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 74A8D3F288 for ; Wed, 18 Jan 2023 07:10:26 -0800 (PST) Received: by mail-pj1-x102e.google.com with SMTP id q64so36067573pjq.4 for ; Wed, 18 Jan 2023 07:10:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=u6zR8ugZMMSbsUYzZxGLGG2mvpL7z7iHt3BZjr/IYFc=; b=KYHlJzqYB0S+TMh1QJwb46T/KhpPwcT8JN1cCEJBxOmCb9ejw8Zk+e+cZBbdB2WFgE wfOnPik0q9Hw2wbxUEGe7kxI/Z7WdP0wAjBxbX8rmcg36gAMEO1GfFz3ohLvzLTpH2tl ULbJQ0G4oQSJvt7sd1uLCAAgXQT9+vsQ/v0DiDni/R0YC2Xw0SNdVeLPrdGLARz8NKK5 HMhL6Ens6OC0f1B1QVLUo/cTIdixQH1788x7tCUs69jhWgJNHuN+DGoBIYIU5CdEsin+ c/UGlcL4TmwIjalSQaEJbPldm/oC/LGiTLBBubvytFov9+SWTj837d9bagC8nBp/87i2 5PNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=u6zR8ugZMMSbsUYzZxGLGG2mvpL7z7iHt3BZjr/IYFc=; b=cFQh7IrahSgbEuVnxN1aIEm3ZmsAMWBtmkAtqC/m08t2Eeok4fwJwnIY7Jf4UXACuD TDveA5u1pM6pyXWBEcwmE2LDgMWlepO8XPyacrHvLPVKNyywvPGOLq/CMidDYdKmdEHY Z1Efdn0n1KVK/5171fvh+lNvOiieuMbO92wOizkfWAZYFGfP0GFT0iWrA+B2EREeYhn4 6cHwazExGxF8FH0H37TzEcZS4RJ3zHRCztPjFcz/4GHmKpDj74bzZADW0ORvGXObKP5m WIGHP/9Bszxn6Gy3f+azW/g3iMa80tzhHiA4ZkgmDTKJ3l0odQVxb8ZBzGS30zdurglm DYPQ== X-Gm-Message-State: AFqh2kr25frj5qyugwS1Cii9oqjYFFUgYX37mU/GY13j/WtrPlwJ9Y8/ ZpKGnQFRA5aRlp3wX4E0BnQI X-Google-Smtp-Source: AMrXdXuoTYMbdhO1E/hIDv1s/NfWac9D2NnkXoBO9E1sFw5QSCw3wXsl9Gz4EmFoS4BQqssmEWhZSA== X-Received: by 2002:a05:6a20:be1d:b0:b8:7e6d:5b52 with SMTP id ge29-20020a056a20be1d00b000b87e6d5b52mr6614642pzb.38.1674054625604; Wed, 18 Jan 2023 07:10:25 -0800 (PST) Received: from localhost.localdomain ([27.111.75.61]) by smtp.gmail.com with ESMTPSA id i15-20020aa796ef000000b0058d9623e7f1sm6721544pfq.73.2023.01.18.07.10.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jan 2023 07:10:24 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v6 13/17] arm64: dts: qcom: sm8450: Fix the base addresses of LLCC banks Date: Wed, 18 Jan 2023 20:39:00 +0530 Message-Id: <20230118150904.26913-14-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230118150904.26913-1-manivannan.sadhasivam@linaro.org> References: <20230118150904.26913-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 570475040d95..12549a2912c6 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3640,8 +3640,11 @@ gem_noc: interconnect@19100000 { system-cache-controller@19200000 { compatible = "qcom,sm8450-llcc"; - reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>, + <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>, + <0 0x19a00000 0 0x80000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; interrupts = ; }; From patchwork Wed Jan 18 15:09:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 644228 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29248C32793 for ; Wed, 18 Jan 2023 15:13:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231714AbjARPNJ (ORCPT ); Wed, 18 Jan 2023 10:13:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45832 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231717AbjARPMV (ORCPT ); Wed, 18 Jan 2023 10:12:21 -0500 Received: from mail-pf1-x433.google.com (mail-pf1-x433.google.com [IPv6:2607:f8b0:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 46302458B5 for ; Wed, 18 Jan 2023 07:10:31 -0800 (PST) Received: by mail-pf1-x433.google.com with SMTP id x4so22264287pfj.1 for ; Wed, 18 Jan 2023 07:10:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=znASgBClq0rwhBOl4/Fw1c5T/s1foKbyxf4XPqRiKDI=; b=WNcEJPVHob+I5LkpCpds/u25pLXDuKLU13sQsuZ8KBFq26kQIcok8LXN7g7/Gkq5qi 9IyXPvPwKwP2zrabInA+cD2HLSM57cYWhP63aHKz8JE8tz48WX0BV0qIGEDFj7HlWiH9 uLt0DK8WfNX1EONBZAvo4vzPm8hRYhjeI+oqmOCAagCpSNXXQP27q04vQMqWeLOaxM7p C+ThtPZL5LOYKlUUjNWWiz3XLqgkSi0CLIVd4bSRcqXLjxyV1lPfZ3Z3/BR1GCjfraQX I68fd6iahaLc34gTFjd6Zl2UHiEUnJD90mqdC96jkSIQC9SIbpmrT/Z18xKQRyqhlICk jw5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=znASgBClq0rwhBOl4/Fw1c5T/s1foKbyxf4XPqRiKDI=; b=Q3pPh/Y+dMBFiXWJ890yRm7qPmtqntUTBc/Stjpx05IGYNCgBd6xhwTNmFKQO412h5 OoiZrxie9hxbhkG10dYpa0AxX5d/dhcBCE95VWNub/Jhdt0OWfPJEDx5hyfJBE41XknJ E07QAjTuQMZCQZab5ZpC6+mDGT89r8FFPWohhG2H9LcGavWo8alGH72grzus2nbiws55 6rTdMiv9iXTLXr1yN0I2nY9UC4PY1jyMTrQjUmKHM1fbB3TqqFiKTjeSee0y4ykKpeD/ F40MDSfPumL8ZTYxxV20bsArm6y6zVyFDL7A9qNagBplEh5Au57nx5kjRK4wwIgYx/DQ lyjw== X-Gm-Message-State: AFqh2koZIOCHr2sZgl7YllJ9ZSqbYA27Pk0nPq8HzOU1P1pRlhOK+U3O ryBdeRbvLxTkpedf7jgI8bW4 X-Google-Smtp-Source: AMrXdXsEh0cnadjqjItUJG/4Fm0w2vGQPPb7P8Y1iRppsvWrDTO5Amgm2TqRzvNQHBUehU+y+MpXuA== X-Received: by 2002:aa7:9204:0:b0:588:4739:9a23 with SMTP id 4-20020aa79204000000b0058847399a23mr6962640pfo.15.1674054631338; Wed, 18 Jan 2023 07:10:31 -0800 (PST) Received: from localhost.localdomain ([27.111.75.61]) by smtp.gmail.com with ESMTPSA id i15-20020aa796ef000000b0058d9623e7f1sm6721544pfq.73.2023.01.18.07.10.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jan 2023 07:10:30 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v6 14/17] arm64: dts: qcom: sm6350: Fix the base addresses of LLCC banks Date: Wed, 18 Jan 2023 20:39:01 +0530 Message-Id: <20230118150904.26913-15-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230118150904.26913-1-manivannan.sadhasivam@linaro.org> References: <20230118150904.26913-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. On SM6350, there is only one LLCC bank available. So let's just pass that as "llcc0_base". Reported-by: Parikshit Pareek Tested-by: Luca Weiss Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 43324bf291c3..c7701f5e4af6 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1174,7 +1174,7 @@ dc_noc: interconnect@9160000 { system-cache-controller@9200000 { compatible = "qcom,sm6350-llcc"; reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg-names = "llcc0_base", "llcc_broadcast_base"; }; gem_noc: interconnect@9680000 { From patchwork Wed Jan 18 15:09:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 643739 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 212E6C38147 for ; Wed, 18 Jan 2023 15:13:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231751AbjARPNq (ORCPT ); Wed, 18 Jan 2023 10:13:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42116 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231817AbjARPMf (ORCPT ); Wed, 18 Jan 2023 10:12:35 -0500 Received: from mail-pj1-x102b.google.com (mail-pj1-x102b.google.com [IPv6:2607:f8b0:4864:20::102b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6357A44BE5 for ; Wed, 18 Jan 2023 07:10:37 -0800 (PST) Received: by mail-pj1-x102b.google.com with SMTP id cx21-20020a17090afd9500b00228f2ecc6dbso2269949pjb.0 for ; Wed, 18 Jan 2023 07:10:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nUusDRy45tnE3HpdbouewJfbkC176V5vp9gS5W4zqOI=; b=mC//8Sq5Uo1MyoAqo1zbEadfDkDmj02pIYl6mTFbVAW+dfWy7iW0ayrVs6Cx45oIGJ 5IkccyBRtHPOWU/WXdjepaXTdKHOaXijv3i+ADEKFk7cUwKbuke4DqU+YgP9hXbAX3eD JIinc2mhacVgyqbLZ6AO5v6V4+Fys4HB+ud/DE40fjgO4WulmIRRCa7GdblLWa8B1MhM yZ4KH21CZ9UkLuDJd4SXwn/J3f+y2ttpCls+xnMBErMwcoKL7A9CmX/KeiHJDzN8fu0V s7w0xJio26DnLajylGBtbo0gfWnEFFMWiE9t8p6Marm77WgUcDOa/uEHKclk7dmuzZOy m2gQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nUusDRy45tnE3HpdbouewJfbkC176V5vp9gS5W4zqOI=; b=kvap77Gbr1x1QmJMkTw035yf3a7q55Nw/hA8Q5ZBmclLGj3+ufXYJwTsJYwmImvAox tcezmvMf3RBbtf9nOD5Yp7vrPGaT6bDGbzCS+PK+RWmDCtz3F+lXiGzgNkSoMJw35dqA IWe4A6vgQsEDZXc3DZmXLnkAufayk8aSq1cSQoNIA9iioNnVixv+mMr74z9cE20k7b9o 0mbY9bJeuYxq5B+7jsSYTWmyV4y8lk3w9PpKVM7xV7gSWG+jYEvpojTPoA1WMXa8K6ov wIP1IG/3RlwjdE/a8QMYR2Id1yF3/iyEUUd7vrUzSiK50sa8ZgYnhFWUO00qd6US998v 97cw== X-Gm-Message-State: AFqh2kq6Je97LQyDtHfbVA+R7WOcNRA1dgPXElEuNXntcMLo1lVOpUO5 TruznsBEjIYXIATqV2caJgMep7bOPRw9uLs= X-Google-Smtp-Source: AMrXdXu+MtoISKq+GP8C3LLZI1VCuURvKs3LObOkGwxViXnQl/5q7zu1KM3N/VXVK49UARuvhXnU0w== X-Received: by 2002:a05:6a20:8b0f:b0:af:ac38:911a with SMTP id l15-20020a056a208b0f00b000afac38911amr6831687pzh.59.1674054636913; Wed, 18 Jan 2023 07:10:36 -0800 (PST) Received: from localhost.localdomain ([27.111.75.61]) by smtp.gmail.com with ESMTPSA id i15-20020aa796ef000000b0058d9623e7f1sm6721544pfq.73.2023.01.18.07.10.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jan 2023 07:10:35 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v6 15/17] qcom: llcc/edac: Fix the base address used for accessing LLCC banks Date: Wed, 18 Jan 2023 20:39:02 +0530 Message-Id: <20230118150904.26913-16-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230118150904.26913-1-manivannan.sadhasivam@linaro.org> References: <20230118150904.26913-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The Qualcomm LLCC/EDAC drivers were using a fixed register stride for accessing the (Control and Status Registers) CSRs of each LLCC bank. This stride only works for some SoCs like SDM845 for which driver support was initially added. But the later SoCs use different register stride that vary between the banks with holes in-between. So it is not possible to use a single register stride for accessing the CSRs of each bank. By doing so could result in a crash. For fixing this issue, let's obtain the base address of each LLCC bank from devicetree and get rid of the fixed stride. This also means, there is no need to rely on reg-names property and the base addresses can be obtained using the index. First index is LLCC bank 0 and last index is LLCC broadcast. If the SoC supports more than one bank, then those need to be defined in devicetree for index from 1..N-1. Reported-by: Parikshit Pareek Tested-by: Luca Weiss Tested-by: Steev Klimaszewski # Thinkpad X13s Tested-by: Andrew Halaney # sa8540p-ride Reviewed-by: Borislav Petkov (AMD) Signed-off-by: Manivannan Sadhasivam --- drivers/edac/qcom_edac.c | 14 +++--- drivers/soc/qcom/llcc-qcom.c | 72 +++++++++++++++++------------- include/linux/soc/qcom/llcc-qcom.h | 6 +-- 3 files changed, 48 insertions(+), 44 deletions(-) diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c index 3256254c3722..1d3cc1930a74 100644 --- a/drivers/edac/qcom_edac.c +++ b/drivers/edac/qcom_edac.c @@ -213,7 +213,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type) for (i = 0; i < reg_data.reg_cnt; i++) { synd_reg = reg_data.synd_reg + (i * 4); - ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg, + ret = regmap_read(drv->regmaps[bank], synd_reg, &synd_val); if (ret) goto clear; @@ -222,8 +222,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type) reg_data.name, i, synd_val); } - ret = regmap_read(drv->regmap, - drv->offsets[bank] + reg_data.count_status_reg, + ret = regmap_read(drv->regmaps[bank], reg_data.count_status_reg, &err_cnt); if (ret) goto clear; @@ -233,8 +232,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type) edac_printk(KERN_CRIT, EDAC_LLCC, "%s: Error count: 0x%4x\n", reg_data.name, err_cnt); - ret = regmap_read(drv->regmap, - drv->offsets[bank] + reg_data.ways_status_reg, + ret = regmap_read(drv->regmaps[bank], reg_data.ways_status_reg, &err_ways); if (ret) goto clear; @@ -296,8 +294,7 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) /* Iterate over the banks and look for Tag RAM or Data RAM errors */ for (i = 0; i < drv->num_banks; i++) { - ret = regmap_read(drv->regmap, - drv->offsets[i] + DRP_INTERRUPT_STATUS, + ret = regmap_read(drv->regmaps[i], DRP_INTERRUPT_STATUS, &drp_error); if (!ret && (drp_error & SB_ECC_ERROR)) { @@ -312,8 +309,7 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) if (!ret) irq_rc = IRQ_HANDLED; - ret = regmap_read(drv->regmap, - drv->offsets[i] + TRP_INTERRUPT_0_STATUS, + ret = regmap_read(drv->regmaps[i], TRP_INTERRUPT_0_STATUS, &trp_error); if (!ret && (trp_error & SB_ECC_ERROR)) { diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 23ce2f78c4ed..72f3f2a9aaa0 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -62,8 +62,6 @@ #define LLCC_TRP_WRSC_CACHEABLE_EN 0x21f2c #define LLCC_TRP_ALGO_CFG8 0x21f30 -#define BANK_OFFSET_STRIDE 0x80000 - #define LLCC_VERSION_2_0_0_0 0x02000000 #define LLCC_VERSION_2_1_0_0 0x02010000 #define LLCC_VERSION_4_1_0_0 0x04010000 @@ -898,8 +896,8 @@ static int qcom_llcc_remove(struct platform_device *pdev) return 0; } -static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, - const char *name) +static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, u8 index, + const char *name) { void __iomem *base; struct regmap_config llcc_regmap_config = { @@ -909,7 +907,7 @@ static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, .fast_io = true, }; - base = devm_platform_ioremap_resource_byname(pdev, name); + base = devm_platform_ioremap_resource(pdev, index); if (IS_ERR(base)) return ERR_CAST(base); @@ -927,6 +925,7 @@ static int qcom_llcc_probe(struct platform_device *pdev) const struct llcc_slice_config *llcc_cfg; u32 sz; u32 version; + struct regmap *regmap; drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); if (!drv_data) { @@ -934,21 +933,51 @@ static int qcom_llcc_probe(struct platform_device *pdev) goto err; } - drv_data->regmap = qcom_llcc_init_mmio(pdev, "llcc_base"); - if (IS_ERR(drv_data->regmap)) { - ret = PTR_ERR(drv_data->regmap); + /* Initialize the first LLCC bank regmap */ + regmap = qcom_llcc_init_mmio(pdev, 0, "llcc0_base"); + if (IS_ERR(regmap)) { + ret = PTR_ERR(regmap); goto err; } - drv_data->bcast_regmap = - qcom_llcc_init_mmio(pdev, "llcc_broadcast_base"); + cfg = of_device_get_match_data(&pdev->dev); + + ret = regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], &num_banks); + if (ret) + goto err; + + num_banks &= LLCC_LB_CNT_MASK; + num_banks >>= LLCC_LB_CNT_SHIFT; + drv_data->num_banks = num_banks; + + drv_data->regmaps = devm_kcalloc(dev, num_banks, sizeof(*drv_data->regmaps), GFP_KERNEL); + if (!drv_data->regmaps) { + ret = -ENOMEM; + goto err; + } + + drv_data->regmaps[0] = regmap; + + /* Initialize rest of LLCC bank regmaps */ + for (i = 1; i < num_banks; i++) { + char *base = kasprintf(GFP_KERNEL, "llcc%d_base", i); + + drv_data->regmaps[i] = qcom_llcc_init_mmio(pdev, i, base); + if (IS_ERR(drv_data->regmaps[i])) { + ret = PTR_ERR(drv_data->regmaps[i]); + kfree(base); + goto err; + } + + kfree(base); + } + + drv_data->bcast_regmap = qcom_llcc_init_mmio(pdev, i, "llcc_broadcast_base"); if (IS_ERR(drv_data->bcast_regmap)) { ret = PTR_ERR(drv_data->bcast_regmap); goto err; } - cfg = of_device_get_match_data(&pdev->dev); - /* Extract version of the IP */ ret = regmap_read(drv_data->bcast_regmap, cfg->reg_offset[LLCC_COMMON_HW_INFO], &version); @@ -957,15 +986,6 @@ static int qcom_llcc_probe(struct platform_device *pdev) drv_data->version = version; - ret = regmap_read(drv_data->regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], - &num_banks); - if (ret) - goto err; - - num_banks &= LLCC_LB_CNT_MASK; - num_banks >>= LLCC_LB_CNT_SHIFT; - drv_data->num_banks = num_banks; - llcc_cfg = cfg->sct_data; sz = cfg->size; @@ -973,16 +993,6 @@ static int qcom_llcc_probe(struct platform_device *pdev) if (llcc_cfg[i].slice_id > drv_data->max_slices) drv_data->max_slices = llcc_cfg[i].slice_id; - drv_data->offsets = devm_kcalloc(dev, num_banks, sizeof(u32), - GFP_KERNEL); - if (!drv_data->offsets) { - ret = -ENOMEM; - goto err; - } - - for (i = 0; i < num_banks; i++) - drv_data->offsets[i] = i * BANK_OFFSET_STRIDE; - drv_data->bitmap = devm_bitmap_zalloc(dev, drv_data->max_slices, GFP_KERNEL); if (!drv_data->bitmap) { diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h index ad1fd718169d..423220e66026 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -120,7 +120,7 @@ struct llcc_edac_reg_offset { /** * struct llcc_drv_data - Data associated with the llcc driver - * @regmap: regmap associated with the llcc device + * @regmaps: regmaps associated with the llcc device * @bcast_regmap: regmap associated with llcc broadcast offset * @cfg: pointer to the data structure for slice configuration * @edac_reg_offset: Offset of the LLCC EDAC registers @@ -129,12 +129,11 @@ struct llcc_edac_reg_offset { * @max_slices: max slices as read from device tree * @num_banks: Number of llcc banks * @bitmap: Bit map to track the active slice ids - * @offsets: Pointer to the bank offsets array * @ecc_irq: interrupt for llcc cache error detection and reporting * @version: Indicates the LLCC version */ struct llcc_drv_data { - struct regmap *regmap; + struct regmap **regmaps; struct regmap *bcast_regmap; const struct llcc_slice_config *cfg; const struct llcc_edac_reg_offset *edac_reg_offset; @@ -143,7 +142,6 @@ struct llcc_drv_data { u32 max_slices; u32 num_banks; unsigned long *bitmap; - u32 *offsets; int ecc_irq; u32 version; }; From patchwork Wed Jan 18 15:09:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 644227 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4BBD3C32793 for ; Wed, 18 Jan 2023 15:14:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231770AbjARPOD (ORCPT ); Wed, 18 Jan 2023 10:14:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45826 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231678AbjARPM5 (ORCPT ); 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Wed, 18 Jan 2023 07:10:41 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v6 16/17] qcom: llcc/edac: Support polling mode for ECC handling Date: Wed, 18 Jan 2023 20:39:03 +0530 Message-Id: <20230118150904.26913-17-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230118150904.26913-1-manivannan.sadhasivam@linaro.org> References: <20230118150904.26913-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Not all Qcom platforms support IRQ mode for ECC handling. For those platforms, the current EDAC driver will not be probed due to missing ECC IRQ in devicetree. So add support for polling mode so that the EDAC driver can be used on all Qcom platforms supporting LLCC. The polling delay of 5000ms is chosen based on Qcom downstream/vendor driver. Reported-by: Luca Weiss Tested-by: Luca Weiss Tested-by: Steev Klimaszewski # Thinkpad X13s Tested-by: Andrew Halaney # sa8540p-ride Signed-off-by: Manivannan Sadhasivam Reviewed-by: Borislav Petkov (AMD) --- drivers/edac/qcom_edac.c | 50 +++++++++++++++++++++--------------- drivers/soc/qcom/llcc-qcom.c | 13 +++++----- 2 files changed, 35 insertions(+), 28 deletions(-) diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c index 1d3cc1930a74..265e0fb39bc7 100644 --- a/drivers/edac/qcom_edac.c +++ b/drivers/edac/qcom_edac.c @@ -76,6 +76,8 @@ #define DRP0_INTERRUPT_ENABLE BIT(6) #define SB_DB_DRP_INTERRUPT_ENABLE 0x3 +#define ECC_POLL_MSEC 5000 + enum { LLCC_DRAM_CE = 0, LLCC_DRAM_UE, @@ -283,8 +285,7 @@ dump_syn_reg(struct edac_device_ctl_info *edev_ctl, int err_type, u32 bank) return ret; } -static irqreturn_t -llcc_ecc_irq_handler(int irq, void *edev_ctl) +static irqreturn_t llcc_ecc_irq_handler(int irq, void *edev_ctl) { struct edac_device_ctl_info *edac_dev_ctl = edev_ctl; struct llcc_drv_data *drv = edac_dev_ctl->dev->platform_data; @@ -328,6 +329,11 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) return irq_rc; } +static void llcc_ecc_check(struct edac_device_ctl_info *edev_ctl) +{ + llcc_ecc_irq_handler(0, edev_ctl); +} + static int qcom_llcc_edac_probe(struct platform_device *pdev) { struct llcc_drv_data *llcc_driv_data = pdev->dev.platform_data; @@ -355,29 +361,31 @@ static int qcom_llcc_edac_probe(struct platform_device *pdev) edev_ctl->ctl_name = "llcc"; edev_ctl->panic_on_ue = LLCC_ERP_PANIC_ON_UE; - rc = edac_device_add_device(edev_ctl); - if (rc) - goto out_mem; - - platform_set_drvdata(pdev, edev_ctl); - - /* Request for ecc irq */ + /* Check if LLCC driver has passed ECC IRQ */ ecc_irq = llcc_driv_data->ecc_irq; - if (ecc_irq < 0) { - rc = -ENODEV; - goto out_dev; - } - rc = devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler, + if (ecc_irq > 0) { + /* Use interrupt mode if IRQ is available */ + rc = devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler, IRQF_TRIGGER_HIGH, "llcc_ecc", edev_ctl); - if (rc) - goto out_dev; + if (!rc) { + edac_op_state = EDAC_OPSTATE_INT; + goto irq_done; + } + } - return rc; + /* Fall back to polling mode otherwise */ + edev_ctl->poll_msec = ECC_POLL_MSEC; + edev_ctl->edac_check = llcc_ecc_check; + edac_op_state = EDAC_OPSTATE_POLL; -out_dev: - edac_device_del_device(edev_ctl->dev); -out_mem: - edac_device_free_ctl_info(edev_ctl); +irq_done: + rc = edac_device_add_device(edev_ctl); + if (rc) { + edac_device_free_ctl_info(edev_ctl); + return rc; + } + + platform_set_drvdata(pdev, edev_ctl); return rc; } diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 72f3f2a9aaa0..7b7c5a38bac6 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -1011,13 +1011,12 @@ static int qcom_llcc_probe(struct platform_device *pdev) goto err; drv_data->ecc_irq = platform_get_irq_optional(pdev, 0); - if (drv_data->ecc_irq >= 0) { - llcc_edac = platform_device_register_data(&pdev->dev, - "qcom_llcc_edac", -1, drv_data, - sizeof(*drv_data)); - if (IS_ERR(llcc_edac)) - dev_err(dev, "Failed to register llcc edac driver\n"); - } + + llcc_edac = platform_device_register_data(&pdev->dev, + "qcom_llcc_edac", -1, drv_data, + sizeof(*drv_data)); + if (IS_ERR(llcc_edac)) + dev_err(dev, "Failed to register llcc edac driver\n"); return 0; err: From patchwork Wed Jan 18 15:09:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 643738 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DAAB2C38147 for ; Wed, 18 Jan 2023 15:16:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230047AbjARPQj (ORCPT ); Wed, 18 Jan 2023 10:16:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48030 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231848AbjARPNV (ORCPT ); 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Wed, 18 Jan 2023 07:10:47 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH v6 17/17] soc: qcom: llcc: Do not create EDAC platform device on SDM845 Date: Wed, 18 Jan 2023 20:39:04 +0530 Message-Id: <20230118150904.26913-18-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230118150904.26913-1-manivannan.sadhasivam@linaro.org> References: <20230118150904.26913-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The platforms based on SDM845 SoC locks the access to EDAC registers in the bootloader. So probing the EDAC driver will result in a crash. Hence, disable the creation of EDAC platform device on all SDM845 devices. The issue has been observed on Lenovo Yoga C630 and DB845c. Cc: # 5.10 Reported-by: Steev Klimaszewski Signed-off-by: Manivannan Sadhasivam --- drivers/soc/qcom/llcc-qcom.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 7b7c5a38bac6..8d840702df50 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -1012,11 +1012,18 @@ static int qcom_llcc_probe(struct platform_device *pdev) drv_data->ecc_irq = platform_get_irq_optional(pdev, 0); - llcc_edac = platform_device_register_data(&pdev->dev, - "qcom_llcc_edac", -1, drv_data, - sizeof(*drv_data)); - if (IS_ERR(llcc_edac)) - dev_err(dev, "Failed to register llcc edac driver\n"); + /* + * The platforms based on SDM845 SoC locks the access to EDAC registers + * in bootloader. So probing the EDAC driver will result in a crash. + * Hence, disable the creation of EDAC platform device on SDM845. + */ + if (!of_device_is_compatible(dev->of_node, "qcom,sdm845-llcc")) { + llcc_edac = platform_device_register_data(&pdev->dev, + "qcom_llcc_edac", -1, drv_data, + sizeof(*drv_data)); + if (IS_ERR(llcc_edac)) + dev_err(dev, "Failed to register llcc edac driver\n"); + } return 0; err: