From patchwork Tue Jan 17 12:02:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 643524 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EAFBBC677F1 for ; Tue, 17 Jan 2023 12:02:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236596AbjAQMCh (ORCPT ); Tue, 17 Jan 2023 07:02:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40726 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236559AbjAQMCf (ORCPT ); Tue, 17 Jan 2023 07:02:35 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 224DA367F8; Tue, 17 Jan 2023 04:02:34 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id CF3B3B80FCD; Tue, 17 Jan 2023 12:02:32 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 24975C43396; Tue, 17 Jan 2023 12:02:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1673956951; bh=oAmv+7J3+twigmZ0NIC+hHJExAy7piy+7Wg0lwkNj/w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BHopN3xTY9bClPaHeQy577Gzy0cqL/KUpUnVPNp/Bngna0rDUF0Y0a33ZvNQ7hGsw +68qi1pQhyMMW6+DrtuRpPfHxYnbV+f615t6UJSAlCcyCQR66NotuCPdhBF2PrG2Vw DUkRnzNIooQMyKuZUFiLShDb4Jq8ybHBXMPj2z6mxGqZoAIXPxfueXcOblTXgknyr5 xDVMxxiO3Bzi2NnjIRzJZVJ4RUYLVCESSe7Z8bCvxWCQRgBK90UpoBskzUrn24PWPZ KaeGWeBQNWjsfMvBdgxyTHgugzFAs1+H3IhogB2fG4qmiGKExQKOfH5RV5deagUibT BHK8hnzu8Ifhw== From: rfoss@kernel.org To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Foss Subject: [PATCH v1 1/3] arm64: dts: qcom: sm8350: Add display system nodes Date: Tue, 17 Jan 2023 13:02:21 +0100 Message-Id: <20230117120223.1055225-2-rfoss@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230117120223.1055225-1-rfoss@kernel.org> References: <20230117120223.1055225-1-rfoss@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Robert Foss Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these nodes the display subsystem is configured to support one DSI output. Signed-off-by: Robert Foss --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 297 ++++++++++++++++++++++++++- 1 file changed, 293 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index fafd92edc855..c78cdaa4adcb 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2020, Linaro Limited */ +#include #include #include #include @@ -2620,14 +2621,302 @@ usb_2_dwc3: usb@a800000 { }; }; + mdss: display-subsystem@ae00000 { + compatible = "qcom,sm8350-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + power-domains = <&dispcc MDSS_GDSC>; + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "nrt_bus", "core"; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x820 0x402>; + + status = "disabled"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* TODO: opp-200000000 should work with + * &rpmhpd_opp_low_svs, but one some of + * sm8350_hdk boards reboot using this + * opp. + */ + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-345000000 { + opp-hz = /bits/ 64 <345000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-460000000 { + opp-hz = /bits/ 64 <460000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,sm8350-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&dpu_opp_table>; + power-domains = <&rpmhpd SM8350_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&dsi0_opp_table>; + power-domains = <&rpmhpd SM8350_MMCX>; + + phys = <&mdss_dsi0_phy>; + + status = "disabled"; + + dsi0_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* TODO: opp-187500000 should work with + * &rpmhpd_opp_low_svs, but one some of + * sm8350_hdk boards reboot using this + * opp. + */ + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible = "qcom,dsi-phy-5nm-8350"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94900 0 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + mdss_dsi1: dsi@ae96000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae96000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>; + + operating-points-v2 = <&dsi1_opp_table>; + power-domains = <&rpmhpd SM8350_MMCX>; + + phys = <&mdss_dsi1_phy>; + + status = "disabled"; + + dsi1_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* TODO: opp-187500000 should work with + * &rpmhpd_opp_low_svs, but one some of + * sm8350_hdk boards reboot using this + * opp. + */ + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae96400 { + compatible = "qcom,dsi-phy-5nm-8350"; + reg = <0 0x0ae96400 0 0x200>, + <0 0x0ae96600 0 0x280>, + <0 0x0ae96900 0 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + }; + dispcc: clock-controller@af00000 { compatible = "qcom,sm8350-dispcc"; reg = <0 0x0af00000 0 0x10000>; clocks = <&rpmhcc RPMH_CXO_CLK>, - <0>, - <0>, - <0>, - <0>, + <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, + <0>, <0>, <0>, <0>; clock-names = "bi_tcxo", From patchwork Tue Jan 17 12:02:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 643835 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CAE72C678D8 for ; Tue, 17 Jan 2023 12:02:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236640AbjAQMCi (ORCPT ); Tue, 17 Jan 2023 07:02:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40732 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236590AbjAQMCf (ORCPT ); Tue, 17 Jan 2023 07:02:35 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5C8C9367FE; Tue, 17 Jan 2023 04:02:35 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id C4AA7612FA; Tue, 17 Jan 2023 12:02:34 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id ED6EAC433F2; Tue, 17 Jan 2023 12:02:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1673956954; bh=+Mmt7JDeLyWJF/zymxG1lOMckzw5H7Yj1D+CR+uParw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LWN1FhuzUlc0Acx4UA9z0dzAs4DftQbFLVIwagkih24eXlO7qYCc9aOIC6mleDu/m vrRaaHDpkn7UmVPdemhrPuPm5MzJIpHEsVk8TiUgPA0zkE3Wh4ufwLbwvaj3hCVkmW bxfA4yCOefR/g0zQKIoO7jYoyFXlJo/BpthkRSdBT+yTgejeb0ARD5zJnzRSDUi1yN hmvd6v4QOrKLXQaqqZ6tkLD/o4mBv9/ppRlXEZwVavvcVORdhcsRrk7AHQGP7lYeA4 NkXccrdSALRHr4a1zr0fSD6CORcqpYES/Vlk9aLJ7bLfZ6XHC/b3HIenKnZ5ef+t6H AyvskoDbBx8DQ== From: rfoss@kernel.org To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Foss Subject: [PATCH v1 2/3] arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes Date: Tue, 17 Jan 2023 13:02:22 +0100 Message-Id: <20230117120223.1055225-3-rfoss@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230117120223.1055225-1-rfoss@kernel.org> References: <20230117120223.1055225-1-rfoss@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Robert Foss Enable the display subsystem and the dsi0 output for the sm8350-hdk board. Signed-off-by: Robert Foss --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index 26a608144886..7878f42e9378 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -221,10 +221,32 @@ &cdsp { firmware-name = "qcom/sm8350/cdsp.mbn"; }; +&dispcc { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l6b_1p2>; + status = "okay"; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l5b_0p88>; + status = "okay"; +}; + &gpi_dma1 { status = "okay"; }; +&mdss { + status = "okay"; +}; + +&mdss_mdp { + status = "okay"; +}; + &mpss { status = "okay"; firmware-name = "qcom/sm8350/modem.mbn"; From patchwork Tue Jan 17 12:02:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 643523 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9087CC3DA78 for ; Tue, 17 Jan 2023 12:02:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236395AbjAQMCz (ORCPT ); Tue, 17 Jan 2023 07:02:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40890 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236798AbjAQMCt (ORCPT ); Tue, 17 Jan 2023 07:02:49 -0500 Received: from sin.source.kernel.org (sin.source.kernel.org [IPv6:2604:1380:40e1:4800::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CD37D36B0A; Tue, 17 Jan 2023 04:02:40 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id E9A7ACE1689; Tue, 17 Jan 2023 12:02:38 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B38C4C43392; Tue, 17 Jan 2023 12:02:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1673956957; bh=b7leQCJ1hzDEzhNOIaU0dSmiOnzI32jbZ622PnNwXdY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bcY3G8vVPQeY2fnf2OCPlwfgh+M8N0byJRF+mzSvpvUtYlMKcCI/El+kpsRQuDvVF GMl5/BgB1e685aQQ2aYz1oGqQLLJ9a+c37UhPX609007dt9wSa44PMFM8yOqgbCWjU lAS3TGRBgHLftnUbgDdNjIAB+mkIKFN8egkxykWwHW7phAY/CsXxeZ6cErATNRjbSk ZBB05wHYkKSKjXqbQFbp+xN6s5KzvJjGXX/LdFi893Pa1pKFMkgHUvUdqtPoV1ni+5 S9rb4VVDN98KaYUs6313c3/2I3ukqXhaumclPDn4WjzCp+Thh+UTptD2rja5CAolpg n+V7NvD3wefkQ== From: rfoss@kernel.org To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Foss Subject: [PATCH v1 3/3] arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge Date: Tue, 17 Jan 2023 13:02:23 +0100 Message-Id: <20230117120223.1055225-4-rfoss@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230117120223.1055225-1-rfoss@kernel.org> References: <20230117120223.1055225-1-rfoss@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Robert Foss The sm8350-hdk ships with the LT9611 UXC DSI/HDMI bridge chip. In order to toggle the board to enable the HDMI output, switch #7 & #8 on the rightmost multi-switch package have to be toggled to On. Signed-off-by: Robert Foss --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 105 ++++++++++++++++++++++++ 1 file changed, 105 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index 7878f42e9378..49ff3033c120 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -20,6 +20,17 @@ chosen { stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <<9611_out>; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -29,6 +40,31 @@ vph_pwr: vph-pwr-regulator { regulator-always-on; regulator-boot-on; }; + + lt9611_1v2: lt9611-1v2-regulator { + compatible = "regulator-fixed"; + regulator-name = "LT9611_1V2"; + + vin-supply = <&vph_pwr>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&tlmm 49 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; + + lt9611_3v3: lt9611-3v3-regulator { + compatible = "regulator-fixed"; + regulator-name = "LT9611_3V3"; + + vin-supply = <&vreg_bob>; + gpio = <&tlmm 47 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + }; }; &adsp { @@ -228,6 +264,15 @@ &dispcc { &mdss_dsi0 { vdda-supply = <&vreg_l6b_1p2>; status = "okay"; + + ports { + port@1 { + endpoint { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; + }; + }; + }; }; &mdss_dsi0_phy { @@ -239,6 +284,46 @@ &gpi_dma1 { status = "okay"; }; +&i2c15 { + clock-frequency = <400000>; + status = "okay"; + + lt9611_codec: hdmi-bridge@2b { + compatible = "lontium,lt9611uxc"; + reg = <0x2b>; + + interrupts-extended = <&tlmm 50 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>; + + vdd-supply = <<9611_1v2>; + vcc-supply = <<9611_3v3>; + + pinctrl-names = "default"; + pinctrl-0 = <<9611_state>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt9611_a: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@2 { + reg = <2>; + + lt9611_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + &mdss { status = "okay"; }; @@ -256,6 +341,10 @@ &qupv3_id_0 { status = "okay"; }; +&qupv3_id_2 { + status = "okay"; +}; + &slpi { status = "okay"; firmware-name = "qcom/sm8350/slpi.mbn"; @@ -347,4 +436,20 @@ usb_hub_enabled_state: usb-hub-enabled-state { drive-strength = <2>; output-low; }; + + lt9611_state: lt9611-state { + rst { + pins = "gpio48"; + function = "normal"; + + output-high; + input-disable; + }; + + irq { + pins = "gpio50"; + function = "gpio"; + bias-disable; + }; + }; };