From patchwork Fri Jan 13 06:40:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moudy Ho X-Patchwork-Id: 642848 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 340AEC54EBE for ; Fri, 13 Jan 2023 06:57:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240674AbjAMG5G (ORCPT ); Fri, 13 Jan 2023 01:57:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56880 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240722AbjAMGzv (ORCPT ); Fri, 13 Jan 2023 01:55:51 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7F5F471887; Thu, 12 Jan 2023 22:41:11 -0800 (PST) X-UUID: 42477e90930d11eda06fc9ecc4dadd91-20230113 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=8k9F/t2cGOgm7cgze3tgM/N3f5OW0K5CP5YZeJ76/Ok=; b=lXUBGSd55VTQxheE2ayM/JyvbAG+XUFis+WdwAZxCGq3SxpB/l3WEsF+Zc7hFrioKArm6OoCopv8a2xM26Uk7oHyWQb0oTd0x2fnVBI4v9H0NCiLi+0DMnN/pcWrMNbI585vHGT49vPWhlgruPL3QHRWFLKN6qRLuUTPtxjAqDM=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.17, REQID:35a1f78c-84d3-4cec-9f6b-1bfa1dc6d2ed, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:543e81c, CLOUDID:611d278c-8530-4eff-9f77-222cf6e2895b, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0 X-CID-BVR: 0,NGT X-UUID: 42477e90930d11eda06fc9ecc4dadd91-20230113 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1888787520; Fri, 13 Jan 2023 14:41:07 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Fri, 13 Jan 2023 14:41:06 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Fri, 13 Jan 2023 14:41:06 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Matthias Brugger , Hans Verkuil CC: Chun-Kuang Hu , , , , , Moudy Ho Subject: [PATCH v5 01/12] media: platform: mtk-mdp3: fix potential frame size overflow in mdp_try_fmt_mplane() Date: Fri, 13 Jan 2023 14:40:53 +0800 Message-ID: <20230113064104.22402-2-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230113064104.22402-1-moudy.ho@mediatek.com> References: <20230113064104.22402-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Fix overflow risk when setting certain formats whose frame size exceeds a RGB24 with 7723x7723 resolution. For example, a 7723x7724 RGB24 frame: 1. bpl (byte per line) = 7723 * 3. 2. Overflow occurs when bpl * 7724 * depth. Fixes: 61890ccaefaf ("media: platform: mtk-mdp3: add MediaTek MDP3 driver") Signed-off-by: Moudy Ho --- drivers/media/platform/mediatek/mdp3/mtk-mdp3-regs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-regs.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-regs.c index 4e84a37ecdfc..c63bd5e479e0 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-regs.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-regs.c @@ -432,9 +432,9 @@ const struct mdp_format *mdp_try_fmt_mplane(struct v4l2_format *f, bpl = clamp(bpl, min_bpl, max_bpl); pix_mp->plane_fmt[i].bytesperline = bpl; - min_si = (bpl * pix_mp->height * fmt->depth[i]) / + min_si = ((u64)bpl * pix_mp->height * fmt->depth[i]) / fmt->row_depth[i]; - max_si = (bpl * s.max_height * fmt->depth[i]) / + max_si = ((u64)bpl * s.max_height * fmt->depth[i]) / fmt->row_depth[i]; si = clamp(si, min_si, max_si); From patchwork Fri Jan 13 06:40:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moudy Ho X-Patchwork-Id: 642852 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C198DC61DB3 for ; Fri, 13 Jan 2023 06:56:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240947AbjAMG4v (ORCPT ); Fri, 13 Jan 2023 01:56:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59746 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240194AbjAMG4G (ORCPT ); Fri, 13 Jan 2023 01:56:06 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B2E516F969; Thu, 12 Jan 2023 22:41:14 -0800 (PST) X-UUID: 427a2cfa930d11eda06fc9ecc4dadd91-20230113 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=4lIPVj72cYKbyxaYWWK3/uUU6T9Hb1zZuzlNN142SOU=; b=sX4UwxW0SfV5dZbAso5mTgQHzziofPTxZeqAbE5nOEBnXUAFQT+X1IzF16UR0gcNH+NWd0XCWKTuo+VG7O8iFP23oenBXaLR72K3YWTgfP6uqYkOVU6yznM5lRZd9px6WD2T+p6nOisFMhgoWO5VvL1LhbKPRxkl445jBlOMgwA=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.17, REQID:b0456c2b-e52b-4f11-80e8-a846a8782b38, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:95 X-CID-INFO: VERSION:1.1.17, REQID:b0456c2b-e52b-4f11-80e8-a846a8782b38, IP:0, URL :0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTION :quarantine,TS:95 X-CID-META: VersionHash:543e81c, CLOUDID:e01d278c-8530-4eff-9f77-222cf6e2895b, B ulkID:230113144110OZVA7G89,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OS I:0,OSA:0 X-CID-APTURL: Status:success,Category:nil,Trust:0,Unknown:0,Malicious:0 X-CID-BVR: 0 X-UUID: 427a2cfa930d11eda06fc9ecc4dadd91-20230113 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1903751245; Fri, 13 Jan 2023 14:41:07 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Fri, 13 Jan 2023 14:41:06 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Fri, 13 Jan 2023 14:41:06 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Matthias Brugger , Hans Verkuil CC: Chun-Kuang Hu , , , , , Moudy Ho Subject: [PATCH v5 03/12] media: platform: mtk-mdp3: chip config split about component settings Date: Fri, 13 Jan 2023 14:40:55 +0800 Message-ID: <20230113064104.22402-4-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230113064104.22402-1-moudy.ho@mediatek.com> References: <20230113064104.22402-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org For different chips, different types and numbers of components are configured in the MDP to achieve the desired application, which will cause ID compatibility problems in the same driver. Subdivide the component ID into two kinds: 1. public_id (compatible with other chips) 2. inner_id (what the current chip actually owns) In addition, the chip configuration related structures of the component are integrated and moved into the header file. Signed-off-by: Moudy Ho --- .../mediatek/mdp3/mt8183/mdp3-plat-mt8183.h | 112 ++++++++++++++ .../platform/mediatek/mdp3/mtk-mdp3-cmdq.c | 4 +- .../platform/mediatek/mdp3/mtk-mdp3-comp.c | 146 +++++++++--------- .../platform/mediatek/mdp3/mtk-mdp3-comp.h | 24 ++- .../platform/mediatek/mdp3/mtk-mdp3-core.c | 2 + .../platform/mediatek/mdp3/mtk-mdp3-core.h | 2 + 6 files changed, 216 insertions(+), 74 deletions(-) diff --git a/drivers/media/platform/mediatek/mdp3/mt8183/mdp3-plat-mt8183.h b/drivers/media/platform/mediatek/mdp3/mt8183/mdp3-plat-mt8183.h index 3084f62e7df5..81fb80ec8ac2 100644 --- a/drivers/media/platform/mediatek/mdp3/mt8183/mdp3-plat-mt8183.h +++ b/drivers/media/platform/mediatek/mdp3/mt8183/mdp3-plat-mt8183.h @@ -32,4 +32,116 @@ static const u32 mt8183_mutex_idx[MDP_MAX_COMP_COUNT] = { [MDP_COMP_CCORR0] = MUTEX_MOD_IDX_MDP_CCORR0, }; +enum mt8183_mdp_comp_id { + /* MT8183 Comp id */ + /* ISP */ + MT8183_MDP_COMP_WPEI = 0, + MT8183_MDP_COMP_WPEO, /* 1 */ + MT8183_MDP_COMP_WPEI2, /* 2 */ + MT8183_MDP_COMP_WPEO2, /* 3 */ + MT8183_MDP_COMP_ISP_IMGI, /* 4 */ + MT8183_MDP_COMP_ISP_IMGO, /* 5 */ + MT8183_MDP_COMP_ISP_IMG2O, /* 6 */ + + /* IPU */ + MT8183_MDP_COMP_IPUI, /* 7 */ + MT8183_MDP_COMP_IPUO, /* 8 */ + + /* MDP */ + MT8183_MDP_COMP_CAMIN, /* 9 */ + MT8183_MDP_COMP_CAMIN2, /* 10 */ + MT8183_MDP_COMP_RDMA0, /* 11 */ + MT8183_MDP_COMP_AAL0, /* 12 */ + MT8183_MDP_COMP_CCORR0, /* 13 */ + MT8183_MDP_COMP_RSZ0, /* 14 */ + MT8183_MDP_COMP_RSZ1, /* 15 */ + MT8183_MDP_COMP_TDSHP0, /* 16 */ + MT8183_MDP_COMP_COLOR0, /* 17 */ + MT8183_MDP_COMP_PATH0_SOUT, /* 18 */ + MT8183_MDP_COMP_PATH1_SOUT, /* 19 */ + MT8183_MDP_COMP_WROT0, /* 20 */ + MT8183_MDP_COMP_WDMA, /* 21 */ + + /* Dummy Engine */ + MT8183_MDP_COMP_RDMA1, /* 22 */ + MT8183_MDP_COMP_RSZ2, /* 23 */ + MT8183_MDP_COMP_TDSHP1, /* 24 */ + MT8183_MDP_COMP_WROT1, /* 25 */ +}; + +static const struct mdp_comp_data mt8183_mdp_comp_data[MDP_MAX_COMP_COUNT] = { + [MDP_COMP_WPEI] = { + {MDP_COMP_TYPE_WPEI, 0, MT8183_MDP_COMP_WPEI}, + {0, 0, 0} + }, + [MDP_COMP_WPEO] = { + {MDP_COMP_TYPE_EXTO, 2, MT8183_MDP_COMP_WPEO}, + {0, 0, 0} + }, + [MDP_COMP_WPEI2] = { + {MDP_COMP_TYPE_WPEI, 1, MT8183_MDP_COMP_WPEI2}, + {0, 0, 0} + }, + [MDP_COMP_WPEO2] = { + {MDP_COMP_TYPE_EXTO, 3, MT8183_MDP_COMP_WPEO2}, + {0, 0, 0} + }, + [MDP_COMP_ISP_IMGI] = { + {MDP_COMP_TYPE_IMGI, 0, MT8183_MDP_COMP_ISP_IMGI}, + {0, 0, 4} + }, + [MDP_COMP_ISP_IMGO] = { + {MDP_COMP_TYPE_EXTO, 0, MT8183_MDP_COMP_ISP_IMGO}, + {0, 0, 4} + }, + [MDP_COMP_ISP_IMG2O] = { + {MDP_COMP_TYPE_EXTO, 1, MT8183_MDP_COMP_ISP_IMG2O}, + {0, 0, 0} + }, + [MDP_COMP_CAMIN] = { + {MDP_COMP_TYPE_DL_PATH, 0, MT8183_MDP_COMP_CAMIN}, + {2, 2, 1} + }, + [MDP_COMP_CAMIN2] = { + {MDP_COMP_TYPE_DL_PATH, 1, MT8183_MDP_COMP_CAMIN2}, + {2, 4, 1} + }, + [MDP_COMP_RDMA0] = { + {MDP_COMP_TYPE_RDMA, 0, MT8183_MDP_COMP_RDMA0}, + {2, 0, 0} + }, + [MDP_COMP_CCORR0] = { + {MDP_COMP_TYPE_CCORR, 0, MT8183_MDP_COMP_CCORR0}, + {1, 0, 0} + }, + [MDP_COMP_RSZ0] = { + {MDP_COMP_TYPE_RSZ, 0, MT8183_MDP_COMP_RSZ0}, + {1, 0, 0} + }, + [MDP_COMP_RSZ1] = { + {MDP_COMP_TYPE_RSZ, 1, MT8183_MDP_COMP_RSZ1}, + {1, 0, 0} + }, + [MDP_COMP_TDSHP0] = { + {MDP_COMP_TYPE_TDSHP, 0, MT8183_MDP_COMP_TDSHP0}, + {0, 0, 0} + }, + [MDP_COMP_PATH0_SOUT] = { + {MDP_COMP_TYPE_PATH, 0, MT8183_MDP_COMP_PATH0_SOUT}, + {0, 0, 0} + }, + [MDP_COMP_PATH1_SOUT] = { + {MDP_COMP_TYPE_PATH, 1, MT8183_MDP_COMP_PATH1_SOUT}, + {0, 0, 0} + }, + [MDP_COMP_WROT0] = { + {MDP_COMP_TYPE_WROT, 0, MT8183_MDP_COMP_WROT0}, + {1, 0, 0} + }, + [MDP_COMP_WDMA] = { + {MDP_COMP_TYPE_WDMA, 0, MT8183_MDP_COMP_WDMA}, + {1, 0, 0} + }, +}; + #endif /* __MDP3_PLAT_MT8183_H__ */ diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c index 124c1b96e96b..dcd77f65b0e3 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c @@ -48,7 +48,7 @@ static int mdp_path_subfrm_require(const struct mdp_path *path, int id, index; /* Decide which mutex to use based on the current pipeline */ - switch (path->comps[0].comp->id) { + switch (path->comps[0].comp->public_id) { case MDP_COMP_RDMA0: *mutex_id = MDP_PIPE_RDMA0; break; @@ -71,7 +71,7 @@ static int mdp_path_subfrm_require(const struct mdp_path *path, ctx = &path->comps[index]; if (is_output_disabled(ctx->param, count)) continue; - id = ctx->comp->id; + id = ctx->comp->public_id; mtk_mutex_write_mod(mutex[*mutex_id], data->mdp_mutex_table_idx[id], false); } diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c index 7bc05f42a23c..1ac9c46e27d4 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c @@ -29,15 +29,51 @@ __get_plat_cfg(const struct mdp_comp_ctx *ctx) return ctx->comp->mdp_dev->mdp_data->mdp_cfg; } +s32 get_comp_inner_id(struct mdp_dev *mdp_dev, enum mtk_mdp_comp_id id) +{ + if (!mdp_dev) + return MDP_COMP_NONE; + if (id <= MDP_COMP_NONE || id >= MDP_MAX_COMP_COUNT) + return MDP_COMP_NONE; + + return mdp_dev->mdp_data->comp_data[id].match.inner_id; +} + +enum mtk_mdp_comp_id get_comp_public_id(struct mdp_dev *mdp_dev, s32 inner_id) +{ + enum mtk_mdp_comp_id public_id = MDP_COMP_NONE; + u32 i; + + if (IS_ERR(mdp_dev) || !inner_id) + goto err_public_id; + + for (i = 0; i < MDP_MAX_COMP_COUNT; i++) { + if (mdp_dev->mdp_data->comp_data[i].match.inner_id == inner_id) { + public_id = i; + return public_id; + } + } + +err_public_id: + dev_err(&mdp_dev->pdev->dev, "Unmapped inner id %d", inner_id); + return public_id; +} + static s64 get_comp_flag(const struct mdp_comp_ctx *ctx) { const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx); + u32 rdma0, rsz1; + + rdma0 = get_comp_inner_id(ctx->comp->mdp_dev, MDP_COMP_RDMA0); + rsz1 = get_comp_inner_id(ctx->comp->mdp_dev, MDP_COMP_RSZ1); + if (!rdma0 || !rsz1) + return MDP_COMP_NONE; if (mdp_cfg && mdp_cfg->rdma_rsz1_sram_sharing) - if (ctx->comp->id == MDP_COMP_RDMA0) - return BIT(MDP_COMP_RDMA0) | BIT(MDP_COMP_RSZ1); + if (ctx->comp->inner_id == rdma0) + return BIT(rdma0) | BIT(rsz1); - return BIT(ctx->comp->id); + return BIT(ctx->comp->inner_id); } static int init_rdma(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) @@ -45,12 +81,17 @@ static int init_rdma(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx); phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; + s32 rdma0; + + rdma0 = get_comp_inner_id(ctx->comp->mdp_dev, MDP_COMP_RDMA0); + if (!rdma0) + return -EINVAL; if (mdp_cfg && mdp_cfg->rdma_support_10bit) { struct mdp_comp *prz1 = ctx->comp->mdp_dev->comp[MDP_COMP_RSZ1]; /* Disable RSZ1 */ - if (ctx->comp->id == MDP_COMP_RDMA0 && prz1) + if (ctx->comp->inner_id == rdma0 && prz1) MM_REG_WRITE(cmd, subsys_id, prz1->reg_base, PRZ_ENABLE, 0x0, BIT(0)); } @@ -578,32 +619,6 @@ static const struct mdp_comp_ops *mdp_comp_ops[MDP_COMP_TYPE_COUNT] = { [MDP_COMP_TYPE_CCORR] = &ccorr_ops, }; -struct mdp_comp_match { - enum mdp_comp_type type; - u32 alias_id; -}; - -static const struct mdp_comp_match mdp_comp_matches[MDP_MAX_COMP_COUNT] = { - [MDP_COMP_WPEI] = { MDP_COMP_TYPE_WPEI, 0 }, - [MDP_COMP_WPEO] = { MDP_COMP_TYPE_EXTO, 2 }, - [MDP_COMP_WPEI2] = { MDP_COMP_TYPE_WPEI, 1 }, - [MDP_COMP_WPEO2] = { MDP_COMP_TYPE_EXTO, 3 }, - [MDP_COMP_ISP_IMGI] = { MDP_COMP_TYPE_IMGI, 0 }, - [MDP_COMP_ISP_IMGO] = { MDP_COMP_TYPE_EXTO, 0 }, - [MDP_COMP_ISP_IMG2O] = { MDP_COMP_TYPE_EXTO, 1 }, - - [MDP_COMP_CAMIN] = { MDP_COMP_TYPE_DL_PATH, 0 }, - [MDP_COMP_CAMIN2] = { MDP_COMP_TYPE_DL_PATH, 1 }, - [MDP_COMP_RDMA0] = { MDP_COMP_TYPE_RDMA, 0 }, - [MDP_COMP_CCORR0] = { MDP_COMP_TYPE_CCORR, 0 }, - [MDP_COMP_RSZ0] = { MDP_COMP_TYPE_RSZ, 0 }, - [MDP_COMP_RSZ1] = { MDP_COMP_TYPE_RSZ, 1 }, - [MDP_COMP_PATH0_SOUT] = { MDP_COMP_TYPE_PATH, 0 }, - [MDP_COMP_PATH1_SOUT] = { MDP_COMP_TYPE_PATH, 1 }, - [MDP_COMP_WROT0] = { MDP_COMP_TYPE_WROT, 0 }, - [MDP_COMP_WDMA] = { MDP_COMP_TYPE_WDMA, 0 }, -}; - static const struct of_device_id mdp_comp_dt_ids[] = { { .compatible = "mediatek,mt8183-mdp3-rdma", @@ -635,21 +650,6 @@ static const struct of_device_id mdp_sub_comp_dt_ids[] = { {} }; -/* Used to describe the item order in MDP property */ -struct mdp_comp_info { - u32 clk_num; - u32 clk_ofst; - u32 dts_reg_ofst; -}; - -static const struct mdp_comp_info mdp_comp_dt_info[MDP_MAX_COMP_COUNT] = { - [MDP_COMP_RDMA0] = {2, 0, 0}, - [MDP_COMP_RSZ0] = {1, 0, 0}, - [MDP_COMP_WROT0] = {1, 0, 0}, - [MDP_COMP_WDMA] = {1, 0, 0}, - [MDP_COMP_CCORR0] = {1, 0, 0}, -}; - static inline bool is_dma_capable(const enum mdp_comp_type type) { return (type == MDP_COMP_TYPE_RDMA || @@ -666,13 +666,13 @@ static inline bool is_bypass_gce_event(const enum mdp_comp_type type) return (type == MDP_COMP_TYPE_PATH); } -static int mdp_comp_get_id(enum mdp_comp_type type, int alias_id) +static int mdp_comp_get_id(struct mdp_dev *mdp, enum mdp_comp_type type, u32 alias_id) { int i; - for (i = 0; i < ARRAY_SIZE(mdp_comp_matches); i++) - if (mdp_comp_matches[i].type == type && - mdp_comp_matches[i].alias_id == alias_id) + for (i = 0; i < mdp->mdp_data->comp_data_len; i++) + if (mdp->mdp_data->comp_data[i].match.type == type && + mdp->mdp_data->comp_data[i].match.alias_id == alias_id) return i; return -ENODEV; } @@ -686,7 +686,7 @@ int mdp_comp_clock_on(struct device *dev, struct mdp_comp *comp) if (ret < 0) { dev_err(dev, "Failed to get power, err %d. type:%d id:%d\n", - ret, comp->type, comp->id); + ret, comp->type, comp->inner_id); return ret; } } @@ -698,7 +698,7 @@ int mdp_comp_clock_on(struct device *dev, struct mdp_comp *comp) if (ret) { dev_err(dev, "Failed to enable clk %d. type:%d id:%d\n", - i, comp->type, comp->id); + i, comp->type, comp->inner_id); goto err_revert; } } @@ -752,8 +752,8 @@ void mdp_comp_clocks_off(struct device *dev, struct mdp_comp *comps, int num) mdp_comp_clock_off(dev, &comps[i]); } -static int mdp_get_subsys_id(struct device *dev, struct device_node *node, - struct mdp_comp *comp) +static int mdp_get_subsys_id(struct mdp_dev *mdp, struct device *dev, + struct device_node *node, struct mdp_comp *comp) { struct platform_device *comp_pdev; struct cmdq_client_reg cmdq_reg; @@ -766,12 +766,12 @@ static int mdp_get_subsys_id(struct device *dev, struct device_node *node, comp_pdev = of_find_device_by_node(node); if (!comp_pdev) { - dev_err(dev, "get comp_pdev fail! comp id=%d type=%d\n", - comp->id, comp->type); + dev_err(dev, "get comp_pdev fail! comp public id=%d, inner id=%d, type=%d\n", + comp->public_id, comp->inner_id, comp->type); return -ENODEV; } - index = mdp_comp_dt_info[comp->id].dts_reg_ofst; + index = mdp->mdp_data->comp_data[comp->public_id].info.dts_reg_ofst; ret = cmdq_dev_get_client_reg(&comp_pdev->dev, &cmdq_reg, index); if (ret != 0) { dev_err(&comp_pdev->dev, "cmdq_dev_get_subsys fail!\n"); @@ -789,8 +789,9 @@ static void __mdp_comp_init(struct mdp_dev *mdp, struct device_node *node, { struct resource res; phys_addr_t base; - int index = mdp_comp_dt_info[comp->id].dts_reg_ofst; + int index; + index = mdp->mdp_data->comp_data[comp->public_id].info.dts_reg_ofst; if (of_address_to_resource(node, index, &res) < 0) base = 0L; else @@ -815,14 +816,15 @@ static int mdp_comp_init(struct mdp_dev *mdp, struct device_node *node, return -EINVAL; } - comp->id = id; - comp->type = mdp_comp_matches[id].type; - comp->alias_id = mdp_comp_matches[id].alias_id; + comp->public_id = id; + comp->type = mdp->mdp_data->comp_data[id].match.type; + comp->inner_id = mdp->mdp_data->comp_data[id].match.inner_id; + comp->alias_id = mdp->mdp_data->comp_data[id].match.alias_id; comp->ops = mdp_comp_ops[comp->type]; __mdp_comp_init(mdp, node, comp); - clk_num = mdp_comp_dt_info[id].clk_num; - clk_ofst = mdp_comp_dt_info[id].clk_ofst; + clk_num = mdp->mdp_data->comp_data[id].info.clk_num; + clk_ofst = mdp->mdp_data->comp_data[id].info.clk_ofst; for (i = 0; i < clk_num; i++) { comp->clks[i] = of_clk_get(node, i + clk_ofst); @@ -830,7 +832,7 @@ static int mdp_comp_init(struct mdp_dev *mdp, struct device_node *node, break; } - mdp_get_subsys_id(dev, node, comp); + mdp_get_subsys_id(mdp, dev, node, comp); /* Set GCE SOF event */ if (is_bypass_gce_event(comp->type) || @@ -888,8 +890,8 @@ static struct mdp_comp *mdp_comp_create(struct mdp_dev *mdp, mdp->comp[id] = comp; mdp->comp[id]->mdp_dev = mdp; - dev_dbg(dev, "%s type:%d alias:%d id:%d base:%#x regs:%p\n", - dev->of_node->name, comp->type, comp->alias_id, id, + dev_dbg(dev, "%s type:%d alias:%d public id:%d inner id:%d base:%#x regs:%p\n", + dev->of_node->name, comp->type, comp->alias_id, id, comp->inner_id, (u32)comp->reg_base, comp->regs); return comp; } @@ -918,7 +920,7 @@ static int mdp_comp_sub_create(struct mdp_dev *mdp) type = (enum mdp_comp_type)(uintptr_t)of_id->data; alias_id = mdp_comp_alias_id[type]; - id = mdp_comp_get_id(type, alias_id); + id = mdp_comp_get_id(mdp, type, alias_id); if (id < 0) { dev_err(dev, "Fail to get sub comp. id: type %d alias %d\n", @@ -978,7 +980,7 @@ int mdp_comp_config(struct mdp_dev *mdp) type = (enum mdp_comp_type)(uintptr_t)of_id->data; alias_id = mdp_comp_alias_id[type]; - id = mdp_comp_get_id(type, alias_id); + id = mdp_comp_get_id(mdp, type, alias_id); if (id < 0) { dev_err(dev, "Fail to get component id: type %d alias %d\n", @@ -1025,16 +1027,18 @@ int mdp_comp_ctx_config(struct mdp_dev *mdp, struct mdp_comp_ctx *ctx, const struct img_ipi_frameparam *frame) { struct device *dev = &mdp->pdev->dev; + enum mtk_mdp_comp_id public_id = MDP_COMP_NONE; int i; - if (param->type < 0 || param->type >= MDP_MAX_COMP_COUNT) { - dev_err(dev, "Invalid component id %d", param->type); + public_id = get_comp_public_id(mdp, param->type); + if (public_id < 0) { + dev_err(dev, "Invalid component id %d", public_id); return -EINVAL; } - ctx->comp = mdp->comp[param->type]; + ctx->comp = mdp->comp[public_id]; if (!ctx->comp) { - dev_err(dev, "Uninit component id %d", param->type); + dev_err(dev, "Uninit component inner id %d", param->type); return -EINVAL; } diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h index dc48f55ac4f7..5188aa0821c4 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h @@ -134,6 +134,24 @@ enum { MDP_GCE_EVENT_MAX, }; +struct mdp_comp_match { + enum mdp_comp_type type; + u32 alias_id; + s32 inner_id; +}; + +/* Used to describe the item order in MDP property */ +struct mdp_comp_info { + u32 clk_num; + u32 clk_ofst; + u32 dts_reg_ofst; +}; + +struct mdp_comp_data { + struct mdp_comp_match match; + struct mdp_comp_info info; +}; + struct mdp_comp_ops; struct mdp_comp { @@ -144,7 +162,8 @@ struct mdp_comp { struct clk *clks[6]; struct device *comp_dev; enum mdp_comp_type type; - enum mtk_mdp_comp_id id; + enum mtk_mdp_comp_id public_id; + s32 inner_id; u32 alias_id; s32 gce_event[MDP_GCE_EVENT_MAX]; const struct mdp_comp_ops *ops; @@ -173,6 +192,9 @@ struct mdp_comp_ops { struct mdp_dev; +s32 get_comp_inner_id(struct mdp_dev *mdp_dev, enum mtk_mdp_comp_id id); +enum mtk_mdp_comp_id get_comp_public_id(struct mdp_dev *mdp_dev, s32 id); + int mdp_comp_config(struct mdp_dev *mdp); void mdp_comp_destroy(struct mdp_dev *mdp); int mdp_comp_clock_on(struct device *dev, struct mdp_comp *comp); diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c index 658037d06250..ee7b5a1bbc88 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c @@ -21,6 +21,8 @@ static const struct mtk_mdp_driver_data mt8183_mdp_driver_data = { .mdp_probe_infra = mt8183_mdp_probe_infra, .mdp_cfg = &mt8183_plat_cfg, .mdp_mutex_table_idx = mt8183_mutex_idx, + .comp_data = mt8183_mdp_comp_data, + .comp_data_len = ARRAY_SIZE(mt8183_mdp_comp_data), }; static const struct of_device_id mdp_of_ids[] = { diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h index 2ef5fbc4f25a..0c398ef75616 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h @@ -54,6 +54,8 @@ struct mtk_mdp_driver_data { const struct of_device_id *mdp_probe_infra; const struct mdp_platform_config *mdp_cfg; const u32 *mdp_mutex_table_idx; + const struct mdp_comp_data *comp_data; + unsigned int comp_data_len; }; struct mdp_dev { From patchwork Fri Jan 13 06:40:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moudy Ho X-Patchwork-Id: 642853 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3A01C61DB3 for ; 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Fri, 13 Jan 2023 14:41:07 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Fri, 13 Jan 2023 14:41:06 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Fri, 13 Jan 2023 14:41:06 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Matthias Brugger , Hans Verkuil CC: Chun-Kuang Hu , , , , , Moudy Ho Subject: [PATCH v5 04/12] media: platform: mtk-mdp3: chip config split about subcomponents Date: Fri, 13 Jan 2023 14:40:56 +0800 Message-ID: <20230113064104.22402-5-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230113064104.22402-1-moudy.ho@mediatek.com> References: <20230113064104.22402-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Integrate and move subcomponent related information into the chip config header file for compatibility with multiple chips Signed-off-by: Moudy Ho --- .../mediatek/mdp3/mt8183/mdp3-plat-mt8183.h | 11 +++++++++++ .../media/platform/mediatek/mdp3/mtk-mdp3-comp.c | 14 ++------------ .../media/platform/mediatek/mdp3/mtk-mdp3-core.c | 1 + .../media/platform/mediatek/mdp3/mtk-mdp3-core.h | 1 + 4 files changed, 15 insertions(+), 12 deletions(-) diff --git a/drivers/media/platform/mediatek/mdp3/mt8183/mdp3-plat-mt8183.h b/drivers/media/platform/mediatek/mdp3/mt8183/mdp3-plat-mt8183.h index 81fb80ec8ac2..a4bfde4a9e16 100644 --- a/drivers/media/platform/mediatek/mdp3/mt8183/mdp3-plat-mt8183.h +++ b/drivers/media/platform/mediatek/mdp3/mt8183/mdp3-plat-mt8183.h @@ -32,6 +32,17 @@ static const u32 mt8183_mutex_idx[MDP_MAX_COMP_COUNT] = { [MDP_COMP_CCORR0] = MUTEX_MOD_IDX_MDP_CCORR0, }; +static const struct of_device_id mt8183_sub_comp_dt_ids[] = { + { + .compatible = "mediatek,mt8183-mdp3-wdma", + .data = (void *)MDP_COMP_TYPE_PATH, + }, { + .compatible = "mediatek,mt8183-mdp3-wrot", + .data = (void *)MDP_COMP_TYPE_PATH, + }, + {} +}; + enum mt8183_mdp_comp_id { /* MT8183 Comp id */ /* ISP */ diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c index 1ac9c46e27d4..8f4786cc4416 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c @@ -639,17 +639,6 @@ static const struct of_device_id mdp_comp_dt_ids[] = { {} }; -static const struct of_device_id mdp_sub_comp_dt_ids[] = { - { - .compatible = "mediatek,mt8183-mdp3-wdma", - .data = (void *)MDP_COMP_TYPE_PATH, - }, { - .compatible = "mediatek,mt8183-mdp3-wrot", - .data = (void *)MDP_COMP_TYPE_PATH, - }, - {} -}; - static inline bool is_dma_capable(const enum mdp_comp_type type) { return (type == MDP_COMP_TYPE_RDMA || @@ -900,6 +889,7 @@ static int mdp_comp_sub_create(struct mdp_dev *mdp) { struct device *dev = &mdp->pdev->dev; struct device_node *node, *parent; + const struct mtk_mdp_driver_data *data = mdp->mdp_data; parent = dev->of_node->parent; @@ -909,7 +899,7 @@ static int mdp_comp_sub_create(struct mdp_dev *mdp) int id, alias_id; struct mdp_comp *comp; - of_id = of_match_node(mdp_sub_comp_dt_ids, node); + of_id = of_match_node(data->mdp_sub_comp_dt_ids, node); if (!of_id) continue; if (!of_device_is_available(node)) { diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c index ee7b5a1bbc88..277253c8c963 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c @@ -19,6 +19,7 @@ static const struct mtk_mdp_driver_data mt8183_mdp_driver_data = { .mdp_probe_infra = mt8183_mdp_probe_infra, + .mdp_sub_comp_dt_ids = mt8183_sub_comp_dt_ids, .mdp_cfg = &mt8183_plat_cfg, .mdp_mutex_table_idx = mt8183_mutex_idx, .comp_data = mt8183_mdp_comp_data, diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h index 0c398ef75616..b83b2c517730 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h @@ -52,6 +52,7 @@ enum mdp_pipe_id { struct mtk_mdp_driver_data { const struct of_device_id *mdp_probe_infra; + const struct of_device_id *mdp_sub_comp_dt_ids; const struct mdp_platform_config *mdp_cfg; const u32 *mdp_mutex_table_idx; const struct mdp_comp_data *comp_data; From patchwork Fri Jan 13 06:40:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moudy Ho X-Patchwork-Id: 642850 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4268C54EBD for ; Fri, 13 Jan 2023 06:57:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240986AbjAMG46 (ORCPT ); Fri, 13 Jan 2023 01:56:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59758 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232506AbjAMG4H (ORCPT ); Fri, 13 Jan 2023 01:56:07 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B2FFB718A0; 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Fri, 13 Jan 2023 14:41:07 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Fri, 13 Jan 2023 14:41:06 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Fri, 13 Jan 2023 14:41:06 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Matthias Brugger , Hans Verkuil CC: Chun-Kuang Hu , , , , , Moudy Ho Subject: [PATCH v5 07/12] media: platform: mtk-mdp3: chip config split about pipe info Date: Fri, 13 Jan 2023 14:40:59 +0800 Message-ID: <20230113064104.22402-8-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230113064104.22402-1-moudy.ho@mediatek.com> References: <20230113064104.22402-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org In MDP3, a pipe is used to represent a data path which consisting of different components and MUTEX, as shown in the following diagram: +----------------------------+ | MUTEX [*1] | +----------------------------+ S ^ S ^ S ^ S ^ S ^ | | | | | | | | | | | | | | | | | | | | +--------------+ | | | | | | | | +-------------+ | +--------------+ | | | | | | +-------------+ | | | +------+ | | | | +------+ | | | | | +------+ | | +------+ | | | | | | | | | | | | | | | | | | | | | | | v E v E v E v E v E +-------+ +-----+ +-------+ +-----+ +-------+ B>--->| RDMA0 |>-->| PQ |>-->| RSZ0 |>-->| PQ |>-->| WROT0 |>-->B +-------+ +-----+ +-------+ +-----+ +-------+ [*1] MUTEX is SOF/EOF signal controller [*2] S = Start of frame (SOF) [*3] E = End of frame (EOF) [*4] B = frame buffer More pipes will be introduced in future chip for applications such as higher frame rate frequency, which should move and reorder the relevant information into the chip configuration header file. Signed-off-by: Moudy Ho --- .../mediatek/mdp3/mt8183/mdp3-plat-mt8183.h | 7 ++++++ .../platform/mediatek/mdp3/mtk-mdp3-cmdq.c | 23 ++++++++++++------- .../platform/mediatek/mdp3/mtk-mdp3-core.c | 15 ++++++++---- .../platform/mediatek/mdp3/mtk-mdp3-core.h | 11 +++++++-- 4 files changed, 41 insertions(+), 15 deletions(-) diff --git a/drivers/media/platform/mediatek/mdp3/mt8183/mdp3-plat-mt8183.h b/drivers/media/platform/mediatek/mdp3/mt8183/mdp3-plat-mt8183.h index c541176780aa..b1d4cbeda932 100644 --- a/drivers/media/platform/mediatek/mdp3/mt8183/mdp3-plat-mt8183.h +++ b/drivers/media/platform/mediatek/mdp3/mt8183/mdp3-plat-mt8183.h @@ -21,6 +21,13 @@ static const struct of_device_id mt8183_mdp_probe_infra[MDP_INFRA_MAX] = { [MDP_INFRA_SCP] = { .compatible = "mediatek,mt8183-scp" } }; +static const struct mdp_pipe_info mt8183_pipe_info[] = { + [MDP_PIPE_WPEI] = {MDP_PIPE_WPEI, 0}, + [MDP_PIPE_WPEI2] = {MDP_PIPE_WPEI2, 1}, + [MDP_PIPE_IMGI] = {MDP_PIPE_IMGI, 2}, + [MDP_PIPE_RDMA0] = {MDP_PIPE_RDMA0, 3} +}; + static const u32 mt8183_mutex_idx[MDP_MAX_COMP_COUNT] = { [MDP_COMP_RDMA0] = MUTEX_MOD_IDX_MDP_RDMA0, [MDP_COMP_RSZ0] = MUTEX_MOD_IDX_MDP_RSZ0, diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c index dcd77f65b0e3..bff14e4944c5 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c @@ -50,21 +50,22 @@ static int mdp_path_subfrm_require(const struct mdp_path *path, /* Decide which mutex to use based on the current pipeline */ switch (path->comps[0].comp->public_id) { case MDP_COMP_RDMA0: - *mutex_id = MDP_PIPE_RDMA0; + index = MDP_PIPE_RDMA0; break; case MDP_COMP_ISP_IMGI: - *mutex_id = MDP_PIPE_IMGI; + index = MDP_PIPE_IMGI; break; case MDP_COMP_WPEI: - *mutex_id = MDP_PIPE_WPEI; + index = MDP_PIPE_WPEI; break; case MDP_COMP_WPEI2: - *mutex_id = MDP_PIPE_WPEI2; + index = MDP_PIPE_WPEI2; break; default: dev_err(dev, "Unknown pipeline and no mutex is assigned"); return -EINVAL; } + *mutex_id = data->pipe_info[index].mutex_id; /* Set mutex mod */ for (index = 0; index < config->num_components; index++) { @@ -286,11 +287,13 @@ static void mdp_auto_release_work(struct work_struct *work) { struct mdp_cmdq_cmd *cmd; struct mdp_dev *mdp; + int id; cmd = container_of(work, struct mdp_cmdq_cmd, auto_release_work); mdp = cmd->mdp; - mtk_mutex_unprepare(mdp->mdp_mutex[MDP_PIPE_RDMA0]); + id = mdp->mdp_data->pipe_info[MDP_PIPE_RDMA0].mutex_id; + mtk_mutex_unprepare(mdp->mdp_mutex[id]); mdp_comp_clocks_off(&mdp->pdev->dev, cmd->comps, cmd->num_comps); @@ -310,6 +313,7 @@ static void mdp_handle_cmdq_callback(struct mbox_client *cl, void *mssg) struct cmdq_cb_data *data; struct mdp_dev *mdp; struct device *dev; + int id; if (!mssg) { pr_info("%s:no callback data\n", __func__); @@ -335,7 +339,8 @@ static void mdp_handle_cmdq_callback(struct mbox_client *cl, void *mssg) INIT_WORK(&cmd->auto_release_work, mdp_auto_release_work); if (!queue_work(mdp->clock_wq, &cmd->auto_release_work)) { dev_err(dev, "%s:queue_work fail!\n", __func__); - mtk_mutex_unprepare(mdp->mdp_mutex[MDP_PIPE_RDMA0]); + id = mdp->mdp_data->pipe_info[MDP_PIPE_RDMA0].mutex_id; + mtk_mutex_unprepare(mdp->mdp_mutex[id]); mdp_comp_clocks_off(&mdp->pdev->dev, cmd->comps, cmd->num_comps); @@ -387,7 +392,8 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param) goto err_free_comps; } - ret = mtk_mutex_prepare(mdp->mdp_mutex[MDP_PIPE_RDMA0]); + i = mdp->mdp_data->pipe_info[MDP_PIPE_RDMA0].mutex_id; + ret = mtk_mutex_prepare(mdp->mdp_mutex[i]); if (ret) { dev_err(dev, "Fail to enable mutex clk\n"); goto err_free_path; @@ -453,7 +459,8 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param) mdp_comp_clocks_off(&mdp->pdev->dev, cmd->comps, cmd->num_comps); err_free_path: - mtk_mutex_unprepare(mdp->mdp_mutex[MDP_PIPE_RDMA0]); + i = mdp->mdp_data->pipe_info[MDP_PIPE_RDMA0].mutex_id; + mtk_mutex_unprepare(mdp->mdp_mutex[i]); kfree(path); err_free_comps: kfree(comps); diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c index 4b02c135b631..79acdccd0b60 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c @@ -24,6 +24,8 @@ static const struct mtk_mdp_driver_data mt8183_mdp_driver_data = { .mdp_mutex_table_idx = mt8183_mutex_idx, .comp_data = mt8183_mdp_comp_data, .comp_data_len = ARRAY_SIZE(mt8183_mdp_comp_data), + .pipe_info = mt8183_pipe_info, + .pipe_info_len = ARRAY_SIZE(mt8183_pipe_info), .format = mt8183_formats, .format_len = ARRAY_SIZE(mt8183_formats), .def_limit = &mt8183_mdp_def_limit, @@ -165,7 +167,7 @@ static int mdp_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct mdp_dev *mdp; struct platform_device *mm_pdev; - int ret, i; + int ret, i, mutex_id; mdp = kzalloc(sizeof(*mdp), GFP_KERNEL); if (!mdp) { @@ -188,9 +190,12 @@ static int mdp_probe(struct platform_device *pdev) ret = -ENODEV; goto err_destroy_device; } - for (i = 0; i < MDP_PIPE_MAX; i++) { - mdp->mdp_mutex[i] = mtk_mutex_get(&mm_pdev->dev); - if (!mdp->mdp_mutex[i]) { + for (i = 0; i < mdp->mdp_data->pipe_info_len; i++) { + mutex_id = mdp->mdp_data->pipe_info[i].mutex_id; + if (mdp->mdp_mutex[mutex_id]) + continue; + mdp->mdp_mutex[mutex_id] = mtk_mutex_get(&mm_pdev->dev); + if (!mdp->mdp_mutex[mutex_id]) { ret = -ENODEV; goto err_free_mutex; } @@ -271,7 +276,7 @@ static int mdp_probe(struct platform_device *pdev) err_deinit_comp: mdp_comp_destroy(mdp); err_free_mutex: - for (i = 0; i < MDP_PIPE_MAX; i++) + for (i = 0; i < mdp->mdp_data->pipe_info_len; i++) mtk_mutex_put(mdp->mdp_mutex[i]); err_destroy_device: kfree(mdp); diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h index 52f87e59ba9e..dd5e23800854 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h @@ -43,10 +43,10 @@ struct mdp_platform_config { /* indicate which mutex is used by each pipepline */ enum mdp_pipe_id { - MDP_PIPE_RDMA0, - MDP_PIPE_IMGI, MDP_PIPE_WPEI, MDP_PIPE_WPEI2, + MDP_PIPE_IMGI, + MDP_PIPE_RDMA0, MDP_PIPE_MAX }; @@ -57,6 +57,8 @@ struct mtk_mdp_driver_data { const u32 *mdp_mutex_table_idx; const struct mdp_comp_data *comp_data; unsigned int comp_data_len; + const struct mdp_pipe_info *pipe_info; + unsigned int pipe_info_len; const struct mdp_format *format; unsigned int format_len; const struct mdp_limit *def_limit; @@ -91,6 +93,11 @@ struct mdp_dev { atomic_t job_count; }; +struct mdp_pipe_info { + enum mdp_pipe_id pipe_id; + u32 mutex_id; +}; + int mdp_vpu_get_locked(struct mdp_dev *mdp); void mdp_vpu_put_locked(struct mdp_dev *mdp); int mdp_vpu_register(struct mdp_dev *mdp); From patchwork Fri Jan 13 06:41:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moudy Ho X-Patchwork-Id: 642851 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37135C54EBE for ; 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Fri, 13 Jan 2023 14:41:07 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Fri, 13 Jan 2023 14:41:06 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Matthias Brugger , Hans Verkuil CC: Chun-Kuang Hu , , , , , Moudy Ho Subject: [PATCH v5 08/12] media: platform: mtk-mdp3: extend mdp_color format for compressed mode Date: Fri, 13 Jan 2023 14:41:00 +0800 Message-ID: <20230113064104.22402-9-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230113064104.22402-1-moudy.ho@mediatek.com> References: <20230113064104.22402-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Due to future support for hardware compression formats, the MDP3 internal color format expression needs to be extended. Signed-off-by: Moudy Ho --- .../platform/mediatek/mdp3/mtk-mdp3-regs.h | 205 +++++++++--------- 1 file changed, 103 insertions(+), 102 deletions(-) diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-regs.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-regs.h index 8e91bcb094e0..e9ab8ac2c0e8 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-regs.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-regs.h @@ -18,11 +18,12 @@ * V-subsample: 0, 1 * Color group: 0-RGB, 1-YUV, 2-raw */ -#define MDP_COLOR(PACKED, LOOSE, VIDEO, PLANE, HF, VF, BITS, GROUP, SWAP, ID)\ - (((PACKED) << 27) | ((LOOSE) << 26) | ((VIDEO) << 23) |\ +#define MDP_COLOR(COMPRESS, PACKED, LOOSE, VIDEO, PLANE, HF, VF, BITS, GROUP, SWAP, ID)\ + (((COMPRESS) << 29) | ((PACKED) << 27) | ((LOOSE) << 26) | ((VIDEO) << 23) |\ ((PLANE) << 21) | ((HF) << 19) | ((VF) << 18) | ((BITS) << 8) |\ ((GROUP) << 6) | ((SWAP) << 5) | ((ID) << 0)) +#define MDP_COLOR_IS_COMPRESS(c) ((0x20000000 & (c)) >> 29) #define MDP_COLOR_IS_10BIT_PACKED(c) ((0x08000000 & (c)) >> 27) #define MDP_COLOR_IS_10BIT_LOOSE(c) (((0x0c000000 & (c)) >> 26) == 1) #define MDP_COLOR_IS_10BIT_TILE(c) (((0x0c000000 & (c)) >> 26) == 3) @@ -44,144 +45,144 @@ enum mdp_color { MDP_COLOR_UNKNOWN = 0, - //MDP_COLOR_FULLG8, - MDP_COLOR_FULLG8_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 8, 2, 0, 21), - MDP_COLOR_FULLG8_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 8, 2, 0, 21), - MDP_COLOR_FULLG8_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 8, 2, 0, 21), - MDP_COLOR_FULLG8_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 8, 2, 0, 21), + /* MDP_COLOR_FULLG8 */ + MDP_COLOR_FULLG8_RGGB = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 8, 2, 0, 21), + MDP_COLOR_FULLG8_GRBG = MDP_COLOR(0, 0, 0, 0, 1, 0, 1, 8, 2, 0, 21), + MDP_COLOR_FULLG8_GBRG = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 8, 2, 0, 21), + MDP_COLOR_FULLG8_BGGR = MDP_COLOR(0, 0, 0, 0, 1, 1, 1, 8, 2, 0, 21), MDP_COLOR_FULLG8 = MDP_COLOR_FULLG8_BGGR, - //MDP_COLOR_FULLG10, - MDP_COLOR_FULLG10_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 10, 2, 0, 21), - MDP_COLOR_FULLG10_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 10, 2, 0, 21), - MDP_COLOR_FULLG10_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 10, 2, 0, 21), - MDP_COLOR_FULLG10_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 10, 2, 0, 21), + /* MDP_COLOR_FULLG10 */ + MDP_COLOR_FULLG10_RGGB = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 10, 2, 0, 21), + MDP_COLOR_FULLG10_GRBG = MDP_COLOR(0, 0, 0, 0, 1, 0, 1, 10, 2, 0, 21), + MDP_COLOR_FULLG10_GBRG = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 10, 2, 0, 21), + MDP_COLOR_FULLG10_BGGR = MDP_COLOR(0, 0, 0, 0, 1, 1, 1, 10, 2, 0, 21), MDP_COLOR_FULLG10 = MDP_COLOR_FULLG10_BGGR, - //MDP_COLOR_FULLG12, - MDP_COLOR_FULLG12_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 12, 2, 0, 21), - MDP_COLOR_FULLG12_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 12, 2, 0, 21), - MDP_COLOR_FULLG12_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 12, 2, 0, 21), - MDP_COLOR_FULLG12_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 12, 2, 0, 21), + /* MDP_COLOR_FULLG12 */ + MDP_COLOR_FULLG12_RGGB = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 12, 2, 0, 21), + MDP_COLOR_FULLG12_GRBG = MDP_COLOR(0, 0, 0, 0, 1, 0, 1, 12, 2, 0, 21), + MDP_COLOR_FULLG12_GBRG = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 12, 2, 0, 21), + MDP_COLOR_FULLG12_BGGR = MDP_COLOR(0, 0, 0, 0, 1, 1, 1, 12, 2, 0, 21), MDP_COLOR_FULLG12 = MDP_COLOR_FULLG12_BGGR, - //MDP_COLOR_FULLG14, - MDP_COLOR_FULLG14_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 14, 2, 0, 21), - MDP_COLOR_FULLG14_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 14, 2, 0, 21), - MDP_COLOR_FULLG14_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 14, 2, 0, 21), - MDP_COLOR_FULLG14_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 14, 2, 0, 21), + /* MDP_COLOR_FULLG14 */ + MDP_COLOR_FULLG14_RGGB = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 14, 2, 0, 21), + MDP_COLOR_FULLG14_GRBG = MDP_COLOR(0, 0, 0, 0, 1, 0, 1, 14, 2, 0, 21), + MDP_COLOR_FULLG14_GBRG = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 14, 2, 0, 21), + MDP_COLOR_FULLG14_BGGR = MDP_COLOR(0, 0, 0, 0, 1, 1, 1, 14, 2, 0, 21), MDP_COLOR_FULLG14 = MDP_COLOR_FULLG14_BGGR, - MDP_COLOR_UFO10 = MDP_COLOR(0, 0, 0, 1, 0, 0, 10, 2, 0, 24), + MDP_COLOR_UFO10 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 10, 2, 0, 24), - //MDP_COLOR_BAYER8, - MDP_COLOR_BAYER8_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 8, 2, 0, 20), - MDP_COLOR_BAYER8_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 8, 2, 0, 20), - MDP_COLOR_BAYER8_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 8, 2, 0, 20), - MDP_COLOR_BAYER8_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 8, 2, 0, 20), + /* MDP_COLOR_BAYER8 */ + MDP_COLOR_BAYER8_RGGB = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 8, 2, 0, 20), + MDP_COLOR_BAYER8_GRBG = MDP_COLOR(0, 0, 0, 0, 1, 0, 1, 8, 2, 0, 20), + MDP_COLOR_BAYER8_GBRG = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 8, 2, 0, 20), + MDP_COLOR_BAYER8_BGGR = MDP_COLOR(0, 0, 0, 0, 1, 1, 1, 8, 2, 0, 20), MDP_COLOR_BAYER8 = MDP_COLOR_BAYER8_BGGR, - //MDP_COLOR_BAYER10, - MDP_COLOR_BAYER10_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 10, 2, 0, 20), - MDP_COLOR_BAYER10_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 10, 2, 0, 20), - MDP_COLOR_BAYER10_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 10, 2, 0, 20), - MDP_COLOR_BAYER10_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 10, 2, 0, 20), + /* MDP_COLOR_BAYER10 */ + MDP_COLOR_BAYER10_RGGB = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 10, 2, 0, 20), + MDP_COLOR_BAYER10_GRBG = MDP_COLOR(0, 0, 0, 0, 1, 0, 1, 10, 2, 0, 20), + MDP_COLOR_BAYER10_GBRG = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 10, 2, 0, 20), + MDP_COLOR_BAYER10_BGGR = MDP_COLOR(0, 0, 0, 0, 1, 1, 1, 10, 2, 0, 20), MDP_COLOR_BAYER10 = MDP_COLOR_BAYER10_BGGR, - //MDP_COLOR_BAYER12, - MDP_COLOR_BAYER12_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 12, 2, 0, 20), - MDP_COLOR_BAYER12_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 12, 2, 0, 20), - MDP_COLOR_BAYER12_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 12, 2, 0, 20), - MDP_COLOR_BAYER12_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 12, 2, 0, 20), + /* MDP_COLOR_BAYER12 */ + MDP_COLOR_BAYER12_RGGB = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 12, 2, 0, 20), + MDP_COLOR_BAYER12_GRBG = MDP_COLOR(0, 0, 0, 0, 1, 0, 1, 12, 2, 0, 20), + MDP_COLOR_BAYER12_GBRG = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 12, 2, 0, 20), + MDP_COLOR_BAYER12_BGGR = MDP_COLOR(0, 0, 0, 0, 1, 1, 1, 12, 2, 0, 20), MDP_COLOR_BAYER12 = MDP_COLOR_BAYER12_BGGR, - //MDP_COLOR_BAYER14, - MDP_COLOR_BAYER14_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 14, 2, 0, 20), - MDP_COLOR_BAYER14_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 14, 2, 0, 20), - MDP_COLOR_BAYER14_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 14, 2, 0, 20), - MDP_COLOR_BAYER14_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 14, 2, 0, 20), + /* MDP_COLOR_BAYER14 */ + MDP_COLOR_BAYER14_RGGB = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 14, 2, 0, 20), + MDP_COLOR_BAYER14_GRBG = MDP_COLOR(0, 0, 0, 0, 1, 0, 1, 14, 2, 0, 20), + MDP_COLOR_BAYER14_GBRG = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 14, 2, 0, 20), + MDP_COLOR_BAYER14_BGGR = MDP_COLOR(0, 0, 0, 0, 1, 1, 1, 14, 2, 0, 20), MDP_COLOR_BAYER14 = MDP_COLOR_BAYER14_BGGR, - MDP_COLOR_RGB48 = MDP_COLOR(0, 0, 0, 1, 0, 0, 48, 0, 0, 23), + MDP_COLOR_RGB48 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 48, 0, 0, 23), /* For bayer+mono raw-16 */ - MDP_COLOR_RGB565_RAW = MDP_COLOR(0, 0, 0, 1, 0, 0, 16, 2, 0, 0), + MDP_COLOR_RGB565_RAW = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 16, 2, 0, 0), - MDP_COLOR_BAYER8_UNPAK = MDP_COLOR(0, 0, 0, 1, 0, 0, 8, 2, 0, 22), - MDP_COLOR_BAYER10_UNPAK = MDP_COLOR(0, 0, 0, 1, 0, 0, 10, 2, 0, 22), - MDP_COLOR_BAYER12_UNPAK = MDP_COLOR(0, 0, 0, 1, 0, 0, 12, 2, 0, 22), - MDP_COLOR_BAYER14_UNPAK = MDP_COLOR(0, 0, 0, 1, 0, 0, 14, 2, 0, 22), + MDP_COLOR_BAYER8_UNPAK = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 8, 2, 0, 22), + MDP_COLOR_BAYER10_UNPAK = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 10, 2, 0, 22), + MDP_COLOR_BAYER12_UNPAK = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 12, 2, 0, 22), + MDP_COLOR_BAYER14_UNPAK = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 14, 2, 0, 22), /* Unified formats */ - MDP_COLOR_GREY = MDP_COLOR(0, 0, 0, 1, 0, 0, 8, 1, 0, 7), - - MDP_COLOR_RGB565 = MDP_COLOR(0, 0, 0, 1, 0, 0, 16, 0, 0, 0), - MDP_COLOR_BGR565 = MDP_COLOR(0, 0, 0, 1, 0, 0, 16, 0, 1, 0), - MDP_COLOR_RGB888 = MDP_COLOR(0, 0, 0, 1, 0, 0, 24, 0, 1, 1), - MDP_COLOR_BGR888 = MDP_COLOR(0, 0, 0, 1, 0, 0, 24, 0, 0, 1), - MDP_COLOR_RGBA8888 = MDP_COLOR(0, 0, 0, 1, 0, 0, 32, 0, 1, 2), - MDP_COLOR_BGRA8888 = MDP_COLOR(0, 0, 0, 1, 0, 0, 32, 0, 0, 2), - MDP_COLOR_ARGB8888 = MDP_COLOR(0, 0, 0, 1, 0, 0, 32, 0, 1, 3), - MDP_COLOR_ABGR8888 = MDP_COLOR(0, 0, 0, 1, 0, 0, 32, 0, 0, 3), - - MDP_COLOR_UYVY = MDP_COLOR(0, 0, 0, 1, 1, 0, 16, 1, 0, 4), - MDP_COLOR_VYUY = MDP_COLOR(0, 0, 0, 1, 1, 0, 16, 1, 1, 4), - MDP_COLOR_YUYV = MDP_COLOR(0, 0, 0, 1, 1, 0, 16, 1, 0, 5), - MDP_COLOR_YVYU = MDP_COLOR(0, 0, 0, 1, 1, 0, 16, 1, 1, 5), - - MDP_COLOR_I420 = MDP_COLOR(0, 0, 0, 3, 1, 1, 8, 1, 0, 8), - MDP_COLOR_YV12 = MDP_COLOR(0, 0, 0, 3, 1, 1, 8, 1, 1, 8), - MDP_COLOR_I422 = MDP_COLOR(0, 0, 0, 3, 1, 0, 8, 1, 0, 9), - MDP_COLOR_YV16 = MDP_COLOR(0, 0, 0, 3, 1, 0, 8, 1, 1, 9), - MDP_COLOR_I444 = MDP_COLOR(0, 0, 0, 3, 0, 0, 8, 1, 0, 10), - MDP_COLOR_YV24 = MDP_COLOR(0, 0, 0, 3, 0, 0, 8, 1, 1, 10), - - MDP_COLOR_NV12 = MDP_COLOR(0, 0, 0, 2, 1, 1, 8, 1, 0, 12), - MDP_COLOR_NV21 = MDP_COLOR(0, 0, 0, 2, 1, 1, 8, 1, 1, 12), - MDP_COLOR_NV16 = MDP_COLOR(0, 0, 0, 2, 1, 0, 8, 1, 0, 13), - MDP_COLOR_NV61 = MDP_COLOR(0, 0, 0, 2, 1, 0, 8, 1, 1, 13), - MDP_COLOR_NV24 = MDP_COLOR(0, 0, 0, 2, 0, 0, 8, 1, 0, 14), - MDP_COLOR_NV42 = MDP_COLOR(0, 0, 0, 2, 0, 0, 8, 1, 1, 14), + MDP_COLOR_GREY = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 8, 1, 0, 7), + + MDP_COLOR_RGB565 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 16, 0, 0, 0), + MDP_COLOR_BGR565 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 16, 0, 1, 0), + MDP_COLOR_RGB888 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 24, 0, 1, 1), + MDP_COLOR_BGR888 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 24, 0, 0, 1), + MDP_COLOR_RGBA8888 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 32, 0, 1, 2), + MDP_COLOR_BGRA8888 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 32, 0, 0, 2), + MDP_COLOR_ARGB8888 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 32, 0, 1, 3), + MDP_COLOR_ABGR8888 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 32, 0, 0, 3), + + MDP_COLOR_UYVY = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 16, 1, 0, 4), + MDP_COLOR_VYUY = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 16, 1, 1, 4), + MDP_COLOR_YUYV = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 16, 1, 0, 5), + MDP_COLOR_YVYU = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 16, 1, 1, 5), + + MDP_COLOR_I420 = MDP_COLOR(0, 0, 0, 0, 3, 1, 1, 8, 1, 0, 8), + MDP_COLOR_YV12 = MDP_COLOR(0, 0, 0, 0, 3, 1, 1, 8, 1, 1, 8), + MDP_COLOR_I422 = MDP_COLOR(0, 0, 0, 0, 3, 1, 0, 8, 1, 0, 9), + MDP_COLOR_YV16 = MDP_COLOR(0, 0, 0, 0, 3, 1, 0, 8, 1, 1, 9), + MDP_COLOR_I444 = MDP_COLOR(0, 0, 0, 0, 3, 0, 0, 8, 1, 0, 10), + MDP_COLOR_YV24 = MDP_COLOR(0, 0, 0, 0, 3, 0, 0, 8, 1, 1, 10), + + MDP_COLOR_NV12 = MDP_COLOR(0, 0, 0, 0, 2, 1, 1, 8, 1, 0, 12), + MDP_COLOR_NV21 = MDP_COLOR(0, 0, 0, 0, 2, 1, 1, 8, 1, 1, 12), + MDP_COLOR_NV16 = MDP_COLOR(0, 0, 0, 0, 2, 1, 0, 8, 1, 0, 13), + MDP_COLOR_NV61 = MDP_COLOR(0, 0, 0, 0, 2, 1, 0, 8, 1, 1, 13), + MDP_COLOR_NV24 = MDP_COLOR(0, 0, 0, 0, 2, 0, 0, 8, 1, 0, 14), + MDP_COLOR_NV42 = MDP_COLOR(0, 0, 0, 0, 2, 0, 0, 8, 1, 1, 14), /* MediaTek proprietary formats */ /* UFO encoded block mode */ - MDP_COLOR_420_BLK_UFO = MDP_COLOR(0, 0, 5, 2, 1, 1, 256, 1, 0, 12), + MDP_COLOR_420_BLK_UFO = MDP_COLOR(0, 0, 0, 5, 2, 1, 1, 256, 1, 0, 12), /* Block mode */ - MDP_COLOR_420_BLK = MDP_COLOR(0, 0, 1, 2, 1, 1, 256, 1, 0, 12), + MDP_COLOR_420_BLK = MDP_COLOR(0, 0, 0, 1, 2, 1, 1, 256, 1, 0, 12), /* Block mode + field mode */ - MDP_COLOR_420_BLKI = MDP_COLOR(0, 0, 3, 2, 1, 1, 256, 1, 0, 12), + MDP_COLOR_420_BLKI = MDP_COLOR(0, 0, 0, 3, 2, 1, 1, 256, 1, 0, 12), /* Block mode */ - MDP_COLOR_422_BLK = MDP_COLOR(0, 0, 1, 1, 1, 0, 512, 1, 0, 4), + MDP_COLOR_422_BLK = MDP_COLOR(0, 0, 0, 1, 1, 1, 0, 512, 1, 0, 4), - MDP_COLOR_IYU2 = MDP_COLOR(0, 0, 0, 1, 0, 0, 24, 1, 0, 25), - MDP_COLOR_YUV444 = MDP_COLOR(0, 0, 0, 1, 0, 0, 24, 1, 0, 30), + MDP_COLOR_IYU2 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 24, 1, 0, 25), + MDP_COLOR_YUV444 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 24, 1, 0, 30), /* Packed 10-bit formats */ - MDP_COLOR_RGBA1010102 = MDP_COLOR(1, 0, 0, 1, 0, 0, 32, 0, 1, 2), - MDP_COLOR_BGRA1010102 = MDP_COLOR(1, 0, 0, 1, 0, 0, 32, 0, 0, 2), + MDP_COLOR_RGBA1010102 = MDP_COLOR(0, 1, 0, 0, 1, 0, 0, 32, 0, 1, 2), + MDP_COLOR_BGRA1010102 = MDP_COLOR(0, 1, 0, 0, 1, 0, 0, 32, 0, 0, 2), /* Packed 10-bit UYVY */ - MDP_COLOR_UYVY_10P = MDP_COLOR(1, 0, 0, 1, 1, 0, 20, 1, 0, 4), + MDP_COLOR_UYVY_10P = MDP_COLOR(0, 1, 0, 0, 1, 1, 0, 20, 1, 0, 4), /* Packed 10-bit NV21 */ - MDP_COLOR_NV21_10P = MDP_COLOR(1, 0, 0, 2, 1, 1, 10, 1, 1, 12), + MDP_COLOR_NV21_10P = MDP_COLOR(0, 1, 0, 0, 2, 1, 1, 10, 1, 1, 12), /* 10-bit block mode */ - MDP_COLOR_420_BLK_10_H = MDP_COLOR(1, 0, 1, 2, 1, 1, 320, 1, 0, 12), + MDP_COLOR_420_BLK_10_H = MDP_COLOR(0, 1, 0, 1, 2, 1, 1, 320, 1, 0, 12), /* 10-bit HEVC tile mode */ - MDP_COLOR_420_BLK_10_V = MDP_COLOR(1, 1, 1, 2, 1, 1, 320, 1, 0, 12), + MDP_COLOR_420_BLK_10_V = MDP_COLOR(0, 1, 1, 1, 2, 1, 1, 320, 1, 0, 12), /* UFO encoded 10-bit block mode */ - MDP_COLOR_420_BLK_U10_H = MDP_COLOR(1, 0, 5, 2, 1, 1, 320, 1, 0, 12), + MDP_COLOR_420_BLK_U10_H = MDP_COLOR(0, 1, 0, 5, 2, 1, 1, 320, 1, 0, 12), /* UFO encoded 10-bit HEVC tile mode */ - MDP_COLOR_420_BLK_U10_V = MDP_COLOR(1, 1, 5, 2, 1, 1, 320, 1, 0, 12), + MDP_COLOR_420_BLK_U10_V = MDP_COLOR(0, 1, 1, 5, 2, 1, 1, 320, 1, 0, 12), /* Loose 10-bit formats */ - MDP_COLOR_UYVY_10L = MDP_COLOR(0, 1, 0, 1, 1, 0, 20, 1, 0, 4), - MDP_COLOR_VYUY_10L = MDP_COLOR(0, 1, 0, 1, 1, 0, 20, 1, 1, 4), - MDP_COLOR_YUYV_10L = MDP_COLOR(0, 1, 0, 1, 1, 0, 20, 1, 0, 5), - MDP_COLOR_YVYU_10L = MDP_COLOR(0, 1, 0, 1, 1, 0, 20, 1, 1, 5), - MDP_COLOR_NV12_10L = MDP_COLOR(0, 1, 0, 2, 1, 1, 10, 1, 0, 12), - MDP_COLOR_NV21_10L = MDP_COLOR(0, 1, 0, 2, 1, 1, 10, 1, 1, 12), - MDP_COLOR_NV16_10L = MDP_COLOR(0, 1, 0, 2, 1, 0, 10, 1, 0, 13), - MDP_COLOR_NV61_10L = MDP_COLOR(0, 1, 0, 2, 1, 0, 10, 1, 1, 13), - MDP_COLOR_YV12_10L = MDP_COLOR(0, 1, 0, 3, 1, 1, 10, 1, 1, 8), - MDP_COLOR_I420_10L = MDP_COLOR(0, 1, 0, 3, 1, 1, 10, 1, 0, 8), + MDP_COLOR_UYVY_10L = MDP_COLOR(0, 0, 1, 0, 1, 1, 0, 20, 1, 0, 4), + MDP_COLOR_VYUY_10L = MDP_COLOR(0, 0, 1, 0, 1, 1, 0, 20, 1, 1, 4), + MDP_COLOR_YUYV_10L = MDP_COLOR(0, 0, 1, 0, 1, 1, 0, 20, 1, 0, 5), + MDP_COLOR_YVYU_10L = MDP_COLOR(0, 0, 1, 0, 1, 1, 0, 20, 1, 1, 5), + MDP_COLOR_NV12_10L = MDP_COLOR(0, 0, 1, 0, 2, 1, 1, 10, 1, 0, 12), + MDP_COLOR_NV21_10L = MDP_COLOR(0, 0, 1, 0, 2, 1, 1, 10, 1, 1, 12), + MDP_COLOR_NV16_10L = MDP_COLOR(0, 0, 1, 0, 2, 1, 0, 10, 1, 0, 13), + MDP_COLOR_NV61_10L = MDP_COLOR(0, 0, 1, 0, 2, 1, 0, 10, 1, 1, 13), + MDP_COLOR_YV12_10L = MDP_COLOR(0, 0, 1, 0, 3, 1, 1, 10, 1, 1, 8), + MDP_COLOR_I420_10L = MDP_COLOR(0, 0, 1, 0, 3, 1, 1, 10, 1, 0, 8), }; static inline bool MDP_COLOR_IS_UV_COPLANE(enum mdp_color c) From patchwork Fri Jan 13 06:41:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moudy Ho X-Patchwork-Id: 642849 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 353A7C54EBD for ; Fri, 13 Jan 2023 06:57:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240774AbjAMG5C (ORCPT ); Fri, 13 Jan 2023 01:57:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56642 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235363AbjAMGz4 (ORCPT ); Fri, 13 Jan 2023 01:55:56 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9072F714AA; Thu, 12 Jan 2023 22:41:13 -0800 (PST) X-UUID: 428e24a8930d11eda06fc9ecc4dadd91-20230113 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=pgMKWf8cswrcZe1AKhWsFWsHR/fVUbTFef1NB0mRUw8=; b=hiLi3lUacpMceljQ6Lulvx1tGtUKnzahqxgcb2kXriMlg7az0RDhatdlA9N7jiDJCytWk3nQ2oaYEksYGGflNoJG9osuMlXgdSYpEZmiUSKymLdJcAImUlvm9KN7oe+CNcKqWQOCUumakldOZ4OIQQef7lmSeyjS09lLfBvnpyg=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.17, REQID:6e5401c6-6f8b-42c5-9521-515fe798d94f, IP:0, U RL:0,TC:0,Content:0,EDM:-30,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-30 X-CID-META: VersionHash:543e81c, CLOUDID:171b8c54-dd49-462e-a4be-2143a3ddc739, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:2,IP:nil,UR L:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0 X-CID-BVR: 0 X-UUID: 428e24a8930d11eda06fc9ecc4dadd91-20230113 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 801805891; Fri, 13 Jan 2023 14:41:07 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Fri, 13 Jan 2023 14:41:07 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Fri, 13 Jan 2023 14:41:07 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Matthias Brugger , Hans Verkuil CC: Chun-Kuang Hu , , , , , Moudy Ho Subject: [PATCH v5 09/12] media: platform: mtk-mdp3: dynamically allocate component clocks Date: Fri, 13 Jan 2023 14:41:01 +0800 Message-ID: <20230113064104.22402-10-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230113064104.22402-1-moudy.ho@mediatek.com> References: <20230113064104.22402-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org For extensibility of adding more MDP3 components in the further, the magic number is removed by dynamically allocating component clocks. Signed-off-by: Moudy Ho --- .../platform/mediatek/mdp3/mtk-mdp3-comp.c | 49 +++++++++++-------- .../platform/mediatek/mdp3/mtk-mdp3-comp.h | 3 +- 2 files changed, 31 insertions(+), 21 deletions(-) diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c index 8f4786cc4416..6288c11e979a 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c @@ -670,7 +670,8 @@ int mdp_comp_clock_on(struct device *dev, struct mdp_comp *comp) { int i, ret; - if (comp->comp_dev) { + /* Only DMA capable components need the pm control */ + if (comp->comp_dev && is_dma_capable(comp->type)) { ret = pm_runtime_resume_and_get(comp->comp_dev); if (ret < 0) { dev_err(dev, @@ -680,7 +681,7 @@ int mdp_comp_clock_on(struct device *dev, struct mdp_comp *comp) } } - for (i = 0; i < ARRAY_SIZE(comp->clks); i++) { + for (i = 0; i < comp->clk_num; i++) { if (IS_ERR_OR_NULL(comp->clks[i])) continue; ret = clk_prepare_enable(comp->clks[i]); @@ -700,7 +701,7 @@ int mdp_comp_clock_on(struct device *dev, struct mdp_comp *comp) continue; clk_disable_unprepare(comp->clks[i]); } - if (comp->comp_dev) + if (comp->comp_dev && is_dma_capable(comp->type)) pm_runtime_put_sync(comp->comp_dev); return ret; @@ -710,13 +711,13 @@ void mdp_comp_clock_off(struct device *dev, struct mdp_comp *comp) { int i; - for (i = 0; i < ARRAY_SIZE(comp->clks); i++) { + for (i = 0; i < comp->clk_num; i++) { if (IS_ERR_OR_NULL(comp->clks[i])) continue; clk_disable_unprepare(comp->clks[i]); } - if (comp->comp_dev) + if (comp->comp_dev && is_dma_capable(comp->type)) pm_runtime_put(comp->comp_dev); } @@ -795,7 +796,7 @@ static int mdp_comp_init(struct mdp_dev *mdp, struct device_node *node, struct mdp_comp *comp, enum mtk_mdp_comp_id id) { struct device *dev = &mdp->pdev->dev; - int clk_num; + struct platform_device *pdev_c; int clk_ofst; int i; s32 event; @@ -805,6 +806,14 @@ static int mdp_comp_init(struct mdp_dev *mdp, struct device_node *node, return -EINVAL; } + pdev_c = of_find_device_by_node(node); + if (!pdev_c) { + dev_warn(dev, "can't find platform device of node:%s\n", + node->name); + return -ENODEV; + } + + comp->comp_dev = &pdev_c->dev; comp->public_id = id; comp->type = mdp->mdp_data->comp_data[id].match.type; comp->inner_id = mdp->mdp_data->comp_data[id].match.inner_id; @@ -812,10 +821,15 @@ static int mdp_comp_init(struct mdp_dev *mdp, struct device_node *node, comp->ops = mdp_comp_ops[comp->type]; __mdp_comp_init(mdp, node, comp); - clk_num = mdp->mdp_data->comp_data[id].info.clk_num; + comp->clk_num = mdp->mdp_data->comp_data[id].info.clk_num; + comp->clks = devm_kzalloc(dev, sizeof(struct clk *) * comp->clk_num, + GFP_KERNEL); + if (!comp->clks) + return -ENOMEM; + clk_ofst = mdp->mdp_data->comp_data[id].info.clk_ofst; - for (i = 0; i < clk_num; i++) { + for (i = 0; i < comp->clk_num; i++) { comp->clks[i] = of_clk_get(node, i + clk_ofst); if (IS_ERR(comp->clks[i])) break; @@ -852,6 +866,11 @@ static void mdp_comp_deinit(struct mdp_comp *comp) if (!comp) return; + if (comp->comp_dev && comp->clks) { + devm_kfree(&comp->mdp_dev->pdev->dev, comp->clks); + comp->clks = NULL; + } + if (comp->regs) iounmap(comp->regs); } @@ -933,7 +952,8 @@ void mdp_comp_destroy(struct mdp_dev *mdp) for (i = 0; i < ARRAY_SIZE(mdp->comp); i++) { if (mdp->comp[i]) { - pm_runtime_disable(mdp->comp[i]->comp_dev); + if (is_dma_capable(mdp->comp[i]->type)) + pm_runtime_disable(mdp->comp[i]->comp_dev); mdp_comp_deinit(mdp->comp[i]); devm_kfree(mdp->comp[i]->comp_dev, mdp->comp[i]); mdp->comp[i] = NULL; @@ -945,7 +965,6 @@ int mdp_comp_config(struct mdp_dev *mdp) { struct device *dev = &mdp->pdev->dev; struct device_node *node, *parent; - struct platform_device *pdev; int ret; memset(mdp_comp_alias_id, 0, sizeof(mdp_comp_alias_id)); @@ -986,18 +1005,8 @@ int mdp_comp_config(struct mdp_dev *mdp) } /* Only DMA capable components need the pm control */ - comp->comp_dev = NULL; if (!is_dma_capable(comp->type)) continue; - - pdev = of_find_device_by_node(node); - if (!pdev) { - dev_warn(dev, "can't find platform device of node:%s\n", - node->name); - return -ENODEV; - } - - comp->comp_dev = &pdev->dev; pm_runtime_enable(comp->comp_dev); } diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h index 5188aa0821c4..8d2ab9184f58 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h @@ -159,7 +159,8 @@ struct mdp_comp { void __iomem *regs; phys_addr_t reg_base; u8 subsys_id; - struct clk *clks[6]; + u8 clk_num; + struct clk **clks; struct device *comp_dev; enum mdp_comp_type type; enum mtk_mdp_comp_id public_id; From patchwork Fri Jan 13 06:41:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moudy Ho X-Patchwork-Id: 642847 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4EADC677F1 for ; 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Fri, 13 Jan 2023 14:41:07 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Matthias Brugger , Hans Verkuil CC: Chun-Kuang Hu , , , , , Moudy Ho Subject: [PATCH v5 11/12] media: platform: mtk-mdp3: decompose hardware-related information in shared memory Date: Fri, 13 Jan 2023 14:41:03 +0800 Message-ID: <20230113064104.22402-12-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230113064104.22402-1-moudy.ho@mediatek.com> References: <20230113064104.22402-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The communication between the MDP3 kernel driver and SCP is to pass a shared memory through the cooperation of "mtk-mdp3-vpu.c" and remoteproc driver. The data structure of this shared memory is defined in "mtk-img-ipi.h", as shown below: vpu->work_addr -> +-----------------------------------------+ | | | To SCP : Input frame parameters | | (struct img_ipi_frameparam) | | | vpu->pool -> +-----------------------------------------+ | | | From SCP : Output component config pool | | (struct img_config) | | | | *struct img_config 1 | | | | | | | | v | | *struct img_config N | | (N = MDP_CONFIG_POOL_SIZE) | +-----------------------------------------+ One output component configuration contains the components currently used by the pipeline, and has the register settings that each component needs to set. Since the quantity, type and function of components on each chip will vary, the effect is that the size of the "struct img_config" and its substructures will be different on each chip. In addition, all chips will have to update their SCP firmware for every change if the output component config structure is defined and shared by a common header. Therefore, all functions that operate on "struct img_config" and its substructures must be separated by chips and so are the relevant definations. Signed-off-by: Moudy Ho --- .../mediatek/mdp3/mt8183/mdp3-comp-mt8183.h | 144 +++++++ .../platform/mediatek/mdp3/mtk-img-ipi.h | 143 ++----- .../platform/mediatek/mdp3/mtk-mdp3-cmdq.c | 118 ++++-- .../platform/mediatek/mdp3/mtk-mdp3-comp.c | 364 +++++++++++++----- .../platform/mediatek/mdp3/mtk-mdp3-core.c | 1 + .../platform/mediatek/mdp3/mtk-mdp3-core.h | 1 + 6 files changed, 522 insertions(+), 249 deletions(-) create mode 100644 drivers/media/platform/mediatek/mdp3/mt8183/mdp3-comp-mt8183.h diff --git a/drivers/media/platform/mediatek/mdp3/mt8183/mdp3-comp-mt8183.h b/drivers/media/platform/mediatek/mdp3/mt8183/mdp3-comp-mt8183.h new file mode 100644 index 000000000000..f6db24060403 --- /dev/null +++ b/drivers/media/platform/mediatek/mdp3/mt8183/mdp3-comp-mt8183.h @@ -0,0 +1,144 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Ping-Hsun Wu + */ + +#ifndef __MDP3_COMP_MT8183_H__ +#define __MDP3_COMP_MT8183_H__ + +#include "mtk-mdp3-type.h" + +/* + * ISP-MDP generic output information + * MD5 of the target SCP blob: + * 6da52bdcf4bf76a0983b313e1d4745d6 + */ + +#define IMG_MAX_SUBFRAMES_8183 14 + +struct img_comp_frame_8183 { + u32 output_disable:1; + u32 bypass:1; + u16 in_width; + u16 in_height; + u16 out_width; + u16 out_height; + struct img_crop crop; + u16 in_total_width; + u16 out_total_width; +} __packed; + +struct img_comp_subfrm_8183 { + u32 tile_disable:1; + struct img_region in; + struct img_region out; + struct img_offset luma; + struct img_offset chroma; + s16 out_vertical; /* Output vertical index */ + s16 out_horizontal; /* Output horizontal index */ +} __packed; + +struct mdp_rdma_subfrm_8183 { + u32 offset[IMG_MAX_PLANES]; + u32 offset_0_p; + u32 src; + u32 clip; + u32 clip_ofst; +} __packed; + +struct mdp_rdma_data_8183 { + u32 src_ctrl; + u32 control; + u32 iova[IMG_MAX_PLANES]; + u32 iova_end[IMG_MAX_PLANES]; + u32 mf_bkgd; + u32 mf_bkgd_in_pxl; + u32 sf_bkgd; + u32 ufo_dec_y; + u32 ufo_dec_c; + u32 transform; + struct mdp_rdma_subfrm_8183 subfrms[IMG_MAX_SUBFRAMES_8183]; +} __packed; + +struct mdp_rsz_subfrm_8183 { + u32 control2; + u32 src; + u32 clip; +} __packed; + +struct mdp_rsz_data_8183 { + u32 coeff_step_x; + u32 coeff_step_y; + u32 control1; + u32 control2; + struct mdp_rsz_subfrm_8183 subfrms[IMG_MAX_SUBFRAMES_8183]; +} __packed; + +struct mdp_wrot_subfrm_8183 { + u32 offset[IMG_MAX_PLANES]; + u32 src; + u32 clip; + u32 clip_ofst; + u32 main_buf; +} __packed; + +struct mdp_wrot_data_8183 { + u32 iova[IMG_MAX_PLANES]; + u32 control; + u32 stride[IMG_MAX_PLANES]; + u32 mat_ctrl; + u32 fifo_test; + u32 filter; + struct mdp_wrot_subfrm_8183 subfrms[IMG_MAX_SUBFRAMES_8183]; +} __packed; + +struct mdp_wdma_subfrm_8183 { + u32 offset[IMG_MAX_PLANES]; + u32 src; + u32 clip; + u32 clip_ofst; +} __packed; + +struct mdp_wdma_data_8183 { + u32 wdma_cfg; + u32 iova[IMG_MAX_PLANES]; + u32 w_in_byte; + u32 uv_stride; + struct mdp_wdma_subfrm_8183 subfrms[IMG_MAX_SUBFRAMES_8183]; +} __packed; + +struct isp_data_8183 { + u64 dl_flags; /* 1 << (enum mdp_comp_type) */ + u32 smxi_iova[4]; + u32 cq_idx; + u32 cq_iova; + u32 tpipe_iova[IMG_MAX_SUBFRAMES_8183]; +} __packed; + +struct img_compparam_8183 { + u16 type; /* enum mdp_comp_id */ + u16 id; /* engine alias_id */ + u32 input; + u32 outputs[IMG_MAX_HW_OUTPUTS]; + u32 num_outputs; + struct img_comp_frame_8183 frame; + struct img_comp_subfrm_8183 subfrms[IMG_MAX_SUBFRAMES_8183]; + u32 num_subfrms; + union { + struct mdp_rdma_data_8183 rdma; + struct mdp_rsz_data_8183 rsz; + struct mdp_wrot_data_8183 wrot; + struct mdp_wdma_data_8183 wdma; + struct isp_data_8183 isp; + }; +} __packed; + +struct img_config_8183 { + struct img_compparam_8183 components[IMG_MAX_COMPONENTS]; + u32 num_components; + struct img_mmsys_ctrl ctrls[IMG_MAX_SUBFRAMES_8183]; + u32 num_subfrms; +} __packed; + +#endif /* __MDP3_COMP_MT8183_H__ */ diff --git a/drivers/media/platform/mediatek/mdp3/mtk-img-ipi.h b/drivers/media/platform/mediatek/mdp3/mtk-img-ipi.h index 239578f9ff96..8c519924a78b 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-img-ipi.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-img-ipi.h @@ -9,13 +9,11 @@ #define __MTK_IMG_IPI_H__ #include +#include #include "mtk-mdp3-type.h" +#include "mt8183/mdp3-comp-mt8183.h" -/* - * ISP-MDP generic input information - * MD5 of the target SCP blob: - * 6da52bdcf4bf76a0983b313e1d4745d6 - */ +/* ISP-MDP generic input information */ #define IMG_IPI_INIT 1 #define IMG_IPI_DEINIT 2 @@ -116,132 +114,37 @@ struct img_frameparam { struct img_ipi_frameparam frameparam; } __packed; -/* ISP-MDP generic output information */ +/* Platform config indicator */ +#define MT8183 8183 -struct img_comp_frame { - u32 output_disable; - u32 bypass; - u32 in_width; - u32 in_height; - u32 out_width; - u32 out_height; - struct img_crop crop; - u32 in_total_width; - u32 out_total_width; -} __packed; +#define CFG_CHECK(plat, p_id) (plat == p_id) -struct img_comp_subfrm { - u32 tile_disable; - struct img_region in; - struct img_region out; - struct img_offset luma; - struct img_offset chroma; - s32 out_vertical; /* Output vertical index */ - s32 out_horizontal; /* Output horizontal index */ -} __packed; +#define _CFG_OFST(plat, cfg, ofst) ((void *)(&(cfg->config_##plat) + ofst)) +#define CFG_OFST(plat, cfg, ofst) \ + (IS_ERR_OR_NULL(cfg) ? NULL : _CFG_OFST(plat, cfg, ofst)) -#define IMG_MAX_SUBFRAMES 14 +#define _CFG_ADDR(plat, cfg, mem) (&(cfg->config_##plat.mem)) +#define CFG_ADDR(plat, cfg, mem) \ + (IS_ERR_OR_NULL(cfg) ? NULL : _CFG_ADDR(plat, cfg, mem)) -struct mdp_rdma_subfrm { - u32 offset[IMG_MAX_PLANES]; - u32 offset_0_p; - u32 src; - u32 clip; - u32 clip_ofst; -} __packed; +#define _CFG_GET(plat, cfg, mem) (cfg->config_##plat.mem) +#define CFG_GET(plat, cfg, mem) \ + (IS_ERR_OR_NULL(cfg) ? 0 : _CFG_GET(plat, cfg, mem)) -struct mdp_rdma_data { - u32 src_ctrl; - u32 control; - u32 iova[IMG_MAX_PLANES]; - u32 iova_end[IMG_MAX_PLANES]; - u32 mf_bkgd; - u32 mf_bkgd_in_pxl; - u32 sf_bkgd; - u32 ufo_dec_y; - u32 ufo_dec_c; - u32 transform; - struct mdp_rdma_subfrm subfrms[IMG_MAX_SUBFRAMES]; -} __packed; +#define _CFG_COMP(plat, comp, mem) (comp->comp_##plat.mem) +#define CFG_COMP(plat, comp, mem) \ + (IS_ERR_OR_NULL(comp) ? 0 : _CFG_COMP(plat, comp, mem)) -struct mdp_rsz_subfrm { - u32 control2; - u32 src; - u32 clip; -} __packed; - -struct mdp_rsz_data { - u32 coeff_step_x; - u32 coeff_step_y; - u32 control1; - u32 control2; - struct mdp_rsz_subfrm subfrms[IMG_MAX_SUBFRAMES]; -} __packed; - -struct mdp_wrot_subfrm { - u32 offset[IMG_MAX_PLANES]; - u32 src; - u32 clip; - u32 clip_ofst; - u32 main_buf; -} __packed; - -struct mdp_wrot_data { - u32 iova[IMG_MAX_PLANES]; - u32 control; - u32 stride[IMG_MAX_PLANES]; - u32 mat_ctrl; - u32 fifo_test; - u32 filter; - struct mdp_wrot_subfrm subfrms[IMG_MAX_SUBFRAMES]; -} __packed; - -struct mdp_wdma_subfrm { - u32 offset[IMG_MAX_PLANES]; - u32 src; - u32 clip; - u32 clip_ofst; -} __packed; - -struct mdp_wdma_data { - u32 wdma_cfg; - u32 iova[IMG_MAX_PLANES]; - u32 w_in_byte; - u32 uv_stride; - struct mdp_wdma_subfrm subfrms[IMG_MAX_SUBFRAMES]; -} __packed; - -struct isp_data { - u64 dl_flags; /* 1 << (enum mdp_comp_type) */ - u32 smxi_iova[4]; - u32 cq_idx; - u32 cq_iova; - u32 tpipe_iova[IMG_MAX_SUBFRAMES]; +struct img_config { + union { + struct img_config_8183 config_8183; + }; } __packed; struct img_compparam { - u32 type; /* enum mdp_comp_id */ - u32 id; /* engine alias_id */ - u32 input; - u32 outputs[IMG_MAX_HW_OUTPUTS]; - u32 num_outputs; - struct img_comp_frame frame; - struct img_comp_subfrm subfrms[IMG_MAX_SUBFRAMES]; - u32 num_subfrms; union { - struct mdp_rdma_data rdma; - struct mdp_rsz_data rsz; - struct mdp_wrot_data wrot; - struct mdp_wdma_data wdma; - struct isp_data isp; + struct img_compparam_8183 comp_8183; }; } __packed; -struct img_config { - struct img_compparam components[IMG_MAX_COMPONENTS]; - u32 num_components; - struct img_mmsys_ctrl ctrls[IMG_MAX_SUBFRAMES]; - u32 num_subfrms; -} __packed; - #endif /* __MTK_IMG_IPI_H__ */ diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c index bff14e4944c5..b2ae2f88cbb9 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c @@ -10,6 +10,7 @@ #include "mtk-mdp3-comp.h" #include "mtk-mdp3-core.h" #include "mtk-mdp3-m2m.h" +#include "mtk-img-ipi.h" #define MDP_PATH_MAX_COMPS IMG_MAX_COMPONENTS @@ -28,24 +29,34 @@ struct mdp_path { #define call_op(ctx, op, ...) \ (has_op(ctx, op) ? (ctx)->comp->ops->op(ctx, ##__VA_ARGS__) : 0) -static bool is_output_disabled(const struct img_compparam *param, u32 count) +static bool is_output_disabled(int p_id, const struct img_compparam *param, u32 count) { - return (count < param->num_subfrms) ? - (param->frame.output_disable || - param->subfrms[count].tile_disable) : - true; + u32 num = 0; + bool dis_output, dis_tile; + + if (CFG_CHECK(MT8183, p_id)) { + num = CFG_COMP(MT8183, param, num_subfrms); + dis_output = CFG_COMP(MT8183, param, frame.output_disable); + dis_tile = CFG_COMP(MT8183, param, frame.output_disable); + } + + return (count < num) ? (dis_output || dis_tile) : true; } static int mdp_path_subfrm_require(const struct mdp_path *path, struct mdp_cmdq_cmd *cmd, s32 *mutex_id, u32 count) { - const struct img_config *config = path->config; + const int p_id = path->mdp_dev->mdp_data->mdp_plat_id; const struct mdp_comp_ctx *ctx; const struct mtk_mdp_driver_data *data = path->mdp_dev->mdp_data; struct device *dev = &path->mdp_dev->pdev->dev; struct mtk_mutex **mutex = path->mdp_dev->mdp_mutex; int id, index; + u32 num_comp = 0; + + if (CFG_CHECK(MT8183, p_id)) + num_comp = CFG_GET(MT8183, path->config, num_components); /* Decide which mutex to use based on the current pipeline */ switch (path->comps[0].comp->public_id) { @@ -68,9 +79,9 @@ static int mdp_path_subfrm_require(const struct mdp_path *path, *mutex_id = data->pipe_info[index].mutex_id; /* Set mutex mod */ - for (index = 0; index < config->num_components; index++) { + for (index = 0; index < num_comp; index++) { ctx = &path->comps[index]; - if (is_output_disabled(ctx->param, count)) + if (is_output_disabled(p_id, ctx->param, count)) continue; id = ctx->comp->public_id; mtk_mutex_write_mod(mutex[*mutex_id], @@ -87,11 +98,12 @@ static int mdp_path_subfrm_run(const struct mdp_path *path, struct mdp_cmdq_cmd *cmd, s32 *mutex_id, u32 count) { - const struct img_config *config = path->config; + const int p_id = path->mdp_dev->mdp_data->mdp_plat_id; const struct mdp_comp_ctx *ctx; struct device *dev = &path->mdp_dev->pdev->dev; struct mtk_mutex **mutex = path->mdp_dev->mdp_mutex; int index; + u32 num_comp = 0; s32 event; if (-1 == *mutex_id) { @@ -99,11 +111,14 @@ static int mdp_path_subfrm_run(const struct mdp_path *path, return -EINVAL; } + if (CFG_CHECK(MT8183, p_id)) + num_comp = CFG_GET(MT8183, path->config, num_components); + /* Wait WROT SRAM shared to DISP RDMA */ /* Clear SOF event for each engine */ - for (index = 0; index < config->num_components; index++) { + for (index = 0; index < num_comp; index++) { ctx = &path->comps[index]; - if (is_output_disabled(ctx->param, count)) + if (is_output_disabled(p_id, ctx->param, count)) continue; event = ctx->comp->gce_event[MDP_GCE_EVENT_SOF]; if (event != MDP_GCE_NO_EVENT) @@ -114,9 +129,9 @@ static int mdp_path_subfrm_run(const struct mdp_path *path, mtk_mutex_enable_by_cmdq(mutex[*mutex_id], (void *)&cmd->pkt); /* Wait SOF events and clear mutex modules (optional) */ - for (index = 0; index < config->num_components; index++) { + for (index = 0; index < num_comp; index++) { ctx = &path->comps[index]; - if (is_output_disabled(ctx->param, count)) + if (is_output_disabled(p_id, ctx->param, count)) continue; event = ctx->comp->gce_event[MDP_GCE_EVENT_SOF]; if (event != MDP_GCE_NO_EVENT) @@ -128,16 +143,22 @@ static int mdp_path_subfrm_run(const struct mdp_path *path, static int mdp_path_ctx_init(struct mdp_dev *mdp, struct mdp_path *path) { - const struct img_config *config = path->config; + const int p_id = mdp->mdp_data->mdp_plat_id; + void *param = NULL; int index, ret; + u32 num_comp = 0; + + if (CFG_CHECK(MT8183, p_id)) + num_comp = CFG_GET(MT8183, path->config, num_components); - if (config->num_components < 1) + if (num_comp < 1) return -EINVAL; - for (index = 0; index < config->num_components; index++) { + for (index = 0; index < num_comp; index++) { + if (CFG_CHECK(MT8183, p_id)) + param = (void *)CFG_ADDR(MT8183, path->config, components[index]); ret = mdp_comp_ctx_config(mdp, &path->comps[index], - &config->components[index], - path->param); + param, path->param); if (ret) return ret; } @@ -148,12 +169,19 @@ static int mdp_path_ctx_init(struct mdp_dev *mdp, struct mdp_path *path) static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd, struct mdp_path *path, u32 count) { - const struct img_config *config = path->config; - const struct img_mmsys_ctrl *ctrl = &config->ctrls[count]; + const int p_id = path->mdp_dev->mdp_data->mdp_plat_id; + const struct img_mmsys_ctrl *ctrl = NULL; const struct img_mux *set; struct mdp_comp_ctx *ctx; s32 mutex_id; int index, ret; + u32 num_comp = 0; + + if (CFG_CHECK(MT8183, p_id)) + num_comp = CFG_GET(MT8183, path->config, num_components); + + if (CFG_CHECK(MT8183, p_id)) + ctrl = CFG_ADDR(MT8183, path->config, ctrls[count]); /* Acquire components */ ret = mdp_path_subfrm_require(path, cmd, &mutex_id, count); @@ -166,9 +194,9 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd, set->value, 0xFFFFFFFF); } /* Config sub-frame information */ - for (index = (config->num_components - 1); index >= 0; index--) { + for (index = (num_comp - 1); index >= 0; index--) { ctx = &path->comps[index]; - if (is_output_disabled(ctx->param, count)) + if (is_output_disabled(p_id, ctx->param, count)) continue; ret = call_op(ctx, config_subfrm, cmd, count); if (ret) @@ -179,16 +207,16 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd, if (ret) return ret; /* Wait components done */ - for (index = 0; index < config->num_components; index++) { + for (index = 0; index < num_comp; index++) { ctx = &path->comps[index]; - if (is_output_disabled(ctx->param, count)) + if (is_output_disabled(p_id, ctx->param, count)) continue; ret = call_op(ctx, wait_comp_event, cmd); if (ret) return ret; } /* Advance to the next sub-frame */ - for (index = 0; index < config->num_components; index++) { + for (index = 0; index < num_comp; index++) { ctx = &path->comps[index]; ret = call_op(ctx, advance_subfrm, cmd, count); if (ret) @@ -207,23 +235,35 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd, static int mdp_path_config(struct mdp_dev *mdp, struct mdp_cmdq_cmd *cmd, struct mdp_path *path) { - const struct img_config *config = path->config; + const int p_id = mdp->mdp_data->mdp_plat_id; struct mdp_comp_ctx *ctx; int index, count, ret; + u32 num_comp = 0; + u32 num_sub = 0; + + if (CFG_CHECK(MT8183, p_id)) + num_comp = CFG_GET(MT8183, path->config, num_components); + + if (CFG_CHECK(MT8183, p_id)) + num_sub = CFG_GET(MT8183, path->config, num_subfrms); /* Config path frame */ /* Reset components */ - for (index = 0; index < config->num_components; index++) { + for (index = 0; index < num_comp; index++) { ctx = &path->comps[index]; ret = call_op(ctx, init_comp, cmd); if (ret) return ret; } /* Config frame mode */ - for (index = 0; index < config->num_components; index++) { - const struct v4l2_rect *compose = - path->composes[ctx->param->outputs[0]]; + for (index = 0; index < num_comp; index++) { + const struct v4l2_rect *compose; + u32 out = 0; + if (CFG_CHECK(MT8183, p_id)) + out = CFG_COMP(MT8183, ctx->param, outputs[0]); + + compose = path->composes[out]; ctx = &path->comps[index]; ret = call_op(ctx, config_frame, cmd, compose); if (ret) @@ -231,13 +271,13 @@ static int mdp_path_config(struct mdp_dev *mdp, struct mdp_cmdq_cmd *cmd, } /* Config path sub-frames */ - for (count = 0; count < config->num_subfrms; count++) { + for (count = 0; count < num_sub; count++) { ret = mdp_path_config_subfrm(cmd, path, count); if (ret) return ret; } /* Post processing information */ - for (index = 0; index < config->num_components; index++) { + for (index = 0; index < num_comp; index++) { ctx = &path->comps[index]; ret = call_op(ctx, post_process, cmd); if (ret) @@ -361,7 +401,9 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param) struct mdp_cmdq_cmd *cmd = NULL; struct mdp_comp *comps = NULL; struct device *dev = &mdp->pdev->dev; + const int p_id = mdp->mdp_data->mdp_plat_id; int i, ret; + u32 num_comp = 0; atomic_inc(&mdp->job_count); if (atomic_read(&mdp->suspended)) { @@ -379,8 +421,11 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param) if (ret) goto err_free_cmd; - comps = kcalloc(param->config->num_components, sizeof(*comps), - GFP_KERNEL); + if (CFG_CHECK(MT8183, p_id)) + num_comp = CFG_GET(MT8183, param->config, num_components); + else + goto err_destroy_pkt; + comps = kcalloc(num_comp, sizeof(*comps), GFP_KERNEL); if (!comps) { ret = -ENOMEM; goto err_destroy_pkt; @@ -412,7 +457,6 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param) path->composes[i] = param->composes[i] ? param->composes[i] : &path->bounds[i]; } - ret = mdp_path_ctx_init(mdp, path); if (ret) { dev_err(dev, "mdp_path_ctx_init error\n"); @@ -426,7 +470,7 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param) } cmdq_pkt_finalize(&cmd->pkt); - for (i = 0; i < param->config->num_components; i++) + for (i = 0; i < num_comp; i++) memcpy(&comps[i], path->comps[i].comp, sizeof(struct mdp_comp)); @@ -435,7 +479,7 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param) cmd->user_cmdq_cb = param->cmdq_cb; cmd->user_cb_data = param->cb_data; cmd->comps = comps; - cmd->num_comps = param->config->num_components; + cmd->num_comps = num_comp; cmd->mdp_ctx = param->mdp_ctx; ret = mdp_comp_clocks_on(&mdp->pdev->dev, cmd->comps, cmd->num_comps); diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c index 6288c11e979a..576b90a2fb9d 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c @@ -19,6 +19,7 @@ #include "mdp_reg_wdma.h" static u32 mdp_comp_alias_id[MDP_COMP_TYPE_COUNT]; +static int p_id; static inline const struct mdp_platform_config * __get_plat_cfg(const struct mdp_comp_ctx *ctx) @@ -107,13 +108,13 @@ static int config_rdma_frame(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd, const struct v4l2_rect *compose) { - const struct mdp_rdma_data *rdma = &ctx->param->rdma; const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx); u32 colorformat = ctx->input->buffer.format.colorformat; bool block10bit = MDP_COLOR_IS_10BIT_PACKED(colorformat); bool en_ufo = MDP_COLOR_IS_UFP(colorformat); phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; + u32 reg = 0; if (mdp_cfg && mdp_cfg->rdma_support_10bit) { if (block10bit) @@ -131,49 +132,78 @@ static int config_rdma_frame(struct mdp_comp_ctx *ctx, 0x00030071); /* Setup source frame info */ - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_CON, rdma->src_ctrl, + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.src_ctrl); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_CON, reg, 0x03C8FE0F); if (mdp_cfg) if (mdp_cfg->rdma_support_10bit && en_ufo) { /* Setup source buffer base */ + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.ufo_dec_y); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_UFO_DEC_LENGTH_BASE_Y, - rdma->ufo_dec_y, 0xFFFFFFFF); + reg, 0xFFFFFFFF); + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.ufo_dec_c); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_UFO_DEC_LENGTH_BASE_C, - rdma->ufo_dec_c, 0xFFFFFFFF); + reg, 0xFFFFFFFF); /* Set 10bit source frame pitch */ - if (block10bit) + if (block10bit) { + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.mf_bkgd_in_pxl); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_BKGD_SIZE_IN_PXL, - rdma->mf_bkgd_in_pxl, 0x001FFFFF); + reg, 0x001FFFFF); + } } - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_CON, rdma->control, + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.control); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_CON, reg, 0x1110); /* Setup source buffer base */ - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_0, rdma->iova[0], + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.iova[0]); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_0, reg, 0xFFFFFFFF); - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_1, rdma->iova[1], + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.iova[1]); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_1, reg, 0xFFFFFFFF); - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_2, rdma->iova[2], + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.iova[2]); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_2, reg, 0xFFFFFFFF); /* Setup source buffer end */ + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.iova_end[0]); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_0, - rdma->iova_end[0], 0xFFFFFFFF); + reg, 0xFFFFFFFF); + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.iova_end[1]); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_1, - rdma->iova_end[1], 0xFFFFFFFF); + reg, 0xFFFFFFFF); + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.iova_end[2]); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_2, - rdma->iova_end[2], 0xFFFFFFFF); + reg, 0xFFFFFFFF); /* Setup source frame pitch */ + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.mf_bkgd); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_BKGD_SIZE_IN_BYTE, - rdma->mf_bkgd, 0x001FFFFF); + reg, 0x001FFFFF); + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.sf_bkgd); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SF_BKGD_SIZE_IN_BYTE, - rdma->sf_bkgd, 0x001FFFFF); + reg, 0x001FFFFF); /* Setup color transform */ + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.transform); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_TRANSFORM_0, - rdma->transform, 0x0F110000); + reg, 0x0F110000); return 0; } @@ -181,47 +211,67 @@ static int config_rdma_frame(struct mdp_comp_ctx *ctx, static int config_rdma_subfrm(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd, u32 index) { - const struct mdp_rdma_subfrm *subfrm = &ctx->param->rdma.subfrms[index]; - const struct img_comp_subfrm *csf = &ctx->param->subfrms[index]; const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx); u32 colorformat = ctx->input->buffer.format.colorformat; bool block10bit = MDP_COLOR_IS_10BIT_PACKED(colorformat); bool en_ufo = MDP_COLOR_IS_UFP(colorformat); phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; + u32 csf_l = 0, csf_r = 0; + u32 reg = 0; /* Enable RDMA */ MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_EN, BIT(0), BIT(0)); /* Set Y pixel offset */ + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset[0]); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_0, - subfrm->offset[0], 0xFFFFFFFF); + reg, 0xFFFFFFFF); /* Set 10bit UFO mode */ - if (mdp_cfg) - if (mdp_cfg->rdma_support_10bit && block10bit && en_ufo) + if (mdp_cfg) { + if (mdp_cfg->rdma_support_10bit && block10bit && en_ufo) { + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset_0_p); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_0_P, - subfrm->offset_0_p, 0xFFFFFFFF); + reg, 0xFFFFFFFF); + } + } /* Set U pixel offset */ + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset[1]); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_1, - subfrm->offset[1], 0xFFFFFFFF); + reg, 0xFFFFFFFF); /* Set V pixel offset */ + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset[2]); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_2, - subfrm->offset[2], 0xFFFFFFFF); + reg, 0xFFFFFFFF); /* Set source size */ - MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_SRC_SIZE, subfrm->src, + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].src); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_SRC_SIZE, reg, 0x1FFF1FFF); /* Set target size */ + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].clip); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_CLIP_SIZE, - subfrm->clip, 0x1FFF1FFF); + reg, 0x1FFF1FFF); /* Set crop offset */ + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].clip_ofst); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_OFFSET_1, - subfrm->clip_ofst, 0x003F001F); + reg, 0x003F001F); + if (CFG_CHECK(MT8183, p_id)) { + csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left); + csf_r = CFG_COMP(MT8183, ctx->param, subfrms[index].in.right); + } if (mdp_cfg && mdp_cfg->rdma_upsample_repeat_only) - if ((csf->in.right - csf->in.left + 1) > 320) + if ((csf_r - csf_l + 1) > 320) MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_RESV_DUMMY_0, BIT(2), BIT(2)); @@ -269,63 +319,97 @@ static int config_rsz_frame(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd, const struct v4l2_rect *compose) { - const struct mdp_rsz_data *rsz = &ctx->param->rsz; phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; + bool bypass = FALSE; + u32 reg = 0; - if (ctx->param->frame.bypass) { + if (CFG_CHECK(MT8183, p_id)) + bypass = CFG_COMP(MT8183, ctx->param, frame.bypass); + + if (bypass) { /* Disable RSZ */ MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, 0x0, BIT(0)); return 0; } - MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_1, rsz->control1, + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rsz.control1); + MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_1, reg, 0x03FFFDF3); - MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_2, rsz->control2, + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rsz.control2); + MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_2, reg, 0x0FFFC290); + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rsz.coeff_step_x); MM_REG_WRITE(cmd, subsys_id, base, PRZ_HORIZONTAL_COEFF_STEP, - rsz->coeff_step_x, 0x007FFFFF); + reg, 0x007FFFFF); + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rsz.coeff_step_y); MM_REG_WRITE(cmd, subsys_id, base, PRZ_VERTICAL_COEFF_STEP, - rsz->coeff_step_y, 0x007FFFFF); + reg, 0x007FFFFF); return 0; } static int config_rsz_subfrm(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd, u32 index) { - const struct mdp_rsz_subfrm *subfrm = &ctx->param->rsz.subfrms[index]; - const struct img_comp_subfrm *csf = &ctx->param->subfrms[index]; const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx); phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; + u32 csf_l = 0, csf_r = 0; + u32 reg = 0; - MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_2, subfrm->control2, + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rsz.subfrms[index].control2); + MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_2, reg, 0x00003800); - MM_REG_WRITE(cmd, subsys_id, base, PRZ_INPUT_IMAGE, subfrm->src, + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rsz.subfrms[index].src); + MM_REG_WRITE(cmd, subsys_id, base, PRZ_INPUT_IMAGE, reg, 0xFFFFFFFF); + if (CFG_CHECK(MT8183, p_id)) { + csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left); + csf_r = CFG_COMP(MT8183, ctx->param, subfrms[index].in.right); + } if (mdp_cfg && mdp_cfg->rsz_disable_dcm_small_sample) - if ((csf->in.right - csf->in.left + 1) <= 16) + if ((csf_r - csf_l + 1) <= 16) MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_1, BIT(27), BIT(27)); + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.left); MM_REG_WRITE(cmd, subsys_id, base, PRZ_LUMA_HORIZONTAL_INTEGER_OFFSET, - csf->luma.left, 0xFFFF); + reg, 0xFFFF); + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.left_subpix); MM_REG_WRITE(cmd, subsys_id, base, PRZ_LUMA_HORIZONTAL_SUBPIXEL_OFFSET, - csf->luma.left_subpix, 0x1FFFFF); + reg, 0x1FFFFF); + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.top); MM_REG_WRITE(cmd, subsys_id, base, PRZ_LUMA_VERTICAL_INTEGER_OFFSET, - csf->luma.top, 0xFFFF); + reg, 0xFFFF); + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.top_subpix); MM_REG_WRITE(cmd, subsys_id, base, PRZ_LUMA_VERTICAL_SUBPIXEL_OFFSET, - csf->luma.top_subpix, 0x1FFFFF); + reg, 0x1FFFFF); + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, subfrms[index].chroma.left); MM_REG_WRITE(cmd, subsys_id, base, PRZ_CHROMA_HORIZONTAL_INTEGER_OFFSET, - csf->chroma.left, 0xFFFF); + reg, 0xFFFF); + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, subfrms[index].chroma.left_subpix); MM_REG_WRITE(cmd, subsys_id, base, PRZ_CHROMA_HORIZONTAL_SUBPIXEL_OFFSET, - csf->chroma.left_subpix, 0x1FFFFF); + reg, 0x1FFFFF); - MM_REG_WRITE(cmd, subsys_id, base, PRZ_OUTPUT_IMAGE, subfrm->clip, + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, rsz.subfrms[index].clip); + MM_REG_WRITE(cmd, subsys_id, base, PRZ_OUTPUT_IMAGE, reg, 0xFFFFFFFF); return 0; @@ -337,11 +421,16 @@ static int advance_rsz_subfrm(struct mdp_comp_ctx *ctx, const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx); if (mdp_cfg && mdp_cfg->rsz_disable_dcm_small_sample) { - const struct img_comp_subfrm *csf = &ctx->param->subfrms[index]; phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; + u32 csf_l = 0, csf_r = 0; - if ((csf->in.right - csf->in.left + 1) <= 16) + if (CFG_CHECK(MT8183, p_id)) { + csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left); + csf_r = CFG_COMP(MT8183, ctx->param, subfrms[index].in.right); + } + + if ((csf_r - csf_l + 1) <= 16) MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_1, 0x0, BIT(27)); } @@ -374,31 +463,47 @@ static int config_wrot_frame(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd, const struct v4l2_rect *compose) { - const struct mdp_wrot_data *wrot = &ctx->param->wrot; const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx); phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; + u32 reg = 0; /* Write frame base address */ - MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR, wrot->iova[0], + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wrot.iova[0]); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR, reg, 0xFFFFFFFF); - MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_C, wrot->iova[1], + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wrot.iova[1]); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_C, reg, 0xFFFFFFFF); - MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_V, wrot->iova[2], + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wrot.iova[2]); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_V, reg, 0xFFFFFFFF); /* Write frame related registers */ - MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL, wrot->control, + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wrot.control); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL, reg, 0xF131510F); /* Write frame Y pitch */ - MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE, wrot->stride[0], + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wrot.stride[0]); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE, reg, 0x0000FFFF); /* Write frame UV pitch */ - MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE_C, wrot->stride[1], + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wrot.stride[1]); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE_C, reg, 0xFFFF); - MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE_V, wrot->stride[2], + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wrot.stride[2]); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE_V, reg, 0xFFFF); /* Write matrix control */ - MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAT_CTRL, wrot->mat_ctrl, 0xF3); + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wrot.mat_ctrl); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAT_CTRL, reg, 0xF3); /* Set the fixed ALPHA as 0xFF */ MM_REG_WRITE(cmd, subsys_id, base, VIDO_DITHER, 0xFF000000, @@ -406,13 +511,18 @@ static int config_wrot_frame(struct mdp_comp_ctx *ctx, /* Set VIDO_EOL_SEL */ MM_REG_WRITE(cmd, subsys_id, base, VIDO_RSV_1, BIT(31), BIT(31)); /* Set VIDO_FIFO_TEST */ - if (wrot->fifo_test != 0) + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wrot.fifo_test); + if (reg != 0) MM_REG_WRITE(cmd, subsys_id, base, VIDO_FIFO_TEST, - wrot->fifo_test, 0xFFF); + reg, 0xFFF); /* Filter enable */ - if (mdp_cfg && mdp_cfg->wrot_filter_constraint) + if (mdp_cfg && mdp_cfg->wrot_filter_constraint) { + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wrot.filter); MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, - wrot->filter, 0x77); + reg, 0x77); + } return 0; } @@ -420,30 +530,44 @@ static int config_wrot_frame(struct mdp_comp_ctx *ctx, static int config_wrot_subfrm(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd, u32 index) { - const struct mdp_wrot_subfrm *subfrm = &ctx->param->wrot.subfrms[index]; phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; + u32 reg = 0; /* Write Y pixel offset */ + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].offset[0]); MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR, - subfrm->offset[0], 0x0FFFFFFF); + reg, 0x0FFFFFFF); /* Write U pixel offset */ + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].offset[1]); MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR_C, - subfrm->offset[1], 0x0FFFFFFF); + reg, 0x0FFFFFFF); /* Write V pixel offset */ + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].offset[2]); MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR_V, - subfrm->offset[2], 0x0FFFFFFF); + reg, 0x0FFFFFFF); /* Write source size */ - MM_REG_WRITE(cmd, subsys_id, base, VIDO_IN_SIZE, subfrm->src, + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].src); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_IN_SIZE, reg, 0x1FFF1FFF); /* Write target size */ - MM_REG_WRITE(cmd, subsys_id, base, VIDO_TAR_SIZE, subfrm->clip, + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].clip); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_TAR_SIZE, reg, 0x1FFF1FFF); - MM_REG_WRITE(cmd, subsys_id, base, VIDO_CROP_OFST, subfrm->clip_ofst, + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].clip_ofst); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_CROP_OFST, reg, 0x1FFF1FFF); + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].main_buf); MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, - subfrm->main_buf, 0x1FFF7F00); + reg, 0x1FFF7F00); /* Enable WROT */ MM_REG_WRITE(cmd, subsys_id, base, VIDO_ROT_EN, BIT(0), BIT(0)); @@ -497,29 +621,41 @@ static int config_wdma_frame(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd, const struct v4l2_rect *compose) { - const struct mdp_wdma_data *wdma = &ctx->param->wdma; phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; + u32 reg = 0; MM_REG_WRITE(cmd, subsys_id, base, WDMA_BUF_CON2, 0x10101050, 0xFFFFFFFF); /* Setup frame information */ - MM_REG_WRITE(cmd, subsys_id, base, WDMA_CFG, wdma->wdma_cfg, + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wdma.wdma_cfg); + MM_REG_WRITE(cmd, subsys_id, base, WDMA_CFG, reg, 0x0F01B8F0); /* Setup frame base address */ - MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_ADDR, wdma->iova[0], + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wdma.iova[0]); + MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_ADDR, reg, 0xFFFFFFFF); - MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_U_ADDR, wdma->iova[1], + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wdma.iova[1]); + MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_U_ADDR, reg, 0xFFFFFFFF); - MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_V_ADDR, wdma->iova[2], + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wdma.iova[2]); + MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_V_ADDR, reg, 0xFFFFFFFF); /* Setup Y pitch */ + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wdma.w_in_byte); MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_W_IN_BYTE, - wdma->w_in_byte, 0x0000FFFF); + reg, 0x0000FFFF); /* Setup UV pitch */ + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wdma.uv_stride); MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_UV_PITCH, - wdma->uv_stride, 0x0000FFFF); + reg, 0x0000FFFF); /* Set the fixed ALPHA as 0xFF */ MM_REG_WRITE(cmd, subsys_id, base, WDMA_ALPHA, 0x800000FF, 0x800000FF); @@ -530,27 +666,39 @@ static int config_wdma_frame(struct mdp_comp_ctx *ctx, static int config_wdma_subfrm(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd, u32 index) { - const struct mdp_wdma_subfrm *subfrm = &ctx->param->wdma.subfrms[index]; phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; + u32 reg = 0; /* Write Y pixel offset */ + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].offset[0]); MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_ADDR_OFFSET, - subfrm->offset[0], 0x0FFFFFFF); + reg, 0x0FFFFFFF); /* Write U pixel offset */ + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].offset[1]); MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_U_ADDR_OFFSET, - subfrm->offset[1], 0x0FFFFFFF); + reg, 0x0FFFFFFF); /* Write V pixel offset */ + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].offset[2]); MM_REG_WRITE(cmd, subsys_id, base, WDMA_DST_V_ADDR_OFFSET, - subfrm->offset[2], 0x0FFFFFFF); + reg, 0x0FFFFFFF); /* Write source size */ - MM_REG_WRITE(cmd, subsys_id, base, WDMA_SRC_SIZE, subfrm->src, + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].src); + MM_REG_WRITE(cmd, subsys_id, base, WDMA_SRC_SIZE, reg, 0x3FFF3FFF); /* Write target size */ - MM_REG_WRITE(cmd, subsys_id, base, WDMA_CLIP_SIZE, subfrm->clip, + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].clip); + MM_REG_WRITE(cmd, subsys_id, base, WDMA_CLIP_SIZE, reg, 0x3FFF3FFF); /* Write clip offset */ - MM_REG_WRITE(cmd, subsys_id, base, WDMA_CLIP_COORD, subfrm->clip_ofst, + if (CFG_CHECK(MT8183, p_id)) + reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].clip_ofst); + MM_REG_WRITE(cmd, subsys_id, base, WDMA_CLIP_COORD, reg, 0x3FFF3FFF); /* Enable WDMA */ @@ -593,13 +741,21 @@ static int init_ccorr(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) static int config_ccorr_subfrm(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd, u32 index) { - const struct img_comp_subfrm *csf = &ctx->param->subfrms[index]; phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; + u32 csf_l = 0, csf_r = 0; + u32 csf_t = 0, csf_b = 0; u32 hsize, vsize; - hsize = csf->in.right - csf->in.left + 1; - vsize = csf->in.bottom - csf->in.top + 1; + if (CFG_CHECK(MT8183, p_id)) { + csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left); + csf_r = CFG_COMP(MT8183, ctx->param, subfrms[index].in.right); + csf_t = CFG_COMP(MT8183, ctx->param, subfrms[index].in.top); + csf_b = CFG_COMP(MT8183, ctx->param, subfrms[index].in.bottom); + } + + hsize = csf_r - csf_l + 1; + vsize = csf_b - csf_t + 1; MM_REG_WRITE(cmd, subsys_id, base, MDP_CCORR_SIZE, (hsize << 16) + (vsize << 0), 0x1FFF1FFF); return 0; @@ -968,6 +1124,7 @@ int mdp_comp_config(struct mdp_dev *mdp) int ret; memset(mdp_comp_alias_id, 0, sizeof(mdp_comp_alias_id)); + p_id = mdp->mdp_data->mdp_plat_id; parent = dev->of_node->parent; /* Iterate over sibling MDP function blocks */ @@ -1027,9 +1184,19 @@ int mdp_comp_ctx_config(struct mdp_dev *mdp, struct mdp_comp_ctx *ctx, { struct device *dev = &mdp->pdev->dev; enum mtk_mdp_comp_id public_id = MDP_COMP_NONE; - int i; + u32 arg; + int i, idx; - public_id = get_comp_public_id(mdp, param->type); + if (!param) { + dev_err(dev, "Invalid component param"); + return -EINVAL; + } + + if (CFG_CHECK(MT8183, p_id)) + arg = CFG_COMP(MT8183, param, type); + else + return -EINVAL; + public_id = get_comp_public_id(mdp, arg); if (public_id < 0) { dev_err(dev, "Invalid component id %d", public_id); return -EINVAL; @@ -1037,13 +1204,26 @@ int mdp_comp_ctx_config(struct mdp_dev *mdp, struct mdp_comp_ctx *ctx, ctx->comp = mdp->comp[public_id]; if (!ctx->comp) { - dev_err(dev, "Uninit component inner id %d", param->type); + dev_err(dev, "Uninit component inner id %d", arg); return -EINVAL; } ctx->param = param; - ctx->input = &frame->inputs[param->input]; - for (i = 0; i < param->num_outputs; i++) - ctx->outputs[i] = &frame->outputs[param->outputs[i]]; + if (CFG_CHECK(MT8183, p_id)) + arg = CFG_COMP(MT8183, param, input); + else + return -EINVAL; + ctx->input = &frame->inputs[arg]; + if (CFG_CHECK(MT8183, p_id)) + idx = CFG_COMP(MT8183, param, num_outputs); + else + return -EINVAL; + for (i = 0; i < idx; i++) { + if (CFG_CHECK(MT8183, p_id)) + arg = CFG_COMP(MT8183, param, outputs[i]); + else + return -EINVAL; + ctx->outputs[i] = &frame->outputs[arg]; + } return 0; } diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c index 79acdccd0b60..8daa7245c90b 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c @@ -18,6 +18,7 @@ #include "mt8183/mdp3-plat-mt8183.h" static const struct mtk_mdp_driver_data mt8183_mdp_driver_data = { + .mdp_plat_id = MT8183, .mdp_probe_infra = mt8183_mdp_probe_infra, .mdp_sub_comp_dt_ids = mt8183_sub_comp_dt_ids, .mdp_cfg = &mt8183_plat_cfg, diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h index dd5e23800854..b7288fe15134 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h @@ -51,6 +51,7 @@ enum mdp_pipe_id { }; struct mtk_mdp_driver_data { + const int mdp_plat_id; const struct of_device_id *mdp_probe_infra; const struct of_device_id *mdp_sub_comp_dt_ids; const struct mdp_platform_config *mdp_cfg;