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[88.207.97.147]) by smtp.googlemail.com with ESMTPSA id sb25-20020a1709076d9900b007b2a58e31dasm8777831ejc.145.2023.01.13.08.44.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Jan 2023 08:44:53 -0800 (PST) From: Robert Marko To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, bhelgaas@google.com, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, mani@kernel.org, svarbanov@mm-sol.com, shawn.guo@linaro.org, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH v2 2/9] arm64: dts: qcom: ipq8074: fix Gen3 PCIe QMP PHY Date: Fri, 13 Jan 2023 17:44:42 +0100 Message-Id: <20230113164449.906002-2-robimarko@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230113164449.906002-1-robimarko@gmail.com> References: <20230113164449.906002-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org IPQ8074 comes in 2 silicon versions: * v1 with 2x Gen2 PCIe ports and QMP PHY-s * v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s v2 is the final and production version that is actually supported by the kernel, however it looks like PCIe related nodes were added for the v1 SoC. Now that we have Gen3 QMP PHY support, we can start fixing the PCIe support by fixing the Gen3 QMP PHY node first. Change the compatible to the Gen3 QMP PHY, correct the register space start and size, add the missing misc PCS register space. Fixes: 33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes") Signed-off-by: Robert Marko --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 31ec24100213..c93e3f39f33d 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -232,9 +232,9 @@ qusb_phy_0: phy@79000 { status = "disabled"; }; - pcie_qmp0: phy@86000 { - compatible = "qcom,ipq8074-qmp-pcie-phy"; - reg = <0x00086000 0x1c4>; + pcie_qmp0: phy@84000 { + compatible = "qcom,ipq8074-qmp-gen3-pcie-phy"; + reg = <0x00084000 0x1bc>; #address-cells = <1>; #size-cells = <1>; ranges; @@ -248,10 +248,11 @@ pcie_qmp0: phy@86000 { "common"; status = "disabled"; - pcie_phy0: phy@86200 { - reg = <0x86200 0x16c>, - <0x86400 0x200>, - <0x86800 0x4f4>; + pcie_phy0: phy@84200 { + reg = <0x84200 0x16c>, + <0x84400 0x200>, + <0x84800 0x1f0>, + <0x84c00 0xf4>; #phy-cells = <0>; #clock-cells = <0>; clocks = <&gcc GCC_PCIE0_PIPE_CLK>; From patchwork Fri Jan 13 16:44:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 642169 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 268FDC67871 for ; Fri, 13 Jan 2023 16:47:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229769AbjAMQrc (ORCPT ); Fri, 13 Jan 2023 11:47:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59998 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229774AbjAMQrI (ORCPT ); Fri, 13 Jan 2023 11:47:08 -0500 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [IPv6:2a00:1450:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B1C374D4AB; Fri, 13 Jan 2023 08:44:57 -0800 (PST) Received: by mail-ej1-x633.google.com with SMTP id ud5so53646862ejc.4; Fri, 13 Jan 2023 08:44:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Myq7mHdqsUE+VFev1hT0NgPEUBx3bz87gHy9ti3y5O0=; b=CSvoS7chzkXNLmc/XORHl9BROENcpS3fJZq2ie/HnCE1o88cqobm9BFVk1wSqQStRI RKXHfAySsNC9u2SCfUg1B6Oy9d3034AQ8e1nD5A8h6/kF7DVgibMchQgh5+w3WDkPzhu Nb9POAtxPwPqzqIXaaRw9SBUaQlCz5n/LZclFK3YfZocECFYkFnJxZ9sb+OP1YTOUFnC T/c14TJeU8YVznPhy2+Fps9Iq/CvPD2MuLwC+rp6MgtNAAL4znLx8qb58Ht3y7lMoWGG Ej+TwprS85rbDpSYAV4Q5KjYtlQVJjjjEKPzMUT9g7/4b70wtpFLE0sLPxY3xT/MbCk8 9wDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Myq7mHdqsUE+VFev1hT0NgPEUBx3bz87gHy9ti3y5O0=; b=w2U8QVIjtDHAoPR0qjTjr14BZuyBTkRnnZ2gcfr6o7uhTIRcMZ0Hjsv3fHnJlln1vB kL5OkwYC2f71RdhAB2WWNKC0aCBeeOElHUeakIUhDBn3xRFDwsGj0eyDJxqPjMzj9Ym0 ry2Z/O1erADjjUJpRke61C+JWe1W+9jGW2pQgU2YoQn33q+SZ7OfYwaLTjW5Tty+lYYt LFS7BCQ4arjpaVTb7vXRgmJn/jk8JYBmhFMcnCmaK+DLeXtVl9HCMlXTN4n0l8w2glnt TZw2DoEkF7c0gCvcRHS4nU3rsAH7Z/0KAIKATui7RL0e0mqXDinHz+8PIIx0WFY5v3T8 vGLg== X-Gm-Message-State: AFqh2kql6KciP18kkiOTepWR3xGmjB0YnkvjpKYjikOVo4b2kUXhI+lX 1oukEtWGM7hze8WmE/hQF8E= X-Google-Smtp-Source: AMrXdXsX/QFL1vjuOlzwdBt9QbrHSmDOuc2kBWTMwdrq6QZ5HvDsgWHK8Utz7kGARCRQ/37C1lUXoQ== X-Received: by 2002:a17:906:370a:b0:7c0:a350:9d29 with SMTP id d10-20020a170906370a00b007c0a3509d29mr66478731ejc.18.1673628296317; Fri, 13 Jan 2023 08:44:56 -0800 (PST) Received: from fedora.. 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[88.207.97.147]) by smtp.googlemail.com with ESMTPSA id sb25-20020a1709076d9900b007b2a58e31dasm8777831ejc.145.2023.01.13.08.44.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Jan 2023 08:44:55 -0800 (PST) From: Robert Marko To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, bhelgaas@google.com, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, mani@kernel.org, svarbanov@mm-sol.com, shawn.guo@linaro.org, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH v2 4/9] arm64: dts: qcom: ipq8074: set Gen2 PCIe pcie max-link-speed Date: Fri, 13 Jan 2023 17:44:44 +0100 Message-Id: <20230113164449.906002-4-robimarko@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230113164449.906002-1-robimarko@gmail.com> References: <20230113164449.906002-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the generic 'max-link-speed' property to describe the Gen2 PCIe link generation limit. This allows the generic DWC code to configure the link speed correctly. Signed-off-by: Robert Marko --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 06e1da176334..5ef4383ab18b 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -801,6 +801,7 @@ pcie1: pci@10000000 { linux,pci-domain = <1>; bus-range = <0x00 0xff>; num-lanes = <1>; + max-link-speed = <2>; #address-cells = <3>; #size-cells = <2>; From patchwork Fri Jan 13 16:44:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 642168 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9166DC54EBD for ; Fri, 13 Jan 2023 16:47:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230246AbjAMQrw (ORCPT ); Fri, 13 Jan 2023 11:47:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34730 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229703AbjAMQrN (ORCPT ); Fri, 13 Jan 2023 11:47:13 -0500 Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [IPv6:2a00:1450:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7F4364D72F; Fri, 13 Jan 2023 08:45:00 -0800 (PST) Received: by mail-ej1-x62a.google.com with SMTP id hw16so41767972ejc.10; Fri, 13 Jan 2023 08:45:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8RXpc+qR14+HHZGpeltUoGyeqhas9NSG4qLAjy0buBE=; b=LFU15355PqIgpndYz2zO+dJjiMLCOYI/Bh87jnvHGBTYG1F0WRKj2up5rZ4FCUu9uS leojmQIOzUl58kE49ZTgFGmokLWB68a31Mhh/0kl7/qgXnBDxGkWgfosXo6IHnihiXU/ FvM2o4ttMQ94ZoWC5zdlrx11M1shpTXDmUgxkeqYLY4kbCYtPRYy+FD+FeL+lt/qy6wt xGqNkxosTkUvSDong4q4pddRpbx9JCqs1ztyRXlsnk1SAHT1Ie/GmMNBmo+/9az77c/7 k2/dEZg2Pvc5zRuBDLYEtKn/CnavYLoL+I4xnyL0V++bRZEuQXTH4K2tiRryytnMcGcT rhNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8RXpc+qR14+HHZGpeltUoGyeqhas9NSG4qLAjy0buBE=; b=JnriOPnmDFYjUa42Fe30rODpiXfrpNze1tN7UvjGi0eFsltYv+eiAxwfqFLp7rzsx9 20gMFyJkVrRg94Eu6cBnHlTShq6Kzml2DPhW1cICFfV1s412140uLJnxh06vdemuSg77 SvfOmmDrZCOLHXXxO6XxG+gPot0l0Efot7C6sjHly6gpFOBp37FZqRgSS8GFbL5c8dbF 2ZrEJ169xO4krv/SFGYKYa5LfcXf06di63smJiXnXKkfaaWlN1RXrN76Fp7CHhW+wbbs Il9oxDO3sNrfSfxGsHhR9k23IdJ8CQdbq22jgjWmS58xTAbeSpGmoXLKrhKs5aQik9ai VlmQ== X-Gm-Message-State: AFqh2kqGIPd6cUrk5liLygTRlKbeiREOogBxKSwpxmKiMeV4JFojj8U7 uQG+6RQwCfZGsCM+ntIYoKU= X-Google-Smtp-Source: AMrXdXutMuO6pW1i7X03FZZXzNxKvY5bHBnsJx9AxrMrz3iwT946EqLjMMnIXQJjLv+Qj+z667yMdg== X-Received: by 2002:a17:906:b053:b0:7ad:ca80:5669 with SMTP id bj19-20020a170906b05300b007adca805669mr83559889ejb.64.1673628299120; Fri, 13 Jan 2023 08:44:59 -0800 (PST) Received: from fedora.. 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[88.207.97.147]) by smtp.googlemail.com with ESMTPSA id sb25-20020a1709076d9900b007b2a58e31dasm8777831ejc.145.2023.01.13.08.44.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Jan 2023 08:44:58 -0800 (PST) From: Robert Marko To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, bhelgaas@google.com, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, mani@kernel.org, svarbanov@mm-sol.com, shawn.guo@linaro.org, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko , Krzysztof Kozlowski Subject: [PATCH v2 6/9] dt-bindings: PCI: qcom: document IPQ8074 Gen3 port Date: Fri, 13 Jan 2023 17:44:46 +0100 Message-Id: <20230113164449.906002-6-robimarko@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230113164449.906002-1-robimarko@gmail.com> References: <20230113164449.906002-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org IPQ8074 has one Gen2 and one Gen3 PCIe port, with Gen2 already supported. Document Gen3 port which uses the same controller as IPQ6018. Signed-off-by: Robert Marko Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 19580350db11..0f258aa1bfaf 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -24,6 +24,7 @@ properties: - qcom,pcie-ipq8064 - qcom,pcie-ipq8064-v2 - qcom,pcie-ipq8074 + - qcom,pcie-ipq8074-gen3 - qcom,pcie-msm8996 - qcom,pcie-qcs404 - qcom,pcie-sa8540p @@ -154,6 +155,7 @@ allOf: contains: enum: - qcom,pcie-ipq6018 + - qcom,pcie-ipq8074-gen3 then: properties: reg: @@ -375,6 +377,7 @@ allOf: contains: enum: - qcom,pcie-ipq6018 + - qcom,pcie-ipq8074-gen3 then: properties: clocks: @@ -695,6 +698,7 @@ allOf: - qcom,pcie-ipq8064 - qcom,pcie-ipq8064v2 - qcom,pcie-ipq8074 + - qcom,pcie-ipq8074-gen3 - qcom,pcie-qcs404 then: required: @@ -778,6 +782,7 @@ allOf: - qcom,pcie-ipq8064 - qcom,pcie-ipq8064-v2 - qcom,pcie-ipq8074 + - qcom,pcie-ipq8074-gen3 - qcom,pcie-qcs404 - qcom,pcie-sa8540p then: From patchwork Fri Jan 13 16:44:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 642167 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 767E4C61DB3 for ; Fri, 13 Jan 2023 16:48:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229703AbjAMQsI (ORCPT ); Fri, 13 Jan 2023 11:48:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33840 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229939AbjAMQrR (ORCPT ); Fri, 13 Jan 2023 11:47:17 -0500 Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [IPv6:2a00:1450:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6637F58D12; Fri, 13 Jan 2023 08:45:03 -0800 (PST) Received: by mail-ej1-x634.google.com with SMTP id l22so23904329eja.12; Fri, 13 Jan 2023 08:45:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wGVN3rLMqJQGbw0wWLclIhoV7qmP5/8gcNfX7fkrepc=; b=gJ8+B0Wi77XymiL/mpPDCUfVYHG0jWaZZhwS+lctfzbnfDK4etJHm7PctM2Fqsi6AU wPF7w4kJlbBfNrrBSf/gj1ixHYlLKhAqVbqZ1RoOulmJ9sqSMsLV8ZDzfSuwlEoZWUpv N3++2HOnLeaBsIKH5/E59POv5Z8XoYanAt8U5UU32NHR6ZlHX3j4GORTfQ0Km2Ai886W F59dxMePI/m/GZHSPhuaMzAKGpSAqoo5Ra+WHrqjcI5/pZIDFiBK4BiglnZiZfZwLZdC 58a7HiMaj9fm1BvKCFR2/qlaSkb0up/+Pte4KAaq1QOYQyi7j38DwztZQtYCAQ/3ZwTc a7Hw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wGVN3rLMqJQGbw0wWLclIhoV7qmP5/8gcNfX7fkrepc=; b=spSXWbcKYrV2uPgDfMYFfkHF/iAhceejxTUstNMDQLxgdSJzF65mi5zhENMK4k1CQa zuvkLG1ItT9O7oAdjOUaD7ETlCLvX6nrp061o3oBBltDpJ2NTFu2xZzX7b9LlnlrFE4B VT3FF3B3c5s653p4IJPbN36EJNqKxrDjJFOxQcjttUjB4icG5VOpu4LJVsiw+qfmOlBx XLsafAHO1BtPrWaqXqbtF1C7/0tPaO5V4aoNZqTHa7mRjkGy1pXHT/KjWKc/MzohpRTD jT588jx1zgut83tK7LSDbFgMMG3kW1UhNTsn6AnME+b+Ue5EDtmtwXTXXcBT0hpzV23D LHRQ== X-Gm-Message-State: AFqh2kquO4vQEO70IPRWqPWkEmHh9xv47+qmJZmZQvI8QWCZwT9ZFAld UbVrkGi/IE88KTlv+so0CPI= X-Google-Smtp-Source: AMrXdXv/TZzs4qGoekuus1X3gQapC74nHEU7+ObqEH43hfzMqlRplFO8iZRR3i+I3baT3olfTmayPA== X-Received: by 2002:a17:907:9814:b0:857:1e36:3b7b with SMTP id ji20-20020a170907981400b008571e363b7bmr16733593ejc.11.1673628301934; Fri, 13 Jan 2023 08:45:01 -0800 (PST) Received: from fedora.. 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[88.207.97.147]) by smtp.googlemail.com with ESMTPSA id sb25-20020a1709076d9900b007b2a58e31dasm8777831ejc.145.2023.01.13.08.45.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Jan 2023 08:45:01 -0800 (PST) From: Robert Marko To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, bhelgaas@google.com, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, mani@kernel.org, svarbanov@mm-sol.com, shawn.guo@linaro.org, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH v2 8/9] arm64: dts: qcom: ipq8074: fix Gen3 PCIe node Date: Fri, 13 Jan 2023 17:44:48 +0100 Message-Id: <20230113164449.906002-8-robimarko@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230113164449.906002-1-robimarko@gmail.com> References: <20230113164449.906002-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org IPQ8074 comes in 2 silicon versions: * v1 with 2x Gen2 PCIe ports and QMP PHY-s * v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s v2 is the final and production version that is actually supported by the kernel, however it looks like PCIe related nodes were added for the v1 SoC. Finish the PCIe fixup by using the correct compatible, adding missing ATU register space, declaring max-link-speed, use correct ranges, add missing clocks and resets. Fixes: 33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes") Signed-off-by: Robert Marko --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 30 +++++++++++++++------------ 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 5ef4383ab18b..74eecca4f9e3 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -854,16 +854,18 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */ }; pcie0: pci@20000000 { - compatible = "qcom,pcie-ipq8074"; + compatible = "qcom,pcie-ipq8074-gen3"; reg = <0x20000000 0xf1d>, <0x20000f20 0xa8>, - <0x00080000 0x2000>, + <0x20001000 0x1000>, + <0x00080000 0x4000>, <0x20100000 0x1000>; - reg-names = "dbi", "elbi", "parf", "config"; + reg-names = "dbi", "elbi", "atu", "parf", "config"; device_type = "pci"; linux,pci-domain = <0>; bus-range = <0x00 0xff>; num-lanes = <1>; + max-link-speed = <3>; #address-cells = <3>; #size-cells = <2>; @@ -871,9 +873,9 @@ pcie0: pci@20000000 { phy-names = "pciephy"; ranges = <0x81000000 0 0x20200000 0x20200000 - 0 0x100000 /* downstream I/O */ - 0x82000000 0 0x20300000 0x20300000 - 0 0xd00000>; /* non-prefetchable memory */ + 0 0x10000>, /* downstream I/O */ + <0x82000000 0 0x20220000 0x20220000 + 0 0xfde0000>; /* non-prefetchable memory */ interrupts = ; interrupt-names = "msi"; @@ -891,28 +893,30 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */ clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, <&gcc GCC_PCIE0_AXI_M_CLK>, <&gcc GCC_PCIE0_AXI_S_CLK>, - <&gcc GCC_PCIE0_AHB_CLK>, - <&gcc GCC_PCIE0_AUX_CLK>; - + <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE0_RCHNG_CLK>; clock-names = "iface", "axi_m", "axi_s", - "ahb", - "aux"; + "axi_bridge", + "rchng"; + resets = <&gcc GCC_PCIE0_PIPE_ARES>, <&gcc GCC_PCIE0_SLEEP_ARES>, <&gcc GCC_PCIE0_CORE_STICKY_ARES>, <&gcc GCC_PCIE0_AXI_MASTER_ARES>, <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, <&gcc GCC_PCIE0_AHB_ARES>, - <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>; + <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, + <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; reset-names = "pipe", "sleep", "sticky", "axi_m", "axi_s", "ahb", - "axi_m_sticky"; + "axi_m_sticky", + "axi_s_sticky"; status = "disabled"; }; };