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Iglesias" , qemu-trivial@nongnu.org, Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 1/4] iothread: Remove unused IOThreadClass / IOTHREAD_CLASS Date: Fri, 13 Jan 2023 21:01:35 +0100 Message-Id: <20230113200138.52869-2-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230113200138.52869-1-philmd@linaro.org> References: <20230113200138.52869-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Since commit be8d853766 ("iothread: add I/O thread object") we never used IOThreadClass / IOTHREAD_CLASS() / IOTHREAD_GET_CLASS(), remove these definitions. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- iothread.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/iothread.c b/iothread.c index 3862a64471..b41c305bd9 100644 --- a/iothread.c +++ b/iothread.c @@ -25,10 +25,6 @@ #include "qemu/rcu.h" #include "qemu/main-loop.h" -typedef ObjectClass IOThreadClass; - -DECLARE_CLASS_CHECKERS(IOThreadClass, IOTHREAD, - TYPE_IOTHREAD) #ifdef CONFIG_POSIX /* Benchmark results from 2016 on NVMe SSD drives show max polling times around From patchwork Fri Jan 13 20:01:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 642050 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp397797pvb; Fri, 13 Jan 2023 12:03:44 -0800 (PST) X-Google-Smtp-Source: AMrXdXtZERgUydNo9fEzAdTcDPUsHTi33hHl2LWCAkM4Tc01gtX+oFaX2W8m+ZmYJ/M0mGWMNclH X-Received: by 2002:a05:622a:2484:b0:3a8:2dba:751e with SMTP id cn4-20020a05622a248400b003a82dba751emr24588773qtb.26.1673640224554; Fri, 13 Jan 2023 12:03:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673640224; cv=none; d=google.com; s=arc-20160816; b=xKdaKbtgHtikA11yxhSVidDEooGtFIiXiC6FIYRLk99Wwb1PwEyg0KL6e/tOBEWxFa TeyKQQvtHdrhV9+g0X1ZDMs7tJP5qk1sEoXKJLX24A7WkpYW7sET7ATMn64T5eeNL95R Fx7oCW6qo+vu7a4ECu/RCOR9gOmVT8tZYrWhJjWsZf1xkZEF034761Ifh16Sz3Dx2NAi sX79L595ZZ7Zst9A9EDKcgOI0xiORdqAzJOSrMbUNWECerCz8XqHH27CpiIs07JoBM+V OPbrfGpETliz/PlPVVhISDp5N/aff2cVTje0RIbg2QvZJUd0Jcx/MK4/RMX44QxBF1oe ZWNA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=tt1mSx+5mpU6vHqq0Q13XSPghb0/iRRovVdL8d0eEs4=; b=ssXCh4zF3DIHfa3rHB9sV02XD644tgvS8UFIWNCQZMzqjLUAgTVch79qcEMsbxnPPu 9PeNejwGtQas1XUkpcPfpa4w3k0B+LPDnpQ39L/vbDKpJJt70Z6KV5/b1skuKX+9xiPP yPRHaUNgvoFj8hzaxBHqZgzAZE1rObhHpcUyqPSQQDIbV31r1FZalHKfAPjl7rpgUqj+ yfKBLjYAZEq1ocihbSLwvPFmR5+yt4JSkAmjJLkrBIhPVCsPZ3pamGuzQHr5GbcrGe6i L1cVzLN1P6+mV1/L8iSQaNGiJEO3eXtrPj9rme1lkqERG/OsIvosPfdvAI1SkSvCmxE8 FbgA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Cn2mKzV6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , qemu-trivial@nongnu.org, Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 2/4] hw/irq: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE() Date: Fri, 13 Jan 2023 21:01:36 +0100 Message-Id: <20230113200138.52869-3-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230113200138.52869-1-philmd@linaro.org> References: <20230113200138.52869-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philmd@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org QOM *DECLARE* macros expect a typedef as first argument, not a structure. Replace 'struct IRQState' by 'IRQState' to avoid when modifying the macros: ../hw/core/irq.c:29:1: error: declaration of anonymous struct must be a definition DECLARE_INSTANCE_CHECKER(struct IRQState, IRQ, ^ Use OBJECT_DECLARE_SIMPLE_TYPE instead of DECLARE_INSTANCE_CHECKER. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/core/irq.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/hw/core/irq.c b/hw/core/irq.c index 3623f711fe..3f14e2dda7 100644 --- a/hw/core/irq.c +++ b/hw/core/irq.c @@ -26,8 +26,7 @@ #include "hw/irq.h" #include "qom/object.h" -DECLARE_INSTANCE_CHECKER(struct IRQState, IRQ, - TYPE_IRQ) +OBJECT_DECLARE_SIMPLE_TYPE(IRQState, IRQ) struct IRQState { Object parent_obj; @@ -68,7 +67,7 @@ qemu_irq *qemu_allocate_irqs(qemu_irq_handler handler, void *opaque, int n) qemu_irq qemu_allocate_irq(qemu_irq_handler handler, void *opaque, int n) { - struct IRQState *irq; + IRQState *irq; irq = IRQ(object_new(TYPE_IRQ)); irq->handler = handler; @@ -94,7 +93,7 @@ void qemu_free_irq(qemu_irq irq) static void qemu_notirq(void *opaque, int line, int level) { - struct IRQState *irq = opaque; + IRQState *irq = opaque; irq->handler(irq->opaque, irq->n, !level); } @@ -120,7 +119,7 @@ void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n) static const TypeInfo irq_type_info = { .name = TYPE_IRQ, .parent = TYPE_OBJECT, - .instance_size = sizeof(struct IRQState), + .instance_size = sizeof(IRQState), }; static void irq_register_types(void) From patchwork Fri Jan 13 20:01:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 642051 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp397886pvb; Fri, 13 Jan 2023 12:03:54 -0800 (PST) X-Google-Smtp-Source: AMrXdXtXx7xGPXKc8TKG5xi3q+aTHXFoyEbqh2uogye/PJ2WBUnHmyVb7AxOQvJNwG+iT/IRszl2 X-Received: by 2002:ad4:4685:0:b0:531:aa15:abd1 with SMTP id pl5-20020ad44685000000b00531aa15abd1mr12909640qvb.51.1673640234396; Fri, 13 Jan 2023 12:03:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673640234; cv=none; d=google.com; s=arc-20160816; b=e7nMjjbes3ZiIc8yp/88vMarPw8B5i2LrG1ZahVmUjugtNo7Yz0i/7EYmNJLVT8s79 G5JqpSBBLrRn5SHuHEvFqoZ1UXrCdP2mKXV2avAUtTvtwmlmIkluetdMMp3wRlVZAJLk Q3R5J5PhS8L9ZMPmR893N9A7P9vCWqwVNT3uY2ZYxLNvMfr5iPQOFnOStF+xniXOW/zp vdPjPerrQYqqvipyirI9Zj9dYcXKw/pBgE6Apgmn9bMf2UywcvTVwrYF5XWZchx6LcCW j2jZDqXyBMzZ2Wo50L3eZELn5kyK0IymlZnSlA38Q4KFPCpJ1Ogp+dPZNXAPcva3x836 rEtA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=cfx0zFqCbh87Y8xDP2juuUaDdoqJVp8e6EOhMeHV/Uk=; b=yfHvHgIXoamF+4NBu5ql6KgyYFgneI7Gh+EjubUACOHJ/j47p+Mjo8FTe9grZrWbv9 XTRICDFUVk8LPh+z1ePReX2KJnawUp25Smx55d3jlvPR/D73ShHD0UVA/X4UJqm3Ot2i P+lYBuF4FULXO0cC+4UKGr+kx0QHNQAqTah/iLCz0ERDtMXTmivdvcBbiAlTmWwLKJjh I2/TYaiqNiR+QNyfUWT81DS+Io4hmTDKh9C1SW7muJhLLQivvJFccaaLDTqekxcnZlhs c7bsgeV4AMpElIOxuBXK815BWb9JxCFkIPXusv3AOtL+OD4njvxZWBglDX6jr+t8lt+2 qoZw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yd4VADnG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , qemu-trivial@nongnu.org, Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 3/4] hw/or-irq: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE() Date: Fri, 13 Jan 2023 21:01:37 +0100 Message-Id: <20230113200138.52869-4-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230113200138.52869-1-philmd@linaro.org> References: <20230113200138.52869-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Missed during automatic conversion from commit 8063396bf3 ("Use OBJECT_DECLARE_SIMPLE_TYPE when possible"). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- include/hw/or-irq.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/hw/or-irq.h b/include/hw/or-irq.h index f2f0a27381..131abc2e0c 100644 --- a/include/hw/or-irq.h +++ b/include/hw/or-irq.h @@ -37,8 +37,7 @@ typedef struct OrIRQState qemu_or_irq; -DECLARE_INSTANCE_CHECKER(qemu_or_irq, OR_IRQ, - TYPE_OR_IRQ) +OBJECT_DECLARE_SIMPLE_TYPE(OrIRQState, OR_IRQ) struct OrIRQState { DeviceState parent_obj; From patchwork Fri Jan 13 20:01:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 642049 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp397579pvb; Fri, 13 Jan 2023 12:03:27 -0800 (PST) X-Google-Smtp-Source: AMrXdXv5s6qxZblAhnnGvUW/9SZbsm6yoG6EfnnarbVdcWYG5PHvD5Zf9nt8Zpu95S3FVDOV25hl X-Received: by 2002:ac8:568a:0:b0:3a6:348c:5159 with SMTP id h10-20020ac8568a000000b003a6348c5159mr96638993qta.26.1673640207076; Fri, 13 Jan 2023 12:03:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673640207; cv=none; d=google.com; s=arc-20160816; b=VWNMgWMTA0N7nSlQ1bZEGmDynJncKkdXpAVAlFL8h/55Hb51CUcWE3U4OLiFXU8ILb U4imKb3rw/RHjwtmEYEjijxah5s3A77sRBINSNDUHjnFoX9uHn7w3cRtg1PDDPkR8xNo ib4EJGA8ZPE7HweJKqRKld/sbOSjTi4BFTD26/Z9Ii5kB+Mtohlz64t/l8/o64YTIIeC C92f1Eie3AusjjGg8tH+Lo8AMZzmTKDs5C1s115pfeV/BQx7rkNRfvMxL3BVh0V5GMub 6IgLu+vl8OdZyJym+8bBDnt+2Uq8zIn6gGbbyvE7mAjh1Jfm8ElIBwusPIXBskZF451o yjyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=EG3Qe0kxJp7FPfJDFX/WhPOIuV6nKtCj0QjnSu6ovew=; b=lmPKkYYTWgB3wk/xlKMn4NphOC2TSoaE9CsbbupVo+FQklJTWtNnPclFL3ywKqs+O6 uL8Od/nBpIlAXvqv0JljjbhbBI0Ne77dpq2HHISHlu+O4XnKc8a6vqaTHyluW7ak2wgv GfooMi69myLP40ov41pqUeGnfLPq/6MZcedSufGLFiKJewkuIbDtmQcl1dJEACWjYXBA K473Li+Hs2QdAGGcxKGih2yK4y7huBjxlCKSqFYCvMy8mhRSPHER5AWgihLotCh+RBW5 ItKt6OV7LC6RKiAqAyfr4amcqAPD6rSChRtcVB9s4zndNI68FiLSl8SsIPlXc/g/Wl0C FVlw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bCW6+6Y7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , qemu-trivial@nongnu.org, Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 4/4] hw: Replace qemu_or_irq typedef by OrIRQState Date: Fri, 13 Jan 2023 21:01:38 +0100 Message-Id: <20230113200138.52869-5-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230113200138.52869-1-philmd@linaro.org> References: <20230113200138.52869-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org OBJECT_DECLARE_SIMPLE_TYPE() macro provides the OrIRQState declaration for free. Besides, the QOM code style is to use the structure name as typedef, and QEMU style is to use Camel Case, so rename qemu_or_irq as OrIRQState. Mechanical change using: $ sed -i -e 's/qemu_or_irq/OrIRQState/g' $(git grep -l qemu_or_irq) Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/arm/exynos4210.c | 4 ++-- hw/arm/mps2-tz.c | 2 +- hw/core/or-irq.c | 18 +++++++++--------- hw/pci-host/raven.c | 2 +- include/hw/arm/armsse.h | 6 +++--- include/hw/arm/bcm2835_peripherals.h | 2 +- include/hw/arm/exynos4210.h | 4 ++-- include/hw/arm/stm32f205_soc.h | 2 +- include/hw/arm/stm32f405_soc.h | 2 +- include/hw/arm/xlnx-versal.h | 6 +++--- include/hw/arm/xlnx-zynqmp.h | 2 +- include/hw/or-irq.h | 2 -- 12 files changed, 25 insertions(+), 27 deletions(-) diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index 8dafa2215b..6f2dda13f6 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -507,7 +507,7 @@ static uint64_t exynos4210_calc_affinity(int cpu) return (0x9 << ARM_AFF1_SHIFT) | cpu; } -static DeviceState *pl330_create(uint32_t base, qemu_or_irq *orgate, +static DeviceState *pl330_create(uint32_t base, OrIRQState *orgate, qemu_irq irq, int nreq, int nevents, int width) { SysBusDevice *busdev; @@ -806,7 +806,7 @@ static void exynos4210_init(Object *obj) for (i = 0; i < ARRAY_SIZE(s->pl330_irq_orgate); i++) { char *name = g_strdup_printf("pl330-irq-orgate%d", i); - qemu_or_irq *orgate = &s->pl330_irq_orgate[i]; + OrIRQState *orgate = &s->pl330_irq_orgate[i]; object_initialize_child(obj, name, orgate, TYPE_OR_IRQ); g_free(name); diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 284c09c91d..07aecd9497 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -152,7 +152,7 @@ struct MPS2TZMachineState { TZMSC msc[4]; CMSDKAPBUART uart[6]; SplitIRQ sec_resp_splitter; - qemu_or_irq uart_irq_orgate; + OrIRQState uart_irq_orgate; DeviceState *lan9118; SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ_MAX]; Clock *sysclk; diff --git a/hw/core/or-irq.c b/hw/core/or-irq.c index d8f3754e96..1df4bc05a7 100644 --- a/hw/core/or-irq.c +++ b/hw/core/or-irq.c @@ -31,7 +31,7 @@ static void or_irq_handler(void *opaque, int n, int level) { - qemu_or_irq *s = OR_IRQ(opaque); + OrIRQState *s = OR_IRQ(opaque); int or_level = 0; int i; @@ -46,7 +46,7 @@ static void or_irq_handler(void *opaque, int n, int level) static void or_irq_reset(DeviceState *dev) { - qemu_or_irq *s = OR_IRQ(dev); + OrIRQState *s = OR_IRQ(dev); int i; for (i = 0; i < MAX_OR_LINES; i++) { @@ -56,7 +56,7 @@ static void or_irq_reset(DeviceState *dev) static void or_irq_realize(DeviceState *dev, Error **errp) { - qemu_or_irq *s = OR_IRQ(dev); + OrIRQState *s = OR_IRQ(dev); assert(s->num_lines <= MAX_OR_LINES); @@ -65,7 +65,7 @@ static void or_irq_realize(DeviceState *dev, Error **errp) static void or_irq_init(Object *obj) { - qemu_or_irq *s = OR_IRQ(obj); + OrIRQState *s = OR_IRQ(obj); qdev_init_gpio_out(DEVICE(obj), &s->out_irq, 1); } @@ -84,7 +84,7 @@ static void or_irq_init(Object *obj) static bool vmstate_extras_needed(void *opaque) { - qemu_or_irq *s = OR_IRQ(opaque); + OrIRQState *s = OR_IRQ(opaque); return s->num_lines >= OLD_MAX_OR_LINES; } @@ -95,7 +95,7 @@ static const VMStateDescription vmstate_or_irq_extras = { .minimum_version_id = 1, .needed = vmstate_extras_needed, .fields = (VMStateField[]) { - VMSTATE_VARRAY_UINT16_UNSAFE(levels, qemu_or_irq, num_lines, 0, + VMSTATE_VARRAY_UINT16_UNSAFE(levels, OrIRQState, num_lines, 0, vmstate_info_bool, bool), VMSTATE_END_OF_LIST(), }, @@ -106,7 +106,7 @@ static const VMStateDescription vmstate_or_irq = { .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { - VMSTATE_BOOL_SUB_ARRAY(levels, qemu_or_irq, 0, OLD_MAX_OR_LINES), + VMSTATE_BOOL_SUB_ARRAY(levels, OrIRQState, 0, OLD_MAX_OR_LINES), VMSTATE_END_OF_LIST(), }, .subsections = (const VMStateDescription*[]) { @@ -116,7 +116,7 @@ static const VMStateDescription vmstate_or_irq = { }; static Property or_irq_properties[] = { - DEFINE_PROP_UINT16("num-lines", qemu_or_irq, num_lines, 1), + DEFINE_PROP_UINT16("num-lines", OrIRQState, num_lines, 1), DEFINE_PROP_END_OF_LIST(), }; @@ -136,7 +136,7 @@ static void or_irq_class_init(ObjectClass *klass, void *data) static const TypeInfo or_irq_type_info = { .name = TYPE_OR_IRQ, .parent = TYPE_DEVICE, - .instance_size = sizeof(qemu_or_irq), + .instance_size = sizeof(OrIRQState), .instance_init = or_irq_init, .class_init = or_irq_class_init, }; diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c index 2c96ddf8fe..5e0a5b9303 100644 --- a/hw/pci-host/raven.c +++ b/hw/pci-host/raven.c @@ -60,7 +60,7 @@ DECLARE_INSTANCE_CHECKER(PREPPCIState, RAVEN_PCI_HOST_BRIDGE, struct PRePPCIState { PCIHostState parent_obj; - qemu_or_irq *or_irq; + OrIRQState *or_irq; qemu_irq pci_irqs[PCI_NUM_PINS]; PCIBus pci_bus; AddressSpace pci_io_as; diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 9648e7a419..cd0931d0a0 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -155,12 +155,12 @@ struct ARMSSE { TZPPC apb_ppc[NUM_INTERNAL_PPCS]; TZMPC mpc[IOTS_NUM_MPC]; CMSDKAPBTimer timer[3]; - qemu_or_irq ppc_irq_orgate; + OrIRQState ppc_irq_orgate; SplitIRQ sec_resp_splitter; SplitIRQ ppc_irq_splitter[NUM_PPCS]; SplitIRQ mpc_irq_splitter[IOTS_NUM_EXP_MPC + IOTS_NUM_MPC]; - qemu_or_irq mpc_irq_orgate; - qemu_or_irq nmi_orgate; + OrIRQState mpc_irq_orgate; + OrIRQState nmi_orgate; SplitIRQ cpu_irq_splitter[NUM_SSE_IRQS]; diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h index c9d25d493e..d724a2fc28 100644 --- a/include/hw/arm/bcm2835_peripherals.h +++ b/include/hw/arm/bcm2835_peripherals.h @@ -56,7 +56,7 @@ struct BCM2835PeripheralState { BCM2835AuxState aux; BCM2835FBState fb; BCM2835DMAState dma; - qemu_or_irq orgated_dma_irq; + OrIRQState orgated_dma_irq; BCM2835ICState ic; BCM2835PropertyState property; BCM2835RngState rng; diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h index 97353f1c02..68db19f0cb 100644 --- a/include/hw/arm/exynos4210.h +++ b/include/hw/arm/exynos4210.h @@ -96,8 +96,8 @@ struct Exynos4210State { MemoryRegion boot_secondary; MemoryRegion bootreg_mem; I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER]; - qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA]; - qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS]; + OrIRQState pl330_irq_orgate[EXYNOS4210_NUM_DMA]; + OrIRQState cpu_irq_orgate[EXYNOS4210_NCPUS]; A9MPPrivState a9mpcore; Exynos4210GicState ext_gic; Exynos4210CombinerState int_combiner; diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h index 849d3ed889..5a4f776264 100644 --- a/include/hw/arm/stm32f205_soc.h +++ b/include/hw/arm/stm32f205_soc.h @@ -63,7 +63,7 @@ struct STM32F205State { STM32F2XXADCState adc[STM_NUM_ADCS]; STM32F2XXSPIState spi[STM_NUM_SPIS]; - qemu_or_irq *adc_irqs; + OrIRQState *adc_irqs; MemoryRegion sram; MemoryRegion flash; diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h index 249ab5434e..c968ce3ab2 100644 --- a/include/hw/arm/stm32f405_soc.h +++ b/include/hw/arm/stm32f405_soc.h @@ -63,7 +63,7 @@ struct STM32F405State { STM32F4xxExtiState exti; STM32F2XXUsartState usart[STM_NUM_USARTS]; STM32F2XXTimerState timer[STM_NUM_TIMERS]; - qemu_or_irq adc_irqs; + OrIRQState adc_irqs; STM32F2XXADCState adc[STM_NUM_ADCS]; STM32F2XXSPIState spi[STM_NUM_SPIS]; diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index cbe8a19c10..b6786e9832 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -85,7 +85,7 @@ struct Versal { } rpu; struct { - qemu_or_irq irq_orgate; + OrIRQState irq_orgate; XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM]; } xram; @@ -103,7 +103,7 @@ struct Versal { XlnxCSUDMA dma_src; XlnxCSUDMA dma_dst; MemoryRegion linear_mr; - qemu_or_irq irq_orgate; + OrIRQState irq_orgate; } ospi; } iou; @@ -113,7 +113,7 @@ struct Versal { XlnxVersalEFuseCtrl efuse_ctrl; XlnxVersalEFuseCache efuse_cache; - qemu_or_irq apb_irq_orgate; + OrIRQState apb_irq_orgate; } pmc; struct { diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 20bdf894aa..687c75e3b0 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -130,7 +130,7 @@ struct XlnxZynqMPState { XlnxZDMA gdma[XLNX_ZYNQMP_NUM_GDMA_CH]; XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH]; XlnxCSUDMA qspi_dma; - qemu_or_irq qspi_irq_orgate; + OrIRQState qspi_irq_orgate; XlnxZynqMPAPUCtrl apu_ctrl; XlnxZynqMPCRF crf; CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC]; diff --git a/include/hw/or-irq.h b/include/hw/or-irq.h index 131abc2e0c..c0a42f3711 100644 --- a/include/hw/or-irq.h +++ b/include/hw/or-irq.h @@ -35,8 +35,6 @@ */ #define MAX_OR_LINES 48 -typedef struct OrIRQState qemu_or_irq; - OBJECT_DECLARE_SIMPLE_TYPE(OrIRQState, OR_IRQ) struct OrIRQState {