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[77.158.188.58]) by smtp.gmail.com with ESMTPSA id l24-20020a1ced18000000b003d99da8d30asm26395909wmh.46.2023.01.12.07.29.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Jan 2023 07:29:53 -0800 (PST) From: bchihi@baylibre.com To: daniel.lezcano@linaro.org, rafael@kernel.org, amitk@kernel.org, rui.zhang@intel.com Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, khilman@baylibre.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, james.lo@mediatek.com, rex-bc.chen@mediatek.com Subject: [PATCH v10 1/6] thermal/drivers/mediatek: Relocate driver to mediatek folder Date: Thu, 12 Jan 2023 16:28:50 +0100 Message-Id: <20230112152855.216072-2-bchihi@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230112152855.216072-1-bchihi@baylibre.com> References: <20230112152855.216072-1-bchihi@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Balsam CHIHI Add MediaTek proprietary folder to upstream more thermal zone and cooler drivers, relocate the original thermal controller driver to it, and rename it as "auxadc_thermal.c" to show its purpose more clearly. Signed-off-by: Balsam CHIHI --- drivers/thermal/Kconfig | 14 ++++--------- drivers/thermal/Makefile | 2 +- drivers/thermal/mediatek/Kconfig | 21 +++++++++++++++++++ drivers/thermal/mediatek/Makefile | 1 + .../auxadc_thermal.c} | 2 +- 5 files changed, 28 insertions(+), 12 deletions(-) create mode 100644 drivers/thermal/mediatek/Kconfig create mode 100644 drivers/thermal/mediatek/Makefile rename drivers/thermal/{mtk_thermal.c => mediatek/auxadc_thermal.c} (99%) diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index e052dae614eb..d35f63daca3b 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -412,16 +412,10 @@ config DA9062_THERMAL zone. Compatible with the DA9062 and DA9061 PMICs. -config MTK_THERMAL - tristate "Temperature sensor driver for mediatek SoCs" - depends on ARCH_MEDIATEK || COMPILE_TEST - depends on HAS_IOMEM - depends on NVMEM || NVMEM=n - depends on RESET_CONTROLLER - default y - help - Enable this option if you want to have support for thermal management - controller present in Mediatek SoCs +menu "Mediatek thermal drivers" +depends on ARCH_MEDIATEK || COMPILE_TEST +source "drivers/thermal/mediatek/Kconfig" +endmenu config AMLOGIC_THERMAL tristate "Amlogic Thermal Support" diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index 2506c6c8ca83..766ce38ff4f3 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -55,7 +55,7 @@ obj-y += st/ obj-y += qcom/ obj-y += tegra/ obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o -obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o +obj-y += mediatek/ obj-$(CONFIG_GENERIC_ADC_THERMAL) += thermal-generic-adc.o obj-$(CONFIG_UNIPHIER_THERMAL) += uniphier_thermal.o obj-$(CONFIG_AMLOGIC_THERMAL) += amlogic_thermal.o diff --git a/drivers/thermal/mediatek/Kconfig b/drivers/thermal/mediatek/Kconfig new file mode 100644 index 000000000000..7558a847d4e9 --- /dev/null +++ b/drivers/thermal/mediatek/Kconfig @@ -0,0 +1,21 @@ +config MTK_THERMAL + tristate "MediaTek thermal drivers" + depends on THERMAL_OF + help + This is the option for MediaTek thermal software solutions. + Please enable corresponding options to get temperature + information from thermal sensors or turn on throttle + mechaisms for thermal mitigation. + +if MTK_THERMAL + +config MTK_SOC_THERMAL + tristate "AUXADC temperature sensor driver for MediaTek SoCs" + depends on HAS_IOMEM + help + Enable this option if you want to get SoC temperature + information for MediaTek platforms. + This driver configures thermal controllers to collect + temperature via AUXADC interface. + +endif diff --git a/drivers/thermal/mediatek/Makefile b/drivers/thermal/mediatek/Makefile new file mode 100644 index 000000000000..53e86e30b26f --- /dev/null +++ b/drivers/thermal/mediatek/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_MTK_SOC_THERMAL) += auxadc_thermal.o diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mediatek/auxadc_thermal.c similarity index 99% rename from drivers/thermal/mtk_thermal.c rename to drivers/thermal/mediatek/auxadc_thermal.c index 8440692e3890..b4ef57fa9183 100644 --- a/drivers/thermal/mtk_thermal.c +++ b/drivers/thermal/mediatek/auxadc_thermal.c @@ -23,7 +23,7 @@ #include #include -#include "thermal_hwmon.h" +#include "../thermal_hwmon.h" /* AUXADC Registers */ #define AUXADC_CON1_SET_V 0x008 From patchwork Thu Jan 12 15:28:51 2023 Content-Type: text/plain; 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[77.158.188.58]) by smtp.gmail.com with ESMTPSA id l24-20020a1ced18000000b003d99da8d30asm26395909wmh.46.2023.01.12.07.29.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Jan 2023 07:29:54 -0800 (PST) From: bchihi@baylibre.com To: daniel.lezcano@linaro.org, rafael@kernel.org, amitk@kernel.org, rui.zhang@intel.com Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, khilman@baylibre.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, james.lo@mediatek.com, rex-bc.chen@mediatek.com Subject: [PATCH v10 2/6] dt-bindings/thermal/mediatek: Add dt-binding document for LVTS thermal controllers Date: Thu, 12 Jan 2023 16:28:51 +0100 Message-Id: <20230112152855.216072-3-bchihi@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230112152855.216072-1-bchihi@baylibre.com> References: <20230112152855.216072-1-bchihi@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Balsam CHIHI Add dt-binding document for mt8192 and mt8195 LVTS thermal controllers. Signed-off-by: Balsam CHIHI --- .../thermal/mediatek,lvts-thermal.yaml | 140 ++++++++++++++++++ 1 file changed, 140 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml diff --git a/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml b/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml new file mode 100644 index 000000000000..43b8777fc1b2 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml @@ -0,0 +1,140 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/mediatek,lvts-thermal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek SoC Low Voltage Thermal Sensor (LVTS) + +maintainers: + - Balsam CHIHI + +description: | + LVTS is a thermal management architecture composed of three subsystems, + a Sensing device - Thermal Sensing Micro Circuit Unit (TSMCU), + a Converter - Low Voltage Thermal Sensor converter (LVTS), and + a Digital controller (LVTS_CTRL). + +properties: + compatible: + enum: + - mediatek,mt8192-lvts-mcu + - mediatek,mt8192-lvts-ap + - mediatek,mt8195-lvts-mcu + - mediatek,mt8195-lvts-ap + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + description: LVTS reset for clearing temporary data on AP/MCU. + + nvmem-cells: + minItems: 1 + items: + - description: Calibration eFuse data 1 for LVTS + - description: Calibration eFuse data 2 for LVTS + + nvmem-cell-names: + minItems: 1 + items: + - const: lvts-calib-data-1 + - const: lvts-calib-data-2 + + "#thermal-sensor-cells": + const: 1 + +allOf: + - $ref: thermal-sensor.yaml# + + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8192-lvts-mcu + - mediatek,mt8192-lvts-ap + then: + properties: + nvmem-cells: + maxItems: 1 + + nvmem-cell-names: + maxItems: 1 + + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8195-lvts-mcu + - mediatek,mt8195-lvts-ap + then: + properties: + nvmem-cells: + maxItems: 2 + + nvmem-cell-names: + maxItems: 2 + +required: + - compatible + - reg + - interrupts + - clocks + - resets + - nvmem-cells + - nvmem-cell-names + - "#thermal-sensor-cells" + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + lvts_mcu: thermal-sensor@11278000 { + compatible = "mediatek,mt8195-lvts-mcu"; + reg = <0 0x11278000 0 0x1000>; + interrupts = ; + clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; + resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>; + nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>; + nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2"; + #thermal-sensor-cells = <1>; + }; + }; + + thermal_zones: thermal-zones { + cpu0-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_mcu MT819x_MCU_LITTLE_CPU0>; + trips { + cpu0_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu0_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; From patchwork Thu Jan 12 15:28:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Balsam CHIHI X-Patchwork-Id: 642478 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14A93C61DB3 for ; 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[77.158.188.58]) by smtp.gmail.com with ESMTPSA id l24-20020a1ced18000000b003d99da8d30asm26395909wmh.46.2023.01.12.07.29.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Jan 2023 07:29:55 -0800 (PST) From: bchihi@baylibre.com To: daniel.lezcano@linaro.org, rafael@kernel.org, amitk@kernel.org, rui.zhang@intel.com Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, khilman@baylibre.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, james.lo@mediatek.com, rex-bc.chen@mediatek.com Subject: [PATCH v10 3/6] arm64/dts/mt8195: Add efuse node to mt8195 Date: Thu, 12 Jan 2023 16:28:52 +0100 Message-Id: <20230112152855.216072-4-bchihi@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230112152855.216072-1-bchihi@baylibre.com> References: <20230112152855.216072-1-bchihi@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Balsam CHIHI Add efuse node. This will be required by the thermal driver to get the calibration data. Signed-off-by: Balsam CHIHI Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 5d31536f4c48..09df105f4606 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1380,6 +1380,12 @@ pciephy_glb_intr: pciephy-glb-intr@193 { dp_calibration: dp-data@1ac { reg = <0x1ac 0x10>; }; + lvts_efuse_data1: lvts1-calib@1bc { + reg = <0x1bc 0x14>; + }; + lvts_efuse_data2: lvts2-calib@1d0 { + reg = <0x1d0 0x38>; + }; }; u3phy2: t-phy@11c40000 { From patchwork Thu Jan 12 15:28:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Balsam CHIHI X-Patchwork-Id: 641862 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60AA3C54EBC for ; Thu, 12 Jan 2023 15:40:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240521AbjALPkS (ORCPT ); Thu, 12 Jan 2023 10:40:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54410 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240508AbjALPja (ORCPT ); Thu, 12 Jan 2023 10:39:30 -0500 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B66434A97C for ; Thu, 12 Jan 2023 07:29:58 -0800 (PST) Received: by mail-wm1-x333.google.com with SMTP id o15so13446917wmr.4 for ; Thu, 12 Jan 2023 07:29:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OAAnrpHxi5e9Zk0ezA98CU0+UFbH/mq4H+Bswht0RG8=; b=yS1n0EgyiIqFNdW1TouV8J1GnzMiG3M0JjZe2ILgOfYGm45K54VSpgqgq2qlFh0kTV RWzJedK012kmPYMN8DqHa8kDc4dmbww5m/ms7XlXhZZUjxaoFwzuNquOu1raGL/Hor/t 6WxfLZsC20cY+DgcMhql0b+WXLShGL3qISDby4v7Fj6v9uaMr7Q1LPFopOkigNcTxl7Y ebS2xAPFXyAX+X4dKB6XdO6x3pqF/7oT5ehFLRp3c0AdoLs9etxFG33wAQ3+LadmEn2i zXpfmFGIv7fREL/LAoiZhH8jRd7mw+hJo9e7pGVNVVCqAmpvJXqAKpF2SUFFHmflcJDW A1Tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OAAnrpHxi5e9Zk0ezA98CU0+UFbH/mq4H+Bswht0RG8=; b=wH7W/OeUNnp3BLdETqM2kdcEviaFlaydyUS1zONOvginKy5dt1HQNTPB5eqtYIKI1E XXFtJ2Njg/QklWgrsRI6/9o6Dwuy8nT4JLRmX+EyU9/385n/qetcwj6RzqbzAdWlrRoa Jt0jUAwuNT1gnbjxpCQ2551EdTV9ACgs2TwQ3EUQs5wLdHIJE86xjA3eEm9cPkwpThhA hnEUGt2DuLoA6o0lV99p/cwzQnl+UiIma8R+1xTLg/OjO9hrN+enIng+Tt78QfDwxj+X 9nQZTcQnXDSM0vmekBxa9hnl32cq9/MZLsGmNhGAIlAGTTEAoLtCzhYbArJn9c7G7fzt XjqQ== X-Gm-Message-State: AFqh2krRq5i1dbJAuQnfAwxmENzhq+2uz3dj8Hjd5MgmiLT8mB/JNt1L xK6w4jIxWp/Pr/xl5lno4SG6dnHeiq12SGA+ X-Google-Smtp-Source: AMrXdXtXyXff6QXC4Mi7q3ee3A2HtL0aEndPWMmFkNDgMEOVlz8aB+JhY7HZo0gZfh4/0V+nWcRT2g== X-Received: by 2002:a1c:6a0d:0:b0:3d9:edd6:bcbe with SMTP id f13-20020a1c6a0d000000b003d9edd6bcbemr12546964wmc.38.1673537396727; Thu, 12 Jan 2023 07:29:56 -0800 (PST) Received: from t480-bl003.civfrance.com (58.188.158.77.rev.sfr.net. [77.158.188.58]) by smtp.gmail.com with ESMTPSA id l24-20020a1ced18000000b003d99da8d30asm26395909wmh.46.2023.01.12.07.29.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Jan 2023 07:29:56 -0800 (PST) From: bchihi@baylibre.com To: daniel.lezcano@linaro.org, rafael@kernel.org, amitk@kernel.org, rui.zhang@intel.com Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, khilman@baylibre.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, james.lo@mediatek.com, rex-bc.chen@mediatek.com Subject: [PATCH v10 4/6] thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver Date: Thu, 12 Jan 2023 16:28:53 +0100 Message-Id: <20230112152855.216072-5-bchihi@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230112152855.216072-1-bchihi@baylibre.com> References: <20230112152855.216072-1-bchihi@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Balsam CHIHI The Low Voltage Thermal Sensor (LVTS) is a multiple sensors, multi controllers contained in a thermal domain. A thermal domains can be the MCU or the AP. Each thermal domains contain up to seven controllers, each thermal controller handle up to four thermal sensors. The LVTS has two Finite State Machines (FSM), one to handle the functionin temperatures range like hot or cold temperature and another one to handle monitoring trip point. The FSM notifies via interrupts when a trip point is crossed. The interrupt is managed at the thermal controller level, so when an interrupt occurs, the driver has to find out which sensor triggered such an interrupt. The sampling of the thermal can be filtered or immediate. For the former, the LVTS measures several points and applies a low pass filter. Signed-off-by: Balsam CHIHI --- drivers/thermal/mediatek/Kconfig | 15 + drivers/thermal/mediatek/Makefile | 1 + drivers/thermal/mediatek/lvts_thermal.c | 1244 +++++++++++++++++++ include/dt-bindings/thermal/mediatek-lvts.h | 19 + 4 files changed, 1279 insertions(+) create mode 100644 drivers/thermal/mediatek/lvts_thermal.c create mode 100644 include/dt-bindings/thermal/mediatek-lvts.h diff --git a/drivers/thermal/mediatek/Kconfig b/drivers/thermal/mediatek/Kconfig index 7558a847d4e9..99597d7b9890 100644 --- a/drivers/thermal/mediatek/Kconfig +++ b/drivers/thermal/mediatek/Kconfig @@ -18,4 +18,19 @@ config MTK_SOC_THERMAL This driver configures thermal controllers to collect temperature via AUXADC interface. +config MTK_LVTS_THERMAL + tristate "LVTS Thermal Driver for MediaTek SoCs" + depends on HAS_IOMEM + help + Enable this option if you want to get SoC temperature + information for supported MediaTek platforms. + This driver configures LVTS (Low Voltage Thermal Sensor) + thermal controllers to collect temperatures via ASIF + (Analog Serial Interface). + +config MTK_LVTS_THERMAL_DEBUGFS + bool "LVTS thermal debugfs" + depends on MTK_LVTS_THERMAL && DEBUG_FS + help + Enable this option to debug the internals of the device driver. endif diff --git a/drivers/thermal/mediatek/Makefile b/drivers/thermal/mediatek/Makefile index 53e86e30b26f..1c6daa1e644b 100644 --- a/drivers/thermal/mediatek/Makefile +++ b/drivers/thermal/mediatek/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_MTK_SOC_THERMAL) += auxadc_thermal.o +obj-$(CONFIG_MTK_LVTS_THERMAL) += lvts_thermal.o diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c new file mode 100644 index 000000000000..a8fe64beb3c4 --- /dev/null +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -0,0 +1,1244 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023 MediaTek Inc. + * Author: Balsam CHIHI + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LVTS_MONCTL0(__base) (__base + 0x0000) +#define LVTS_MONCTL1(__base) (__base + 0x0004) +#define LVTS_MONCTL2(__base) (__base + 0x0008) +#define LVTS_MONINT(__base) (__base + 0x000C) +#define LVTS_MONINTSTS(__base) (__base + 0x0010) +#define LVTS_MONIDET0(__base) (__base + 0x0014) +#define LVTS_MONIDET1(__base) (__base + 0x0018) +#define LVTS_MONIDET2(__base) (__base + 0x001C) +#define LVTS_MONIDET3(__base) (__base + 0x0020) +#define LVTS_H2NTHRE(__base) (__base + 0x0024) +#define LVTS_HTHRE(__base) (__base + 0x0028) +#define LVTS_OFFSETH(__base) (__base + 0x0030) +#define LVTS_OFFSETL(__base) (__base + 0x0034) +#define LVTS_MSRCTL0(__base) (__base + 0x0038) +#define LVTS_MSRCTL1(__base) (__base + 0x003C) +#define LVTS_TSSEL(__base) (__base + 0x0040) +#define LVTS_CALSCALE(__base) (__base + 0x0048) +#define LVTS_ID(__base) (__base + 0x004C) +#define LVTS_CONFIG(__base) (__base + 0x0050) +#define LVTS_EDATA00(__base) (__base + 0x0054) +#define LVTS_EDATA01(__base) (__base + 0x0058) +#define LVTS_EDATA02(__base) (__base + 0x005C) +#define LVTS_EDATA03(__base) (__base + 0x0060) +#define LVTS_MSR0(__base) (__base + 0x0090) +#define LVTS_MSR1(__base) (__base + 0x0094) +#define LVTS_MSR2(__base) (__base + 0x0098) +#define LVTS_MSR3(__base) (__base + 0x009C) +#define LVTS_IMMD0(__base) (__base + 0x00A0) +#define LVTS_IMMD1(__base) (__base + 0x00A4) +#define LVTS_IMMD2(__base) (__base + 0x00A8) +#define LVTS_IMMD3(__base) (__base + 0x00AC) +#define LVTS_PROTCTL(__base) (__base + 0x00C0) +#define LVTS_PROTTA(__base) (__base + 0x00C4) +#define LVTS_PROTTB(__base) (__base + 0x00C8) +#define LVTS_PROTTC(__base) (__base + 0x00CC) +#define LVTS_CLKEN(__base) (__base + 0x00E4) + +#define LVTS_SENSOR_MAX 4 +#define LVTS_GOLDEN_TEMP_MAX 62 +#define LVTS_GOLDEN_TEMP_DEFAULT 50 +#define LVTS_COEFF_A -250460 +#define LVTS_COEFF_B 250460 + +#define LVTS_MSR_IMMEDIATE_MODE 0 +#define LVTS_MSR_FILTERED_MODE 1 + +#define LVTS_HW_SHUTDOWN_MT8195 105000 + +static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT; +static int coeff_b = LVTS_COEFF_B; + +struct lvts_sensor_data { + int dt_id; +}; + +struct lvts_ctrl_data { + struct lvts_sensor_data lvts_sensor[LVTS_SENSOR_MAX]; + int cal_offset[LVTS_SENSOR_MAX]; + int hw_tshut_temp; + int num_lvts_sensor; + int offset; + int mode; +}; + +struct lvts_data { + struct lvts_ctrl_data *lvts_ctrl; + int num_lvts_ctrl; +}; + +struct lvts_sensor { + struct thermal_zone_device *tz; + void __iomem *msr; + void __iomem *base; + int id; + int dt_id; +}; + +struct lvts_ctrl { + struct lvts_sensor sensors[LVTS_SENSOR_MAX]; + u32 calibration[LVTS_SENSOR_MAX]; + u32 hw_tshut_raw_temp; + int num_lvts_sensor; + int mode; + void __iomem *base; +}; + +struct lvts_domain { + struct lvts_ctrl *lvts_ctrl; + struct reset_control *reset; + struct clk *clk; + int num_lvts_ctrl; + void __iomem *base; + size_t calib_len; + u8 *calib; +}; + +#ifdef CONFIG_MTK_LVTS_THERMAL_DEBUGFS + +static struct dentry *root; + +#define LVTS_DEBUG_FS_REGS(__reg) \ +{ \ + .name = __stringify(__reg), \ + .offset = __reg(0), \ +} + +static const struct debugfs_reg32 lvts_regs[] = { + LVTS_DEBUG_FS_REGS(LVTS_MONCTL0), + LVTS_DEBUG_FS_REGS(LVTS_MONCTL1), + LVTS_DEBUG_FS_REGS(LVTS_MONCTL2), + LVTS_DEBUG_FS_REGS(LVTS_MONINT), + LVTS_DEBUG_FS_REGS(LVTS_MONINTSTS), + LVTS_DEBUG_FS_REGS(LVTS_MONIDET0), + LVTS_DEBUG_FS_REGS(LVTS_MONIDET1), + LVTS_DEBUG_FS_REGS(LVTS_MONIDET2), + LVTS_DEBUG_FS_REGS(LVTS_MONIDET3), + LVTS_DEBUG_FS_REGS(LVTS_H2NTHRE), + LVTS_DEBUG_FS_REGS(LVTS_HTHRE), + LVTS_DEBUG_FS_REGS(LVTS_OFFSETH), + LVTS_DEBUG_FS_REGS(LVTS_OFFSETL), + LVTS_DEBUG_FS_REGS(LVTS_MSRCTL0), + LVTS_DEBUG_FS_REGS(LVTS_MSRCTL1), + LVTS_DEBUG_FS_REGS(LVTS_TSSEL), + LVTS_DEBUG_FS_REGS(LVTS_CALSCALE), + LVTS_DEBUG_FS_REGS(LVTS_ID), + LVTS_DEBUG_FS_REGS(LVTS_CONFIG), + LVTS_DEBUG_FS_REGS(LVTS_EDATA00), + LVTS_DEBUG_FS_REGS(LVTS_EDATA01), + LVTS_DEBUG_FS_REGS(LVTS_EDATA02), + LVTS_DEBUG_FS_REGS(LVTS_EDATA03), + LVTS_DEBUG_FS_REGS(LVTS_MSR0), + LVTS_DEBUG_FS_REGS(LVTS_MSR1), + LVTS_DEBUG_FS_REGS(LVTS_MSR2), + LVTS_DEBUG_FS_REGS(LVTS_MSR3), + LVTS_DEBUG_FS_REGS(LVTS_IMMD0), + LVTS_DEBUG_FS_REGS(LVTS_IMMD1), + LVTS_DEBUG_FS_REGS(LVTS_IMMD2), + LVTS_DEBUG_FS_REGS(LVTS_IMMD3), + LVTS_DEBUG_FS_REGS(LVTS_PROTCTL), + LVTS_DEBUG_FS_REGS(LVTS_PROTTA), + LVTS_DEBUG_FS_REGS(LVTS_PROTTB), + LVTS_DEBUG_FS_REGS(LVTS_PROTTC), + LVTS_DEBUG_FS_REGS(LVTS_CLKEN), +}; + +static int lvts_debugfs_init(struct device *dev, + struct lvts_domain *lvts_td) +{ + struct debugfs_regset32 *regset; + struct lvts_ctrl *lvts_ctrl; + struct dentry *dentry; + struct dentry *dom_dentry; + char name[64]; + int i; + + if (!root) + root = debugfs_create_dir("lvts", NULL); + + dom_dentry = debugfs_create_dir(dev_name(dev), root); + if (!dom_dentry) + return 0; + + for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { + + lvts_ctrl = &lvts_td->lvts_ctrl[i]; + + sprintf(name, "controller%d", i); + dentry = debugfs_create_dir(name, dom_dentry); + if (!dentry) + continue; + + regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); + if (!regset) + continue; + + regset->base = lvts_ctrl->base; + regset->regs = lvts_regs; + regset->nregs = ARRAY_SIZE(lvts_regs); + + debugfs_create_regset32("registers", 0400, dentry, regset); + } + + return 0; +} + +static void lvts_debugfs_exit(void) +{ + debugfs_remove_recursive(root); +} + +#else + +static inline int lvts_debugfs_init(struct device *dev, + struct lvts_domain *lvts_td) +{ + return 0; +} + +static void lvts_debugfs_exit(void) { } + +#endif + +static int lvts_raw_to_temp(u32 raw_temp) +{ + int temperature; + + temperature = ((s64)(raw_temp & 0xFFFF) * LVTS_COEFF_A) >> 14; + temperature += coeff_b; + + return temperature; +} + +static u32 lvts_temp_to_raw(int temperature) +{ + u32 raw_temp = ((s64)(coeff_b - temperature)) << 14; + + raw_temp = div_s64(raw_temp, -LVTS_COEFF_A); + + return raw_temp; +} + +static int lvts_get_temp(struct thermal_zone_device *tz, int *temp) +{ + struct lvts_sensor *lvts_sensor = tz->devdata; + void __iomem *msr = lvts_sensor->msr; + u32 value; + + /* + * Measurement registers: + * + * LVTS_MSR[0-3] / LVTS_IMMD[0-3] + * + * Bits: + * + * 32-17: Unused + * 16 : Valid temperature + * 15-0 : Raw temperature + */ + value = readl(msr); + + /* + * As the thermal zone temperature will read before the + * hardware sensor is fully initialized, we have to check the + * validity of the temperature returned when reading the + * measurement register. The thermal controller will set the + * valid bit temperature only when it is totally initialized. + * + * Otherwise, we may end up with garbage values out of the + * functionning temperature and directly jump to a system + * shutdown. + */ + if (!(value & BIT(16))) + return -EAGAIN; + + *temp = lvts_raw_to_temp(value & 0xFFFF); + + return 0; +} + +static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high) +{ + struct lvts_sensor *lvts_sensor = tz->devdata; + void __iomem *base = lvts_sensor->base; + u32 raw_low = lvts_temp_to_raw(low); + u32 raw_high = lvts_temp_to_raw(high); + + /* + * Hot to normal temperature threshold + * + * LVTS_H2NTHRE + * + * Bits: + * + * 14-0 : Raw temperature for threshold + */ + if (low != -INT_MAX) { + dev_dbg(&tz->device, "Setting low limit temperature interrupt: %d\n", low); + writel(raw_low, LVTS_H2NTHRE(base)); + } + + /* + * Hot temperature threshold + * + * LVTS_HTHRE + * + * Bits: + * + * 14-0 : Raw temperature for threshold + */ + dev_dbg(&tz->device, "Setting high limit temperature interrupt: %d\n", high); + writel(raw_high, LVTS_HTHRE(base)); + + return 0; +} + +static irqreturn_t lvts_ctrl_irq_handler(struct lvts_ctrl *lvts_ctrl) +{ + irqreturn_t iret = IRQ_NONE; + u32 value, masks[] = { 0x0009001F, 0X000881F0, 0x00247C00, 0x1FC00000 }; + int i; + + /* + * Interrupt monitoring status + * + * LVTS_MONINTST + * + * Bits: + * + * 31 : Interrupt for stage 3 + * 30 : Interrupt for stage 2 + * 29 : Interrupt for state 1 + * 28 : Interrupt using filter on sensor 3 + * + * 27 : Interrupt using immediate on sensor 3 + * 26 : Interrupt normal to hot on sensor 3 + * 25 : Interrupt high offset on sensor 3 + * 24 : Interrupt low offset on sensor 3 + * + * 23 : Interrupt hot threshold on sensor 3 + * 22 : Interrupt cold threshold on sensor 3 + * 21 : Interrupt using filter on sensor 2 + * 20 : Interrupt using filter on sensor 1 + * + * 19 : Interrupt using filter on sensor 0 + * 18 : Interrupt using immediate on sensor 2 + * 17 : Interrupt using immediate on sensor 1 + * 16 : Interrupt using immediate on sensor 0 + * + * 15 : Interrupt device access timeout interrupt + * 14 : Interrupt normal to hot on sensor 2 + * 13 : Interrupt high offset interrupt on sensor 2 + * 12 : Interrupt low offset interrupt on sensor 2 + * + * 11 : Interrupt hot threshold on sensor 2 + * 10 : Interrupt cold threshold on sensor 2 + * 9 : Interrupt normal to hot on sensor 1 + * 8 : Interrupt high offset interrupt on sensor 1 + * + * 7 : Interrupt low offset interrupt on sensor 1 + * 6 : Interrupt hot threshold on sensor 1 + * 5 : Interrupt cold threshold on sensor 1 + * 4 : Interrupt normal to hot on sensor 0 + * + * 3 : Interrupt high offset interrupt on sensor 0 + * 2 : Interrupt low offset interrupt on sensor 0 + * 1 : Interrupt hot threshold on sensor 0 + * 0 : Interrupt cold threshold on sensor 0 + * + * We are interested in the sensor(s) responsible of the + * interrupt event. We update the thermal framework with the + * thermal zone associated with the sensor. The framework will + * take care of the rest whatever the kind of interrupt, we + * are only interested in which sensor raised the interrupt. + * + * sensor 3 interrupt: 0001 1111 1100 0000 0000 0000 0000 0000 + * => 0x1FC00000 + * sensor 2 interrupt: 0000 0000 0010 0100 0111 1100 0000 0000 + * => 0x00247C00 + * sensor 1 interrupt: 0000 0000 0001 0001 0000 0011 1110 0000 + * => 0X000881F0 + * sensor 0 interrupt: 0000 0000 0000 1001 0000 0000 0001 1111 + * => 0x0009001F + */ + value = readl(LVTS_MONINTSTS(lvts_ctrl->base)); + + /* + * Let's figure out which sensors raised the interrupt + * + * NOTE: the masks array must be ordered with the index + * corresponding to the sensor id eg. index=0, mask for + * sensor0. + */ + for (i = 0; i < ARRAY_SIZE(masks); i++) { + + if (!(value & masks[i])) + continue; + + thermal_zone_device_update(lvts_ctrl->sensors[i].tz, + THERMAL_TRIP_VIOLATED); + iret |= IRQ_HANDLED; + } + + /* + * Write back to clear the interrupt status (W1C) + */ + writel(value, LVTS_MONINTSTS(lvts_ctrl->base)); + + return iret; +} + +/* + * Temperature interrupt handler. Even if the driver supports more + * interrupt modes, we use the interrupt when the temperature crosses + * the hot threshold the way up and the way down (modulo the + * hysteresis). + * + * Each thermal domain has a couple of interrupts, one for hardware + * reset and another one for all the thermal events happening on the + * different sensors. + * + * The interrupt is configured for thermal events when crossing the + * hot temperature limit. At each interrupt, we check in every + * controller if there is an interrupt pending. + */ +static irqreturn_t lvts_irq_handler(int irq, void *data) +{ + struct lvts_domain *lvts_td = data; + irqreturn_t iret = IRQ_NONE; + int i; + + for (i = 0; i < lvts_td->num_lvts_ctrl; i++) + iret |= lvts_ctrl_irq_handler(lvts_td->lvts_ctrl); + + return iret; +} + +static struct thermal_zone_device_ops lvts_ops = { + .get_temp = lvts_get_temp, + .set_trips = lvts_set_trips, +}; + +static int __init lvts_sensor_init(struct device *dev, + struct lvts_ctrl *lvts_ctrl, + struct lvts_ctrl_data *lvts_ctrl_data) +{ + struct lvts_sensor *lvts_sensor = lvts_ctrl->sensors; + void __iomem *msr_regs[] = { + LVTS_MSR0(lvts_ctrl->base), + LVTS_MSR1(lvts_ctrl->base), + LVTS_MSR2(lvts_ctrl->base), + LVTS_MSR3(lvts_ctrl->base) + }; + + void __iomem *imm_regs[] = { + LVTS_IMMD0(lvts_ctrl->base), + LVTS_IMMD1(lvts_ctrl->base), + LVTS_IMMD2(lvts_ctrl->base), + LVTS_IMMD3(lvts_ctrl->base) + }; + + int i; + + for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++) { + + int dt_id = lvts_ctrl_data->lvts_sensor[i].dt_id; + + /* + * At this point, we don't know which id matches which + * sensor. Let's set arbitrally the id from the index. + */ + lvts_sensor[i].id = i; + + /* + * The thermal zone registration will set the trip + * point interrupt in the thermal controller + * register. But this one will be reset in the + * initialization after. So we need to post pone the + * thermal zone creation after the controller is + * setup. For this reason, we store the device tree + * node id from the data in the sensor structure + */ + lvts_sensor[i].dt_id = dt_id; + + /* + * We assign the base address of the thermal + * controller as a back pointer. So it will be + * accessible from the different thermal framework ops + * as we pass the lvts_sensor pointer as thermal zone + * private data. + */ + lvts_sensor[i].base = lvts_ctrl->base; + + /* + * Each sensor has its own register address to read from. + */ + lvts_sensor[i].msr = lvts_ctrl_data->mode == LVTS_MSR_IMMEDIATE_MODE ? + imm_regs[i] : msr_regs[i]; + }; + + lvts_ctrl->num_lvts_sensor = lvts_ctrl_data->num_lvts_sensor; + + return 0; +} + +/* + * The efuse blob values follows the sensor enumeration per thermal + * controller. The decoding of the stream is as follow: + * + * <--?-> <----big0 ???---> <-sensor0-> <-0-> + * ------------------------------------------ + * index in the stream: : | 0x0 | 0x1 | 0x2 | 0x3 | 0x4 | 0x5 | 0x6 | + * ------------------------------------------ + * + * <--sensor1--><-0-> <----big1 ???---> <-sen + * ------------------------------------------ + * | 0x7 | 0x8 | 0x9 | 0xA | 0xB | OxC | OxD | + * ------------------------------------------ + * + * sor0-> <-0-> <-sensor1-> <-0-> .......... + * ------------------------------------------ + * | 0x7 | 0x8 | 0x9 | 0xA | 0xB | OxC | OxD | + * ------------------------------------------ + * + * And so on ... + * + * The data description gives the offset of the calibration data in + * this bytes stream for each sensor. + * + * Each thermal controller can handle up to 4 sensors max, we don't + * care if there are less as the array of calibration is sized to 4 + * anyway. The unused sensor slot will be zeroed. + */ +static int __init lvts_calibration_init(struct device *dev, + struct lvts_ctrl *lvts_ctrl, + struct lvts_ctrl_data *lvts_ctrl_data, + u8 *efuse_calibration) +{ + int i; + + for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++) + memcpy(&lvts_ctrl->calibration[i], + efuse_calibration + lvts_ctrl_data->cal_offset[i], 2); + + return 0; +} + +/* + * The efuse bytes stream can be split into different chunk of + * nvmems. This function reads and concatenate those into a single + * buffer so it can be read sequentially when initializing the + * calibration data. + */ +static int lvts_calibration_read(struct device *dev, struct lvts_domain *lvts_td, + struct lvts_data *lvts_data) +{ + struct device_node *np = dev_of_node(dev); + struct nvmem_cell *cell; + struct property *prop; + const char *cell_name; + + of_property_for_each_string(np, "nvmem-cell-names", prop, cell_name) { + size_t len; + u8 *efuse; + + cell = of_nvmem_cell_get(np, cell_name); + if (IS_ERR(cell)) { + dev_dbg(dev, "Failed to get cell '%s'\n", cell_name); + return PTR_ERR(cell); + } + + efuse = nvmem_cell_read(cell, &len); + + nvmem_cell_put(cell); + + if (IS_ERR(efuse)) { + dev_dbg(dev, "Failed to read cell '%s'\n", cell_name); + return PTR_ERR(efuse); + } + + lvts_td->calib = devm_krealloc(dev, lvts_td->calib, + lvts_td->calib_len + len, GFP_KERNEL); + if (!lvts_td->calib) + return -ENOMEM; + + memcpy(lvts_td->calib + lvts_td->calib_len, efuse, len); + + lvts_td->calib_len += len; + + kfree(efuse); + } + + return 0; +} + +static int __init lvts_golden_temp_init(struct device *dev, u32 *value) +{ + u32 gt; + + gt = (*value) >> 24; + + if (gt && gt < LVTS_GOLDEN_TEMP_MAX) + golden_temp = gt; + + coeff_b = golden_temp * 500 + LVTS_COEFF_B; + + return 0; +} + +static int __init lvts_ctrl_init(struct device *dev, + struct lvts_domain *lvts_td, + struct lvts_data *lvts_data) +{ + size_t size = sizeof(*lvts_td->lvts_ctrl) * lvts_data->num_lvts_ctrl; + struct lvts_ctrl *lvts_ctrl; + int i, ret; + + /* + * Create the calibration bytes stream from efuse data + */ + ret = lvts_calibration_read(dev, lvts_td, lvts_data); + if (ret) + return ret; + + /* + * The golden temp information is contained in the first chunk + * of efuse data. + */ + ret = lvts_golden_temp_init(dev, (u32 *)lvts_td->calib); + if (ret) + return ret; + + lvts_ctrl = devm_kzalloc(dev, size, GFP_KERNEL); + if (!lvts_ctrl) + return -ENOMEM; + + for (i = 0; i < lvts_data->num_lvts_ctrl; i++) { + + lvts_ctrl[i].base = lvts_td->base + lvts_data->lvts_ctrl[i].offset; + + ret = lvts_sensor_init(dev, &lvts_ctrl[i], + &lvts_data->lvts_ctrl[i]); + if (ret) + return ret; + + ret = lvts_calibration_init(dev, &lvts_ctrl[i], + &lvts_data->lvts_ctrl[i], + lvts_td->calib); + if (ret) + return ret; + + /* + * The mode the ctrl will use to read the temperature + * (filtered or immediate) + */ + lvts_ctrl[i].mode = lvts_data->lvts_ctrl[i].mode; + + /* + * The temperature to raw temperature must be done + * after initializing the calibration. + */ + lvts_ctrl[i].hw_tshut_raw_temp = + lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp); + } + + /* + * We no longer need the efuse bytes stream, let's free it + */ + devm_kfree(dev, lvts_td->calib); + + lvts_td->lvts_ctrl = lvts_ctrl; + lvts_td->num_lvts_ctrl = lvts_data->num_lvts_ctrl; + + return 0; +} + +/* + * At this point the configuration register is the only place in the + * driver where we write multiple values. Per hardware constraint, + * each write in the configuration register must be separated by a + * delay of 2 us. + */ +static void lvts_write_config(struct lvts_ctrl *lvts_ctrl, u32 *cmds, int nr_cmds) +{ + int i; + + /* + * Configuration register + */ + for (i = 0; i < nr_cmds; i++) { + writel(cmds[i], LVTS_CONFIG(lvts_ctrl->base)); + usleep_range(2, 4); + } +} + +static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl) +{ + u32 value; + + /* + * LVTS_PROTCTL : Thermal Protection Sensor Selection + * + * Bits: + * + * 19-18 : Sensor to base the protection on + * 17-16 : Strategy: + * 00 : Average of 4 sensors + * 01 : Max of 4 sensors + * 10 : Selected sensor with bits 19-18 + * 11 : Reserved + */ + value = BIT(16); + writel(value, LVTS_PROTCTL(lvts_ctrl->base)); + + /* + * LVTS_PROTTA : Stage 1 temperature threshold + * LVTS_PROTTB : Stage 2 temperature threshold + * LVTS_PROTTC : Stage 3 temperature threshold + * + * Bits: + * + * 14-0: Raw temperature threshold + * + * writel(0x0, LVTS_PROTTA(lvts_ctrl->base)); + * writel(0x0, LVTS_PROTTB(lvts_ctrl->base)); + */ + writel(lvts_ctrl->hw_tshut_raw_temp, LVTS_PROTTC(lvts_ctrl->base)); + + /* + * LVTS_MONINT : Interrupt configuration register + * + * The LVTS_MONINT register layout is the same as the LVTS_MONINTSTS + * register, except we set the bits to enable the interrupt. + */ + value = 0x9FBF7BDE; + writel(value, LVTS_MONINT(lvts_ctrl->base)); + + return 0; +} + +static int lvts_domain_reset(struct device *dev, struct reset_control *reset) +{ + int ret; + + ret = reset_control_assert(reset); + if (ret) + return ret; + + return reset_control_deassert(reset); +} + +/* + * Enable or disable the clocks of a specified thermal controller + */ +static int lvts_ctrl_set_enable(struct lvts_ctrl *lvts_ctrl, int enable) +{ + /* + * LVTS_CLKEN : Internal LVTS clock + * + * Bits: + * + * 0 : enable / disable clock + */ + writel(enable, LVTS_CLKEN(lvts_ctrl->base)); + + return 0; +} + +static inline int lvts_ctrl_enable(struct device *dev, struct lvts_ctrl *lvts_ctrl) +{ + return lvts_ctrl_set_enable(lvts_ctrl, 1); +} + +static inline int lvts_ctrl_disable(struct device *dev, struct lvts_ctrl *lvts_ctrl) +{ + return lvts_ctrl_set_enable(lvts_ctrl, 0); +} + +static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ctrl) +{ + u32 id, cmds[] = { 0xC103FFFF, 0xC502FF55 }; + + lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds)); + + /* + * LVTS_ID : Get ID and status of the thermal controller + * + * Bits: + * + * 0-5 : thermal controller id + * 7 : thermal controller connection is valid + */ + id = readl(LVTS_ID(lvts_ctrl->base)); + if (!(id & BIT(7))) + return -EIO; + + return 0; +} + +static int lvts_ctrl_initialize(struct device *dev, struct lvts_ctrl *lvts_ctrl) +{ + /* + * Write device mask: 0xC1030000 + */ + u32 cmds[] = { + 0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1, + 0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300, + 0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC, + 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1 + }; + + lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds)); + + return 0; +} + +static int lvts_ctrl_calibrate(struct device *dev, struct lvts_ctrl *lvts_ctrl) +{ + int i; + void __iomem *lvts_edata[] = { + LVTS_EDATA00(lvts_ctrl->base), + LVTS_EDATA01(lvts_ctrl->base), + LVTS_EDATA02(lvts_ctrl->base), + LVTS_EDATA03(lvts_ctrl->base) + }; + + /* + * LVTS_EDATA0X : Efuse calibration reference value for sensor X + * + * Bits: + * + * 20-0 : Efuse value for normalization data + */ + for (i = 0; i < LVTS_SENSOR_MAX; i++) + writel(lvts_ctrl->calibration[i], lvts_edata[i]); + + return 0; +} + +static int lvts_ctrl_configure(struct device *dev, struct lvts_ctrl *lvts_ctrl) +{ + u32 period_unit = (118 * 1000) / (256 * 38); + u32 grp_interval = 1; + u32 flt_interval = 1; + u32 sensor_interval = 1; + u32 hw_filter = 0x2; + u32 value; + + /* + * LVTS_TSSEL : Sensing point index numbering + * + * Bits: + * + * 31-24: ADC Sense 3 + * 23-16: ADC Sense 2 + * 15-8 : ADC Sense 1 + * 7-0 : ADC Sense 0 + */ + value = 0x13121110; + writel(value, LVTS_TSSEL(lvts_ctrl->base)); + + /* + * LVTS_CALSCALE : ADC voltage round + */ + value = 0x300; + writel(value, LVTS_CALSCALE(lvts_ctrl->base)); + + /* + * LVTS_MSRCTL0 : Sensor filtering strategy + * + * Filters: + * + * 000 : One sample + * 001 : Avg 2 samples + * 010 : 4 samples, drop min and max, avg 2 samples + * 011 : 6 samples, drop min and max, avg 4 samples + * 100 : 10 samples, drop min and max, avg 8 samples + * 101 : 18 samples, drop min and max, avg 16 samples + * + * Bits: + * + * 0-2 : Sensor0 filter + * 3-5 : Sensor1 filter + * 6-8 : Sensor2 filter + * 9-11 : Sensor3 filter + */ + value = hw_filter << 9 | hw_filter << 6 | hw_filter << 3 | hw_filter; + writel(value, LVTS_MSRCTL0(lvts_ctrl->base)); + + /* + * LVTS_MSRCTL1 : Measurement control + * + * Bits: + * + * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3 + * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2 + * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1 + * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0 + * + * That configuration will ignore the filtering and the delays + * introduced below in MONCTL1 and MONCTL2 + */ + if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) { + value = BIT(9) | BIT(6) | BIT(5) | BIT(4); + writel(value, LVTS_MSRCTL1(lvts_ctrl->base)); + } + + /* + * LVTS_MONCTL1 : Period unit and group interval configuration + * + * The clock source of LVTS thermal controller is 26MHz. + * + * The period unit is a time base for all the interval delays + * specified in the registers. By default we use 12. The time + * conversion is done by multiplying by 256 and 1/26.10^6 + * + * An interval delay multiplied by the period unit gives the + * duration in seconds. + * + * - Filter interval delay is a delay between two samples of + * the same sensor. + * + * - Sensor interval delay is a delay between two samples of + * different sensors. + * + * - Group interval delay is a delay between different rounds. + * + * For example: + * If Period unit = C, filter delay = 1, sensor delay = 2, group delay = 1, + * and two sensors, TS1 and TS2, are in a LVTS thermal controller + * and then + * Period unit time = C * 1/26M * 256 = 12 * 38.46ns * 256 = 118.149us + * Filter interval delay = 1 * Period unit = 118.149us + * Sensor interval delay = 2 * Period unit = 236.298us + * Group interval delay = 1 * Period unit = 118.149us + * + * TS1 TS1 ... TS1 TS2 TS2 ... TS2 TS1... + * <--> Filter interval delay + * <--> Sensor interval delay + * <--> Group interval delay + * Bits: + * 29 - 20 : Group interval + * 16 - 13 : Send a single interrupt when crossing the hot threshold (1) + * or an interrupt everytime the hot threshold is crossed (0) + * 9 - 0 : Period unit + * + */ + value = grp_interval << 20 | period_unit; + writel(value, LVTS_MONCTL1(lvts_ctrl->base)); + + /* + * LVTS_MONCTL2 : Filtering and sensor interval + * + * Bits: + * + * 25-16 : Interval unit in PERIOD_UNIT between sample on + * the same sensor, filter interval + * 9-0 : Interval unit in PERIOD_UNIT between each sensor + * + */ + value = flt_interval << 16 | sensor_interval; + writel(value, LVTS_MONCTL2(lvts_ctrl->base)); + + return lvts_irq_init(lvts_ctrl); +} + +static int lvts_ctrl_start(struct device *dev, struct lvts_ctrl *lvts_ctrl) +{ + struct lvts_sensor *lvts_sensors = lvts_ctrl->sensors; + struct thermal_zone_device *tz; + u32 sensor_map = 0; + int i; + + for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++) { + + int dt_id = lvts_sensors[i].dt_id; + + tz = devm_thermal_of_zone_register(dev, dt_id, &lvts_sensors[i], + &lvts_ops); + if (IS_ERR(tz)) { + /* + * This thermal zone is not described in the + * device tree. It is not an error from the + * thermal OF code POV, we just continue. + */ + if (PTR_ERR(tz) == -ENODEV) + continue; + + return PTR_ERR(tz); + } + + /* + * The thermal zone pointer will be needed in the + * interrupt handler, we store it in the sensor + * structure. The thermal domain structure will be + * passed to the interrupt handler private data as the + * interrupt is shared for all the controller + * belonging to the thermal domain. + */ + lvts_sensors[i].tz = tz; + + /* + * This sensor was correctly associated with a thermal + * zone, let's set the corresponding bit in the sensor + * map, so we can enable the temperature monitoring in + * the hardware thermal controller. + */ + sensor_map |= BIT(i); + } + + /* + * Bits: + * 9: Single point access flow + * 0-3: Enable sensing point 0-3 + * + * The initialization of the thermal zones give us + * which sensor point to enable. If any thermal zone + * was not described in the device tree, it won't be + * enabled here in the sensor map. + */ + writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base)); + + return 0; +} + +static int lvts_domain_init(struct device *dev, struct lvts_domain *lvts_td, + struct lvts_data *lvts_data) +{ + struct lvts_ctrl *lvts_ctrl; + int i, ret; + + ret = lvts_ctrl_init(dev, lvts_td, lvts_data); + if (ret) + return ret; + + ret = lvts_domain_reset(dev, lvts_td->reset); + if (ret) { + dev_dbg(dev, "Failed to reset domain"); + return ret; + } + + for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { + + lvts_ctrl = &lvts_td->lvts_ctrl[i]; + + /* + * Initialization steps: + * + * - Enable the clock + * - Connect to the LVTS + * - Initialize the LVTS + * - Prepare the calibration data + * - Select monitored sensors + * [ Configure sampling ] + * [ Configure the interrupt ] + * - Start measurement + */ + ret = lvts_ctrl_enable(dev, lvts_ctrl); + if (ret) { + dev_dbg(dev, "Failed to enable LVTS clock"); + return ret; + } + + ret = lvts_ctrl_connect(dev, lvts_ctrl); + if (ret) { + dev_dbg(dev, "Failed to connect to LVTS controller"); + return ret; + } + + ret = lvts_ctrl_initialize(dev, lvts_ctrl); + if (ret) { + dev_dbg(dev, "Failed to initialize controller"); + return ret; + } + + ret = lvts_ctrl_calibrate(dev, lvts_ctrl); + if (ret) { + dev_dbg(dev, "Failed to calibrate controller"); + return ret; + } + + ret = lvts_ctrl_configure(dev, lvts_ctrl); + if (ret) { + dev_dbg(dev, "Failed to configure controller"); + return ret; + } + + ret = lvts_ctrl_start(dev, lvts_ctrl); + if (ret) { + dev_dbg(dev, "Failed to start controller"); + return ret; + } + } + + return lvts_debugfs_init(dev, lvts_td); +} + +static int lvts_probe(struct platform_device *pdev) +{ + struct lvts_data *lvts_data; + struct lvts_domain *lvts_td; + struct device *dev = &pdev->dev; + struct resource *res; + int irq, ret; + + lvts_td = devm_kzalloc(dev, sizeof(*lvts_td), GFP_KERNEL); + if (!lvts_td) + return -ENOMEM; + + lvts_data = (struct lvts_data *)of_device_get_match_data(dev); + if (!lvts_data) { + dev_dbg(dev, "No platforme data"); + return -ENODATA; + }; + + lvts_td->clk = devm_clk_get_enabled(dev, NULL); + if (IS_ERR(lvts_td->clk)) { + dev_dbg(dev, "Failed to retrieve clock\n"); + return PTR_ERR(lvts_td->clk); + } + + res = platform_get_mem_or_io(pdev, 0); + if (!res) { + dev_dbg(dev, "No IO resource\n"); + return -ENXIO; + } + + lvts_td->base = devm_ioremap_resource(dev, res); + if (IS_ERR(lvts_td->base)) { + dev_dbg(dev, "Failed to map io resource\n"); + return PTR_ERR(lvts_td->base); + } + + lvts_td->reset = devm_reset_control_get_by_index(dev, 0); + if (IS_ERR(lvts_td->reset)) { + dev_dbg(dev, "Failed to get reset control\n"); + return PTR_ERR(lvts_td->reset); + } + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_dbg(dev, "No irq resource\n"); + return irq; + } + + ret = lvts_domain_init(dev, lvts_td, lvts_data); + if (ret) { + dev_dbg(dev, "Failed to initialize the lvts domain\n"); + return ret; + } + + /* + * At this point the LVTS is initialized and enabled. We can + * safely enable the interrupt. + */ + ret = devm_request_threaded_irq(dev, irq, NULL, lvts_irq_handler, + IRQF_ONESHOT, dev_name(dev), lvts_td); + if (ret) { + dev_dbg(dev, "Failed to request interrupt\n"); + return ret; + } + + platform_set_drvdata(pdev, lvts_td); + + return 0; +} + +static int lvts_remove(struct platform_device *pdev) +{ + struct lvts_domain *lvts_td; + struct device *dev = &pdev->dev; + int i; + + lvts_td = platform_get_drvdata(pdev); + + for (i = 0; i < lvts_td->num_lvts_ctrl; i++) + lvts_ctrl_disable(dev, &lvts_td->lvts_ctrl[i]); + + lvts_debugfs_exit(); + + return 0; +} + +static struct lvts_ctrl_data mt819x_lvts_data_ctrl[] = { + { + .cal_offset = { 0x4, 0x7 }, + .lvts_sensor = { + { .dt_id = MT819x_MCU_BIG_CPU0 }, + { .dt_id = MT819x_MCU_BIG_CPU1 } + }, + .num_lvts_sensor = 2, + .offset = 0x0, + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, + }, + + { + .cal_offset = { 0xd, 0x10 }, + .lvts_sensor = { + { .dt_id = MT819x_MCU_BIG_CPU2 }, + { .dt_id = MT819x_MCU_BIG_CPU3 } + }, + .num_lvts_sensor = 2, + .offset = 0x100, + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, + }, + + { + .cal_offset = { 0x16, 0x19, 0x1c, 0x1f }, + .lvts_sensor = { + { .dt_id = MT819x_MCU_LITTLE_CPU0 }, + { .dt_id = MT819x_MCU_LITTLE_CPU1 }, + { .dt_id = MT819x_MCU_LITTLE_CPU2 }, + { .dt_id = MT819x_MCU_LITTLE_CPU3 } + }, + .num_lvts_sensor = 4, + .offset = 0x200, + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, + } +}; + +static struct lvts_data mt819x_lvts_mcu_data = { + .lvts_ctrl = mt819x_lvts_data_ctrl, + .num_lvts_ctrl = ARRAY_SIZE(mt819x_lvts_data_ctrl), +}; + +static const struct of_device_id lvts_of_match[] = { + { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt819x_lvts_mcu_data }, + {}, +}; +MODULE_DEVICE_TABLE(of, lvts_of_match); + +static struct platform_driver lvts_driver = { + .probe = lvts_probe, + .remove = lvts_remove, + .driver = { + .name = "mtk-lvts-thermal", + .of_match_table = lvts_of_match, + }, +}; +module_platform_driver(lvts_driver); + +MODULE_AUTHOR("Balsam CHIHI "); +MODULE_DESCRIPTION("MediaTek LVTS Thermal Driver"); +MODULE_LICENSE("GPL"); diff --git a/include/dt-bindings/thermal/mediatek-lvts.h b/include/dt-bindings/thermal/mediatek-lvts.h new file mode 100644 index 000000000000..80d060400236 --- /dev/null +++ b/include/dt-bindings/thermal/mediatek-lvts.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2023 MediaTek Inc. + * Author: Balsam CHIHI + */ + +#ifndef __MEDIATEK_LVTS_DT_H +#define __MEDIATEK_LVTS_DT_H + +#define MT819x_MCU_BIG_CPU0 0 +#define MT819x_MCU_BIG_CPU1 1 +#define MT819x_MCU_BIG_CPU2 2 +#define MT819x_MCU_BIG_CPU3 3 +#define MT819x_MCU_LITTLE_CPU0 4 +#define MT819x_MCU_LITTLE_CPU1 5 +#define MT819x_MCU_LITTLE_CPU2 6 +#define MT819x_MCU_LITTLE_CPU3 7 + +#endif /* __MEDIATEK_LVTS_DT_H */ From patchwork Thu Jan 12 15:28:54 2023 Content-Type: text/plain; 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[77.158.188.58]) by smtp.gmail.com with ESMTPSA id l24-20020a1ced18000000b003d99da8d30asm26395909wmh.46.2023.01.12.07.29.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Jan 2023 07:29:57 -0800 (PST) From: bchihi@baylibre.com To: daniel.lezcano@linaro.org, rafael@kernel.org, amitk@kernel.org, rui.zhang@intel.com Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, khilman@baylibre.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, james.lo@mediatek.com, rex-bc.chen@mediatek.com Subject: [PATCH v10 5/6] arm64/dts/mt8195: Add thermal zones and thermal nodes Date: Thu, 12 Jan 2023 16:28:54 +0100 Message-Id: <20230112152855.216072-6-bchihi@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230112152855.216072-1-bchihi@baylibre.com> References: <20230112152855.216072-1-bchihi@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Balsam CHIHI Add thermal zones and thermal nodes for the mt8195. Signed-off-by: Balsam CHIHI --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 129 +++++++++++++++++++++++ 1 file changed, 129 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 09df105f4606..683e5057d68d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include / { compatible = "mediatek,mt8195"; @@ -954,6 +955,17 @@ spi0: spi@1100a000 { status = "disabled"; }; + lvts_ap: thermal-sensor@1100b000 { + compatible = "mediatek,mt8195-lvts-ap"; + reg = <0 0x1100b000 0 0x1000>; + interrupts = ; + clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; + resets = <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>; + nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>; + nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2"; + #thermal-sensor-cells = <1>; + }; + spi1: spi@11010000 { compatible = "mediatek,mt8195-spi", "mediatek,mt6765-spi"; @@ -1114,6 +1126,17 @@ mmc2: mmc@11250000 { status = "disabled"; }; + lvts_mcu: thermal-sensor@11278000 { + compatible = "mediatek,mt8195-lvts-mcu"; + reg = <0 0x11278000 0 0x1000>; + interrupts = ; + clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; + resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>; + nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>; + nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2"; + #thermal-sensor-cells = <1>; + }; + xhci1: usb@11290000 { compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci"; @@ -2387,4 +2410,110 @@ dp_tx: dp-tx@1c600000 { status = "disabled"; }; }; + + thermal_zones: thermal-zones { + cpu0-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu MT819x_MCU_LITTLE_CPU0>; + trips { + cpu0_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu MT819x_MCU_LITTLE_CPU1>; + trips { + cpu1_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu2-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu MT819x_MCU_LITTLE_CPU2>; + trips { + cpu2_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu3-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu MT819x_MCU_LITTLE_CPU3>; + trips { + cpu3_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu4-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu MT819x_MCU_BIG_CPU0>; + trips { + cpu4_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu5-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu MT819x_MCU_BIG_CPU1>; + trips { + cpu5_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu6-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu MT819x_MCU_BIG_CPU2>; + trips { + cpu6_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu7-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu MT819x_MCU_BIG_CPU3>; + trips { + cpu7_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; }; From patchwork Thu Jan 12 15:28:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Balsam CHIHI X-Patchwork-Id: 642477 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F297C54EBD for ; Thu, 12 Jan 2023 15:39:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240532AbjALPjw (ORCPT ); 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[77.158.188.58]) by smtp.gmail.com with ESMTPSA id l24-20020a1ced18000000b003d99da8d30asm26395909wmh.46.2023.01.12.07.29.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Jan 2023 07:29:57 -0800 (PST) From: bchihi@baylibre.com To: daniel.lezcano@linaro.org, rafael@kernel.org, amitk@kernel.org, rui.zhang@intel.com Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, khilman@baylibre.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, james.lo@mediatek.com, rex-bc.chen@mediatek.com Subject: [PATCH v10 6/6] arm64/dts/mt8195: Add temperature mitigation threshold Date: Thu, 12 Jan 2023 16:28:55 +0100 Message-Id: <20230112152855.216072-7-bchihi@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230112152855.216072-1-bchihi@baylibre.com> References: <20230112152855.216072-1-bchihi@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Balsam CHIHI The mt8195 board has several hotspots around the CPUs. Specify the targeted temperature threshold when to apply the mitigation and define the associated cooling devices. Signed-off-by: Balsam CHIHI --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 153 ++++++++++++++++++++--- 1 file changed, 137 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 683e5057d68d..0d6642603095 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include #include / { @@ -2413,107 +2414,227 @@ dp_tx: dp-tx@1c600000 { thermal_zones: thermal-zones { cpu0-thermal { - polling-delay = <0>; - polling-delay-passive = <0>; + polling-delay = <1000>; + polling-delay-passive = <250>; thermal-sensors = <&lvts_mcu MT819x_MCU_LITTLE_CPU0>; trips { + cpu0_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; cpu0_crit: trip-crit { temperature = <100000>; hysteresis = <2000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu0_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu1-thermal { - polling-delay = <0>; - polling-delay-passive = <0>; + polling-delay = <1000>; + polling-delay-passive = <250>; thermal-sensors = <&lvts_mcu MT819x_MCU_LITTLE_CPU1>; trips { + cpu1_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; cpu1_crit: trip-crit { temperature = <100000>; hysteresis = <2000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu1_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu2-thermal { - polling-delay = <0>; - polling-delay-passive = <0>; + polling-delay = <1000>; + polling-delay-passive = <250>; thermal-sensors = <&lvts_mcu MT819x_MCU_LITTLE_CPU2>; trips { + cpu2_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; cpu2_crit: trip-crit { temperature = <100000>; hysteresis = <2000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu2_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu3-thermal { - polling-delay = <0>; - polling-delay-passive = <0>; + polling-delay = <1000>; + polling-delay-passive = <250>; thermal-sensors = <&lvts_mcu MT819x_MCU_LITTLE_CPU3>; trips { + cpu3_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; cpu3_crit: trip-crit { temperature = <100000>; hysteresis = <2000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu3_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu4-thermal { - polling-delay = <0>; - polling-delay-passive = <0>; + polling-delay = <1000>; + polling-delay-passive = <250>; thermal-sensors = <&lvts_mcu MT819x_MCU_BIG_CPU0>; trips { + cpu4_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; cpu4_crit: trip-crit { temperature = <100000>; hysteresis = <2000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu4_alert>; + cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu5-thermal { - polling-delay = <0>; - polling-delay-passive = <0>; + polling-delay = <1000>; + polling-delay-passive = <250>; thermal-sensors = <&lvts_mcu MT819x_MCU_BIG_CPU1>; trips { + cpu5_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; cpu5_crit: trip-crit { temperature = <100000>; hysteresis = <2000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu5_alert>; + cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu6-thermal { - polling-delay = <0>; - polling-delay-passive = <0>; + polling-delay = <1000>; + polling-delay-passive = <250>; thermal-sensors = <&lvts_mcu MT819x_MCU_BIG_CPU2>; trips { + cpu6_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; cpu6_crit: trip-crit { temperature = <100000>; hysteresis = <2000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu6_alert>; + cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu7-thermal { - polling-delay = <0>; - polling-delay-passive = <0>; + polling-delay = <1000>; + polling-delay-passive = <250>; thermal-sensors = <&lvts_mcu MT819x_MCU_BIG_CPU3>; trips { + cpu7_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; cpu7_crit: trip-crit { temperature = <100000>; hysteresis = <2000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu7_alert>; + cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; }; };