From patchwork Wed Jan 11 12:37:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 641455 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B472BC5479D for ; Wed, 11 Jan 2023 12:37:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231420AbjAKMha (ORCPT ); Wed, 11 Jan 2023 07:37:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48178 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236064AbjAKMhY (ORCPT ); Wed, 11 Jan 2023 07:37:24 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED74521A2; Wed, 11 Jan 2023 04:37:22 -0800 (PST) X-UUID: ae8ae89c91ac11ed945fc101203acc17-20230111 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=uCG4zYttmZUBQAK3IT9ABFmka0Q4FRHaDmf82O8hATU=; b=FKrG4tDzLuJvP3GBknGnTt5gVD9gXOtUoZ5MWz0Z8HsIXgj1Ulah9/t7gT+h7R/dhX+WQoTAD0v+nID60VAHNW4jq94n5XXlfN5B2jNjDZthkZqpOJzaIflQQAG0aQwu/TAY0RQ4LCW77Ht1QuMgMardzMsueYld5X+M+I0/yV0=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.17, REQID:59415797-dd02-4abd-ac34-a9aac8473859, IP:0, U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:90 X-CID-INFO: VERSION:1.1.17, REQID:59415797-dd02-4abd-ac34-a9aac8473859, IP:0, URL :0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTIO N:quarantine,TS:90 X-CID-META: VersionHash:543e81c, CLOUDID:d12285f5-ff42-4fb0-b929-626456a83c14, B ulkID:230111203716X9C0JKEN,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OS I:0,OSA:0 X-CID-APTURL: Status:success,Category:nil,Trust:0,Unknown:0,Malicious:0 X-CID-BVR: 0 X-UUID: ae8ae89c91ac11ed945fc101203acc17-20230111 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 60869025; Wed, 11 Jan 2023 20:37:16 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 11 Jan 2023 20:37:15 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 11 Jan 2023 20:37:15 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski , Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Stephen Boyd , AngeloGioacchino Del Regno , CC: , , , , , , Allen-KH Cheng Subject: [PATCH 2/9] dt-bindings: spmi: spmi-mtk-pmif: Document mediatek,mt8195-spmi as fallback of mediatek,mt8186-spmi Date: Wed, 11 Jan 2023 20:37:04 +0800 Message-ID: <20230111123711.32020-3-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230111123711.32020-1-allen-kh.cheng@mediatek.com> References: <20230111123711.32020-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The mt8186-spmi is used as compatible with mt8195-spmi on the MT8186, document this situation. Signed-off-by: Allen-KH Cheng --- .../devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml b/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml index abcbbe13723f..e4f465abcfe9 100644 --- a/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml +++ b/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml @@ -18,9 +18,14 @@ allOf: properties: compatible: - enum: - - mediatek,mt6873-spmi - - mediatek,mt8195-spmi + oneOf: + - enum: + - mediatek,mt6873-spmi + - mediatek,mt8195-spmi + - items: + - enum: + - mediatek,mt8186-spmi + - const: mediatek,mt8195-spmi reg: maxItems: 2 From patchwork Wed Jan 11 12:37:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 641457 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76494C46467 for ; Wed, 11 Jan 2023 12:37:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237682AbjAKMh1 (ORCPT ); Wed, 11 Jan 2023 07:37:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48158 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232251AbjAKMhX (ORCPT ); Wed, 11 Jan 2023 07:37:23 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B44E6658A; Wed, 11 Jan 2023 04:37:21 -0800 (PST) X-UUID: ae8e3d7691ac11ed945fc101203acc17-20230111 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=/qs5AP02dhkCWqdSuirwOLn7ESeQZZWhOOpRZScjecQ=; b=na3MEbNFBY/winbUnT2Xem7DQi9zQDLZhzCXY4RhYNEry3wjJVO8x8N+kW4GX2A3q9AFdvMBYSQLU7dgwvQKhUoIIE+nIpaODqUnZFsnl7i/NiCkqBXwK9BYxhZmUYmJe2Orq0PgSmXaDN02B3mSkyWF/2bz1Q7mQvHmtYzUISE=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.17, REQID:0e39f8e8-c6cc-4e29-b1ec-d6afad077754, IP:0, U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:90 X-CID-INFO: VERSION:1.1.17, REQID:0e39f8e8-c6cc-4e29-b1ec-d6afad077754, IP:0, URL :0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTIO N:quarantine,TS:90 X-CID-META: VersionHash:543e81c, CLOUDID:d22285f5-ff42-4fb0-b929-626456a83c14, B ulkID:2301112037166JRN7V5M,BulkQuantity:1,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:43,QS:nil,BEC:nil,COL:0,OSI :0,OSA:0 X-CID-APTURL: Status:success,Category:nil,Trust:0,Unknown:0,Malicious:0 X-CID-BVR: 0,NGT X-UUID: ae8e3d7691ac11ed945fc101203acc17-20230111 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1796133815; Wed, 11 Jan 2023 20:37:16 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 11 Jan 2023 20:37:16 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 11 Jan 2023 20:37:16 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski , Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Stephen Boyd , AngeloGioacchino Del Regno , CC: , , , , , , Allen-KH Cheng Subject: [PATCH 3/9] arm64: dts: mediatek: mt8186: Add SPMI node Date: Wed, 11 Jan 2023 20:37:05 +0800 Message-ID: <20230111123711.32020-4-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230111123711.32020-1-allen-kh.cheng@mediatek.com> References: <20230111123711.32020-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add SPMI node for MT8186 SoC. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index 3d88480913eb..a8ff984f1192 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -605,6 +605,25 @@ clock-names = "spi", "wrap"; }; + spmi: spmi@10015000 { + compatible = "mediatek,mt8186-spmi", + "mediatek,mt8195-spmi"; + reg = <0 0x10015000 0 0x000e00>, + <0 0x1001B000 0 0x000100>; + reg-names = "pmif", "spmimst"; + clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, + <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, + <&topckgen CLK_TOP_SPMI_MST>; + clock-names = "pmif_sys_ck", + "pmif_tmr_ck", + "spmimst_clk_mux"; + assigned-clocks = <&topckgen CLK_TOP_SPMI_MST>; + assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; + interrupts = , + ; + status = "disabled"; + }; + systimer: timer@10017000 { compatible = "mediatek,mt8186-timer", "mediatek,mt6765-timer"; From patchwork Wed Jan 11 12:37:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 641456 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8813C67871 for ; Wed, 11 Jan 2023 12:37:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231561AbjAKMh3 (ORCPT ); Wed, 11 Jan 2023 07:37:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48180 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236011AbjAKMhY (ORCPT ); Wed, 11 Jan 2023 07:37:24 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1DCD865C0; Wed, 11 Jan 2023 04:37:22 -0800 (PST) X-UUID: b022bd3891ac11eda06fc9ecc4dadd91-20230111 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=y17TmDmZzJ4uREjBGg1ymgXuWt+fPVJmNlFq7S8gsaI=; b=svtRSjSrxWOqGsaN44OfQtQsplXc+fn52VOVbC5xIeWizBk/dz7bR0WPgKBAggltpiggcORG1mn3xCmXIm0Q1Sfxz4iMGOtysqWFHsTiwXHpFXOV27LAF85y2wBCYb43eWg69z8ViuFaAMhGvAEZZPh3J9ggOtbYTIJICtbihe4=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.17, REQID:95549313-2970-4fcb-a1cd-915ee5cf30db, IP:0, U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:543e81c, CLOUDID:ee2285f5-ff42-4fb0-b929-626456a83c14, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0 X-CID-BVR: 0,NGT X-UUID: b022bd3891ac11eda06fc9ecc4dadd91-20230111 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 347402808; Wed, 11 Jan 2023 20:37:19 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 11 Jan 2023 20:37:18 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 11 Jan 2023 20:37:17 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski , Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Stephen Boyd , AngeloGioacchino Del Regno , CC: , , , , , , Allen-KH Cheng Subject: [PATCH 6/9] arm64: dts: mediatek: mt8186: Add audio controller node Date: Wed, 11 Jan 2023 20:37:08 +0800 Message-ID: <20230111123711.32020-7-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230111123711.32020-1-allen-kh.cheng@mediatek.com> References: <20230111123711.32020-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add audio controller node for MT8186 SoC. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 62 ++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index 2700c830316f..c52f9be1e750 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -998,6 +998,68 @@ }; }; + afe: audio-controller@11210000 { + compatible = "mediatek,mt8186-sound"; + reg = <0 0x11210000 0 0x2000>; + clocks = <&infracfg_ao CLK_INFRA_AO_AUDIO>, + <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_BCLK>, + <&topckgen CLK_TOP_AUDIO>, + <&topckgen CLK_TOP_AUD_INTBUS>, + <&topckgen CLK_TOP_MAINPLL_D2_D4>, + <&topckgen CLK_TOP_AUD_1>, + <&apmixedsys CLK_APMIXED_APLL1>, + <&topckgen CLK_TOP_AUD_2>, + <&apmixedsys CLK_APMIXED_APLL2>, + <&topckgen CLK_TOP_AUD_ENGEN1>, + <&topckgen CLK_TOP_APLL1_D8>, + <&topckgen CLK_TOP_AUD_ENGEN2>, + <&topckgen CLK_TOP_APLL2_D8>, + <&topckgen CLK_TOP_APLL_I2S0_MCK_SEL>, + <&topckgen CLK_TOP_APLL_I2S1_MCK_SEL>, + <&topckgen CLK_TOP_APLL_I2S2_MCK_SEL>, + <&topckgen CLK_TOP_APLL_I2S4_MCK_SEL>, + <&topckgen CLK_TOP_APLL_TDMOUT_MCK_SEL>, + <&topckgen CLK_TOP_APLL12_CK_DIV0>, + <&topckgen CLK_TOP_APLL12_CK_DIV1>, + <&topckgen CLK_TOP_APLL12_CK_DIV2>, + <&topckgen CLK_TOP_APLL12_CK_DIV4>, + <&topckgen CLK_TOP_APLL12_CK_DIV_TDMOUT_M>, + <&topckgen CLK_TOP_AUDIO_H>, + <&clk26m>; + clock-names = "aud_infra_clk", + "mtkaif_26m_clk", + "top_mux_audio", + "top_mux_audio_int", + "top_mainpll_d2_d4", + "top_mux_aud_1", + "top_apll1_ck", + "top_mux_aud_2", + "top_apll2_ck", + "top_mux_aud_eng1", + "top_apll1_d8", + "top_mux_aud_eng2", + "top_apll2_d8", + "top_i2s0_m_sel", + "top_i2s1_m_sel", + "top_i2s2_m_sel", + "top_i2s4_m_sel", + "top_tdm_m_sel", + "top_apll12_div0", + "top_apll12_div1", + "top_apll12_div2", + "top_apll12_div4", + "top_apll12_div_tdm", + "top_mux_audio_h", + "top_clk26m_clk"; + interrupts = ; + mediatek,apmixedsys = <&apmixedsys>; + mediatek,infracfg = <&infracfg_ao>; + mediatek,topckgen = <&topckgen>; + resets = <&watchdog MT8186_TOPRGU_AUDIO_SW_RST>; + reset-names = "audiosys"; + status = "disabled"; + }; + mmc0: mmc@11230000 { compatible = "mediatek,mt8186-mmc", "mediatek,mt8183-mmc"; From patchwork Wed Jan 11 12:37:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 641453 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 590A4C46467 for ; Wed, 11 Jan 2023 12:37:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238284AbjAKMhd (ORCPT ); Wed, 11 Jan 2023 07:37:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48252 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237970AbjAKMh2 (ORCPT ); Wed, 11 Jan 2023 07:37:28 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D2366558; Wed, 11 Jan 2023 04:37:25 -0800 (PST) X-UUID: b080e4e491ac11eda06fc9ecc4dadd91-20230111 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=cqez+BT8T3P+bnOJ89Ly81+tB76MJsWmGJ/qmPRTHh4=; b=RnFV5b7lc667HA65k5XkZ5KUiMvBwh5hTOo0+gl5PgSKMsRCL804Om7NsxdcywOnONTrJwo9kifbM/F2Tn1DtgrPxR//AACseNH/eMET9fc2ZcU1hUlKVQX5fQP/V++yU4EX2zxXw95fWDZbw2IXHY2AM+/Vl6x/Uo6vSGPYiiM=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.17, REQID:5c5c5857-bd87-409e-8543-63a066284747, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:95 X-CID-INFO: VERSION:1.1.17, REQID:5c5c5857-bd87-409e-8543-63a066284747, IP:0, URL :0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTION :quarantine,TS:95 X-CID-META: VersionHash:543e81c, CLOUDID:885b5b54-dd49-462e-a4be-2143a3ddc739, B ulkID:230111203722OEEZ7EM0,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OS I:0,OSA:0 X-CID-APTURL: Status:success,Category:nil,Trust:0,Unknown:0,Malicious:0 X-CID-BVR: 0,NGT X-UUID: b080e4e491ac11eda06fc9ecc4dadd91-20230111 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1068262159; Wed, 11 Jan 2023 20:37:19 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 11 Jan 2023 20:37:19 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 11 Jan 2023 20:37:19 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski , Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Stephen Boyd , AngeloGioacchino Del Regno , CC: , , , , , , Allen-KH Cheng Subject: [PATCH 8/9] dt-bindings: display: mediatek: Fix the fallback for mediatek,mt8186-disp-ccorr Date: Wed, 11 Jan 2023 20:37:10 +0800 Message-ID: <20230111123711.32020-9-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230111123711.32020-1-allen-kh.cheng@mediatek.com> References: <20230111123711.32020-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The mt8186-disp-ccorr is not fully compatible with the mt8183-disp-ccorr implementation. It causes a crash when system resumes if it binds to the device. We should use mt8192-disp-ccorr as fallback of mt8186-disp-ccorr. Fixes: 8a26ea19d4dc ("dt-bindings: display: mediatek: add MT8186 SoC binding") Signed-off-by: Allen-KH Cheng Reviewed-by: Rob Herring --- .../devicetree/bindings/display/mediatek/mediatek,ccorr.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml index 63fb02014a56..117e3db43f84 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml @@ -32,7 +32,7 @@ properties: - items: - enum: - mediatek,mt8186-disp-ccorr - - const: mediatek,mt8183-disp-ccorr + - const: mediatek,mt8192-disp-ccorr reg: maxItems: 1 From patchwork Wed Jan 11 12:37:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 641454 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79080C63797 for ; Wed, 11 Jan 2023 12:37:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238322AbjAKMhc (ORCPT ); Wed, 11 Jan 2023 07:37:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48240 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235719AbjAKMh1 (ORCPT ); Wed, 11 Jan 2023 07:37:27 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD805766A; Wed, 11 Jan 2023 04:37:25 -0800 (PST) X-UUID: b148a8a891ac11eda06fc9ecc4dadd91-20230111 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=jykuStcNhIaqoh/2vR5M8cvji1f+ctzxDeF4MG+9YW0=; b=RKRjS8/rMN40GOjerItxJVs0PBCfHWdRudgDLxhK9j/daUl4x/gA0lbXvvYrGni9oog0P0jKltk+6FciboM8x+LqAzsdrIupzC8xFh/GY1Go70qsEBdrtyvatGaNRB5Coyc1d3pbUlvbfzA3CbFeVB5AfS0xx/m6Csf0xDe+TpA=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.17, REQID:97e55e01-38ea-4e66-9de2-0982bbb8e867, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:543e81c, CLOUDID:ab4af68b-8530-4eff-9f77-222cf6e2895b, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0 X-CID-BVR: 0 X-UUID: b148a8a891ac11eda06fc9ecc4dadd91-20230111 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 34577008; Wed, 11 Jan 2023 20:37:21 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 11 Jan 2023 20:37:19 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 11 Jan 2023 20:37:19 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski , Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Stephen Boyd , AngeloGioacchino Del Regno , CC: , , , , , , Allen-KH Cheng Subject: [PATCH 9/9] arm64: dts: mediatek: mt8186: Add display nodes Date: Wed, 11 Jan 2023 20:37:11 +0800 Message-ID: <20230111123711.32020-10-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230111123711.32020-1-allen-kh.cheng@mediatek.com> References: <20230111123711.32020-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add display nodes and GCE info for MT8186 SoC. Also, add GCE (Global Command Engine) properties to the display nodes in order to enable the usage of the CMDQ (Command Queue), which is required for operating the display. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 128 +++++++++++++++++++++++ 1 file changed, 128 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index eab30ab01572..8670d37970ef 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -5,6 +5,7 @@ */ /dts-v1/; #include +#include #include #include #include @@ -632,6 +633,15 @@ clocks = <&clk13m>; }; + gce: mailbox@1022c000 { + compatible = "mediatek,mt8186-gce"; + reg = <0 0X1022c000 0 0x4000>; + interrupts = ; + #mbox-cells = <2>; + clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; + clock-names = "gce"; + }; + scp: scp@10500000 { compatible = "mediatek,mt8186-scp"; reg = <0 0x10500000 0 0x40000>, @@ -1197,6 +1207,20 @@ reg = <0 0x14000000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, + <&gce 1 CMDQ_THR_PRIO_HIGHEST>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; + }; + + mutex: mutex@14001000 { + compatible = "mediatek,mt8186-disp-mutex"; + reg = <0 0x14001000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_MUTEX0>; + interrupts = ; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; + mediatek,gce-events = , + ; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; }; smi_common: smi@14002000 { @@ -1230,6 +1254,49 @@ power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; }; + ovl0: ovl@14005000 { + compatible = "mediatek,mt8186-disp-ovl", + "mediatek,mt8192-disp-ovl"; + reg = <0 0x14005000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_OVL0>; + interrupts = ; + iommus = <&iommu_mm IOMMU_PORT_L0_OVL_RDMA0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + ovl0_2l: ovl@14006000 { + compatible = "mediatek,mt8186-disp-ovl-2l", + "mediatek,mt8192-disp-ovl-2l"; + reg = <0 0x14006000 0 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; + interrupts = ; + iommus = <&iommu_mm IOMMU_PORT_L1_OVL_2L_RDMA0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; + }; + + rdma0: rdma@14007000 { + compatible = "mediatek,mt8186-disp-rdma", + "mediatek,mt8183-disp-rdma"; + reg = <0 0x14007000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_RDMA0>; + interrupts = ; + iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + color0: color@14009000 { + compatible = "mediatek,mt8186-disp-color", + "mediatek,mt8173-disp-color"; + reg = <0 0x14009000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_COLOR0>; + interrupts = ; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + dpi0: dpi@1400a000 { compatible = "mediatek,mt8186-dpi"; reg = <0 0x1400a000 0 0x1000>; @@ -1247,6 +1314,56 @@ }; }; + ccorr0: ccorr@1400b000 { + compatible = "mediatek,mt8186-disp-ccorr", + "mediatek,mt8192-disp-ccorr"; + reg = <0 0x1400b000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_CCORR0>; + interrupts = ; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + aal0: aal@1400c000 { + compatible = "mediatek,mt8186-disp-aal", + "mediatek,mt8183-disp-aal"; + reg = <0 0x1400c000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_AAL0>; + interrupts = ; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + gamma0: gamma@1400d000 { + compatible = "mediatek,mt8186-disp-gamma", + "mediatek,mt8183-disp-gamma"; + reg = <0 0x1400d000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_GAMMA0>; + interrupts = ; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + postmask0: postmask@1400e000 { + compatible = "mediatek,mt8186-disp-postmask", + "mediatek,mt8192-disp-postmask"; + reg = <0 0x1400e000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; + interrupts = ; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + dither0: dither@1400f000 { + compatible = "mediatek,mt8186-disp-dither", + "mediatek,mt8183-disp-dither"; + reg = <0 0x1400f000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_DITHER0>; + interrupts = ; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + dsi0: dsi@14013000 { compatible = "mediatek,mt8186-dsi"; reg = <0 0x14013000 0 0x1000>; @@ -1280,6 +1397,17 @@ #iommu-cells = <1>; }; + rdma1: rdma@1401f000 { + compatible = "mediatek,mt8186-disp-rdma", + "mediatek,mt8183-disp-rdma"; + reg = <0 0x1401f000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_RDMA1>; + interrupts = ; + iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA1>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xf000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + wpesys: clock-controller@14020000 { compatible = "mediatek,mt8186-wpesys"; reg = <0 0x14020000 0 0x1000>;