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([2602:47:d48c:8101:158e:facf:7a46:ba9f]) by smtp.gmail.com with ESMTPSA id l2-20020a17090a384200b0022727d4af8dsm577574pjf.48.2023.01.09.12.08.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 12:08:22 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Ilya Leoshkevich , =?utf-8?q?P?= =?utf-8?q?hilippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 01/27] target/s390x: Use tcg_constant_* in local contexts Date: Mon, 9 Jan 2023 12:07:53 -0800 Message-Id: <20230109200819.3916395-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109200819.3916395-1-richard.henderson@linaro.org> References: <20230109200819.3916395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Replace tcg_const_* with tcg_constant_* in contexts where the free to remove is nearby. Reviewed-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 416 +++++++++++++---------------------- 1 file changed, 149 insertions(+), 267 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index a339b277e9..f1c0e1af0d 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -171,8 +171,6 @@ static uint64_t inline_branch_miss[CC_OP_MAX]; static void pc_to_link_info(TCGv_i64 out, DisasContext *s, uint64_t pc) { - TCGv_i64 tmp; - if (s->base.tb->flags & FLAG_MASK_32) { if (s->base.tb->flags & FLAG_MASK_64) { tcg_gen_movi_i64(out, pc); @@ -181,9 +179,7 @@ static void pc_to_link_info(TCGv_i64 out, DisasContext *s, uint64_t pc) pc |= 0x80000000; } assert(!(s->base.tb->flags & FLAG_MASK_64)); - tmp = tcg_const_i64(pc); - tcg_gen_deposit_i64(out, out, tmp, 0, 32); - tcg_temp_free_i64(tmp); + tcg_gen_deposit_i64(out, out, tcg_constant_i64(pc), 0, 32); } static TCGv_i64 psw_addr; @@ -348,11 +344,8 @@ static void per_branch(DisasContext *s, bool to_next) tcg_gen_movi_i64(gbea, s->base.pc_next); if (s->base.tb->flags & FLAG_MASK_PER) { - TCGv_i64 next_pc = to_next ? tcg_const_i64(s->pc_tmp) : psw_addr; + TCGv_i64 next_pc = to_next ? tcg_constant_i64(s->pc_tmp) : psw_addr; gen_helper_per_branch(cpu_env, gbea, next_pc); - if (to_next) { - tcg_temp_free_i64(next_pc); - } } #endif } @@ -370,9 +363,8 @@ static void per_branch_cond(DisasContext *s, TCGCond cond, gen_set_label(lab); } else { - TCGv_i64 pc = tcg_const_i64(s->base.pc_next); + TCGv_i64 pc = tcg_constant_i64(s->base.pc_next); tcg_gen_movcond_i64(cond, gbea, arg1, arg2, gbea, pc); - tcg_temp_free_i64(pc); } #endif } @@ -426,23 +418,17 @@ static int get_mem_index(DisasContext *s) static void gen_exception(int excp) { - TCGv_i32 tmp = tcg_const_i32(excp); - gen_helper_exception(cpu_env, tmp); - tcg_temp_free_i32(tmp); + gen_helper_exception(cpu_env, tcg_constant_i32(excp)); } static void gen_program_exception(DisasContext *s, int code) { - TCGv_i32 tmp; + /* Remember what pgm exeption this was. */ + tcg_gen_st_i32(tcg_constant_i32(code), cpu_env, + offsetof(CPUS390XState, int_pgm_code)); - /* Remember what pgm exception this was. */ - tmp = tcg_const_i32(code); - tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_code)); - tcg_temp_free_i32(tmp); - - tmp = tcg_const_i32(s->ilen); - tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_ilen)); - tcg_temp_free_i32(tmp); + tcg_gen_st_i32(tcg_constant_i32(s->ilen), cpu_env, + offsetof(CPUS390XState, int_pgm_ilen)); /* update the psw */ update_psw_addr(s); @@ -461,9 +447,7 @@ static inline void gen_illegal_opcode(DisasContext *s) static inline void gen_data_exception(uint8_t dxc) { - TCGv_i32 tmp = tcg_const_i32(dxc); - gen_helper_data_exception(cpu_env, tmp); - tcg_temp_free_i32(tmp); + gen_helper_data_exception(cpu_env, tcg_constant_i32(dxc)); } static inline void gen_trap(DisasContext *s) @@ -584,13 +568,13 @@ static void gen_op_calc_cc(DisasContext *s) switch (s->cc_op) { default: - dummy = tcg_const_i64(0); + dummy = tcg_constant_i64(0); /* FALLTHRU */ case CC_OP_ADD_64: case CC_OP_SUB_64: case CC_OP_ADD_32: case CC_OP_SUB_32: - local_cc_op = tcg_const_i32(s->cc_op); + local_cc_op = tcg_constant_i32(s->cc_op); break; case CC_OP_CONST0: case CC_OP_CONST1: @@ -660,13 +644,6 @@ static void gen_op_calc_cc(DisasContext *s) tcg_abort(); } - if (local_cc_op) { - tcg_temp_free_i32(local_cc_op); - } - if (dummy) { - tcg_temp_free_i64(dummy); - } - /* We now have cc in cc_op as constant */ set_cc_static(s); } @@ -1284,9 +1261,9 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, Most commonly we're single-stepping or some other condition that disables all use of goto_tb. Just update the PC and exit. */ - TCGv_i64 next = tcg_const_i64(s->pc_tmp); + TCGv_i64 next = tcg_constant_i64(s->pc_tmp); if (is_imm) { - cdest = tcg_const_i64(dest); + cdest = tcg_constant_i64(dest); } if (c->is_64) { @@ -1296,21 +1273,15 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, } else { TCGv_i32 t0 = tcg_temp_new_i32(); TCGv_i64 t1 = tcg_temp_new_i64(); - TCGv_i64 z = tcg_const_i64(0); + TCGv_i64 z = tcg_constant_i64(0); tcg_gen_setcond_i32(c->cond, t0, c->u.s32.a, c->u.s32.b); tcg_gen_extu_i32_i64(t1, t0); tcg_temp_free_i32(t0); tcg_gen_movcond_i64(TCG_COND_NE, psw_addr, t1, z, cdest, next); per_branch_cond(s, TCG_COND_NE, t1, z); tcg_temp_free_i64(t1); - tcg_temp_free_i64(z); } - if (is_imm) { - tcg_temp_free_i64(cdest); - } - tcg_temp_free_i64(next); - ret = DISAS_PC_UPDATED; } @@ -1394,10 +1365,9 @@ static DisasJumpType op_addc64(DisasContext *s, DisasOps *o) { compute_carry(s); - TCGv_i64 zero = tcg_const_i64(0); + TCGv_i64 zero = tcg_constant_i64(0); tcg_gen_add2_i64(o->out, cc_src, o->in1, zero, cc_src, zero); tcg_gen_add2_i64(o->out, cc_src, o->out, cc_src, o->in2, zero); - tcg_temp_free_i64(zero); return DISAS_NEXT; } @@ -2077,9 +2047,8 @@ static DisasJumpType op_clc(DisasContext *s, DisasOps *o) tcg_gen_qemu_ld64(cc_dst, o->in2, get_mem_index(s)); break; default: - vl = tcg_const_i32(l); + vl = tcg_constant_i32(l); gen_helper_clc(cc_op, cpu_env, vl, o->addr1, o->in2); - tcg_temp_free_i32(vl); set_cc_static(s); return DISAS_NEXT; } @@ -2099,11 +2068,9 @@ static DisasJumpType op_clcl(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } - t1 = tcg_const_i32(r1); - t2 = tcg_const_i32(r2); + t1 = tcg_constant_i32(r1); + t2 = tcg_constant_i32(r2); gen_helper_clcl(cc_op, cpu_env, t1, t2); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); set_cc_static(s); return DISAS_NEXT; } @@ -2120,11 +2087,9 @@ static DisasJumpType op_clcle(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } - t1 = tcg_const_i32(r1); - t3 = tcg_const_i32(r3); + t1 = tcg_constant_i32(r1); + t3 = tcg_constant_i32(r3); gen_helper_clcle(cc_op, cpu_env, t1, o->in2, t3); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t3); set_cc_static(s); return DISAS_NEXT; } @@ -2141,24 +2106,22 @@ static DisasJumpType op_clclu(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } - t1 = tcg_const_i32(r1); - t3 = tcg_const_i32(r3); + t1 = tcg_constant_i32(r1); + t3 = tcg_constant_i32(r3); gen_helper_clclu(cc_op, cpu_env, t1, o->in2, t3); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t3); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_clm(DisasContext *s, DisasOps *o) { - TCGv_i32 m3 = tcg_const_i32(get_field(s, m3)); + TCGv_i32 m3 = tcg_constant_i32(get_field(s, m3)); TCGv_i32 t1 = tcg_temp_new_i32(); + tcg_gen_extrl_i64_i32(t1, o->in1); gen_helper_clm(cc_op, cpu_env, t1, m3, o->in2); set_cc_static(s); tcg_temp_free_i32(t1); - tcg_temp_free_i32(m3); return DISAS_NEXT; } @@ -2217,8 +2180,8 @@ static DisasJumpType op_cdsg(DisasContext *s, DisasOps *o) /* Note that R1:R1+1 = expected value and R3:R3+1 = new value. */ addr = get_address(s, 0, b2, d2); - t_r1 = tcg_const_i32(r1); - t_r3 = tcg_const_i32(r3); + t_r1 = tcg_constant_i32(r1); + t_r3 = tcg_constant_i32(r3); if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { gen_helper_cdsg(cpu_env, addr, t_r1, t_r3); } else if (HAVE_CMPXCHG128) { @@ -2228,8 +2191,6 @@ static DisasJumpType op_cdsg(DisasContext *s, DisasOps *o) ret = DISAS_NORETURN; } tcg_temp_free_i64(addr); - tcg_temp_free_i32(t_r1); - tcg_temp_free_i32(t_r3); set_cc_static(s); return ret; @@ -2238,14 +2199,13 @@ static DisasJumpType op_cdsg(DisasContext *s, DisasOps *o) static DisasJumpType op_csst(DisasContext *s, DisasOps *o) { int r3 = get_field(s, r3); - TCGv_i32 t_r3 = tcg_const_i32(r3); + TCGv_i32 t_r3 = tcg_constant_i32(r3); if (tb_cflags(s->base.tb) & CF_PARALLEL) { gen_helper_csst_parallel(cc_op, cpu_env, t_r3, o->addr1, o->in2); } else { gen_helper_csst(cc_op, cpu_env, t_r3, o->addr1, o->in2); } - tcg_temp_free_i32(t_r3); set_cc_static(s); return DISAS_NEXT; @@ -2343,9 +2303,9 @@ static DisasJumpType op_cuXX(DisasContext *s, DisasOps *o) m3 = 0; } - tr1 = tcg_const_i32(r1); - tr2 = tcg_const_i32(r2); - chk = tcg_const_i32(m3); + tr1 = tcg_constant_i32(r1); + tr2 = tcg_constant_i32(r2); + chk = tcg_constant_i32(m3); switch (s->insn->data) { case 12: @@ -2370,9 +2330,6 @@ static DisasJumpType op_cuXX(DisasContext *s, DisasOps *o) g_assert_not_reached(); } - tcg_temp_free_i32(tr1); - tcg_temp_free_i32(tr2); - tcg_temp_free_i32(chk); set_cc_static(s); return DISAS_NEXT; } @@ -2380,15 +2337,11 @@ static DisasJumpType op_cuXX(DisasContext *s, DisasOps *o) #ifndef CONFIG_USER_ONLY static DisasJumpType op_diag(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r3 = tcg_const_i32(get_field(s, r3)); - TCGv_i32 func_code = tcg_const_i32(get_field(s, i2)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3)); + TCGv_i32 func_code = tcg_constant_i32(get_field(s, i2)); gen_helper_diag(cpu_env, r1, r3, func_code); - - tcg_temp_free_i32(func_code); - tcg_temp_free_i32(r3); - tcg_temp_free_i32(r1); return DISAS_NEXT; } #endif @@ -2494,18 +2447,13 @@ static DisasJumpType op_ex(DisasContext *s, DisasOps *o) update_cc_op(s); if (r1 == 0) { - v1 = tcg_const_i64(0); + v1 = tcg_constant_i64(0); } else { v1 = regs[r1]; } - ilen = tcg_const_i32(s->ilen); + ilen = tcg_constant_i32(s->ilen); gen_helper_ex(cpu_env, ilen, v1, o->in2); - tcg_temp_free_i32(ilen); - - if (r1 == 0) { - tcg_temp_free_i64(v1); - } return DISAS_PC_CC_UPDATED; } @@ -2657,12 +2605,11 @@ static DisasJumpType op_idte(DisasContext *s, DisasOps *o) TCGv_i32 m4; if (s390_has_feat(S390_FEAT_LOCAL_TLB_CLEARING)) { - m4 = tcg_const_i32(get_field(s, m4)); + m4 = tcg_constant_i32(get_field(s, m4)); } else { - m4 = tcg_const_i32(0); + m4 = tcg_constant_i32(0); } gen_helper_idte(cpu_env, o->in1, o->in2, m4); - tcg_temp_free_i32(m4); return DISAS_NEXT; } @@ -2671,12 +2618,11 @@ static DisasJumpType op_ipte(DisasContext *s, DisasOps *o) TCGv_i32 m4; if (s390_has_feat(S390_FEAT_LOCAL_TLB_CLEARING)) { - m4 = tcg_const_i32(get_field(s, m4)); + m4 = tcg_constant_i32(get_field(s, m4)); } else { - m4 = tcg_const_i32(0); + m4 = tcg_constant_i32(0); } gen_helper_ipte(cpu_env, o->in1, o->in2, m4); - tcg_temp_free_i32(m4); return DISAS_NEXT; } @@ -2732,16 +2678,12 @@ static DisasJumpType op_msa(DisasContext *s, DisasOps *o) g_assert_not_reached(); }; - t_r1 = tcg_const_i32(r1); - t_r2 = tcg_const_i32(r2); - t_r3 = tcg_const_i32(r3); - type = tcg_const_i32(s->insn->data); + t_r1 = tcg_constant_i32(r1); + t_r2 = tcg_constant_i32(r2); + t_r3 = tcg_constant_i32(r3); + type = tcg_constant_i32(s->insn->data); gen_helper_msa(cc_op, cpu_env, t_r1, t_r2, t_r3, type); set_cc_static(s); - tcg_temp_free_i32(t_r1); - tcg_temp_free_i32(t_r2); - tcg_temp_free_i32(t_r3); - tcg_temp_free_i32(type); return DISAS_NEXT; } @@ -3002,10 +2944,9 @@ static DisasJumpType op_loc(DisasContext *s, DisasOps *o) tcg_gen_extu_i32_i64(t, t32); tcg_temp_free_i32(t32); - z = tcg_const_i64(0); + z = tcg_constant_i64(0); tcg_gen_movcond_i64(TCG_COND_NE, o->out, t, z, o->in2, o->in1); tcg_temp_free_i64(t); - tcg_temp_free_i64(z); } return DISAS_NEXT; @@ -3014,11 +2955,10 @@ static DisasJumpType op_loc(DisasContext *s, DisasOps *o) #ifndef CONFIG_USER_ONLY static DisasJumpType op_lctl(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r3 = tcg_const_i32(get_field(s, r3)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3)); + gen_helper_lctl(cpu_env, r1, o->in2, r3); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r3); /* Exit to main loop to reevaluate s390_cpu_exec_interrupt. */ s->exit_to_mainloop = true; return DISAS_TOO_MANY; @@ -3026,11 +2966,10 @@ static DisasJumpType op_lctl(DisasContext *s, DisasOps *o) static DisasJumpType op_lctlg(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r3 = tcg_const_i32(get_field(s, r3)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3)); + gen_helper_lctlg(cpu_env, r1, o->in2, r3); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r3); /* Exit to main loop to reevaluate s390_cpu_exec_interrupt. */ s->exit_to_mainloop = true; return DISAS_TOO_MANY; @@ -3090,11 +3029,10 @@ static DisasJumpType op_lpswe(DisasContext *s, DisasOps *o) static DisasJumpType op_lam(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r3 = tcg_const_i32(get_field(s, r3)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3)); + gen_helper_lam(cpu_env, r1, o->in2, r3); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r3); return DISAS_NEXT; } @@ -3304,9 +3242,6 @@ static DisasJumpType op_lcbb(DisasContext *s, DisasOps *o) static DisasJumpType op_mc(DisasContext *s, DisasOps *o) { -#if !defined(CONFIG_USER_ONLY) - TCGv_i32 i2; -#endif const uint16_t monitor_class = get_field(s, i2); if (monitor_class & 0xff00) { @@ -3315,9 +3250,8 @@ static DisasJumpType op_mc(DisasContext *s, DisasOps *o) } #if !defined(CONFIG_USER_ONLY) - i2 = tcg_const_i32(monitor_class); - gen_helper_monitor_call(cpu_env, o->addr1, i2); - tcg_temp_free_i32(i2); + gen_helper_monitor_call(cpu_env, o->addr1, + tcg_constant_i32(monitor_class)); #endif /* Defaults to a NOP. */ return DISAS_NEXT; @@ -3381,9 +3315,9 @@ static DisasJumpType op_movx(DisasContext *s, DisasOps *o) static DisasJumpType op_mvc(DisasContext *s, DisasOps *o) { - TCGv_i32 l = tcg_const_i32(get_field(s, l1)); + TCGv_i32 l = tcg_constant_i32(get_field(s, l1)); + gen_helper_mvc(cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); return DISAS_NEXT; } @@ -3395,9 +3329,9 @@ static DisasJumpType op_mvcrl(DisasContext *s, DisasOps *o) static DisasJumpType op_mvcin(DisasContext *s, DisasOps *o) { - TCGv_i32 l = tcg_const_i32(get_field(s, l1)); + TCGv_i32 l = tcg_constant_i32(get_field(s, l1)); + gen_helper_mvcin(cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); return DISAS_NEXT; } @@ -3413,11 +3347,9 @@ static DisasJumpType op_mvcl(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } - t1 = tcg_const_i32(r1); - t2 = tcg_const_i32(r2); + t1 = tcg_constant_i32(r1); + t2 = tcg_constant_i32(r2); gen_helper_mvcl(cc_op, cpu_env, t1, t2); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); set_cc_static(s); return DISAS_NEXT; } @@ -3434,11 +3366,9 @@ static DisasJumpType op_mvcle(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } - t1 = tcg_const_i32(r1); - t3 = tcg_const_i32(r3); + t1 = tcg_constant_i32(r1); + t3 = tcg_constant_i32(r3); gen_helper_mvcle(cc_op, cpu_env, t1, o->in2, t3); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t3); set_cc_static(s); return DISAS_NEXT; } @@ -3455,11 +3385,9 @@ static DisasJumpType op_mvclu(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } - t1 = tcg_const_i32(r1); - t3 = tcg_const_i32(r3); + t1 = tcg_constant_i32(r1); + t3 = tcg_constant_i32(r3); gen_helper_mvclu(cc_op, cpu_env, t1, o->in2, t3); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t3); set_cc_static(s); return DISAS_NEXT; } @@ -3494,49 +3422,45 @@ static DisasJumpType op_mvcs(DisasContext *s, DisasOps *o) static DisasJumpType op_mvn(DisasContext *s, DisasOps *o) { - TCGv_i32 l = tcg_const_i32(get_field(s, l1)); + TCGv_i32 l = tcg_constant_i32(get_field(s, l1)); + gen_helper_mvn(cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); return DISAS_NEXT; } static DisasJumpType op_mvo(DisasContext *s, DisasOps *o) { - TCGv_i32 l = tcg_const_i32(get_field(s, l1)); + TCGv_i32 l = tcg_constant_i32(get_field(s, l1)); + gen_helper_mvo(cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); return DISAS_NEXT; } static DisasJumpType op_mvpg(DisasContext *s, DisasOps *o) { - TCGv_i32 t1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 t2 = tcg_const_i32(get_field(s, r2)); + TCGv_i32 t1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 t2 = tcg_constant_i32(get_field(s, r2)); gen_helper_mvpg(cc_op, cpu_env, regs[0], t1, t2); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_mvst(DisasContext *s, DisasOps *o) { - TCGv_i32 t1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 t2 = tcg_const_i32(get_field(s, r2)); + TCGv_i32 t1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 t2 = tcg_constant_i32(get_field(s, r2)); gen_helper_mvst(cc_op, cpu_env, t1, t2); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_mvz(DisasContext *s, DisasOps *o) { - TCGv_i32 l = tcg_const_i32(get_field(s, l1)); + TCGv_i32 l = tcg_constant_i32(get_field(s, l1)); + gen_helper_mvz(cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); return DISAS_NEXT; } @@ -3624,13 +3548,12 @@ static DisasJumpType op_msdb(DisasContext *s, DisasOps *o) static DisasJumpType op_nabs(DisasContext *s, DisasOps *o) { - TCGv_i64 z, n; - z = tcg_const_i64(0); - n = tcg_temp_new_i64(); + TCGv_i64 z = tcg_constant_i64(0); + TCGv_i64 n = tcg_temp_new_i64(); + tcg_gen_neg_i64(n, o->in2); tcg_gen_movcond_i64(TCG_COND_GE, o->out, o->in2, z, n, o->in2); tcg_temp_free_i64(n); - tcg_temp_free_i64(z); return DISAS_NEXT; } @@ -3655,9 +3578,9 @@ static DisasJumpType op_nabsf128(DisasContext *s, DisasOps *o) static DisasJumpType op_nc(DisasContext *s, DisasOps *o) { - TCGv_i32 l = tcg_const_i32(get_field(s, l1)); + TCGv_i32 l = tcg_constant_i32(get_field(s, l1)); + gen_helper_nc(cc_op, cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); set_cc_static(s); return DISAS_NEXT; } @@ -3689,9 +3612,9 @@ static DisasJumpType op_negf128(DisasContext *s, DisasOps *o) static DisasJumpType op_oc(DisasContext *s, DisasOps *o) { - TCGv_i32 l = tcg_const_i32(get_field(s, l1)); + TCGv_i32 l = tcg_constant_i32(get_field(s, l1)); + gen_helper_oc(cc_op, cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); set_cc_static(s); return DISAS_NEXT; } @@ -3741,9 +3664,9 @@ static DisasJumpType op_oi(DisasContext *s, DisasOps *o) static DisasJumpType op_pack(DisasContext *s, DisasOps *o) { - TCGv_i32 l = tcg_const_i32(get_field(s, l1)); + TCGv_i32 l = tcg_constant_i32(get_field(s, l1)); + gen_helper_pack(cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); return DISAS_NEXT; } @@ -3757,9 +3680,8 @@ static DisasJumpType op_pka(DisasContext *s, DisasOps *o) gen_program_exception(s, PGM_SPECIFICATION); return DISAS_NORETURN; } - l = tcg_const_i32(l2); + l = tcg_constant_i32(l2); gen_helper_pka(cpu_env, o->addr1, o->in2, l); - tcg_temp_free_i32(l); return DISAS_NEXT; } @@ -3773,9 +3695,8 @@ static DisasJumpType op_pku(DisasContext *s, DisasOps *o) gen_program_exception(s, PGM_SPECIFICATION); return DISAS_NORETURN; } - l = tcg_const_i32(l2); + l = tcg_constant_i32(l2); gen_helper_pku(cpu_env, o->addr1, o->in2, l); - tcg_temp_free_i32(l); return DISAS_NEXT; } @@ -4022,9 +3943,8 @@ static DisasJumpType op_sam(DisasContext *s, DisasOps *o) } s->pc_tmp &= mask; - tsam = tcg_const_i64(sam); + tsam = tcg_constant_i64(sam); tcg_gen_deposit_i64(psw_mask, psw_mask, tsam, 31, 2); - tcg_temp_free_i64(tsam); /* Always exit the TB, since we (may have) changed execution mode. */ return DISAS_TOO_MANY; @@ -4085,12 +4005,11 @@ static DisasJumpType op_servc(DisasContext *s, DisasOps *o) static DisasJumpType op_sigp(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r3 = tcg_const_i32(get_field(s, r3)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3)); + gen_helper_sigp(cc_op, cpu_env, o->in2, r1, r3); set_cc_static(s); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r3); return DISAS_NEXT; } #endif @@ -4359,21 +4278,19 @@ static DisasJumpType op_stckc(DisasContext *s, DisasOps *o) static DisasJumpType op_stctg(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r3 = tcg_const_i32(get_field(s, r3)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3)); + gen_helper_stctg(cpu_env, r1, o->in2, r3); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r3); return DISAS_NEXT; } static DisasJumpType op_stctl(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r3 = tcg_const_i32(get_field(s, r3)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3)); + gen_helper_stctl(cpu_env, r1, o->in2, r3); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r3); return DISAS_NEXT; } @@ -4600,11 +4517,10 @@ static DisasJumpType op_st64(DisasContext *s, DisasOps *o) static DisasJumpType op_stam(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r3 = tcg_const_i32(get_field(s, r3)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3)); + gen_helper_stam(cpu_env, r1, o->in2, r3); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r3); return DISAS_NEXT; } @@ -4662,7 +4578,7 @@ static DisasJumpType op_stm(DisasContext *s, DisasOps *o) int r1 = get_field(s, r1); int r3 = get_field(s, r3); int size = s->insn->data; - TCGv_i64 tsize = tcg_const_i64(size); + TCGv_i64 tsize = tcg_constant_i64(size); while (1) { if (size == 8) { @@ -4677,7 +4593,6 @@ static DisasJumpType op_stm(DisasContext *s, DisasOps *o) r1 = (r1 + 1) & 15; } - tcg_temp_free_i64(tsize); return DISAS_NEXT; } @@ -4686,8 +4601,8 @@ static DisasJumpType op_stmh(DisasContext *s, DisasOps *o) int r1 = get_field(s, r1); int r3 = get_field(s, r3); TCGv_i64 t = tcg_temp_new_i64(); - TCGv_i64 t4 = tcg_const_i64(4); - TCGv_i64 t32 = tcg_const_i64(32); + TCGv_i64 t4 = tcg_constant_i64(4); + TCGv_i64 t32 = tcg_constant_i64(32); while (1) { tcg_gen_shl_i64(t, regs[r1], t32); @@ -4700,8 +4615,6 @@ static DisasJumpType op_stmh(DisasContext *s, DisasOps *o) } tcg_temp_free_i64(t); - tcg_temp_free_i64(t4); - tcg_temp_free_i64(t32); return DISAS_NEXT; } @@ -4720,26 +4633,20 @@ static DisasJumpType op_stpq(DisasContext *s, DisasOps *o) static DisasJumpType op_srst(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r2 = tcg_const_i32(get_field(s, r2)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2)); gen_helper_srst(cpu_env, r1, r2); - - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r2); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_srstu(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r2 = tcg_const_i32(get_field(s, r2)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2)); gen_helper_srstu(cpu_env, r1, r2); - - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r2); set_cc_static(s); return DISAS_NEXT; } @@ -4797,10 +4704,9 @@ static DisasJumpType op_subb64(DisasContext *s, DisasOps *o) * Borrow is {0, -1}, so add to subtract; replicate the * borrow input to produce 128-bit -1 for the addition. */ - TCGv_i64 zero = tcg_const_i64(0); + TCGv_i64 zero = tcg_constant_i64(0); tcg_gen_add2_i64(o->out, cc_src, o->in1, zero, cc_src, cc_src); tcg_gen_sub2_i64(o->out, cc_src, o->out, cc_src, o->in2, zero); - tcg_temp_free_i64(zero); return DISAS_NEXT; } @@ -4812,13 +4718,11 @@ static DisasJumpType op_svc(DisasContext *s, DisasOps *o) update_psw_addr(s); update_cc_op(s); - t = tcg_const_i32(get_field(s, i1) & 0xff); + t = tcg_constant_i32(get_field(s, i1) & 0xff); tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_code)); - tcg_temp_free_i32(t); - t = tcg_const_i32(s->ilen); + t = tcg_constant_i32(s->ilen); tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_ilen)); - tcg_temp_free_i32(t); gen_exception(EXCP_SVC); return DISAS_NORETURN; @@ -4875,18 +4779,18 @@ static DisasJumpType op_tprot(DisasContext *s, DisasOps *o) static DisasJumpType op_tp(DisasContext *s, DisasOps *o) { - TCGv_i32 l1 = tcg_const_i32(get_field(s, l1) + 1); + TCGv_i32 l1 = tcg_constant_i32(get_field(s, l1) + 1); + gen_helper_tp(cc_op, cpu_env, o->addr1, l1); - tcg_temp_free_i32(l1); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_tr(DisasContext *s, DisasOps *o) { - TCGv_i32 l = tcg_const_i32(get_field(s, l1)); + TCGv_i32 l = tcg_constant_i32(get_field(s, l1)); + gen_helper_tr(cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); set_cc_static(s); return DISAS_NEXT; } @@ -4901,27 +4805,27 @@ static DisasJumpType op_tre(DisasContext *s, DisasOps *o) static DisasJumpType op_trt(DisasContext *s, DisasOps *o) { - TCGv_i32 l = tcg_const_i32(get_field(s, l1)); + TCGv_i32 l = tcg_constant_i32(get_field(s, l1)); + gen_helper_trt(cc_op, cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_trtr(DisasContext *s, DisasOps *o) { - TCGv_i32 l = tcg_const_i32(get_field(s, l1)); + TCGv_i32 l = tcg_constant_i32(get_field(s, l1)); + gen_helper_trtr(cc_op, cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_trXX(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r2 = tcg_const_i32(get_field(s, r2)); - TCGv_i32 sizes = tcg_const_i32(s->insn->opc & 3); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2)); + TCGv_i32 sizes = tcg_constant_i32(s->insn->opc & 3); TCGv_i32 tst = tcg_temp_new_i32(); int m3 = get_field(s, m3); @@ -4940,9 +4844,6 @@ static DisasJumpType op_trXX(DisasContext *s, DisasOps *o) } gen_helper_trXX(cc_op, cpu_env, r1, r2, tst, sizes); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r2); - tcg_temp_free_i32(sizes); tcg_temp_free_i32(tst); set_cc_static(s); return DISAS_NEXT; @@ -4950,19 +4851,19 @@ static DisasJumpType op_trXX(DisasContext *s, DisasOps *o) static DisasJumpType op_ts(DisasContext *s, DisasOps *o) { - TCGv_i32 t1 = tcg_const_i32(0xff); + TCGv_i32 t1 = tcg_constant_i32(0xff); + tcg_gen_atomic_xchg_i32(t1, o->in2, t1, get_mem_index(s), MO_UB); tcg_gen_extract_i32(cc_op, t1, 7, 1); - tcg_temp_free_i32(t1); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_unpk(DisasContext *s, DisasOps *o) { - TCGv_i32 l = tcg_const_i32(get_field(s, l1)); + TCGv_i32 l = tcg_constant_i32(get_field(s, l1)); + gen_helper_unpk(cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); return DISAS_NEXT; } @@ -4976,9 +4877,8 @@ static DisasJumpType op_unpka(DisasContext *s, DisasOps *o) gen_program_exception(s, PGM_SPECIFICATION); return DISAS_NORETURN; } - l = tcg_const_i32(l1); + l = tcg_constant_i32(l1); gen_helper_unpka(cc_op, cpu_env, o->addr1, l, o->in2); - tcg_temp_free_i32(l); set_cc_static(s); return DISAS_NEXT; } @@ -4993,9 +4893,8 @@ static DisasJumpType op_unpku(DisasContext *s, DisasOps *o) gen_program_exception(s, PGM_SPECIFICATION); return DISAS_NORETURN; } - l = tcg_const_i32(l1); + l = tcg_constant_i32(l1); gen_helper_unpku(cc_op, cpu_env, o->addr1, l, o->in2); - tcg_temp_free_i32(l); set_cc_static(s); return DISAS_NEXT; } @@ -5014,7 +4913,7 @@ static DisasJumpType op_xc(DisasContext *s, DisasOps *o) /* If the addresses are identical, this is a store/memset of zero. */ if (b1 == b2 && d1 == d2 && (l + 1) <= 32) { - o->in2 = tcg_const_i64(0); + o->in2 = tcg_constant_i64(0); l++; while (l >= 8) { @@ -5047,9 +4946,8 @@ static DisasJumpType op_xc(DisasContext *s, DisasOps *o) /* But in general we'll defer to a helper. */ o->in2 = get_address(s, 0, b2, d2); - t32 = tcg_const_i32(l); + t32 = tcg_constant_i32(l); gen_helper_xc(cc_op, cpu_env, t32, o->addr1, o->in2); - tcg_temp_free_i32(t32); set_cc_static(s); return DISAS_NEXT; } @@ -5114,46 +5012,39 @@ static DisasJumpType op_zero2(DisasContext *s, DisasOps *o) #ifndef CONFIG_USER_ONLY static DisasJumpType op_clp(DisasContext *s, DisasOps *o) { - TCGv_i32 r2 = tcg_const_i32(get_field(s, r2)); + TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2)); gen_helper_clp(cpu_env, r2); - tcg_temp_free_i32(r2); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_pcilg(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r2 = tcg_const_i32(get_field(s, r2)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2)); gen_helper_pcilg(cpu_env, r1, r2); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r2); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_pcistg(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r2 = tcg_const_i32(get_field(s, r2)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2)); gen_helper_pcistg(cpu_env, r1, r2); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r2); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_stpcifc(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 ar = tcg_const_i32(get_field(s, b2)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 ar = tcg_constant_i32(get_field(s, b2)); gen_helper_stpcifc(cpu_env, r1, o->addr1, ar); - tcg_temp_free_i32(ar); - tcg_temp_free_i32(r1); set_cc_static(s); return DISAS_NEXT; } @@ -5166,38 +5057,31 @@ static DisasJumpType op_sic(DisasContext *s, DisasOps *o) static DisasJumpType op_rpcit(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r2 = tcg_const_i32(get_field(s, r2)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2)); gen_helper_rpcit(cpu_env, r1, r2); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r2); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_pcistb(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 r3 = tcg_const_i32(get_field(s, r3)); - TCGv_i32 ar = tcg_const_i32(get_field(s, b2)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3)); + TCGv_i32 ar = tcg_constant_i32(get_field(s, b2)); gen_helper_pcistb(cpu_env, r1, r3, o->addr1, ar); - tcg_temp_free_i32(ar); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r3); set_cc_static(s); return DISAS_NEXT; } static DisasJumpType op_mpcifc(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 = tcg_const_i32(get_field(s, r1)); - TCGv_i32 ar = tcg_const_i32(get_field(s, b2)); + TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1)); + TCGv_i32 ar = tcg_constant_i32(get_field(s, b2)); gen_helper_mpcifc(cpu_env, r1, o->addr1, ar); - tcg_temp_free_i32(ar); - tcg_temp_free_i32(r1); set_cc_static(s); return DISAS_NEXT; } @@ -6318,16 +6202,15 @@ static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s) if (unlikely(s->ex_value)) { /* Drop the EX data now, so that it's clear on exception paths. */ - TCGv_i64 zero = tcg_const_i64(0); - int i; - tcg_gen_st_i64(zero, cpu_env, offsetof(CPUS390XState, ex_value)); - tcg_temp_free_i64(zero); + tcg_gen_st_i64(tcg_constant_i64(0), cpu_env, + offsetof(CPUS390XState, ex_value)); /* Extract the values saved by EXECUTE. */ insn = s->ex_value & 0xffffffffffff0000ull; ilen = s->ex_value & 0xf; - /* register insn bytes with translator so plugins work */ - for (i = 0; i < ilen; i++) { + + /* Register insn bytes with translator so plugins work. */ + for (int i = 0; i < ilen; i++) { uint8_t byte = extract64(insn, 56 - (i * 8), 8); translator_fake_ldb(byte, pc + i); } @@ -6452,9 +6335,8 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s) #ifndef CONFIG_USER_ONLY if (s->base.tb->flags & FLAG_MASK_PER) { - TCGv_i64 addr = tcg_const_i64(s->base.pc_next); + TCGv_i64 addr = tcg_constant_i64(s->base.pc_next); gen_helper_per_ifetch(cpu_env, addr); - tcg_temp_free_i64(addr); } #endif From patchwork Mon Jan 9 20:07:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 640675 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp2336210pvb; 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([2602:47:d48c:8101:158e:facf:7a46:ba9f]) by smtp.gmail.com with ESMTPSA id l2-20020a17090a384200b0022727d4af8dsm577574pjf.48.2023.01.09.12.08.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 12:08:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Ilya Leoshkevich Subject: [PATCH v3 02/27] target/s390x: Use tcg_constant_* for DisasCompare Date: Mon, 9 Jan 2023 12:07:54 -0800 Message-Id: <20230109200819.3916395-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109200819.3916395-1-richard.henderson@linaro.org> References: <20230109200819.3916395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The a and b fields are not modified by the consumer, and while we need not free a constant, tcg will quietly ignore such frees, so free_compare need not be changed. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 44 ++++++++++++++++++------------------ 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index f1c0e1af0d..2fa052249f 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -830,7 +830,7 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask) c->is_64 = false; c->u.s32.a = tcg_temp_new_i32(); tcg_gen_extrl_i64_i32(c->u.s32.a, cc_dst); - c->u.s32.b = tcg_const_i32(0); + c->u.s32.b = tcg_constant_i32(0); break; case CC_OP_LTGT_32: case CC_OP_LTUGTU_32: @@ -845,7 +845,7 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask) case CC_OP_NZ: case CC_OP_FLOGR: c->u.s64.a = cc_dst; - c->u.s64.b = tcg_const_i64(0); + c->u.s64.b = tcg_constant_i64(0); c->g1 = true; break; case CC_OP_LTGT_64: @@ -859,14 +859,14 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask) case CC_OP_TM_64: case CC_OP_ICM: c->u.s64.a = tcg_temp_new_i64(); - c->u.s64.b = tcg_const_i64(0); + c->u.s64.b = tcg_constant_i64(0); tcg_gen_and_i64(c->u.s64.a, cc_src, cc_dst); break; case CC_OP_ADDU: case CC_OP_SUBU: c->is_64 = true; - c->u.s64.b = tcg_const_i64(0); + c->u.s64.b = tcg_constant_i64(0); c->g1 = true; switch (mask) { case 8 | 2: @@ -889,65 +889,65 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask) switch (mask) { case 0x8 | 0x4 | 0x2: /* cc != 3 */ cond = TCG_COND_NE; - c->u.s32.b = tcg_const_i32(3); + c->u.s32.b = tcg_constant_i32(3); break; case 0x8 | 0x4 | 0x1: /* cc != 2 */ cond = TCG_COND_NE; - c->u.s32.b = tcg_const_i32(2); + c->u.s32.b = tcg_constant_i32(2); break; case 0x8 | 0x2 | 0x1: /* cc != 1 */ cond = TCG_COND_NE; - c->u.s32.b = tcg_const_i32(1); + c->u.s32.b = tcg_constant_i32(1); break; case 0x8 | 0x2: /* cc == 0 || cc == 2 => (cc & 1) == 0 */ cond = TCG_COND_EQ; c->g1 = false; c->u.s32.a = tcg_temp_new_i32(); - c->u.s32.b = tcg_const_i32(0); + c->u.s32.b = tcg_constant_i32(0); tcg_gen_andi_i32(c->u.s32.a, cc_op, 1); break; case 0x8 | 0x4: /* cc < 2 */ cond = TCG_COND_LTU; - c->u.s32.b = tcg_const_i32(2); + c->u.s32.b = tcg_constant_i32(2); break; case 0x8: /* cc == 0 */ cond = TCG_COND_EQ; - c->u.s32.b = tcg_const_i32(0); + c->u.s32.b = tcg_constant_i32(0); break; case 0x4 | 0x2 | 0x1: /* cc != 0 */ cond = TCG_COND_NE; - c->u.s32.b = tcg_const_i32(0); + c->u.s32.b = tcg_constant_i32(0); break; case 0x4 | 0x1: /* cc == 1 || cc == 3 => (cc & 1) != 0 */ cond = TCG_COND_NE; c->g1 = false; c->u.s32.a = tcg_temp_new_i32(); - c->u.s32.b = tcg_const_i32(0); + c->u.s32.b = tcg_constant_i32(0); tcg_gen_andi_i32(c->u.s32.a, cc_op, 1); break; case 0x4: /* cc == 1 */ cond = TCG_COND_EQ; - c->u.s32.b = tcg_const_i32(1); + c->u.s32.b = tcg_constant_i32(1); break; case 0x2 | 0x1: /* cc > 1 */ cond = TCG_COND_GTU; - c->u.s32.b = tcg_const_i32(1); + c->u.s32.b = tcg_constant_i32(1); break; case 0x2: /* cc == 2 */ cond = TCG_COND_EQ; - c->u.s32.b = tcg_const_i32(2); + c->u.s32.b = tcg_constant_i32(2); break; case 0x1: /* cc == 3 */ cond = TCG_COND_EQ; - c->u.s32.b = tcg_const_i32(3); + c->u.s32.b = tcg_constant_i32(3); break; default: /* CC is masked by something else: (8 >> cc) & mask. */ cond = TCG_COND_NE; c->g1 = false; - c->u.s32.a = tcg_const_i32(8); - c->u.s32.b = tcg_const_i32(0); - tcg_gen_shr_i32(c->u.s32.a, c->u.s32.a, cc_op); + c->u.s32.a = tcg_temp_new_i32(); + c->u.s32.b = tcg_constant_i32(0); + tcg_gen_shr_i32(c->u.s32.a, tcg_constant_i32(8), cc_op); tcg_gen_andi_i32(c->u.s32.a, c->u.s32.a, mask); break; } @@ -1604,7 +1604,7 @@ static DisasJumpType op_bct32(DisasContext *s, DisasOps *o) tcg_gen_subi_i64(t, regs[r1], 1); store_reg32_i64(r1, t); c.u.s32.a = tcg_temp_new_i32(); - c.u.s32.b = tcg_const_i32(0); + c.u.s32.b = tcg_constant_i32(0); tcg_gen_extrl_i64_i32(c.u.s32.a, t); tcg_temp_free_i64(t); @@ -1628,7 +1628,7 @@ static DisasJumpType op_bcth(DisasContext *s, DisasOps *o) tcg_gen_subi_i64(t, t, 1); store_reg32h_i64(r1, t); c.u.s32.a = tcg_temp_new_i32(); - c.u.s32.b = tcg_const_i32(0); + c.u.s32.b = tcg_constant_i32(0); tcg_gen_extrl_i64_i32(c.u.s32.a, t); tcg_temp_free_i64(t); @@ -1649,7 +1649,7 @@ static DisasJumpType op_bct64(DisasContext *s, DisasOps *o) tcg_gen_subi_i64(regs[r1], regs[r1], 1); c.u.s64.a = regs[r1]; - c.u.s64.b = tcg_const_i64(0); + c.u.s64.b = tcg_constant_i64(0); return help_branch(s, &c, is_imm, imm, o->in2); } From patchwork Mon Jan 9 20:07:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 640674 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp2335943pvb; Mon, 9 Jan 2023 12:12:50 -0800 (PST) X-Google-Smtp-Source: AMrXdXsNge/hnYxqycgWjomX9B2UutfmbTpGmWdXLPB+QiXJUU5i02P5DWzzA+yVebdyD4be04gT X-Received: by 2002:a05:6214:1147:b0:531:7d2b:e655 with SMTP id b7-20020a056214114700b005317d2be655mr58211196qvt.22.1673295169860; Mon, 09 Jan 2023 12:12:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673295169; cv=none; d=google.com; s=arc-20160816; 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([2602:47:d48c:8101:158e:facf:7a46:ba9f]) by smtp.gmail.com with ESMTPSA id l2-20020a17090a384200b0022727d4af8dsm577574pjf.48.2023.01.09.12.08.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 12:08:24 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Ilya Leoshkevich Subject: [PATCH v3 03/27] target/s390x: Use tcg_constant_i32 for fpinst_extract_m34 Date: Mon, 9 Jan 2023 12:07:55 -0800 Message-Id: <20230109200819.3916395-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109200819.3916395-1-richard.henderson@linaro.org> References: <20230109200819.3916395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Return a constant or NULL, which means the free may be removed from all callers of fpinst_extract_m34. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 26 +------------------------- 1 file changed, 1 insertion(+), 25 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 2fa052249f..83805085a9 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -1775,7 +1775,7 @@ static TCGv_i32 fpinst_extract_m34(DisasContext *s, bool m3_with_fpe, return NULL; } - return tcg_const_i32(deposit32(m3, 4, 4, m4)); + return tcg_constant_i32(deposit32(m3, 4, 4, m4)); } static DisasJumpType op_cfeb(DisasContext *s, DisasOps *o) @@ -1786,7 +1786,6 @@ static DisasJumpType op_cfeb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_cfeb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1799,7 +1798,6 @@ static DisasJumpType op_cfdb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_cfdb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1812,7 +1810,6 @@ static DisasJumpType op_cfxb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_cfxb(o->out, cpu_env, o->in1, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1825,7 +1822,6 @@ static DisasJumpType op_cgeb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_cgeb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1838,7 +1834,6 @@ static DisasJumpType op_cgdb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_cgdb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1851,7 +1846,6 @@ static DisasJumpType op_cgxb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_cgxb(o->out, cpu_env, o->in1, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1864,7 +1858,6 @@ static DisasJumpType op_clfeb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_clfeb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1877,7 +1870,6 @@ static DisasJumpType op_clfdb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_clfdb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1890,7 +1882,6 @@ static DisasJumpType op_clfxb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_clfxb(o->out, cpu_env, o->in1, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1903,7 +1894,6 @@ static DisasJumpType op_clgeb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_clgeb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1916,7 +1906,6 @@ static DisasJumpType op_clgdb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_clgdb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1929,7 +1918,6 @@ static DisasJumpType op_clgxb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_clgxb(o->out, cpu_env, o->in1, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1942,7 +1930,6 @@ static DisasJumpType op_cegb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_cegb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -1954,7 +1941,6 @@ static DisasJumpType op_cdgb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_cdgb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -1966,7 +1952,6 @@ static DisasJumpType op_cxgb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_cxgb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); return_low128(o->out2); return DISAS_NEXT; } @@ -1979,7 +1964,6 @@ static DisasJumpType op_celgb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_celgb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -1991,7 +1975,6 @@ static DisasJumpType op_cdlgb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_cdlgb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -2003,7 +1986,6 @@ static DisasJumpType op_cxlgb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_cxlgb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); return_low128(o->out2); return DISAS_NEXT; } @@ -2466,7 +2448,6 @@ static DisasJumpType op_fieb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_fieb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -2478,7 +2459,6 @@ static DisasJumpType op_fidb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_fidb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -2491,7 +2471,6 @@ static DisasJumpType op_fixb(DisasContext *s, DisasOps *o) } gen_helper_fixb(o->out, cpu_env, o->in1, o->in2, m34); return_low128(o->out2); - tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -2766,7 +2745,6 @@ static DisasJumpType op_ledb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_ledb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -2778,7 +2756,6 @@ static DisasJumpType op_ldxb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_ldxb(o->out, cpu_env, o->in1, o->in2, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -2790,7 +2767,6 @@ static DisasJumpType op_lexb(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } gen_helper_lexb(o->out, cpu_env, o->in1, o->in2, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } From patchwork Mon Jan 9 20:07:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 640677 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp2336643pvb; Mon, 9 Jan 2023 12:14:42 -0800 (PST) X-Google-Smtp-Source: AMrXdXsqSuBy+jwl2lWv8cmohSKcVOi3uOzqsY0MZ2A5w1BrqJhV+29Sz2qtdXiPt73HJrK4kHjK X-Received: by 2002:a67:eb10:0:b0:3ce:f235:1c9b with SMTP id a16-20020a67eb10000000b003cef2351c9bmr4263224vso.15.1673295282309; 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([2602:47:d48c:8101:158e:facf:7a46:ba9f]) by smtp.gmail.com with ESMTPSA id l2-20020a17090a384200b0022727d4af8dsm577574pjf.48.2023.01.09.12.08.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 12:08:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Ilya Leoshkevich Subject: [PATCH v3 04/27] target/s390x: Use tcg_constant_* in translate_vx.c.inc Date: Mon, 9 Jan 2023 12:07:56 -0800 Message-Id: <20230109200819.3916395-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109200819.3916395-1-richard.henderson@linaro.org> References: <20230109200819.3916395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In most cases, this is a simple local allocate and free replaced by tcg_constant_*. In three cases, a variable temp was initialized with a constant value -- reorg to localize the constant. In gen_acc, this fixes a leak. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate_vx.c.inc | 45 +++++++++++++---------------- 1 file changed, 20 insertions(+), 25 deletions(-) diff --git a/target/s390x/tcg/translate_vx.c.inc b/target/s390x/tcg/translate_vx.c.inc index d39ee81cd6..3fadc82e5c 100644 --- a/target/s390x/tcg/translate_vx.c.inc +++ b/target/s390x/tcg/translate_vx.c.inc @@ -319,12 +319,10 @@ static void gen_gvec128_4_i64(gen_gvec128_4_i64_fn fn, uint8_t d, uint8_t a, static void gen_addi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah, uint64_t b) { - TCGv_i64 bl = tcg_const_i64(b); - TCGv_i64 bh = tcg_const_i64(0); + TCGv_i64 bl = tcg_constant_i64(b); + TCGv_i64 bh = tcg_constant_i64(0); tcg_gen_add2_i64(dl, dh, al, ah, bl, bh); - tcg_temp_free_i64(bl); - tcg_temp_free_i64(bh); } static DisasJumpType op_vbperm(DisasContext *s, DisasOps *o) @@ -609,9 +607,8 @@ static DisasJumpType op_vlei(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } - tmp = tcg_const_i64((int16_t)get_field(s, i2)); + tmp = tcg_constant_i64((int16_t)get_field(s, i2)); write_vec_element_i64(tmp, get_field(s, v1), enr, es); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } @@ -1107,11 +1104,13 @@ static DisasJumpType op_vseg(DisasContext *s, DisasOps *o) static DisasJumpType op_vst(DisasContext *s, DisasOps *o) { - TCGv_i64 tmp = tcg_const_i64(16); + TCGv_i64 tmp; /* Probe write access before actually modifying memory */ - gen_helper_probe_write_access(cpu_env, o->addr1, tmp); + gen_helper_probe_write_access(cpu_env, o->addr1, + tcg_constant_i64(16)); + tmp = tcg_temp_new_i64(); read_vec_element_i64(tmp, get_field(s, v1), 0, ES_64); tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEUQ); gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); @@ -1270,9 +1269,10 @@ static DisasJumpType op_vstm(DisasContext *s, DisasOps *o) } /* Probe write access before actually modifying memory */ - tmp = tcg_const_i64((v3 - v1 + 1) * 16); - gen_helper_probe_write_access(cpu_env, o->addr1, tmp); + gen_helper_probe_write_access(cpu_env, o->addr1, + tcg_constant_i64((v3 - v1 + 1) * 16)); + tmp = tcg_temp_new_i64(); for (;; v1++) { read_vec_element_i64(tmp, v1, 0, ES_64); tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEUQ); @@ -1359,7 +1359,7 @@ static DisasJumpType op_va(DisasContext *s, DisasOps *o) static void gen_acc(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, uint8_t es) { const uint8_t msb_bit_nr = NUM_VEC_ELEMENT_BITS(es) - 1; - TCGv_i64 msb_mask = tcg_const_i64(dup_const(es, 1ull << msb_bit_nr)); + TCGv_i64 msb_mask = tcg_constant_i64(dup_const(es, 1ull << msb_bit_nr)); TCGv_i64 t1 = tcg_temp_new_i64(); TCGv_i64 t2 = tcg_temp_new_i64(); TCGv_i64 t3 = tcg_temp_new_i64(); @@ -1416,7 +1416,7 @@ static void gen_acc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, { TCGv_i64 th = tcg_temp_new_i64(); TCGv_i64 tl = tcg_temp_new_i64(); - TCGv_i64 zero = tcg_const_i64(0); + TCGv_i64 zero = tcg_constant_i64(0); tcg_gen_add2_i64(tl, th, al, zero, bl, zero); tcg_gen_add2_i64(tl, th, th, zero, ah, zero); @@ -1425,7 +1425,6 @@ static void gen_acc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, tcg_temp_free_i64(th); tcg_temp_free_i64(tl); - tcg_temp_free_i64(zero); } static DisasJumpType op_vacc(DisasContext *s, DisasOps *o) @@ -1455,15 +1454,14 @@ static void gen_ac2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh, TCGv_i64 cl, TCGv_i64 ch) { TCGv_i64 tl = tcg_temp_new_i64(); - TCGv_i64 th = tcg_const_i64(0); + TCGv_i64 zero = tcg_constant_i64(0); /* extract the carry only */ tcg_gen_extract_i64(tl, cl, 0, 1); tcg_gen_add2_i64(dl, dh, al, ah, bl, bh); - tcg_gen_add2_i64(dl, dh, dl, dh, tl, th); + tcg_gen_add2_i64(dl, dh, dl, dh, tl, zero); tcg_temp_free_i64(tl); - tcg_temp_free_i64(th); } static DisasJumpType op_vac(DisasContext *s, DisasOps *o) @@ -1484,7 +1482,7 @@ static void gen_accc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah, { TCGv_i64 tl = tcg_temp_new_i64(); TCGv_i64 th = tcg_temp_new_i64(); - TCGv_i64 zero = tcg_const_i64(0); + TCGv_i64 zero = tcg_constant_i64(0); tcg_gen_andi_i64(tl, cl, 1); tcg_gen_add2_i64(tl, th, tl, zero, al, zero); @@ -1495,7 +1493,6 @@ static void gen_accc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah, tcg_temp_free_i64(tl); tcg_temp_free_i64(th); - tcg_temp_free_i64(zero); } static DisasJumpType op_vaccc(DisasContext *s, DisasOps *o) @@ -1597,14 +1594,13 @@ static void gen_avgl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) static void gen_avgl_i64(TCGv_i64 dl, TCGv_i64 al, TCGv_i64 bl) { TCGv_i64 dh = tcg_temp_new_i64(); - TCGv_i64 zero = tcg_const_i64(0); + TCGv_i64 zero = tcg_constant_i64(0); tcg_gen_add2_i64(dl, dh, al, zero, bl, zero); gen_addi2_i64(dl, dh, dl, dh, 1); tcg_gen_extract2_i64(dl, dl, dh, 1); tcg_temp_free_i64(dh); - tcg_temp_free_i64(zero); } static DisasJumpType op_vavgl(DisasContext *s, DisasOps *o) @@ -2440,7 +2436,7 @@ static void gen_scbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, { TCGv_i64 th = tcg_temp_new_i64(); TCGv_i64 tl = tcg_temp_new_i64(); - TCGv_i64 zero = tcg_const_i64(0); + TCGv_i64 zero = tcg_constant_i64(0); tcg_gen_sub2_i64(tl, th, al, zero, bl, zero); tcg_gen_andi_i64(th, th, 1); @@ -2452,7 +2448,6 @@ static void gen_scbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, tcg_temp_free_i64(th); tcg_temp_free_i64(tl); - tcg_temp_free_i64(zero); } static DisasJumpType op_vscbi(DisasContext *s, DisasOps *o) @@ -2572,11 +2567,12 @@ static DisasJumpType op_vsumq(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } - sumh = tcg_const_i64(0); + sumh = tcg_temp_new_i64(); suml = tcg_temp_new_i64(); - zero = tcg_const_i64(0); + zero = tcg_constant_i64(0); tmpl = tcg_temp_new_i64(); + tcg_gen_mov_i64(sumh, zero); read_vec_element_i64(suml, get_field(s, v3), max_idx, es); for (idx = 0; idx <= max_idx; idx++) { read_vec_element_i64(tmpl, get_field(s, v2), idx, es); @@ -2587,7 +2583,6 @@ static DisasJumpType op_vsumq(DisasContext *s, DisasOps *o) tcg_temp_free_i64(sumh); tcg_temp_free_i64(suml); - tcg_temp_free_i64(zero); tcg_temp_free_i64(tmpl); return DISAS_NEXT; } From patchwork Mon Jan 9 20:07:57 2023 Content-Type: text/plain; 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Signed-off-by: Ilya Leoshkevich Message-Id: <20221103130011.2670186-1-iii@linux.ibm.com> Signed-off-by: Richard Henderson --- tests/tcg/s390x/Makefile.softmmu-target | 1 + tests/tcg/s390x/bal.S | 24 ++++++++++++++++++++++++ 2 files changed, 25 insertions(+) create mode 100644 tests/tcg/s390x/bal.S diff --git a/tests/tcg/s390x/Makefile.softmmu-target b/tests/tcg/s390x/Makefile.softmmu-target index a34fa68473..295df08491 100644 --- a/tests/tcg/s390x/Makefile.softmmu-target +++ b/tests/tcg/s390x/Makefile.softmmu-target @@ -7,3 +7,4 @@ QEMU_OPTS=-action panic=exit-failure -kernel -Wl,--build-id=none $< -o $@ TESTS += unaligned-lowcore +TESTS += bal diff --git a/tests/tcg/s390x/bal.S b/tests/tcg/s390x/bal.S new file mode 100644 index 0000000000..e54d8874ff --- /dev/null +++ b/tests/tcg/s390x/bal.S @@ -0,0 +1,24 @@ + .org 0x200 /* lowcore padding */ + .globl _start +_start: + lpswe start24_psw +_start24: + lgrl %r0,initial_r0 + lgrl %r1,expected_r0 + bal %r0,0f +0: + cgrjne %r0,%r1,1f + lpswe success_psw +1: + lpswe failure_psw + .align 8 +start24_psw: + .quad 0x160000000000,_start24 /* 24-bit mode, cc = 1, pm = 6 */ +initial_r0: + .quad 0x1234567887654321 +expected_r0: + .quad 0x1234567896000000 + 0b /* ilc = 2, cc = 1, pm = 6 */ +success_psw: + .quad 0x2000000000000,0xfff /* see is_special_wait_psw() */ +failure_psw: + .quad 0x2000000000000,0 /* disabled wait */ From patchwork Mon Jan 9 20:07:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 640681 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp2337565pvb; Mon, 9 Jan 2023 12:16:33 -0800 (PST) X-Google-Smtp-Source: AMrXdXtKvp10ZWMUvQlHng0DHQfqKPdr228j+QlclPmoCTKGlD+bfeBmnM56yl1IR5HV2sFow99V X-Received: by 2002:a67:b205:0:b0:3b1:5691:2bca with SMTP id b5-20020a67b205000000b003b156912bcamr32831965vsf.11.1673295393320; Mon, 09 Jan 2023 12:16:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673295393; cv=none; d=google.com; s=arc-20160816; b=tcHxhyI2WvQXPWmnWV7TZx0IbR8AhQRLXgu3TJ80zfeiduzbhMLFbht5Bv7eef6qgq be2t1BThWzmvcnq4c/vnLF+Yq7MpvWx5i6mvPXVUPfaF8tsPfRxEG/f+g7XNzkW0Vd2N vWhnxO6a5x/ULlo6Xqjxsz7OvUN3Y19DpwOYQ0/Y/JY+ElCASnaRIuRW/DNk5ccERMQ+ ZMaWbAsH8ROt4unl1LSGAklenHTv7KSj/Sqf9pihHkVHt4OYpAWCJPII6HQNx0wGYrMB 0tRUixRGfp0hTk0gvX97j8xTSY/RlQm3gnBn31kn3hqvVGN8WE0H7azSKFNTgEbJhO7h 6Rpg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=7Jm8IvT8OnM6ntzNw++ITlfcs7TcV+gT1sswHnCP9Os=; b=HAlgiD0WwF4Ur8TNliXoZfjTjYesByErgQvJdDfs7HuYzqxiLcR4/dADu0hWTqdez/ efRAoY0XwbYoyvTAgeG2uTnpVByvEHnvZct9hDPU2YOUpffcIrBRBlz39sufI9LVP8FJ vPO52MchAcf8HgGLYmOzi661veyurgMd9TTP8jUldOasYnkVWKUSMlNiEPZ4zXdQZJ1Y bsf62YMmRFMskdgCI/Q5BxmWrtp2IHshuxvdIqpVcOMkkkaeWUBempcbOWyH6jIQ/rKH uMJiePvMJGJZahXBVAtyl4Lu/66twkiCa+mP2BKby7QylIYXKjdZbsO/+9J9gaA9jw6j Z6yw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HczyxnSG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Ilya Leoshkevich Message-Id: <20221129015328.55439-1-iii@linux.ibm.com> Signed-off-by: Richard Henderson --- tests/tcg/s390x/Makefile.softmmu-target | 1 + tests/tcg/s390x/sam.S | 67 +++++++++++++++++++++++++ 2 files changed, 68 insertions(+) create mode 100644 tests/tcg/s390x/sam.S diff --git a/tests/tcg/s390x/Makefile.softmmu-target b/tests/tcg/s390x/Makefile.softmmu-target index 295df08491..d6ca8d7342 100644 --- a/tests/tcg/s390x/Makefile.softmmu-target +++ b/tests/tcg/s390x/Makefile.softmmu-target @@ -8,3 +8,4 @@ QEMU_OPTS=-action panic=exit-failure -kernel TESTS += unaligned-lowcore TESTS += bal +TESTS += sam diff --git a/tests/tcg/s390x/sam.S b/tests/tcg/s390x/sam.S new file mode 100644 index 0000000000..4cab2dd200 --- /dev/null +++ b/tests/tcg/s390x/sam.S @@ -0,0 +1,67 @@ +/* DAT on, home-space mode, 64-bit mode */ +#define DAT_PSWM 0x400c00180000000 +#define VIRTUAL_BASE 0x123456789abcd000 + + .org 0x8e +program_interruption_code: + .org 0x150 +program_old_psw: + .org 0x1d0 /* program new PSW */ + .quad 0,pgm_handler + .org 0x200 /* lowcore padding */ + + .globl _start +_start: + lctlg %c13,%c13,hasce + lpswe dat_psw +start_dat: + sam24 +sam24_suppressed: + /* sam24 should fail */ +fail: + basr %r12,%r0 + lpswe failure_psw-.(%r12) +pgm_handler: + chhsi program_interruption_code,6 /* specification exception? */ + jne fail + clc suppressed_psw(16),program_old_psw /* correct location? */ + jne fail + lpswe success_psw + + .align 8 +dat_psw: + .quad DAT_PSWM,VIRTUAL_BASE+start_dat +suppressed_psw: + .quad DAT_PSWM,VIRTUAL_BASE+sam24_suppressed +success_psw: + .quad 0x2000000000000,0xfff /* see is_special_wait_psw() */ +failure_psw: + .quad 0x2000000000000,0 /* disabled wait */ +hasce: + /* DT = 0b11 (region-first-table), TL = 3 (2k entries) */ + .quad region_first_table + (3 << 2) + 3 + .align 0x1000 +region_first_table: + .org region_first_table + ((VIRTUAL_BASE >> 53) & 0x7ff) * 8 + /* TT = 0b11 (region-first-table), TL = 3 (2k entries) */ + .quad region_second_table + (3 << 2) + 3 + .org region_first_table + 0x800 * 8 +region_second_table: + .org region_second_table + ((VIRTUAL_BASE >> 42) & 0x7ff) * 8 + /* TT = 0b10 (region-second-table), TL = 3 (2k entries) */ + .quad region_third_table + (2 << 2) + 3 + .org region_second_table + 0x800 * 8 +region_third_table: + .org region_third_table + ((VIRTUAL_BASE >> 31) & 0x7ff) * 8 + /* TT = 0b01 (region-third-table), TL = 3 (2k entries) */ + .quad segment_table + (1 << 2) + 3 + .org region_third_table + 0x800 * 8 +segment_table: + .org segment_table + ((VIRTUAL_BASE >> 20) & 0x7ff) * 8 + /* TT = 0b00 (segment-table) */ + .quad page_table + .org segment_table + 0x800 * 8 +page_table: + .org page_table + ((VIRTUAL_BASE >> 12) & 0xff) * 8 + .quad 0 + .org page_table + 0x100 * 8 From patchwork Mon Jan 9 20:07:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 640682 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp2338039pvb; Mon, 9 Jan 2023 12:17:34 -0800 (PST) X-Google-Smtp-Source: AMrXdXsfZEOR4RyhSaxmJX6RuWG9R/vIp9TegLs9a7MjRlBttLGVQDp6bSF4gAnDkfR35M3oHccN X-Received: by 2002:a05:6902:b15:b0:7ba:f028:b326 with SMTP id ch21-20020a0569020b1500b007baf028b326mr5871335ybb.26.1673295453983; Mon, 09 Jan 2023 12:17:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673295453; cv=none; d=google.com; s=arc-20160816; b=TITzHu8dTCZzmrWTw2r3+zQZ9cL7uTUQJZP7eeusfAh7mp24Q+0mopHuBhidHLcahN uasxd6FMBznlx3MUSFLkgPJ+H4QqvYMpBVdAX8P3CZuYCgr2sD0oumcZwpWSggEDLpbs aZJhXIi5Yiu1iYwOUmJLmz6xaGegsKO95y14fpnhBWDYP6oOz5GCWCEfCsgouTwokLpz iAcGAeagUfqxpn1WOPI06XCkfO57VNtOrEwKsxUIHTAJHFLwnH4JtHBdDsie9jzQEFO/ jSAHQqMvE71nx0j57GFIF/2mxc7KpuayrrMb0AKM/s9/SVBrSqgmMaY0MtmWUb6+I1va Q70g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=0zBrdaSUeRUDXCt0EzlV8qE/5LvkgTmGDIbtmZQgP5w=; b=WN+LG7T11z/4ijuyL7J+5pt9de9NWQpgnJkMEw+x3eLiQvKkEltu/+dEPGwPhXJv2G Ef1mtF/NfA/6CRW1hz2g9g6BzzkOxwHsCLV4cBv3dS1snydf+ixNjZv9kjstNE6R73pE 93BIQ+Pe7/1gtMdofLESk7WN1D7E2vxH9urSb34CZ58tOU3L3NE8kilgVWbB1SthEYia FPjVOChKV4zxt8PFjgaQm1ce85YlUpwH84gOKabermwIDowHBhgYcNrtXHacbT2QvijX do8s/I4MlPxK/qXfeYMkptkhTMZCkWp43d+ep7hmR9XYDRWDOx5O2xYOOtqdXCpVBIhN 5jWA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bjHG9r+P; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d48c:8101:158e:facf:7a46:ba9f]) by smtp.gmail.com with ESMTPSA id l2-20020a17090a384200b0022727d4af8dsm577574pjf.48.2023.01.09.12.08.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 12:08:29 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Ilya Leoshkevich Subject: [PATCH v3 07/27] target/s390x: Change help_goto_direct to work on displacements Date: Mon, 9 Jan 2023 12:07:59 -0800 Message-Id: <20230109200819.3916395-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109200819.3916395-1-richard.henderson@linaro.org> References: <20230109200819.3916395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 83805085a9..f13ea43ce9 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -1145,8 +1145,10 @@ struct DisasInsn { /* ====================================================================== */ /* Miscellaneous helpers, used by several operations. */ -static DisasJumpType help_goto_direct(DisasContext *s, uint64_t dest) +static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp) { + uint64_t dest = s->base.pc_next + disp; + if (dest == s->pc_tmp) { per_branch(s, true); return DISAS_NEXT; @@ -1169,7 +1171,8 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, bool is_imm, int imm, TCGv_i64 cdest) { DisasJumpType ret; - uint64_t dest = s->base.pc_next + (int64_t)imm * 2; + int64_t disp = (int64_t)imm * 2; + uint64_t dest = s->base.pc_next + disp; TCGLabel *lab; /* Take care of the special cases first. */ @@ -1185,7 +1188,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, goto egress; } if (c->cond == TCG_COND_ALWAYS) { - ret = help_goto_direct(s, dest); + ret = help_goto_direct(s, disp); goto egress; } } else { @@ -1558,7 +1561,7 @@ static DisasJumpType op_bal(DisasContext *s, DisasOps *o) static DisasJumpType op_basi(DisasContext *s, DisasOps *o) { pc_to_link_info(o->out, s, s->pc_tmp); - return help_goto_direct(s, s->base.pc_next + (int64_t)get_field(s, i2) * 2); + return help_goto_direct(s, (int64_t)get_field(s, i2) * 2); } static DisasJumpType op_bc(DisasContext *s, DisasOps *o) From patchwork Mon Jan 9 20:08:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 640672 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp2335016pvb; Mon, 9 Jan 2023 12:10:54 -0800 (PST) X-Google-Smtp-Source: AMrXdXtWh98p4RHVn++k0bsqczJVRunVdQ3ClOG8y/Upn05VVvTAXlxzMFqWBP7IBPb0+6DYtV6O X-Received: by 2002:a81:7744:0:b0:443:6227:3ab3 with SMTP id s65-20020a817744000000b0044362273ab3mr25586507ywc.4.1673295054776; Mon, 09 Jan 2023 12:10:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673295054; cv=none; d=google.com; s=arc-20160816; b=LpdfCRb2o4SFIvTNf6/L99fdPeVp7sCw2SS0XG8DnENk7XLvLX9dsC7v2IHcgSZNY0 dbXvClIcfye8JG9RDcuqhVUc69C7o2LdfZBX4Mmt2xM/asvdvjHTmwi7CV3VbzaAAll9 6JiG+bUmU9ZAyEVeOHZWZjL1o8BPNRgIwrU4gwjqS0zSCc3MBvurnfQweDiea1Ma0ikH mO2Iu3cTC1WheGJSrHBo5MBYvKs4cAj211zAzHZBkmbLmAOECUg5fkqi3bMhGbluv3te 1teV/YvE/xT83TQK+cw9z1a6qrqK0svZigjV8xASOo1Je2xFE3CgzL0C5hQozn461hMj s4Uw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=W+5Eh/DdcatVyopp39LTL5JN35D5TSKPLpjfcSQeFls=; b=0/UgczEakqVx9bBs9eZgX9JTn9xHvaGuzNEFdKveZHv1ebyPvG5gJaMZaBPb4tgjjf oKoz78LwZESf/FzL+zbg1Rs586A09qH21PNtQPX/HFssaKotg+xyxksJ0bpZ8p4kuVp1 VgZr43i4DgX75/RCQX8QtAufeLStN8jAzSGj0hiiBkhM9WRkvXcMW1pmFyN63rvoqccg YBVhOSeafu3QkvEIphoRPggsYpIAa5BOH5lwKA0Eu46LHq1Zm5j17PMBf1ekOaIgh4qc RBzF6KiEQfpexaC22OrKly1ECREMnvxeiOxgogZZtFwTja7hUeCvVWxXj+g7Yt7bj0VH BJcA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RJclhlNi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d48c:8101:158e:facf:7a46:ba9f]) by smtp.gmail.com with ESMTPSA id l2-20020a17090a384200b0022727d4af8dsm577574pjf.48.2023.01.09.12.08.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 12:08:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Ilya Leoshkevich Subject: [PATCH v3 08/27] target/s390x: Introduce gen_psw_addr_disp Date: Mon, 9 Jan 2023 12:08:00 -0800 Message-Id: <20230109200819.3916395-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109200819.3916395-1-richard.henderson@linaro.org> References: <20230109200819.3916395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 69 ++++++++++++++++++++++++------------ 1 file changed, 46 insertions(+), 23 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index f13ea43ce9..b41f5af988 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -169,6 +169,11 @@ static uint64_t inline_branch_hit[CC_OP_MAX]; static uint64_t inline_branch_miss[CC_OP_MAX]; #endif +static void gen_psw_addr_disp(DisasContext *s, TCGv_i64 dest, int64_t disp) +{ + tcg_gen_movi_i64(dest, s->base.pc_next + disp); +} + static void pc_to_link_info(TCGv_i64 out, DisasContext *s, uint64_t pc) { if (s->base.tb->flags & FLAG_MASK_32) { @@ -334,18 +339,24 @@ static void return_low128(TCGv_i64 dest) static void update_psw_addr(DisasContext *s) { - /* psw.addr */ - tcg_gen_movi_i64(psw_addr, s->base.pc_next); + gen_psw_addr_disp(s, psw_addr, 0); } static void per_branch(DisasContext *s, bool to_next) { #ifndef CONFIG_USER_ONLY - tcg_gen_movi_i64(gbea, s->base.pc_next); + gen_psw_addr_disp(s, gbea, 0); if (s->base.tb->flags & FLAG_MASK_PER) { - TCGv_i64 next_pc = to_next ? tcg_constant_i64(s->pc_tmp) : psw_addr; - gen_helper_per_branch(cpu_env, gbea, next_pc); + if (to_next) { + TCGv_i64 next_pc = tcg_temp_new_i64(); + + gen_psw_addr_disp(s, next_pc, s->ilen); + gen_helper_per_branch(cpu_env, gbea, next_pc); + tcg_temp_free_i64(next_pc); + } else { + gen_helper_per_branch(cpu_env, gbea, psw_addr); + } } #endif } @@ -358,20 +369,23 @@ static void per_branch_cond(DisasContext *s, TCGCond cond, TCGLabel *lab = gen_new_label(); tcg_gen_brcond_i64(tcg_invert_cond(cond), arg1, arg2, lab); - tcg_gen_movi_i64(gbea, s->base.pc_next); + gen_psw_addr_disp(s, gbea, 0); gen_helper_per_branch(cpu_env, gbea, psw_addr); gen_set_label(lab); } else { - TCGv_i64 pc = tcg_constant_i64(s->base.pc_next); + TCGv_i64 pc = tcg_temp_new_i64(); + + gen_psw_addr_disp(s, pc, 0); tcg_gen_movcond_i64(cond, gbea, arg1, arg2, gbea, pc); + tcg_temp_free_i64(pc); } #endif } static void per_breaking_event(DisasContext *s) { - tcg_gen_movi_i64(gbea, s->base.pc_next); + gen_psw_addr_disp(s, gbea, 0); } static void update_cc_op(DisasContext *s) @@ -1147,21 +1161,19 @@ struct DisasInsn { static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp) { - uint64_t dest = s->base.pc_next + disp; - - if (dest == s->pc_tmp) { + if (disp == s->ilen) { per_branch(s, true); return DISAS_NEXT; } - if (use_goto_tb(s, dest)) { + if (use_goto_tb(s, s->base.pc_next + disp)) { update_cc_op(s); per_breaking_event(s); tcg_gen_goto_tb(0); - tcg_gen_movi_i64(psw_addr, dest); + gen_psw_addr_disp(s, psw_addr, disp); tcg_gen_exit_tb(s->base.tb, 0); return DISAS_NORETURN; } else { - tcg_gen_movi_i64(psw_addr, dest); + gen_psw_addr_disp(s, psw_addr, disp); per_branch(s, false); return DISAS_PC_UPDATED; } @@ -1219,14 +1231,14 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, /* Branch not taken. */ tcg_gen_goto_tb(0); - tcg_gen_movi_i64(psw_addr, s->pc_tmp); + gen_psw_addr_disp(s, psw_addr, s->ilen); tcg_gen_exit_tb(s->base.tb, 0); /* Branch taken. */ gen_set_label(lab); per_breaking_event(s); tcg_gen_goto_tb(1); - tcg_gen_movi_i64(psw_addr, dest); + gen_psw_addr_disp(s, psw_addr, disp); tcg_gen_exit_tb(s->base.tb, 1); ret = DISAS_NORETURN; @@ -1249,12 +1261,12 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, /* Branch not taken. */ update_cc_op(s); tcg_gen_goto_tb(0); - tcg_gen_movi_i64(psw_addr, s->pc_tmp); + gen_psw_addr_disp(s, psw_addr, s->ilen); tcg_gen_exit_tb(s->base.tb, 0); gen_set_label(lab); if (is_imm) { - tcg_gen_movi_i64(psw_addr, dest); + gen_psw_addr_disp(s, psw_addr, disp); } per_breaking_event(s); ret = DISAS_PC_UPDATED; @@ -1264,9 +1276,12 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, Most commonly we're single-stepping or some other condition that disables all use of goto_tb. Just update the PC and exit. */ - TCGv_i64 next = tcg_constant_i64(s->pc_tmp); + TCGv_i64 next = tcg_temp_new_i64(); + + gen_psw_addr_disp(s, next, s->ilen); if (is_imm) { - cdest = tcg_constant_i64(dest); + cdest = tcg_temp_new_i64(); + gen_psw_addr_disp(s, cdest, disp); } if (c->is_64) { @@ -1285,6 +1300,10 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, tcg_temp_free_i64(t1); } + tcg_temp_free_i64(next); + if (is_imm) { + tcg_temp_free_i64(cdest); + } ret = DISAS_PC_UPDATED; } @@ -5829,7 +5848,8 @@ static void in2_a2(DisasContext *s, DisasOps *o) static void in2_ri2(DisasContext *s, DisasOps *o) { - o->in2 = tcg_const_i64(s->base.pc_next + (int64_t)get_field(s, i2) * 2); + o->in2 = tcg_temp_new_i64(); + gen_psw_addr_disp(s, o->in2, (int64_t)get_field(s, i2) * 2); } #define SPEC_in2_ri2 0 @@ -6314,8 +6334,11 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s) #ifndef CONFIG_USER_ONLY if (s->base.tb->flags & FLAG_MASK_PER) { - TCGv_i64 addr = tcg_constant_i64(s->base.pc_next); + TCGv_i64 addr = tcg_temp_new_i64(); + + gen_psw_addr_disp(s, addr, 0); gen_helper_per_ifetch(cpu_env, addr); + tcg_temp_free_i64(addr); } #endif @@ -6436,7 +6459,7 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s) if (s->base.tb->flags & FLAG_MASK_PER) { /* An exception might be triggered, save PSW if not already done. */ if (ret == DISAS_NEXT || ret == DISAS_TOO_MANY) { - tcg_gen_movi_i64(psw_addr, s->pc_tmp); + gen_psw_addr_disp(s, psw_addr, s->ilen); } /* Call the helper to check for a possible PER exception. */ From patchwork Mon Jan 9 20:08:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 640679 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp2336716pvb; Mon, 9 Jan 2023 12:14:53 -0800 (PST) X-Google-Smtp-Source: AMrXdXss5idxwWuBCzQ2EctzXfVTisAof8L492c7pTr6BnRT2ZY80NcEXovVPmQqzKLXtuEDiAjH X-Received: by 2002:ac8:470e:0:b0:3a9:756b:d9d1 with SMTP id f14-20020ac8470e000000b003a9756bd9d1mr79148564qtp.19.1673295293714; Mon, 09 Jan 2023 12:14:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673295293; cv=none; d=google.com; s=arc-20160816; b=kwPJxWjL0bjE17SpCDdDs+6xvzrtERL3p0vRZokz5icpnnPIj7K0Pk0GJnvUGNse6/ M0ExOCgkNsNH/XnU0Qnbc+anoP5IKkLFn9GmlQa83LLT4Pq0OrtTRIkeUqB772GzEIjS l+M7mIPC+FKX2bdAt5ZnSZ/iiTVzM9eR3ji8VVxO5WT/+tNtWh8hmOPdcnsIAdWkBGDi DL+J/nGXKpU8lO3CwkyZE+U+VcR7o4l6SqkE+vV3NzyuR71mmuXW4aqiX878UzBvPpw+ AAD0we20HD9mgOvtCHKPdUiseNZn9mTKq1zspYCcpn0fsm+wHcCZFfAM1+lFR2uUB6O3 nKCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=fuFmEK8Iwf94SJtJ1ovewqobkADHJCdvU7OnItfY0Yw=; b=DgFgloNxJMQMfF3odW5Umj7EobXFDHpxZWzQHdJtktXvY/tb9OmgpqnJ59fHhVlvXz BLRD6gPsp/BSh5I3T9RT+3smJPF7TwYaIK0aJlunW+lsztdovlD+4oorn3Y/mmiodArS A9scEKUpiQg8sdlKb06m1/430Nj4FN31UX/thVD6UoPwnoG0YQKJ4R85OCQMpIaiRFee 6WTCL52hJD+eCKxUla3zO5WXegvyr0da1fjDmzssvHgv4+YwPuQrR0y5nJYCcfqVrnwy cVzR9ChwdwaN9YjhMk/0pv27qvLLtTfJggor4Q98F2imIvJNt/OKs9XAw7km2pyGcRL+ thhA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hOHop+L0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d48c:8101:158e:facf:7a46:ba9f]) by smtp.gmail.com with ESMTPSA id l2-20020a17090a384200b0022727d4af8dsm577574pjf.48.2023.01.09.12.08.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 12:08:31 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Ilya Leoshkevich , =?utf-8?q?P?= =?utf-8?q?hilippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 09/27] target/s390x: Remove pc argument to pc_to_link_into Date: Mon, 9 Jan 2023 12:08:01 -0800 Message-Id: <20230109200819.3916395-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109200819.3916395-1-richard.henderson@linaro.org> References: <20230109200819.3916395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org All callers pass s->pc_tmp. Reviewed-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index b41f5af988..fadb87ad4a 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -174,8 +174,10 @@ static void gen_psw_addr_disp(DisasContext *s, TCGv_i64 dest, int64_t disp) tcg_gen_movi_i64(dest, s->base.pc_next + disp); } -static void pc_to_link_info(TCGv_i64 out, DisasContext *s, uint64_t pc) +static void pc_to_link_info(TCGv_i64 out, DisasContext *s) { + uint64_t pc = s->pc_tmp; + if (s->base.tb->flags & FLAG_MASK_32) { if (s->base.tb->flags & FLAG_MASK_64) { tcg_gen_movi_i64(out, pc); @@ -1534,7 +1536,7 @@ static DisasJumpType op_ni(DisasContext *s, DisasOps *o) static DisasJumpType op_bas(DisasContext *s, DisasOps *o) { - pc_to_link_info(o->out, s, s->pc_tmp); + pc_to_link_info(o->out, s); if (o->in2) { tcg_gen_mov_i64(psw_addr, o->in2); per_branch(s, false); @@ -1549,7 +1551,7 @@ static void save_link_info(DisasContext *s, DisasOps *o) TCGv_i64 t; if (s->base.tb->flags & (FLAG_MASK_32 | FLAG_MASK_64)) { - pc_to_link_info(o->out, s, s->pc_tmp); + pc_to_link_info(o->out, s); return; } gen_op_calc_cc(s); @@ -1579,7 +1581,7 @@ static DisasJumpType op_bal(DisasContext *s, DisasOps *o) static DisasJumpType op_basi(DisasContext *s, DisasOps *o) { - pc_to_link_info(o->out, s, s->pc_tmp); + pc_to_link_info(o->out, s); return help_goto_direct(s, (int64_t)get_field(s, i2) * 2); } From patchwork Mon Jan 9 20:08:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 640676 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp2336409pvb; Mon, 9 Jan 2023 12:14:07 -0800 (PST) X-Google-Smtp-Source: AMrXdXs0kAFiVnXwzhWA4eoL+qCrl5tUTQQtqiXVbhVkvPHExLqEYPZJfHFFUzXVpijo06XZoUoi X-Received: by 2002:a05:6214:5f85:b0:4d8:42df:19de with SMTP id ls5-20020a0562145f8500b004d842df19demr85656549qvb.23.1673295246949; Mon, 09 Jan 2023 12:14:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673295246; cv=none; d=google.com; s=arc-20160816; b=K6TWx2LI37REip48dt8+wWACikqy/Z4Sj8CzCC9uQd5hLWEd0+f3mg47KTvCpnM4wk KxQJrY3fphyMKVfYcK7Axtsy3wXb9fy5UJ04DgWR1x11g0QKvBNN9D1E0Tvf70kDgSwI t2eSYB0aT3nf0lhoO6jzHwniImoufDM2SYd4la3mxCKynJjOtX+6FS4sXsW0p8FTFard 441U7ybN57lv9kBZfvXuXSZ6vYZckUmYDi1xkCEz6qm2lsyaytgq6VFkgaDAw0QYRB8j wT9HKWHo8PmbD2QyrTY9lcfCevpYYocPWwdpIgLwxs9YcxPTyn8l9Pj95UgPM+UGu3Fj 9+HA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=aRf7w7ZOWvevd8ePH3+KPSTGXAG+AAapDCGBGEQxlrc=; b=LvqGFYitPFWjUALWht0nTcHMcAeWZuNt5hrJIG0uRGUeqmV2mhhDgqJoHBci4X+V7M jUoies1DO2MCXAcNSGsyKYqE4t4+LFJYGQHQHhzudeDF0fcvIZ27NpnFiejWwNmDMXT3 uBf9n5pbNSMWqeVTczNM7kh5TeBarpHymSIARikM2gRzFAzMAOQVwL3IZ6J8nRzlnkkq Qqq8YhS9wqnWFPHcF58a8FzFATZtCBdFRm0uXOlqfbnYsZYrir1rT6qpQ4jJRLtCVPOx rz1tLCVIEvgEeNY+FJd4c7EWCZsNvFkOktgPxpPeJKkUUCEkvpxKU09W0wQ4mD8qGZ0j /Aig== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xoiuMtac; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d48c:8101:158e:facf:7a46:ba9f]) by smtp.gmail.com with ESMTPSA id l2-20020a17090a384200b0022727d4af8dsm577574pjf.48.2023.01.09.12.08.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 12:08:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Ilya Leoshkevich Subject: [PATCH v3 10/27] target/s390x: Use gen_psw_addr_disp in pc_to_link_info Date: Mon, 9 Jan 2023 12:08:02 -0800 Message-Id: <20230109200819.3916395-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109200819.3916395-1-richard.henderson@linaro.org> References: <20230109200819.3916395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This is slightly more complicated than a straight displacement for 31 and 24-bit modes. Dont bother with a cant-happen assert. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index fadb87ad4a..05a11df00e 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -176,17 +176,20 @@ static void gen_psw_addr_disp(DisasContext *s, TCGv_i64 dest, int64_t disp) static void pc_to_link_info(TCGv_i64 out, DisasContext *s) { - uint64_t pc = s->pc_tmp; + TCGv_i64 tmp; - if (s->base.tb->flags & FLAG_MASK_32) { - if (s->base.tb->flags & FLAG_MASK_64) { - tcg_gen_movi_i64(out, pc); - return; - } - pc |= 0x80000000; + if (s->base.tb->flags & FLAG_MASK_64) { + gen_psw_addr_disp(s, out, s->ilen); + return; } - assert(!(s->base.tb->flags & FLAG_MASK_64)); - tcg_gen_deposit_i64(out, out, tcg_constant_i64(pc), 0, 32); + + tmp = tcg_temp_new_i64(); + gen_psw_addr_disp(s, tmp, s->ilen); + if (s->base.tb->flags & FLAG_MASK_32) { + tcg_gen_ori_i64(tmp, tmp, 0x80000000); + } + tcg_gen_deposit_i64(out, out, tmp, 0, 32); + tcg_temp_free_i64(tmp); } static TCGv_i64 psw_addr; From patchwork Mon Jan 9 20:08:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 640678 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp2336714pvb; Mon, 9 Jan 2023 12:14:53 -0800 (PST) X-Google-Smtp-Source: AMrXdXu8pGubcs++iSrzDTf3N9GTFTxgoxhhoyVfJwqok2ZMecKHJWwsiXKQDdy4U/miKSdTh/3K X-Received: by 2002:ac8:65d6:0:b0:3a9:691e:8dc6 with SMTP id t22-20020ac865d6000000b003a9691e8dc6mr94393001qto.47.1673295293562; Mon, 09 Jan 2023 12:14:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673295293; cv=none; d=google.com; s=arc-20160816; b=MWBKpEdlc0FkdgAd8CZQH7ebhigZGnLxpA1dmg8XYXHGuTnNWn90Z9uVvQ8q92gC7j e38w4oisLMJ4xvG6fNLZS3vIC6/fRF/fd42qel0BciHZhw9EByCvPmLl+P9aee3Uj2xN lLGI7OIY819pJ086r5nNR76lUjmMRnoOOu9F3bdJltmAxciM0U9G4EuwplAdATuDbHAP iqkkB7ZKbcXn4V8o9p4A3zgPVHDdnpmoJ+012VkWxyiyOWkCpqV3vhYGpxSrGUEhCWVt ac2WfCfgBjPmXnrMT7z22BVKsbuRT//c4EldPbG6epcP2rGu58KgytADUh4ybIAriHcd p62Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=rzW2RGRVBHiiLOC7jWYoqfyrR/GmVs5nUcJKMJ/tfDc=; b=Fr4UOKWnqAG3HNT2LJrAxjQPDHl9lpQRBGVqibhnBcXf2WIsDlhX2N/DAoXpGYJiBb uxH5Etkqy/ainGSZ+RHpt92Mbeqd6BFDBc+TT+OLBNubN/be9JdqlqwcnpQcn0uMYCsL g48nElwokV5KQMmBZPz7iyXiUPUDtCtMlICVBNMUUtS5DRn77ZJ9r/X+d/f5srX/b3jD HvgVO4l89YPU2wGvI+gAuQdUjSal5PyJ48XZzJqZRBKexG5bOrd9xTflEi2aXkxpzX0l 1O0MIfz2DP6F+6VH4IamvvUjWbwBThe3P720IymzAsP9e6V1dzBnLV35wqX93lT8gRhM Q8Pw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nVRKJ0QD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d48c:8101:158e:facf:7a46:ba9f]) by smtp.gmail.com with ESMTPSA id l2-20020a17090a384200b0022727d4af8dsm577574pjf.48.2023.01.09.12.08.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 12:08:33 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Ilya Leoshkevich , =?utf-8?q?P?= =?utf-8?q?hilippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 11/27] target/s390x: Use gen_psw_addr_disp in save_link_info Date: Mon, 9 Jan 2023 12:08:03 -0800 Message-Id: <20230109200819.3916395-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109200819.3916395-1-richard.henderson@linaro.org> References: <20230109200819.3916395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Trivial but non-mechanical conversion away from pc_tmp. Reviewed-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 05a11df00e..001cfa9162 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -1558,9 +1558,11 @@ static void save_link_info(DisasContext *s, DisasOps *o) return; } gen_op_calc_cc(s); - tcg_gen_andi_i64(o->out, o->out, 0xffffffff00000000ull); - tcg_gen_ori_i64(o->out, o->out, ((s->ilen / 2) << 30) | s->pc_tmp); t = tcg_temp_new_i64(); + tcg_gen_andi_i64(o->out, o->out, 0xffffffff00000000ull); + gen_psw_addr_disp(s, t, s->ilen); + tcg_gen_or_i64(o->out, o->out, t); + tcg_gen_ori_i64(o->out, o->out, (s->ilen / 2) << 30); tcg_gen_shri_i64(t, psw_mask, 16); tcg_gen_andi_i64(t, t, 0x0f000000); tcg_gen_or_i64(o->out, o->out, t); From patchwork Mon Jan 9 20:08:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 640670 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp2334972pvb; Mon, 9 Jan 2023 12:10:49 -0800 (PST) X-Google-Smtp-Source: AMrXdXsjGA6Eexlgt6uulV90baMDVOeOQsVXx55B64WAS0JLu1nPew6m3vpyxUxfAIn4vo55gNlB X-Received: by 2002:a05:6122:1792:b0:3ca:3a1d:6bad with SMTP id o18-20020a056122179200b003ca3a1d6badmr39384264vkf.16.1673295049220; Mon, 09 Jan 2023 12:10:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673295049; cv=none; d=google.com; s=arc-20160816; b=Fpo2PbPTpj/aitey3kmVR1NU3jH2HcYzmJ7Rm4yzCsoZwiFgF3SoRTPf2SKnBJpJEg 59AL1Hjg2OrLRq0a2rklrpKnIZaNSph/qPCHHAiuhhFX49YTJPR/JAfyztTRIES+Q+5F CaFs1+JcpUbuUsiEEPORVN0gd9oiIVZOQEyEn22QWoPRah/wZ8r0Tr1D6Ihg3sVpG+Mg 8sTBIqWn09+naG9QEpgEvkWa2k8uaCfC8ZN/17hVuzUOUDZbTOvq5EZ50tvUV+Brn6Wd GHPkViei8PvlU80IZOgdDYsHafxuo/LllOpIqUadSq9oYTEUWzaJyFIU40trHyDSFJGq JL+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=LQBI7dFc7kEPaCFgnTuGOTxG1+cWJVCWRSLqHnmhHaM=; b=IvHFHHTleH3wbnhD0CKiZgx9OanRMI6rzlac7LGYNkOJXzXWllmRSsneyUVPvaX05g veWtIxh1ra+LO5oEjWXip/ZcWCvpQUw3T2ZQLTUccXgDbZtp4ih1iRMJKI2uLDbLvXh5 T5U3QBOu5U2T0seQ9PTq8PZcHXIpN7VKwaQIYtGEx/sJj2ViJ2MuwGUUV9vTyxgok5l0 n/YR3BCrxRKkGH+IysM9UwdQij6PFMRWWHL52L7lXQvKOkk+qIdzw1i152yviDELVkOg yz9Cg3ytR64ZCFAmA8/t8sCXR0Crl1oUTxnOwVb3tlq2AbgJx56UHwvgnQV2AWq51FrR 8eNA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mSgoQdZA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d48c:8101:158e:facf:7a46:ba9f]) by smtp.gmail.com with ESMTPSA id l2-20020a17090a384200b0022727d4af8dsm577574pjf.48.2023.01.09.12.08.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 12:08:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Ilya Leoshkevich Subject: [PATCH v3 12/27] target/s390x: Use gen_psw_addr_disp in op_sam Date: Mon, 9 Jan 2023 12:08:04 -0800 Message-Id: <20230109200819.3916395-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109200819.3916395-1-richard.henderson@linaro.org> References: <20230109200819.3916395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Complicated because we may now require a runtime jump. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 40 +++++++++++++++++++++++++----------- 1 file changed, 28 insertions(+), 12 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 001cfa9162..624bd18735 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -3924,7 +3924,7 @@ static DisasJumpType op_sacf(DisasContext *s, DisasOps *o) static DisasJumpType op_sam(DisasContext *s, DisasOps *o) { int sam = s->insn->data; - TCGv_i64 tsam; + TCGLabel *fault = NULL; uint64_t mask; switch (sam) { @@ -3939,20 +3939,36 @@ static DisasJumpType op_sam(DisasContext *s, DisasOps *o) break; } - /* Bizarre but true, we check the address of the current insn for the - specification exception, not the next to be executed. Thus the PoO - documents that Bad Things Happen two bytes before the end. */ - if (s->base.pc_next & ~mask) { - gen_program_exception(s, PGM_SPECIFICATION); - return DISAS_NORETURN; - } - s->pc_tmp &= mask; + /* + * Bizarre but true, we check the address of the current insn for the + * specification exception, not the next to be executed. Thus the PoO + * documents that Bad Things Happen two bytes before the end. + */ + if (mask != -1) { + TCGv_i64 t = tcg_temp_new_i64(); + fault = gen_new_label(); - tsam = tcg_constant_i64(sam); - tcg_gen_deposit_i64(psw_mask, psw_mask, tsam, 31, 2); + gen_psw_addr_disp(s, t, 0); + tcg_gen_andi_i64(t, t, ~mask); + tcg_gen_brcondi_i64(TCG_COND_NE, t, 0, fault); + tcg_temp_free_i64(t); + } + + update_cc_op(s); + + tcg_gen_deposit_i64(psw_mask, psw_mask, tcg_constant_i64(sam), 31, 2); + + gen_psw_addr_disp(s, psw_addr, s->ilen); + tcg_gen_andi_i64(psw_addr, psw_addr, mask); /* Always exit the TB, since we (may have) changed execution mode. */ - return DISAS_TOO_MANY; + tcg_gen_lookup_and_goto_ptr(); + + if (mask != -1) { + gen_set_label(fault); + gen_program_exception(s, PGM_SPECIFICATION); + } + return DISAS_NORETURN; } static DisasJumpType op_sar(DisasContext *s, DisasOps *o) From patchwork Mon Jan 9 20:08:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 640687 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp2339252pvb; Mon, 9 Jan 2023 12:20:20 -0800 (PST) X-Google-Smtp-Source: AMrXdXtNdV01JBIpIM/jxafqPCNIUxT/sKrbp6/xj+lGNdD14zkQpdfNmBVgeuXyGxSWygaEVAkL X-Received: by 2002:a05:622a:418b:b0:3a8:2f65:6ccb with SMTP id cd11-20020a05622a418b00b003a82f656ccbmr79657282qtb.65.1673295619963; Mon, 09 Jan 2023 12:20:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673295619; cv=none; d=google.com; s=arc-20160816; b=PI2uZMmLe5Ag6iQdBVnOfBH/foJvVFjzlSngan8RV35/UMtkBzKNJlUQbXdWYPpOi/ srotPlYAOKRynDWj0DFok7uG5sosj6biASr172K/EhLK/ut2ZQtoLj8EWK3PCYoU+/cu hAETdmpOzxgKM6cjzywDn9FJ5eVN8EcHiEzj7YN7kL87WoQRM2thd+EEno/Dmxw5TmwW kI7RZPo6AujC2tz0S/9HzHuu+Ryenz2pd3o5LRfojlAhNEyp/K/srVoZ2Z3dAGQX9zXo 1PKuR1pm0vYTyzqp7SMcERzdhh3MzaD9x2rP9ov8WTkVt3gChPd6hGCa3fREqY1VK6iK u68A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=7YAEntzWlG5+v74Y9jfKjHpqon5dqwdjfhEi1TOWUto=; b=W9j3fsBJ3mJ9eFzxqljOFS4PdqojOAx2GHqqqAubUCcK3iHBeaoX6Y+nLyvPfSQzQz toxxs3GkQsHFwpOsrfdPvdBXS9xPJ8TI7C3rpZZ77twkLXyuiN9Ns5jpkfdAP3hLZctV DyLdsHJDXzxq/X69UUPEG1niD/aTL2UMvhDklqN4wqJlRe2i8hyHoRUKEpuDPANdu0qn mWN50e7LbFhmFfKgGsXbJHm8XsOawa6fSYl4sFFXMvymh/h7PZq0S7cOxICFp/uHF9nS AYDne91jVVXNhcBITG/zLffZexOCvqJE81eGMjNVMPKSkZDrA1esE3dzYXpUOanS/C2u 1d9g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Hc8QJAl0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d48c:8101:158e:facf:7a46:ba9f]) by smtp.gmail.com with ESMTPSA id l2-20020a17090a384200b0022727d4af8dsm577574pjf.48.2023.01.09.12.08.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 12:08:36 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Ilya Leoshkevich Subject: [PATCH v3 13/27] target/s390x: Use ilen instead in branches Date: Mon, 9 Jan 2023 12:08:05 -0800 Message-Id: <20230109200819.3916395-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109200819.3916395-1-richard.henderson@linaro.org> References: <20230109200819.3916395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Remove the remaining uses of pc_tmp, and remove the variable. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 624bd18735..449e854c82 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -141,12 +141,6 @@ struct DisasContext { TCGOp *insn_start; DisasFields fields; uint64_t ex_value; - /* - * During translate_one(), pc_tmp is used to determine the instruction - * to be executed after base.pc_next - e.g. next sequential instruction - * or a branch target. - */ - uint64_t pc_tmp; uint32_t ilen; enum cc_op cc_op; bool exit_to_mainloop; @@ -1198,7 +1192,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, goto egress; } if (is_imm) { - if (dest == s->pc_tmp) { + if (disp == s->ilen) { /* Branch to next. */ per_branch(s, true); ret = DISAS_NEXT; @@ -1222,7 +1216,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, } } - if (use_goto_tb(s, s->pc_tmp)) { + if (use_goto_tb(s, s->base.pc_next + s->ilen)) { if (is_imm && use_goto_tb(s, dest)) { /* Both exits can use goto_tb. */ update_cc_op(s); @@ -6255,7 +6249,6 @@ static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s) g_assert_not_reached(); } } - s->pc_tmp = s->base.pc_next + ilen; s->ilen = ilen; /* We can't actually determine the insn format until we've looked up @@ -6492,7 +6485,7 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s) out: /* Advance to the next instruction. */ - s->base.pc_next = s->pc_tmp; + s->base.pc_next += s->ilen; return ret; } From patchwork Mon Jan 9 20:08:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 640669 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp2334875pvb; Mon, 9 Jan 2023 12:10:39 -0800 (PST) X-Google-Smtp-Source: AMrXdXsy2VOEdNTJuH3s+XsD/dqJ5Y55pl2mvPPbmLTYYeRQqFeMm3ejeWv30EFOloZ86Z5pCVev X-Received: by 2002:a81:357:0:b0:38f:a2a7:403b with SMTP id 84-20020a810357000000b0038fa2a7403bmr14185462ywd.14.1673295039508; Mon, 09 Jan 2023 12:10:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673295039; cv=none; d=google.com; s=arc-20160816; b=ZzUUh8Ve+zp8SF+YKw25RyoIHYAZZh1eyq/sEfWsE2IHNDdg2s1kpvvGGjvFMF0NAT ZbEwuBPhp3FkEQApNt7FnFl5mgb1CpZaAL5yFL1h73/mHTDZuXuX3MGcp+z3liBZrewP QgfX+b7cRVV7+WaxthDoqPH/htEo7VWETq+OnB944DAFQvAowuRQ7Q6gFxMh7LXOzJT8 +sHzOSH4nY4jeE1Z4jKn98uryBVADK4CPVzzMpVElUA4W/1BbxCswoC8aEFcVO42/N3J sSANiSNYJtMKPhAtyMcY8/0tYX07GVmqApg0ntzKDxQD5Oa7FEWfROyT+NGT/kIro65t VfPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=3kEe5fNGYkVr+4UJdUprtIi1urVwj9zZaNxQZb+ASkI=; b=jNT7j1TuBbYkNKqciEI9trnjZ6ysPIGU6+4omDHXpI3UILjkSL7Iv5cG0V6N8TIzEL +qY4SZsFaRNNHut9eqS6W9TjY1uKiWgsJF5VPATSzE2AI2Vrqeth5gQ0lf6lWifxQ+Yv O4NT915S3a9ijftmFioIDsblDCXLgjra1Ftl8NZOOnQeg9LY74sf0UHv7BlcTu7UedSc C5N70cAVjwxjBv5lonxcU0bRAx+JBBhI5IksvZkQpUngi7pcPoQcp0Qd2R8iufXRnqCF MZ12Du6X9xxPp9c+xUaJ498GTvfdqR7GKzahliD2wq//0xZmmt1KBygBI+E6JREpkY+m VDMg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vGdj34Ou; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d48c:8101:158e:facf:7a46:ba9f]) by smtp.gmail.com with ESMTPSA id l2-20020a17090a384200b0022727d4af8dsm577574pjf.48.2023.01.09.12.08.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 12:08:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Ilya Leoshkevich Subject: [PATCH v3 14/27] target/s390x: Assert masking of psw.addr in cpu_get_tb_cpu_state Date: Mon, 9 Jan 2023 12:08:06 -0800 Message-Id: <20230109200819.3916395-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109200819.3916395-1-richard.henderson@linaro.org> References: <20230109200819.3916395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When changing modes via SAM, we raise a specification exception if the new PC is out of range. The masking in s390x_tr_init_disas_context was too late to be correct, but may be removed. Add a debugging assert in cpu_get_tb_cpu_state. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/cpu.h | 20 ++++++++++++++------ target/s390x/tcg/translate.c | 6 +----- 2 files changed, 15 insertions(+), 11 deletions(-) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 7d6d01325b..c7eeebfc53 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -379,17 +379,25 @@ static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch) } static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc, - target_ulong *cs_base, uint32_t *flags) + target_ulong *cs_base, uint32_t *pflags) { - *pc = env->psw.addr; - *cs_base = env->ex_value; - *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; + int flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; if (env->cregs[0] & CR0_AFP) { - *flags |= FLAG_MASK_AFP; + flags |= FLAG_MASK_AFP; } if (env->cregs[0] & CR0_VECTOR) { - *flags |= FLAG_MASK_VECTOR; + flags |= FLAG_MASK_VECTOR; } + *pflags = flags; + *cs_base = env->ex_value; + *pc = env->psw.addr; +#ifdef CONFIG_DEBUG_TCG + if (!(flags & FLAG_MASK_32)) { + assert(*pc <= 0xffffff); + } else if (!(flags & FLAG_MASK_64)) { + assert(*pc <= 0x7fffffff); + } +#endif } /* PER bits from control register 9 */ diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 449e854c82..de2d8edb47 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -6493,11 +6493,7 @@ static void s390x_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc = container_of(dcbase, DisasContext, base); - /* 31-bit mode */ - if (!(dc->base.tb->flags & FLAG_MASK_64)) { - dc->base.pc_first &= 0x7fffffff; - dc->base.pc_next = dc->base.pc_first; - } + /* Note cpu_get_tb_cpu_state asserts PC is masked for the mode. */ dc->cc_op = CC_OP_DYNAMIC; dc->ex_value = dc->base.tb->cs_base; From patchwork Mon Jan 9 20:08:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 640693 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp2340306pvb; Mon, 9 Jan 2023 12:22:47 -0800 (PST) X-Google-Smtp-Source: AMrXdXvaUgmvEQ8hg+hBdx51bVJEd6EOOAug3ILcoV3trma+pyFFFad1Paks3V0Yg4JC8qgRoVBu X-Received: by 2002:a05:6214:c6c:b0:4c6:fcf7:9aea with SMTP id t12-20020a0562140c6c00b004c6fcf79aeamr120429482qvj.49.1673295767509; Mon, 09 Jan 2023 12:22:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673295767; cv=none; d=google.com; s=arc-20160816; b=KVHAlCpwxqB/vstky75pzbdw+teSgWNBRujxEF9GMtYRJqUhuNUaClbQfHgBLXjxd1 2/P2QuM1br3kRebRdqvQXCdwdFscAi8UfPvZ9R/iSAmxFz9Qdjk8/Ses78UxKxgHfrD1 2571nG+EeDe9TQgbSuvE09TVKE5SnJDTZeMJvspX96jY4mVfIQVYrC7u8JNfOWGOVxaS k6A1tvCuC3FEAnS7KCOx61p+CL4N220X4OS8jFZs7MPe0evvYQKtX75lMVKk5/7eB79p x6/Osie3hEcOblpb+D37ZqAlnyJIH7WqSza7Hz+oZitAcGrNybUnoibZvqZaMjhkVKjM NbWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=LthcmYqoGylcnimKyPE4SUZ0KHnZX+uAbIpucCo0mYE=; b=fI877+g3FrvN6d/w87KV1AaAfisYoA6ss47QQRcyzUWu0ah7VZN3WqR77LVH3ZC2Qs 2barMvWpyeWi13U5NGif/KHINbpb+OhpfkSRT9HWfc5On1EUAw0IHdkMYN8BTg+al5TC hUR/EaX8hRvAuH0IWG548YDkLKOcHl2u2/NqfzijxsjqYyncQ2rzQJS1tT2Ci2O/b9zF vP+SyYJiAfkHfCJOmRhS7u7cXC52yuvAWjakZzW6LcuyeMpGVQJ8X0qqzgUY4V/8EKZB plaBc9oznb5RhGNM/Yzh7iiXGBeMZvSpTGYj/Ovy983HkniSE1BTM4/3mEBQkt1esqK2 unuQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HnDKjEAb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d48c:8101:158e:facf:7a46:ba9f]) by smtp.gmail.com with ESMTPSA id l2-20020a17090a384200b0022727d4af8dsm577574pjf.48.2023.01.09.12.08.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 12:08:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Ilya Leoshkevich Subject: [PATCH v3 15/27] target/s390x: Add disp argument to update_psw_addr Date: Mon, 9 Jan 2023 12:08:07 -0800 Message-Id: <20230109200819.3916395-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109200819.3916395-1-richard.henderson@linaro.org> References: <20230109200819.3916395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Rename to update_psw_addr_disp at the same time. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index de2d8edb47..56e1259dc6 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -336,9 +336,9 @@ static void return_low128(TCGv_i64 dest) tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUS390XState, retxl)); } -static void update_psw_addr(DisasContext *s) +static void update_psw_addr_disp(DisasContext *s, int64_t disp) { - gen_psw_addr_disp(s, psw_addr, 0); + gen_psw_addr_disp(s, psw_addr, disp); } static void per_branch(DisasContext *s, bool to_next) @@ -444,7 +444,7 @@ static void gen_program_exception(DisasContext *s, int code) offsetof(CPUS390XState, int_pgm_ilen)); /* update the psw */ - update_psw_addr(s); + update_psw_addr_disp(s, 0); /* Save off cc. */ update_cc_op(s); @@ -1168,11 +1168,11 @@ static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp) update_cc_op(s); per_breaking_event(s); tcg_gen_goto_tb(0); - gen_psw_addr_disp(s, psw_addr, disp); + update_psw_addr_disp(s, disp); tcg_gen_exit_tb(s->base.tb, 0); return DISAS_NORETURN; } else { - gen_psw_addr_disp(s, psw_addr, disp); + update_psw_addr_disp(s, disp); per_branch(s, false); return DISAS_PC_UPDATED; } @@ -2448,7 +2448,7 @@ static DisasJumpType op_ex(DisasContext *s, DisasOps *o) return DISAS_NORETURN; } - update_psw_addr(s); + update_psw_addr_disp(s, 0); update_cc_op(s); if (r1 == 0) { @@ -3175,7 +3175,7 @@ static DisasJumpType op_lpd(DisasContext *s, DisasOps *o) /* In a parallel context, stop the world and single step. */ if (tb_cflags(s->base.tb) & CF_PARALLEL) { - update_psw_addr(s); + update_psw_addr_disp(s, 0); update_cc_op(s); gen_exception(EXCP_ATOMIC); return DISAS_NORETURN; @@ -4492,7 +4492,7 @@ static DisasJumpType op_stura(DisasContext *s, DisasOps *o) tcg_gen_qemu_st_tl(o->in1, o->in2, MMU_REAL_IDX, s->insn->data); if (s->base.tb->flags & FLAG_MASK_PER) { - update_psw_addr(s); + update_psw_addr_disp(s, 0); gen_helper_per_store_real(cpu_env); } return DISAS_NEXT; @@ -4730,7 +4730,7 @@ static DisasJumpType op_svc(DisasContext *s, DisasOps *o) { TCGv_i32 t; - update_psw_addr(s); + update_psw_addr_disp(s, 0); update_cc_op(s); t = tcg_constant_i32(get_field(s, i1) & 0xff); @@ -6475,7 +6475,7 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s) if (s->base.tb->flags & FLAG_MASK_PER) { /* An exception might be triggered, save PSW if not already done. */ if (ret == DISAS_NEXT || ret == DISAS_TOO_MANY) { - gen_psw_addr_disp(s, psw_addr, s->ilen); + update_psw_addr_disp(s, s->ilen); } /* Call the helper to check for a possible PER exception. */ @@ -6544,7 +6544,7 @@ static void s390x_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) case DISAS_NORETURN: break; case DISAS_TOO_MANY: - update_psw_addr(dc); + update_psw_addr_disp(dc, 0); /* FALLTHRU */ case DISAS_PC_UPDATED: /* Next TB starts off with CC_OP_DYNAMIC, so make sure the From patchwork Mon Jan 9 20:08:08 2023 Content-Type: text/plain; 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([2602:47:d48c:8101:158e:facf:7a46:ba9f]) by smtp.gmail.com with ESMTPSA id l2-20020a17090a384200b0022727d4af8dsm577574pjf.48.2023.01.09.12.08.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 12:08:39 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Ilya Leoshkevich Subject: [PATCH v3 16/27] target/s390x: Don't set gbea for user-only Date: Mon, 9 Jan 2023 12:08:08 -0800 Message-Id: <20230109200819.3916395-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109200819.3916395-1-richard.henderson@linaro.org> References: <20230109200819.3916395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The rest of the per_* functions have this ifdef; this one seemed to be missing. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 56e1259dc6..b84b0062ca 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -384,7 +384,9 @@ static void per_branch_cond(DisasContext *s, TCGCond cond, static void per_breaking_event(DisasContext *s) { +#ifndef CONFIG_USER_ONLY gen_psw_addr_disp(s, gbea, 0); +#endif } static void update_cc_op(DisasContext *s) From patchwork Mon Jan 9 20:08:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 640686 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp2338832pvb; Mon, 9 Jan 2023 12:19:19 -0800 (PST) X-Google-Smtp-Source: AMrXdXsiDvMktUxD2SBlTUrihJovH0wvqMNXxvVlCU3UoqLOYfiHMWHtF7KTZj+dMLi8Ge5Js2gh X-Received: by 2002:a05:6102:a47:b0:3b2:e40d:1d9c with SMTP id i7-20020a0561020a4700b003b2e40d1d9cmr33522960vss.11.1673295559724; Mon, 09 Jan 2023 12:19:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673295559; cv=none; d=google.com; s=arc-20160816; b=TpN9sDRGL6fkezaueCeNHaeSongsXx4F6Zw9/3D6xsKnxW654GHkqOZFvlpOdsjKGF SAZ+T1r2YjrAls0VKHGKxMO+2t0BTQJDu1/xloJ5vQgd2GC9QXDgZX9fAOIxIqqzWum+ KLx+4+YgbJzH1hzwoGa8fMGIrc+CdSGq+3OlaRu9qxzmiuWo8qNX8nL2R5Ad7aK7Hrq2 8XvCPHssjqrwYQO+2B2k98t1JltY8KETxIUZTK3zlyl10CMCA67QLzRB3chySEYNJQZW /N0pGWlsYdH4rAAtBDnas1H6+c7ksRrKiXwYKxl10FJEJ10HRJm1kmTWnTkbcbr0XM3Q Uq+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=pQ4eU68d6z+rZoABNFvXkHrbyWgsMN7s71IQ0UJs6N0=; b=bLTtyzC+wV6dc+qCsAW4G6+OslOpn+l1IEFM1DorJ6WrjkTVsDTvDbZ5xW80p8BgC0 zdIlnnonclmkpUVZ10l9oMb95r9PsvqM8yCPYFlvbhJOpHqyieQx0T+O01jaZiPMfSwd nzmM2ZHViNjeRnZ4Qp2AzGyfG/8UU7kf08oB5yEwPSixRvrBEK6F1NyyvGcnDifJUy7V CgPlManhhOMI4ORPcNr0OAeo107EFY9AUp+5Rc2AUkIiQS5J8U6Klk/JFielXnihM0Ch P/cdjTVcxSmdkdva/HjkdNQXvGDTW8/d6UFGD+pM98OowoFO+97Zdezm48hP2haEq2LY 5M7w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wLW+rxir; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d48c:8101:158e:facf:7a46:ba9f]) by smtp.gmail.com with ESMTPSA id l2-20020a17090a384200b0022727d4af8dsm577574pjf.48.2023.01.09.12.08.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 12:08:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Ilya Leoshkevich Subject: [PATCH v3 17/27] target/s390x: Introduce per_enabled Date: Mon, 9 Jan 2023 12:08:09 -0800 Message-Id: <20230109200819.3916395-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109200819.3916395-1-richard.henderson@linaro.org> References: <20230109200819.3916395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Hoist the test of FLAG_MASK_PER to a helper. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index b84b0062ca..b02b76dfad 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -341,12 +341,21 @@ static void update_psw_addr_disp(DisasContext *s, int64_t disp) gen_psw_addr_disp(s, psw_addr, disp); } +static inline bool per_enabled(DisasContext *s) +{ +#ifdef CONFIG_USER_ONLY + return false; +#else + return unlikely(s->base.tb->flags & FLAG_MASK_PER); +#endif +} + static void per_branch(DisasContext *s, bool to_next) { #ifndef CONFIG_USER_ONLY gen_psw_addr_disp(s, gbea, 0); - if (s->base.tb->flags & FLAG_MASK_PER) { + if (per_enabled(s)) { if (to_next) { TCGv_i64 next_pc = tcg_temp_new_i64(); @@ -364,7 +373,7 @@ static void per_branch_cond(DisasContext *s, TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2) { #ifndef CONFIG_USER_ONLY - if (s->base.tb->flags & FLAG_MASK_PER) { + if (per_enabled(s)) { TCGLabel *lab = gen_new_label(); tcg_gen_brcond_i64(tcg_invert_cond(cond), arg1, arg2, lab); @@ -665,7 +674,7 @@ static void gen_op_calc_cc(DisasContext *s) static bool use_goto_tb(DisasContext *s, uint64_t dest) { - if (unlikely(s->base.tb->flags & FLAG_MASK_PER)) { + if (per_enabled(s)) { return false; } return translator_use_goto_tb(&s->base, dest); @@ -4493,7 +4502,7 @@ static DisasJumpType op_stura(DisasContext *s, DisasOps *o) { tcg_gen_qemu_st_tl(o->in1, o->in2, MMU_REAL_IDX, s->insn->data); - if (s->base.tb->flags & FLAG_MASK_PER) { + if (per_enabled(s)) { update_psw_addr_disp(s, 0); gen_helper_per_store_real(cpu_env); } @@ -6351,7 +6360,7 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s) } #ifndef CONFIG_USER_ONLY - if (s->base.tb->flags & FLAG_MASK_PER) { + if (per_enabled(s)) { TCGv_i64 addr = tcg_temp_new_i64(); gen_psw_addr_disp(s, addr, 0); @@ -6474,7 +6483,7 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s) } #ifndef CONFIG_USER_ONLY - if (s->base.tb->flags & FLAG_MASK_PER) { + if (per_enabled(s)) { /* An exception might be triggered, save PSW if not already done. */ if (ret == DISAS_NEXT || ret == DISAS_TOO_MANY) { update_psw_addr_disp(s, s->ilen); @@ -6499,7 +6508,7 @@ static void s390x_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) dc->cc_op = CC_OP_DYNAMIC; dc->ex_value = dc->base.tb->cs_base; - dc->exit_to_mainloop = (dc->base.tb->flags & FLAG_MASK_PER) || dc->ex_value; + dc->exit_to_mainloop = per_enabled(dc) || dc->ex_value; } static void s390x_tr_tb_start(DisasContextBase *db, CPUState *cs) From patchwork Mon Jan 9 20:08:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 640685 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp2338816pvb; Mon, 9 Jan 2023 12:19:17 -0800 (PST) X-Google-Smtp-Source: AMrXdXsWSayYH9WV/4Uiz2pkB6kpbLTmGEk8A0uYzKV+fEpNUlqFwwGUPO4tyKTX8o9PBMfeTYQ1 X-Received: by 2002:ac8:4692:0:b0:3a7:e66d:a97c with SMTP id g18-20020ac84692000000b003a7e66da97cmr554611qto.4.1673295557226; Mon, 09 Jan 2023 12:19:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673295557; cv=none; d=google.com; s=arc-20160816; b=szijQTn5ACT9CmdJRpetkOqEiEZSgRwkVkNORc+kXXhyzpksXXAbmPR/KBvDEVP8BL m2uikyTWFHk1qVDpcFZnYHrvbA/istQRkftvUyYd7sTj2tl0MFBPxBwkEKxKbW04U+ck gPw/8ZiQZPW0B4Lz0uzstyU2+J8vdqV/1RhoiZri6Fa3V7HwHXkkFBmITdjj7DLwd8tu iuti8nt3WYy9L4ev2nKm8Rd3Rhte2q0RdABwGgUNx0z6EnvS2EubJlAlUpLYQeQEnSwN keHqae5CmbxEmqn4aEXkhpiXTEf5V3Nz8JML7UXQtY/fb4iwVaYY+n3I/lslF0lxGxTV 9Kvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=huHLV3sTv30gudJNWzDsqVS9kBrPAjakiU9Bz/DYeo4=; b=TGNA6w4zwyZqtlsxs3TiMnjRnx5gffa2utuMIQ/I+cgdNBj89VuXWh089VYiuCCpW7 uEQMUMf1N/RiNyZv7Y6hOuT3ujr/yBf0nh/01YIttLR88iW/uVC5Jns1VLsm5Ds697SY RzWfqHBL2/41YStRcvLu2zipKMG/dN6bDUNnyGjGogXWgS4DDmdphZPnobCHGrLOtFo2 zZtBq4WMXhLnQ8OW2WbsdTvL5uYNky4bvj9CbPf+qlkrgxdZ/Au+cv8POrppnTa3RfLd sTyCW75OEn6TR3py5uZIW1L4mso9EoA4XARzDSG4ZrqL48a2J4PimMyc4BCXuVarsYJO DLfw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=D+H7sClq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d48c:8101:158e:facf:7a46:ba9f]) by smtp.gmail.com with ESMTPSA id l2-20020a17090a384200b0022727d4af8dsm577574pjf.48.2023.01.09.12.08.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 12:08:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Ilya Leoshkevich Subject: [PATCH v3 18/27] target/s390x: Disable conditional branch-to-next for PER Date: Mon, 9 Jan 2023 12:08:10 -0800 Message-Id: <20230109200819.3916395-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109200819.3916395-1-richard.henderson@linaro.org> References: <20230109200819.3916395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org For PER, we require a conditional call to helper_per_branch for the conditional branch. Fold the remaining optimization into a call to helper_goto_direct, which will take care of the remaining gbea adjustment. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index b02b76dfad..bbe39dd083 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -1203,13 +1203,12 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, goto egress; } if (is_imm) { - if (disp == s->ilen) { - /* Branch to next. */ - per_branch(s, true); - ret = DISAS_NEXT; - goto egress; - } - if (c->cond == TCG_COND_ALWAYS) { + /* + * Do not optimize a conditional branch if PER enabled, because we + * still need a conditional call to helper_per_branch. + */ + if (c->cond == TCG_COND_ALWAYS + || (disp == s->ilen && !per_enabled(s))) { ret = help_goto_direct(s, disp); goto egress; } From patchwork Mon Jan 9 20:08:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 640692 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp2340041pvb; Mon, 9 Jan 2023 12:22:05 -0800 (PST) X-Google-Smtp-Source: AMrXdXue4oymomvd7QJ762g5af77Lp8Kzqbh1LzTG3AbReLcKWDKn9q2r6qCizTr2mg1XRqscPet X-Received: by 2002:ad4:4e09:0:b0:51f:f4f4:e4f8 with SMTP id dl9-20020ad44e09000000b0051ff4f4e4f8mr79903044qvb.25.1673295725253; Mon, 09 Jan 2023 12:22:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673295725; cv=none; d=google.com; s=arc-20160816; b=FTbrSEOt2SG1HnWs//n1G03xsXmzNcdxvrJd6gbatInDr8yUnCrxhg8aO6uB3ekalD n5PNfRgnjkk6BCR9v3lfm1eL3oQ7dWHVq93/dOrk9bvPXGlA+eoxthYB0+yAOLfVvRF0 FjCv9MtLIlFvVITwv8xcJMpQ//CejXcH0cSvRBo1inszKlrCUB+3pJkgs8cCdIxsnJ7K ngRdaf6srX2Sp2PUH/k85u0/0xPOS5+wwh7enX3bE2odpymfiPDvehK4LIkRih3QmrhE W6wBoDZ9RxZFdTIjToQVubmgMa6whazGkUbyNJK2G7Xx/rPiPGXper5KIoZUYLEzBMjK dFdg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=rOafY3nfVG5SzehtqB5mgOADFoO+3I8xljC1PBVfEGM=; b=MzXuhy//DDuJiUkSrN8r/8YaDTRyuawlluTVCbLrQe0GlEiuWEzQmfgsT4WRt5Uu5B OAdlKYrev8PUI3eCwQ230+y0MdIVguPVrGAEY654gm2pxUwT1vZOwbqIlmZEXlAglId4 DuGJHyg0WmRjXHz84xRn0BvshpuczxQ+i0fe00TrvE9XDpkppFdItfZxRMFTQE7lsgSk 4NAL4Z2+d2S3e/TZuOs0lV6UfV7yF9rBCeJeu5Ufk8EBBVPVmZvvYd1d8J2DbQKYpQev BQjOcgm5nsiyxnYPpjcTqNXfxW00Xm8kyxdVImMh+iV4urQiKAsQNUffRIJmRwZsihJ9 E2hg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="X/WHElWW"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d48c:8101:158e:facf:7a46:ba9f]) by smtp.gmail.com with ESMTPSA id l2-20020a17090a384200b0022727d4af8dsm577574pjf.48.2023.01.09.12.08.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 12:08:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Ilya Leoshkevich Subject: [PATCH v3 19/27] target/s390x: Introduce help_goto_indirect Date: Mon, 9 Jan 2023 12:08:11 -0800 Message-Id: <20230109200819.3916395-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109200819.3916395-1-richard.henderson@linaro.org> References: <20230109200819.3916395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add a small helper to handle unconditional indirect jumps. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index bbe39dd083..dd3bd9531b 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -1189,6 +1189,13 @@ static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp) } } +static DisasJumpType help_goto_indirect(DisasContext *s, TCGv_i64 dest) +{ + tcg_gen_mov_i64(psw_addr, dest); + per_branch(s, false); + return DISAS_PC_UPDATED; +} + static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, bool is_imm, int imm, TCGv_i64 cdest) { @@ -1219,9 +1226,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, goto egress; } if (c->cond == TCG_COND_ALWAYS) { - tcg_gen_mov_i64(psw_addr, cdest); - per_branch(s, false); - ret = DISAS_PC_UPDATED; + ret = help_goto_indirect(s, cdest); goto egress; } } @@ -1545,9 +1550,7 @@ static DisasJumpType op_bas(DisasContext *s, DisasOps *o) { pc_to_link_info(o->out, s); if (o->in2) { - tcg_gen_mov_i64(psw_addr, o->in2); - per_branch(s, false); - return DISAS_PC_UPDATED; + return help_goto_indirect(s, o->in2); } else { return DISAS_NEXT; } @@ -1580,9 +1583,7 @@ static DisasJumpType op_bal(DisasContext *s, DisasOps *o) { save_link_info(s, o); if (o->in2) { - tcg_gen_mov_i64(psw_addr, o->in2); - per_branch(s, false); - return DISAS_PC_UPDATED; + return help_goto_indirect(s, o->in2); } else { return DISAS_NEXT; } From patchwork Mon Jan 9 20:08:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 640698 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp2341427pvb; Mon, 9 Jan 2023 12:25:37 -0800 (PST) X-Google-Smtp-Source: AMrXdXthhF4GBFqMrqlAJMU/gtX3mmxQZgOxYA7d8woRZFis4DwsREM5Kx1oDciPXSu+Mb1vTxAY X-Received: by 2002:ac8:4e16:0:b0:3a9:8c90:dcec with SMTP id c22-20020ac84e16000000b003a98c90dcecmr77926579qtw.68.1673295937764; Mon, 09 Jan 2023 12:25:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673295937; cv=none; d=google.com; s=arc-20160816; b=Q1QECI2W3STGEhQN01ii/AoS4oJnnnmv5YktI5eVbqWBkWDe6zl6MtRSO9h6nBQq8j GVj0jIP1YqMjWY99cEnJph/Q2ZIyd74IaNSGRU/LGtNaI/OxzO4o39IwwcXjcdAnNtTl 9+YAxaZx5isohJkNcycyFQm9ayK4tVToVfzUFBIbE1ui7fQA8U0CPgGXvNLdPSWSQXdL skQQ4wrWQ7YLil6jTdWxFvBaLLTMsCUhd6MbnMXHF8+yk1E2D6ak0gKxFVUywnTESEWt slaPCCCI+55Y+wFfBJEny5V9lph0KrKSxqkPZWwS6JDRT97sh0zqL7AqaYgBIn3jaikQ FNvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Y50Lp3m9kvjNtC3mDiVU9iejxX6y2luF3bPL5MUhbdU=; b=bmyjp7F4py7SY/K+85+RXTqXvnkw95SjUS0kTsFE+bH6U5g0y/N/HHG7VF/GXczGGv CJZD7LylluAeJ2rb6yO/y3goi0F9+j/Iwu0XM41eutYRpHWOSDOT1RsLpU0wDw5Bwa2F ZKdZE0Akn7Sg3sgKcYHizDflK4eO8Yhp259WXDmj+dJ1khXd+McCpgPJDK8edohnOOp+ mfWQti6QdH3cX9fC28be8VcUUN+aX0jqBAZjV7kVa/w7n6wfbns1zlbrAHkWwh0WkO2+ QCYMsXsLtRQabXKRJL0zyXticHp9EDLlIozxFfqu4UTluBen32Eixd52+vDwkZZqIBqV F+Ow== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ltRRooQv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d48c:8101:158e:facf:7a46:ba9f]) by smtp.gmail.com with ESMTPSA id l2-20020a17090a384200b0022727d4af8dsm577574pjf.48.2023.01.09.12.08.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 12:08:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Ilya Leoshkevich Subject: [PATCH v3 20/27] target/s390x: Split per_branch Date: Mon, 9 Jan 2023 12:08:12 -0800 Message-Id: <20230109200819.3916395-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109200819.3916395-1-richard.henderson@linaro.org> References: <20230109200819.3916395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Split into per_branch_dest and per_branch_disp, which can be used for direct and indirect. In preperation for TARGET_TB_PCREL, call per_branch_* before indirect branches. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/s390x/tcg/translate.c | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index dd3bd9531b..e3855f6e09 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -350,21 +350,25 @@ static inline bool per_enabled(DisasContext *s) #endif } -static void per_branch(DisasContext *s, bool to_next) +static void per_branch_dest(DisasContext *s, TCGv_i64 dest) { #ifndef CONFIG_USER_ONLY gen_psw_addr_disp(s, gbea, 0); - if (per_enabled(s)) { - if (to_next) { - TCGv_i64 next_pc = tcg_temp_new_i64(); + gen_helper_per_branch(cpu_env, gbea, dest); + } +#endif +} - gen_psw_addr_disp(s, next_pc, s->ilen); - gen_helper_per_branch(cpu_env, gbea, next_pc); - tcg_temp_free_i64(next_pc); - } else { - gen_helper_per_branch(cpu_env, gbea, psw_addr); - } +static void per_branch_disp(DisasContext *s, int64_t disp) +{ +#ifndef CONFIG_USER_ONLY + gen_psw_addr_disp(s, gbea, 0); + if (per_enabled(s)) { + TCGv_i64 dest = tcg_temp_new_i64(); + gen_psw_addr_disp(s, dest, disp); + gen_helper_per_branch(cpu_env, gbea, dest); + tcg_temp_free_i64(dest); } #endif } @@ -1172,7 +1176,7 @@ struct DisasInsn { static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp) { if (disp == s->ilen) { - per_branch(s, true); + per_branch_disp(s, disp); return DISAS_NEXT; } if (use_goto_tb(s, s->base.pc_next + disp)) { @@ -1184,7 +1188,7 @@ static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp) return DISAS_NORETURN; } else { update_psw_addr_disp(s, disp); - per_branch(s, false); + per_branch_dest(s, psw_addr); return DISAS_PC_UPDATED; } } @@ -1192,7 +1196,7 @@ static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp) static DisasJumpType help_goto_indirect(DisasContext *s, TCGv_i64 dest) { tcg_gen_mov_i64(psw_addr, dest); - per_branch(s, false); + per_branch_dest(s, psw_addr); return DISAS_PC_UPDATED; } From patchwork Mon Jan 9 20:08:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 640680 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp2337279pvb; Mon, 9 Jan 2023 12:16:02 -0800 (PST) X-Google-Smtp-Source: AMrXdXu4jlsauIVT7HmSJEpeHcE6odAftq1pEbr5Eq4QdDgWH1orRGO1g41q/vvm4/kaeY/g1veQ X-Received: by 2002:ac8:445a:0:b0:3a8:e35:258f with SMTP id m26-20020ac8445a000000b003a80e35258fmr93621781qtn.31.1673295362120; Mon, 09 Jan 2023 12:16:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673295362; cv=none; d=google.com; s=arc-20160816; b=q8ohvX8h1Vl7JQVXMsBdlguKAzPy1N79Jond46PE3GUoIQ4G3Bi2Vc5nrc+S89JN3Z 6kwU1AGu9hqazV4h+7oFeTvnzYICQyl5nvh3Pa6FZPT9dIDkL5UQiaVLMM5jJ2lU6h5Y SNT+PA/3C094VNuhXlolqKn3kpNWCN3GwJLRKjkAZfbVcBVpNagSZnrMpibzAnH8P6sc 2brHrOOEzyGnwSxKFfTWUs7uThbzGBhtmjQajWDXqCUnPeTdA8ujWO97urCc4/ssyuTD MbCwhIi/WLgDRLpclRL1NrpTOIoz90OZ23z+AZoIl/pvRCiZF9CvcuujTFpITcoYY6TA yQxA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=M5QVDR5p8K9NnSXHNw0nEbXh8IznLvlZ3YQDGipeghY=; b=dhzGJy9guCoq8JbQpq60g6w800hKAEuiWFMLBf2YbWoooSoLdnmbTxYeMOjSnN6Ucw ShY2+fCT6p84Pq92sh6mVAM8du0PawKzlMVU/8TDWNQ1dT40bMelustto0mmwpZJJA2h tq41k1sKcUYkJ93UijTrnXQCRpV24dWv6IeZyfQ3EVyazzzCidJM6vhNzmW90MSmMiHU 8PDRMgwt52+x2dqmXtc94AafEpTBLBdt2WvcPtN7ITizm4mMVd7cgqFPuysLZtF1fqgh OEdvwPj5qHObtyRXuwjgjW5j0ZU7c6e8S6rczr1dtOKiA7hwydK+ECFjcy9SVtReWGYn 7e+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wZSBkM82; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d48c:8101:158e:facf:7a46:ba9f]) by smtp.gmail.com with ESMTPSA id l2-20020a17090a384200b0022727d4af8dsm577574pjf.48.2023.01.09.12.08.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 12:08:44 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Ilya Leoshkevich Subject: [PATCH v3 21/27] target/s390x: Simplify help_branch Date: Mon, 9 Jan 2023 12:08:13 -0800 Message-Id: <20230109200819.3916395-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109200819.3916395-1-richard.henderson@linaro.org> References: <20230109200819.3916395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Always use a tcg branch, instead of movcond. The movcond was not a bad idea before PER was added, but since then we have either 2 or 3 actions to perform on each leg of the branch, and multiple movcond is inefficient. Reorder the taken branch to be fallthrough of the tcg branch. This will be helpful later with TARGET_TB_PCREL. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 154 ++++++++++------------------------- 1 file changed, 44 insertions(+), 110 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index e3855f6e09..aca2d214bb 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -373,28 +373,6 @@ static void per_branch_disp(DisasContext *s, int64_t disp) #endif } -static void per_branch_cond(DisasContext *s, TCGCond cond, - TCGv_i64 arg1, TCGv_i64 arg2) -{ -#ifndef CONFIG_USER_ONLY - if (per_enabled(s)) { - TCGLabel *lab = gen_new_label(); - tcg_gen_brcond_i64(tcg_invert_cond(cond), arg1, arg2, lab); - - gen_psw_addr_disp(s, gbea, 0); - gen_helper_per_branch(cpu_env, gbea, psw_addr); - - gen_set_label(lab); - } else { - TCGv_i64 pc = tcg_temp_new_i64(); - - gen_psw_addr_disp(s, pc, 0); - tcg_gen_movcond_i64(cond, gbea, arg1, arg2, gbea, pc); - tcg_temp_free_i64(pc); - } -#endif -} - static void per_breaking_event(DisasContext *s) { #ifndef CONFIG_USER_ONLY @@ -1205,7 +1183,6 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, { DisasJumpType ret; int64_t disp = (int64_t)imm * 2; - uint64_t dest = s->base.pc_next + disp; TCGLabel *lab; /* Take care of the special cases first. */ @@ -1235,96 +1212,53 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, } } - if (use_goto_tb(s, s->base.pc_next + s->ilen)) { - if (is_imm && use_goto_tb(s, dest)) { - /* Both exits can use goto_tb. */ - update_cc_op(s); + update_cc_op(s); - lab = gen_new_label(); - if (c->is_64) { - tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab); - } else { - tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab); - } - - /* Branch not taken. */ - tcg_gen_goto_tb(0); - gen_psw_addr_disp(s, psw_addr, s->ilen); - tcg_gen_exit_tb(s->base.tb, 0); - - /* Branch taken. */ - gen_set_label(lab); - per_breaking_event(s); - tcg_gen_goto_tb(1); - gen_psw_addr_disp(s, psw_addr, disp); - tcg_gen_exit_tb(s->base.tb, 1); - - ret = DISAS_NORETURN; - } else { - /* Fallthru can use goto_tb, but taken branch cannot. */ - /* Store taken branch destination before the brcond. This - avoids having to allocate a new local temp to hold it. - We'll overwrite this in the not taken case anyway. */ - if (!is_imm) { - tcg_gen_mov_i64(psw_addr, cdest); - } - - lab = gen_new_label(); - if (c->is_64) { - tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab); - } else { - tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab); - } - - /* Branch not taken. */ - update_cc_op(s); - tcg_gen_goto_tb(0); - gen_psw_addr_disp(s, psw_addr, s->ilen); - tcg_gen_exit_tb(s->base.tb, 0); - - gen_set_label(lab); - if (is_imm) { - gen_psw_addr_disp(s, psw_addr, disp); - } - per_breaking_event(s); - ret = DISAS_PC_UPDATED; - } - } else { - /* Fallthru cannot use goto_tb. This by itself is vanishingly rare. - Most commonly we're single-stepping or some other condition that - disables all use of goto_tb. Just update the PC and exit. */ - - TCGv_i64 next = tcg_temp_new_i64(); - - gen_psw_addr_disp(s, next, s->ilen); - if (is_imm) { - cdest = tcg_temp_new_i64(); - gen_psw_addr_disp(s, cdest, disp); - } - - if (c->is_64) { - tcg_gen_movcond_i64(c->cond, psw_addr, c->u.s64.a, c->u.s64.b, - cdest, next); - per_branch_cond(s, c->cond, c->u.s64.a, c->u.s64.b); - } else { - TCGv_i32 t0 = tcg_temp_new_i32(); - TCGv_i64 t1 = tcg_temp_new_i64(); - TCGv_i64 z = tcg_constant_i64(0); - tcg_gen_setcond_i32(c->cond, t0, c->u.s32.a, c->u.s32.b); - tcg_gen_extu_i32_i64(t1, t0); - tcg_temp_free_i32(t0); - tcg_gen_movcond_i64(TCG_COND_NE, psw_addr, t1, z, cdest, next); - per_branch_cond(s, TCG_COND_NE, t1, z); - tcg_temp_free_i64(t1); - } - - tcg_temp_free_i64(next); - if (is_imm) { - tcg_temp_free_i64(cdest); - } - ret = DISAS_PC_UPDATED; + /* + * Store taken branch destination before the brcond. This + * avoids having to allocate a new local temp to hold it. + * We'll overwrite this in the not taken case anyway. + */ + if (!is_imm) { + tcg_gen_mov_i64(psw_addr, cdest); } + lab = gen_new_label(); + if (c->is_64) { + tcg_gen_brcond_i64(tcg_invert_cond(c->cond), + c->u.s64.a, c->u.s64.b, lab); + } else { + tcg_gen_brcond_i32(tcg_invert_cond(c->cond), + c->u.s32.a, c->u.s32.b, lab); + } + + /* Branch taken. */ + if (is_imm) { + gen_psw_addr_disp(s, psw_addr, disp); + } + per_branch_dest(s, psw_addr); + + if (is_imm && use_goto_tb(s, s->base.pc_next + disp)) { + tcg_gen_goto_tb(0); + tcg_gen_exit_tb(s->base.tb, 0); + } else { + tcg_gen_lookup_and_goto_ptr(); + } + + gen_set_label(lab); + + /* Branch not taken. */ + if (use_goto_tb(s, s->base.pc_next + s->ilen)) { + tcg_gen_goto_tb(1); + gen_psw_addr_disp(s, psw_addr, s->ilen); + tcg_gen_exit_tb(s->base.tb, 1); + } else { + gen_psw_addr_disp(s, psw_addr, s->ilen); + tcg_gen_lookup_and_goto_ptr(); + } + + ret = DISAS_NORETURN; + egress: free_compare(c); return ret; From patchwork Mon Jan 9 20:08:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 640673 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp2335728pvb; Mon, 9 Jan 2023 12:12:22 -0800 (PST) X-Google-Smtp-Source: AMrXdXv556dzfV+QgIXJtkir7YcCgaTGsCXVwbrwOrIa6cUEf49uNFHvv1JCcIBmjK9+6X6uw6bR X-Received: by 2002:ac8:7c92:0:b0:3a7:eb36:5cb1 with SMTP id y18-20020ac87c92000000b003a7eb365cb1mr87744525qtv.36.1673295142059; Mon, 09 Jan 2023 12:12:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673295142; cv=none; d=google.com; s=arc-20160816; b=AQdEtieJsY+Xi5ixJNaSrCK9J2U2bvUz29db6lF2Kt049MtkG5OHNJRAsoxqkCWCkP /ZdIZKJwPEi94wLytNVUoIZZcfOO44TGhMBauKJV7cZI6FyWJnTTRUJlEIy72nir0bDQ thsGfimigpJVE7XW2oXfYpNXS8vebmj3QPMESkjxQAX9/kl+yifzyPJW+iEkSIQ0kgw+ +Hu4ARrtkm7TO7pfZgBqT4iNGV+rCfOpX7dLsYrj9G1jlcUWpv0pPPNFSlZWci9zJiN6 aA3jVfFubWkgB1URfXexp/yW/cMWvgAg4eXBbF6SEa6cvwNRkjoaugrN/+CMajcTO+TX 0ygQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=+SI0XUmUuaGz6hJl5x1dC7kSwvxrktFEO3C5LNkUTlA=; b=MhyOPnE4a8y2fUxEh8x+7xtK2WszD6VbUOfBwXLwsK9dEhy1VgWui1vPeRQwtcRQgs zD8pyjlU2ZooOv9rtPHxvHElz9/RPoQMuEifzifJ6a5wCeQxdz3xHsuK8jL/8Trp7Him C9t0LFkKy1DgpaGNAahxJxzu3PZvuibtkYazFi9WnrDwN3fMK7r/9v2Iv01q6eJLnl2J UvEVjUG0BQX3oxJoN2mewNUozlRg6+nZk1W/FWspKBb0ONqsmOYSz+v7nR6XEOYrxygr ljfG8Q+CSu9oZWHHRtQxNMS1/YD1k/vQq9+css+nrj7Ma3EXqhUcwkgF2TVD5jevwa+A /v7A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dRdUGTRl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d48c:8101:158e:facf:7a46:ba9f]) by smtp.gmail.com with ESMTPSA id l2-20020a17090a384200b0022727d4af8dsm577574pjf.48.2023.01.09.12.08.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 12:08:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Ilya Leoshkevich Subject: [PATCH v3 22/27] target/s390x: Split per_breaking_event from per_branch_* Date: Mon, 9 Jan 2023 12:08:14 -0800 Message-Id: <20230109200819.3916395-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109200819.3916395-1-richard.henderson@linaro.org> References: <20230109200819.3916395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This allows us to update gbea before other updates to psw_addr, which will be important for TARGET_TB_PCREL. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index aca2d214bb..3b7591790d 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -353,7 +353,6 @@ static inline bool per_enabled(DisasContext *s) static void per_branch_dest(DisasContext *s, TCGv_i64 dest) { #ifndef CONFIG_USER_ONLY - gen_psw_addr_disp(s, gbea, 0); if (per_enabled(s)) { gen_helper_per_branch(cpu_env, gbea, dest); } @@ -363,7 +362,6 @@ static void per_branch_dest(DisasContext *s, TCGv_i64 dest) static void per_branch_disp(DisasContext *s, int64_t disp) { #ifndef CONFIG_USER_ONLY - gen_psw_addr_disp(s, gbea, 0); if (per_enabled(s)) { TCGv_i64 dest = tcg_temp_new_i64(); gen_psw_addr_disp(s, dest, disp); @@ -1153,13 +1151,14 @@ struct DisasInsn { static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp) { + per_breaking_event(s); + if (disp == s->ilen) { per_branch_disp(s, disp); return DISAS_NEXT; } if (use_goto_tb(s, s->base.pc_next + disp)) { update_cc_op(s); - per_breaking_event(s); tcg_gen_goto_tb(0); update_psw_addr_disp(s, disp); tcg_gen_exit_tb(s->base.tb, 0); @@ -1173,6 +1172,7 @@ static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp) static DisasJumpType help_goto_indirect(DisasContext *s, TCGv_i64 dest) { + per_breaking_event(s); tcg_gen_mov_i64(psw_addr, dest); per_branch_dest(s, psw_addr); return DISAS_PC_UPDATED; @@ -1233,6 +1233,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, } /* Branch taken. */ + per_breaking_event(s); if (is_imm) { gen_psw_addr_disp(s, psw_addr, disp); } From patchwork Mon Jan 9 20:08:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 640691 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp2339901pvb; Mon, 9 Jan 2023 12:21:48 -0800 (PST) X-Google-Smtp-Source: AMrXdXtpV/NeCjX0He85y2bewFaSo/ZROLi46OdaRkCIXp4gooZqM1JN2si4SfmE7JgAa3Xk7ZNM X-Received: by 2002:a05:6214:2b90:b0:532:2c0e:412a with SMTP id kr16-20020a0562142b9000b005322c0e412amr9908823qvb.52.1673295708306; Mon, 09 Jan 2023 12:21:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673295708; cv=none; d=google.com; s=arc-20160816; b=Xsnt/1qN1Wu8U3U+Ts2S1dYRypAbaDDKUyem9wFtpuoDdc7tOqRlO55C/lUVGnJOYy pRQB5A3ZYjgAbIMmVTGr3P2SQ4s5pgTNYo5g9JVngNRxxmpGQm87ikzNI18HBpR8vg0l Mi7myyvfV50Q0n1+Rb5EXXvx3T0i7npguixDV8QlcFhyGK7V1tBV6E/lrrzkTFzra52K Qo0ZWkesvcUMkSInJs/jkYHTBd9dLRde8hpmhunSH6ECO7CZxmex1tR22PHhYXK9plJ5 sa20HpNrUlFb2Faz4k3j0Nn2gdoBtjWd3paKDp9HgJPmnowKNB9duaWDeAIL2523ewAn qVcw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=bgQOHiO8qTwsgUx9kJDYlFOqQZeKGAhI8ggOyt7Pfe4=; b=ymuWYsjRg+UkLCFCq6t94S/ah5gTROxCBGIj7SsFOI3NvVnyuFzM4omk0wXNXEURdq 0Ud/nQI7t1yRSJ6v/WzrU5HstObO60s+J3guQiSAt7Gz7JGQJaHrZCeGTiW4bkfXmGxk BgeK5rPENhnl21ONqw6ZwqPEB4s56H6cnKEFwFVOUewQGC7CbHdsruQ6yYefxHe/CPBQ qWyomRGtPIkKmcrw4BeZ4lDllbZiTUNRiSvImUMuggNcdeR5vy9fK/uaBy2i68q5WE34 7rehRN24AbeUHynVz0zVUNI1HVyqrOsc8c/9rza27NlBgIRva/565r3Y9hbgBfilfOHj 8b7w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=odaz2PCy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d48c:8101:158e:facf:7a46:ba9f]) by smtp.gmail.com with ESMTPSA id l2-20020a17090a384200b0022727d4af8dsm577574pjf.48.2023.01.09.12.08.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 12:08:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Ilya Leoshkevich Subject: [PATCH v3 23/27] target/s390x: Remove PER check from use_goto_tb Date: Mon, 9 Jan 2023 12:08:15 -0800 Message-Id: <20230109200819.3916395-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109200819.3916395-1-richard.henderson@linaro.org> References: <20230109200819.3916395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org While it is common for the PC update to happen in the shadow of a goto_tb, it is not required to be there. By moving it before the goto_tb, we can also place the call to helper_per_branch there, and then afterward chain to the next tb. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 3b7591790d..3d9a79af42 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -654,9 +654,6 @@ static void gen_op_calc_cc(DisasContext *s) static bool use_goto_tb(DisasContext *s, uint64_t dest) { - if (per_enabled(s)) { - return false; - } return translator_use_goto_tb(&s->base, dest); } @@ -1157,15 +1154,16 @@ static DisasJumpType help_goto_direct(DisasContext *s, int64_t disp) per_branch_disp(s, disp); return DISAS_NEXT; } + + update_psw_addr_disp(s, disp); + per_branch_dest(s, psw_addr); + if (use_goto_tb(s, s->base.pc_next + disp)) { update_cc_op(s); tcg_gen_goto_tb(0); - update_psw_addr_disp(s, disp); tcg_gen_exit_tb(s->base.tb, 0); return DISAS_NORETURN; } else { - update_psw_addr_disp(s, disp); - per_branch_dest(s, psw_addr); return DISAS_PC_UPDATED; } } From patchwork Mon Jan 9 20:08:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 640688 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp2339387pvb; Mon, 9 Jan 2023 12:20:41 -0800 (PST) X-Google-Smtp-Source: AMrXdXukn93a58QyD5X912Z1zA58+sUzhCRG4SMHgWXl5bdM/GvI7ZfJmYnY4NjZOzoTdN4yazoN X-Received: by 2002:a67:cc1e:0:b0:3ce:cae4:754 with SMTP id q30-20020a67cc1e000000b003cecae40754mr7899900vsl.16.1673295641583; Mon, 09 Jan 2023 12:20:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673295641; cv=none; d=google.com; s=arc-20160816; b=D/Mhyf/7RcvbRgpUR9XcMjVPjX69ESIOPMobr6hkHJarUvuHVmPBthdURpLP4MFVtX nW4TWxdzpAdZUaJjJ/G01CFRou7EVbMoGOak/VX7pabbKlM34z3U7IcsiAAz1sB2FXQO Yrh9dpDaRlzZBAV27WJGefkJJYUIDhhRDWsBf3fDuNDgZ7LyS0LbpMyrpcH56zL/hjyZ KvouvXitX+rgx86J0T7/cHwaAZAB9GSXuPyPgj8+SI3szX3eB+bsaLOloupAEQSMRFqo 4Qf/sEZs0XI3hXMRO/Mi0qcHpoXGmndrp9DRfxqYCCHfKtV9839ewEw/Hq8yKWRqOqJZ Gvuw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=qoDF/rY8HtyNlykYqkZFXY86Nrt61o0/K7nWThd7Dr8=; b=bSTT/yvWsSm9PPNxzORqdeiFp63rgiO2Kf3SKxOOiJrZ3zZHGysMqu+hiIpDLUagYA i77VPgEpfsmIWE6gmiLj4Kr0wQOTx5pmS5RVXqzyDaHD3w71GALvKhfv+LCMbYv+SxfF Bt4fyTJLhXHXlezCkW8+0Qoksuo7gPUYomkchJ7K3FVhlh1yx4tWPHMkEfsHiF7gBhhX lykddv7APnuwLjPPzvlV27GoMoKixT4gkUIFP83H65y0pT6ekrYQyG/YL6a7aVP5h5wJ +KzYLWnl9Sds54OP4dFLEJ4gC/n9Qg98E8OLhDt7ZZqIkJ7WbOyOLrUvh5EMgp0h0ClN Mt2A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="C55XT/Y8"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d48c:8101:158e:facf:7a46:ba9f]) by smtp.gmail.com with ESMTPSA id l2-20020a17090a384200b0022727d4af8dsm577574pjf.48.2023.01.09.12.08.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 12:08:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Ilya Leoshkevich Subject: [PATCH v3 24/27] target/s390x: Fix successful-branch PER events Date: Mon, 9 Jan 2023 12:08:16 -0800 Message-Id: <20230109200819.3916395-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109200819.3916395-1-richard.henderson@linaro.org> References: <20230109200819.3916395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Ilya Leoshkevich The branching code sets per_perc_atmid, but afterwards it does goto_tb/exit_tb, so per_check_exception() added by translate_one() is not reached. Fix by raising PER exception in per_branch(). Signed-off-by: Ilya Leoshkevich Message-Id: <20221130174610.434590-1-iii@linux.ibm.com> Signed-off-by: Richard Henderson --- target/s390x/tcg/misc_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/s390x/tcg/misc_helper.c b/target/s390x/tcg/misc_helper.c index 576157b1f3..e5015daf07 100644 --- a/target/s390x/tcg/misc_helper.c +++ b/target/s390x/tcg/misc_helper.c @@ -618,6 +618,7 @@ void HELPER(per_branch)(CPUS390XState *env, uint64_t from, uint64_t to) || get_per_in_range(env, to)) { env->per_address = from; env->per_perc_atmid = PER_CODE_EVENT_BRANCH | get_per_atmid(env); + tcg_s390_program_interrupt(env, PGM_PER, GETPC()); } } } From patchwork Mon Jan 9 20:08:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 640684 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp2338644pvb; Mon, 9 Jan 2023 12:18:50 -0800 (PST) X-Google-Smtp-Source: AMrXdXu9AA5Q/N0O90oSVg2jVLYdRELEVjY1riaZpRmv1N/cbM8OWtGYvX7tHxZwGGqHU82MmWu4 X-Received: by 2002:ac8:5191:0:b0:3a6:93cf:7dec with SMTP id c17-20020ac85191000000b003a693cf7decmr90360052qtn.48.1673295530111; Mon, 09 Jan 2023 12:18:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673295530; cv=none; d=google.com; s=arc-20160816; b=DSxnZxaij9VfW3rJ4KOvO+3E1aWi/3+f/MG81qvxVV8TZn7QQWRwLuuMDCfrXzA4u+ TTidV7dYORUp0wdeLd/ugFpXjuWTygGMXS+1dim5mQgOnrzreFNSLjBBhIzbfmzroVCt +LbrapAz8pqRTkVtHFu7MOezxo6Z5GNp/FSdSC0F+dyL3sLJpQHrls2O6ukLGhOGA4Nj LcT7kRa3tKFdndriUmBoKYgaEiiIw7lIQiOWKYEniZ7O9820PEqByNyu4wm1jpxP3yd5 UdPVzlY9JRLfl5OPHD26vwldj+zGWEY5fkxxL/dIvCEQ7VqaWt01QGa3ec63kTOhTi5d oQDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=6a8SyY9eZgzz8AJukTfXtGKf9OCDu+smgkxjoQH9ksA=; b=X92y5AHzkFSyDf+/fALdDWE9O1+d2gBFZDbknYfrgkmR9mEHPr0/q8ZQIVmUYBj7Dh I1ocj08mQd/l5hXzyZWZLPpYv401mgYy2daLZARCWXj4f0r5WDVZSxpq62Se4hyOwDtM deaAq+4K8xTDnd9L0GFJFhMQH4g18IU8PNoljpT1iite/2uRpQfW/L5XWFRlxhmoyGAN 8FXkX2xTIAq/zKukJ9XPuWR8NRpHHOtpYIpGZO9QcmoSy324AysvqjSfpfIFxFAsUFB0 xCrbX38YnIZGkKmzpbxuCgL9qkSiSHnhbx1eHqgbsm15F3Zout71cYk5KJ7RlEi1jEr0 hPFw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CKutZpt7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d48c:8101:158e:facf:7a46:ba9f]) by smtp.gmail.com with ESMTPSA id l2-20020a17090a384200b0022727d4af8dsm577574pjf.48.2023.01.09.12.08.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 12:08:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Ilya Leoshkevich Subject: [PATCH v3 25/27] tests/tcg/s390x: Add per.S Date: Mon, 9 Jan 2023 12:08:17 -0800 Message-Id: <20230109200819.3916395-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109200819.3916395-1-richard.henderson@linaro.org> References: <20230109200819.3916395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Ilya Leoshkevich Add a small test to avoid regressions. Signed-off-by: Ilya Leoshkevich Message-Id: <20221130174610.434590-2-iii@linux.ibm.com> Signed-off-by: Richard Henderson --- tests/tcg/s390x/Makefile.softmmu-target | 1 + tests/tcg/s390x/per.S | 55 +++++++++++++++++++++++++ 2 files changed, 56 insertions(+) create mode 100644 tests/tcg/s390x/per.S diff --git a/tests/tcg/s390x/Makefile.softmmu-target b/tests/tcg/s390x/Makefile.softmmu-target index d6ca8d7342..7ee69e78d8 100644 --- a/tests/tcg/s390x/Makefile.softmmu-target +++ b/tests/tcg/s390x/Makefile.softmmu-target @@ -9,3 +9,4 @@ QEMU_OPTS=-action panic=exit-failure -kernel TESTS += unaligned-lowcore TESTS += bal TESTS += sam +TESTS += per diff --git a/tests/tcg/s390x/per.S b/tests/tcg/s390x/per.S new file mode 100644 index 0000000000..02f8422c44 --- /dev/null +++ b/tests/tcg/s390x/per.S @@ -0,0 +1,55 @@ +#define N_ITERATIONS 10 + + .org 0x8d +ilc: + .org 0x8e +program_interruption_code: + .org 0x96 +per_code: + .org 0x150 +program_old_psw: + .org 0x1d0 /* program new PSW */ + .quad 0,pgm_handler + .org 0x200 /* lowcore padding */ + + .globl _start +_start: + lpswe per_on_psw +start_per: + lghi %r0,N_ITERATIONS + xgr %r1,%r1 + lctlg %c9,%c11,per_on_regs +loop: + brct %r0,loop + lctlg %c9,%c11,per_off_regs + cgijne %r1,N_ITERATIONS-1,fail /* expected number of events? */ + lpswe success_psw +fail: + lpswe failure_psw + +pgm_handler: + chhsi program_interruption_code,0x80 /* PER event? */ + jne fail + cli per_code,0x80 /* successful-branching event? */ + jne fail + la %r1,1(%r1) /* increment event counter */ + mvc return_psw(8),program_old_psw + lg %r3,program_old_psw+8 + llgc %r2,ilc + sgr %r3,%r2 /* rewind PSW */ + stg %r3,return_psw+8 + lpswe return_psw + + .align 8 +per_on_psw: + .quad 0x4000000000000000,start_per +per_on_regs: + .quad 0x80000000,0,-1 /* successful-branching everywhere */ +per_off_regs: + .quad 0,0,0 +return_psw: + .quad 0,0 +success_psw: + .quad 0x2000000000000,0xfff /* see is_special_wait_psw() */ +failure_psw: + .quad 0x2000000000000,0 /* disabled wait */ From patchwork Mon Jan 9 20:08:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 640683 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp2338205pvb; Mon, 9 Jan 2023 12:17:53 -0800 (PST) X-Google-Smtp-Source: AMrXdXuS8KMMyQzyM6NJKyBJ461GEZYkxwVitFM7iTx0Mq/DkNczfbhp2rsALvz203Ic5cfvmBIN X-Received: by 2002:a0c:f78c:0:b0:532:31e5:1566 with SMTP id s12-20020a0cf78c000000b0053231e51566mr5071979qvn.12.1673295473264; Mon, 09 Jan 2023 12:17:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673295473; cv=none; d=google.com; s=arc-20160816; b=MT3VWUkqBdzu8WtTalIFe9HNbSvt6oB4t4TJR6UoPOWdmN1V6QCVXVtWqpPZPQiBlN yYI4YL4Dp3yv0AW2OcZXke0dpJOt3VPQ8eIwTYIMxPXmrU4ovmA5VcMa80K/x72Vq/cV JkJXR7PmLz/gT+STIMGtG0JvxOhJt2qzPKwdvXy5dpAX1ESzi3dSdkAR+SPB4cA4EOp1 Xl91EDJZVTA7Yd52NqFzU/H9E+UAZU/C4gFwy67a2qgwQnvWwJBa1RNP1smi+yPtxftL fV9HZG5H24l8CwL0MxCHi7JZzulyktn3VFISCsOE4al6yP1F/zRFk2B+RqRMoIEA3SD/ NuYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=hj+kl1Rsv/DprYRzUBEWVOIFytk4nYZYRE9FcH6D9mQ=; b=VrOGNRmml60jCCbSI2Q1xz5uUQamSve/YqE3mzicvaBpUxsCjVENock6KuLpzIES6f PHAFQJ3tc5DE+9F0WjXbEycYm7qba1wMPRdUptmRmJM8UUfSAVMhrE0+mlGIugE/VS6e dhxJ+jaMCRT5vAfmPLnu8CWa/7zyIa9AC3dm9GcqOhR8P9UqsvZDkqhkat37hdUufuLo YrhTsbfMSQXTjQNec6pGDskFxDEWCiZIbcjF7Qo8jnN20VjyKHr7GCKPqBMvt68iBHbY iZmaA3HYVCXkATmOAd2qKkHsneOHuBRZXzZRmYRBYQv226cwRlpm9tfSDVuw9y6hCUw7 G6Kw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="RmfEhc/6"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d48c:8101:158e:facf:7a46:ba9f]) by smtp.gmail.com with ESMTPSA id l2-20020a17090a384200b0022727d4af8dsm577574pjf.48.2023.01.09.12.08.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 12:08:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Ilya Leoshkevich Subject: [PATCH v3 26/27] target/s390x: Pass original r2 register to BCR Date: Mon, 9 Jan 2023 12:08:18 -0800 Message-Id: <20230109200819.3916395-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109200819.3916395-1-richard.henderson@linaro.org> References: <20230109200819.3916395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We do not modify any general-purpose registers in BCR, which means that we may be able to avoid saving the value across a branch. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/insn-data.h.inc | 2 +- target/s390x/tcg/translate.c | 10 ++++++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.h.inc index 79c6ab509a..a03a19e9b9 100644 --- a/target/s390x/tcg/insn-data.h.inc +++ b/target/s390x/tcg/insn-data.h.inc @@ -121,7 +121,7 @@ /* BRANCH INDIRECT ON CONDITION */ C(0xe347, BIC, RXY_b, MIE2,0, m2_64w, 0, 0, bc, 0) /* BRANCH ON CONDITION */ - C(0x0700, BCR, RR_b, Z, 0, r2_nz, 0, 0, bc, 0) + C(0x0700, BCR, RR_b, Z, 0, r2_o_nz, 0, 0, bc, 0) C(0x4700, BC, RX_b, Z, 0, a2, 0, 0, bc, 0) /* BRANCH RELATIVE ON CONDITION */ C(0xa704, BRC, RI_c, Z, 0, 0, 0, 0, bc, 0) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 3d9a79af42..afed4e2981 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -5706,6 +5706,16 @@ static void in2_r2_nz(DisasContext *s, DisasOps *o) } #define SPEC_in2_r2_nz 0 +static void in2_r2_o_nz(DisasContext *s, DisasOps *o) +{ + int r2 = get_field(s, r2); + if (r2 != 0) { + o->in2 = regs[r2]; + o->g_in2 = true; + } +} +#define SPEC_in2_r2_o_nz 0 + static void in2_r2_8s(DisasContext *s, DisasOps *o) { o->in2 = tcg_temp_new_i64(); From patchwork Mon Jan 9 20:08:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 640668 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp2334504pvb; Mon, 9 Jan 2023 12:09:48 -0800 (PST) X-Google-Smtp-Source: AMrXdXvTzlcuwpn0grmsR8TfcAFPCUToPIUakGeZx2707SgsWk1yCqMrjMpTVvHCInyVAhDHlJpX X-Received: by 2002:a67:c785:0:b0:3b5:1126:2b64 with SMTP id t5-20020a67c785000000b003b511262b64mr28593139vsk.13.1673294988277; Mon, 09 Jan 2023 12:09:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673294988; cv=none; d=google.com; s=arc-20160816; b=FMDqDN9YEmgjxH+isPQaUjJV7bxdS6EtoZMe6fQZ2fFXtlAN26PQo8u6V2fumEiv/2 hD5q2Ogx6MYCvTHcTQ2/YQx/O5y5z40NQTQINdDkpJEZPaTiWRhMA1+UZTpEvOhGD6qQ zTPew7XbEKe3KWDJNkhtAIvRMU+LzESTwBAg0FfLo0B/45X7sRGEaTnyDZ26YFuCUdBW 7GuaLHTYO4bgHiP5MdfDcq4AZqNYDspXmAbszhDZNX6Tmdiv/mE4YrKGs3U4sktv93bS nTYg4D4LD55AdE8camHM+6S8XYxaPZ5qvPIYc47BpES3BrvelA51Dcpn0U1KzGJWxncu OzLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=XA3AgmTJV6twi3UhuBbD+P3p6iyT4YFKtf10vXvXuoA=; b=h1i/b100LCWiN67EmmQI/WdkSmvfGE4aBoyFWgF31jG9aWi+/cAosJPZ0QiphFXdA8 8oqW6x3OZLxvKBtN2o2mdYQYQHpw72JKmAwCEqs6SHton4WPcOjA3mI1SV3c7GZQOsmH CzR5z/3kQd6FWXICIVn2WRbwB2vWhEty/fndi1fq6JsL7m99P9o5cK/8d8X8cu3IvHaO icgrZrdtX/fGFXK3S40VAuYcvDvESbz4PmPE1flrSBnXmOM6DDtOQg+M5UcQ2DiPSYGM i76kTGY6SnAMMiOymxTDFB3GBTIMtKKHfmJx1OodvTNgF+dmaM/yVLgYqHAcCmASzJKp ZT4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Bu1k6uOG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d48c:8101:158e:facf:7a46:ba9f]) by smtp.gmail.com with ESMTPSA id l2-20020a17090a384200b0022727d4af8dsm577574pjf.48.2023.01.09.12.08.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 12:08:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Ilya Leoshkevich Subject: [PATCH v3 27/27] target/s390x: Enable TARGET_TB_PCREL Date: Mon, 9 Jan 2023 12:08:19 -0800 Message-Id: <20230109200819.3916395-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109200819.3916395-1-richard.henderson@linaro.org> References: <20230109200819.3916395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/cpu-param.h | 4 ++ target/s390x/cpu.c | 12 +++++ target/s390x/tcg/translate.c | 86 +++++++++++++++++++++++------------- 3 files changed, 71 insertions(+), 31 deletions(-) diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h index bf951a002e..52bb95de57 100644 --- a/target/s390x/cpu-param.h +++ b/target/s390x/cpu-param.h @@ -14,4 +14,8 @@ #define TARGET_VIRT_ADDR_SPACE_BITS 64 #define NB_MMU_MODES 4 +#ifndef CONFIG_USER_ONLY +# define TARGET_TB_PCREL 1 +#endif + #endif diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index b10a8541ff..933ff06395 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -37,6 +37,7 @@ #ifndef CONFIG_USER_ONLY #include "sysemu/reset.h" #endif +#include "exec/exec-all.h" #define CR0_RESET 0xE0UL #define CR14_RESET 0xC2000000UL; @@ -83,6 +84,16 @@ uint64_t s390_cpu_get_psw_mask(CPUS390XState *env) return r; } +static void s390_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) +{ + /* The program counter is always up to date with TARGET_TB_PCREL. */ + if (!TARGET_TB_PCREL) { + S390CPU *cpu = S390_CPU(cs); + cpu->env.psw.addr = tb_pc(tb); + } +} + static void s390_cpu_set_pc(CPUState *cs, vaddr value) { S390CPU *cpu = S390_CPU(cs); @@ -274,6 +285,7 @@ static void s390_cpu_reset_full(DeviceState *dev) static const struct TCGCPUOps s390_tcg_ops = { .initialize = s390x_translate_init, + .synchronize_from_tb = s390_cpu_synchronize_from_tb, .restore_state_to_opc = s390x_restore_state_to_opc, #ifdef CONFIG_USER_ONLY diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index afed4e2981..704db55cd4 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -139,6 +139,7 @@ struct DisasContext { DisasContextBase base; const DisasInsn *insn; TCGOp *insn_start; + target_ulong pc_save; DisasFields fields; uint64_t ex_value; uint32_t ilen; @@ -163,29 +164,6 @@ static uint64_t inline_branch_hit[CC_OP_MAX]; static uint64_t inline_branch_miss[CC_OP_MAX]; #endif -static void gen_psw_addr_disp(DisasContext *s, TCGv_i64 dest, int64_t disp) -{ - tcg_gen_movi_i64(dest, s->base.pc_next + disp); -} - -static void pc_to_link_info(TCGv_i64 out, DisasContext *s) -{ - TCGv_i64 tmp; - - if (s->base.tb->flags & FLAG_MASK_64) { - gen_psw_addr_disp(s, out, s->ilen); - return; - } - - tmp = tcg_temp_new_i64(); - gen_psw_addr_disp(s, tmp, s->ilen); - if (s->base.tb->flags & FLAG_MASK_32) { - tcg_gen_ori_i64(tmp, tmp, 0x80000000); - } - tcg_gen_deposit_i64(out, out, tmp, 0, 32); - tcg_temp_free_i64(tmp); -} - static TCGv_i64 psw_addr; static TCGv_i64 psw_mask; static TCGv_i64 gbea; @@ -336,9 +314,39 @@ static void return_low128(TCGv_i64 dest) tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUS390XState, retxl)); } +static void gen_psw_addr_disp(DisasContext *s, TCGv_i64 dest, int64_t disp) +{ + assert(s->pc_save != -1); + if (TARGET_TB_PCREL) { + disp += s->base.pc_next - s->pc_save; + tcg_gen_addi_i64(dest, psw_addr, disp); + } else { + tcg_gen_movi_i64(dest, s->base.pc_next + disp); + } +} + +static void pc_to_link_info(TCGv_i64 out, DisasContext *s) +{ + TCGv_i64 tmp; + + if (s->base.tb->flags & FLAG_MASK_64) { + gen_psw_addr_disp(s, out, s->ilen); + return; + } + + tmp = tcg_temp_new_i64(); + gen_psw_addr_disp(s, tmp, s->ilen); + if (s->base.tb->flags & FLAG_MASK_32) { + tcg_gen_ori_i64(tmp, tmp, 0x80000000); + } + tcg_gen_deposit_i64(out, out, tmp, 0, 32); + tcg_temp_free_i64(tmp); +} + static void update_psw_addr_disp(DisasContext *s, int64_t disp) { gen_psw_addr_disp(s, psw_addr, disp); + s->pc_save = s->base.pc_next + disp; } static inline bool per_enabled(DisasContext *s) @@ -1172,6 +1180,7 @@ static DisasJumpType help_goto_indirect(DisasContext *s, TCGv_i64 dest) { per_breaking_event(s); tcg_gen_mov_i64(psw_addr, dest); + s->pc_save = -1; per_branch_dest(s, psw_addr); return DISAS_PC_UPDATED; } @@ -1181,6 +1190,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, { DisasJumpType ret; int64_t disp = (int64_t)imm * 2; + TCGv_i64 cdest_save = NULL; TCGLabel *lab; /* Take care of the special cases first. */ @@ -1213,12 +1223,12 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, update_cc_op(s); /* - * Store taken branch destination before the brcond. This - * avoids having to allocate a new local temp to hold it. - * We'll overwrite this in the not taken case anyway. + * Save taken branch destination across the brcond if required. */ if (!is_imm) { - tcg_gen_mov_i64(psw_addr, cdest); + cdest_save = tcg_temp_local_new_i64(); + tcg_gen_mov_i64(cdest_save, cdest); + cdest = cdest_save; } lab = gen_new_label(); @@ -1234,6 +1244,11 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, per_breaking_event(s); if (is_imm) { gen_psw_addr_disp(s, psw_addr, disp); + } else { + tcg_gen_mov_i64(psw_addr, cdest); + } + if (cdest_save) { + tcg_temp_free_i64(cdest_save); } per_branch_dest(s, psw_addr); @@ -1247,15 +1262,15 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, gen_set_label(lab); /* Branch not taken. */ + gen_psw_addr_disp(s, psw_addr, s->ilen); if (use_goto_tb(s, s->base.pc_next + s->ilen)) { tcg_gen_goto_tb(1); - gen_psw_addr_disp(s, psw_addr, s->ilen); tcg_gen_exit_tb(s->base.tb, 1); } else { - gen_psw_addr_disp(s, psw_addr, s->ilen); tcg_gen_lookup_and_goto_ptr(); } + s->pc_save = -1; ret = DISAS_NORETURN; egress: @@ -6453,6 +6468,7 @@ static void s390x_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) /* Note cpu_get_tb_cpu_state asserts PC is masked for the mode. */ + dc->pc_save = dc->base.pc_first; dc->cc_op = CC_OP_DYNAMIC; dc->ex_value = dc->base.tb->cs_base; dc->exit_to_mainloop = per_enabled(dc) || dc->ex_value; @@ -6465,9 +6481,13 @@ static void s390x_tr_tb_start(DisasContextBase *db, CPUState *cs) static void s390x_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc = container_of(dcbase, DisasContext, base); + target_ulong pc_arg = dc->base.pc_next; + if (TARGET_TB_PCREL) { + pc_arg &= ~TARGET_PAGE_MASK; + } /* Delay the set of ilen until we've read the insn. */ - tcg_gen_insn_start(dc->base.pc_next, dc->cc_op, 0); + tcg_gen_insn_start(pc_arg, dc->cc_op, 0); dc->insn_start = tcg_last_op(); } @@ -6561,7 +6581,11 @@ void s390x_restore_state_to_opc(CPUState *cs, CPUS390XState *env = &cpu->env; int cc_op = data[1]; - env->psw.addr = data[0]; + if (TARGET_TB_PCREL) { + env->psw.addr = (env->psw.addr & TARGET_PAGE_MASK) | data[0]; + } else { + env->psw.addr = data[0]; + } /* Update the CC opcode if it is not already up-to-date. */ if ((cc_op != CC_OP_DYNAMIC) && (cc_op != CC_OP_STATIC)) {