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[213.113.123.174]) by smtp.gmail.com with ESMTPSA id v11sm5884443lfb.68.2019.04.07.23.28.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 07 Apr 2019 23:28:54 -0700 (PDT) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Imre Kaloz , Krzysztof Halasa Cc: Linus Walleij , Marc Zyngier , Jason Cooper , Thomas Gleixner , devicetree@vger.kernel.org, Rob Herring Subject: [PATCH 10/31 v3] irqchip: ixp4xx: Add DT bindings Date: Mon, 8 Apr 2019 08:28:10 +0200 Message-Id: <20190408062831.16422-11-linus.walleij@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190408062831.16422-1-linus.walleij@linaro.org> References: <20190408062831.16422-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds device tree bindings for the IXP4xx interrupt controller. It's a standard 2-cell controller. Cc: Marc Zyngier Cc: Jason Cooper Cc: Thomas Gleixner Cc: devicetree@vger.kernel.org Reviewed-by: Rob Herring Signed-off-by: Linus Walleij --- ChangeLog v2->v3: - Dropped oneOf on compatible - Dropped description on reg, set maxItems 1 - Drop the description on interrupt-cells - Collect Rob's review tag ChangeLog v1->v2: - Converted to use JSON yaml schema, why not. - Not keeping Rob's ACK because I think he wants to take a second look. --- .../intel,ixp4xx-interrupt.yaml | 54 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml -- 2.20.1 diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml b/Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml new file mode 100644 index 000000000000..bae10e261fa9 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2018 Linaro Ltd. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt/intel-ixp4xx-interrupt.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel IXP4xx XScale Networking Processors Interrupt Controller + +maintainers: + - Linus Walleij + +description: | + This interrupt controller is found in the Intel IXP4xx processors. + Some processors have 32 interrupts, some have up to 64 interrupts. + The exact number of interrupts is determined from the compatible + string. + + The distinct IXP4xx families with different interrupt controller + variations are IXP42x, IXP43x, IXP45x and IXP46x. Those four + families were the only ones to reach the developer and consumer + market. + +properties: + compatible: + items: + - enum: + - intel,ixp42x-interrupt + - intel,ixp43x-interrupt + - intel,ixp45x-interrupt + - intel,ixp46x-interrupt + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +examples: + - | + intcon: interrupt-controller@c8003000 { + compatible = "intel,ixp43x-interrupt"; + reg = <0xc8003000 0x100>; + interrupt-controller; + #interrupt-cells = <2>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index bc918f318797..ad05704fbd68 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1690,6 +1690,7 @@ M: Imre Kaloz M: Krzysztof Halasa L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained +F: Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml F: arch/arm/mach-ixp4xx/ F: drivers/clocksource/timer-ixp4xx.c F: drivers/gpio/gpio-ixp4xx.c From patchwork Mon Apr 8 06:28:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 161924 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3328466jan; Sun, 7 Apr 2019 23:29:02 -0700 (PDT) X-Google-Smtp-Source: APXvYqwTgfcZIMAIMvNvSHRo/Q4ZXn6Td2v+TWbh8rdsLJC3IY0GCY79XMtvgKEYTrjBqXRATjqA X-Received: by 2002:a62:61c2:: with SMTP id v185mr28201286pfb.117.1554704942295; Sun, 07 Apr 2019 23:29:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554704942; cv=none; d=google.com; s=arc-20160816; b=h3gqRmDj1gAXCaXafWneJ+e0k9wr8Qt77E1hHvqeW5aR9mPMHkpkfyS5QdlbIZTrgt jyH19XC1hS713WjDq6AWI1BStXPCwiREzp8bJ912uM8FeOcLQ5aMPmwVA0RZmBtGATsW +AecOfwQalaYPEC0oYO9FQ67vX4IAWVFSd/L62JCPiBsz3fm/dpWOkvi/XnptR6q5Kui QH2NGAboDIdZkLjOdrAsd0qDHp7/P4ShDITfUsaMtmquXt2gV5Zi5BSC2EuR33FJF8if Ei+4bCROPNVpCXpFj8EHJQamZ0EIzeYD0h0DM9ywr5viCENCLz5PNXL6i1H3lykVqXYz c5xQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=gt5njNU4TzcBg2aki+ensrUky5DwlpzaTnF6n88RKGk=; b=j6GxhMITwc0J9zW7xgq9zCg0L7LPZyjDHHaoMWNiwtgFs0WYKXvnm9NNZjubw+QIeb 82z10tmqY8Kvzzh1lZebOlL2+OeAfe0oMkEeVQoFc85J+Q/B1Z0dvZVq8x1fqFUUaACL kVpC3U8hbpdFqQuSjJQigvnnQ1WF3L+cGQ6QVlbBQHgzv9LqszQZceu1W4zSiq3LD439 TWJqnHySTE6XAocqJrlu/FKv0NeSHHingtlSPXTdsDeRhadf2AXAUdfr2Ff47R+Qk7UQ xSyIP24srBLzfqyZcXI7gNp6yazuZUCPjeKSf3IckvLb1T8gHD8SvI4fYboek6Lhgyza y04w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UmZ1gsKu; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[213.113.123.174]) by smtp.gmail.com with ESMTPSA id v11sm5884443lfb.68.2019.04.07.23.28.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 07 Apr 2019 23:28:58 -0700 (PDT) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Imre Kaloz , Krzysztof Halasa Cc: Linus Walleij , Daniel Lezcano , Thomas Gleixner , devicetree@vger.kernel.org, Rob Herring Subject: [PATCH 12/31 v3] clocksource/drivers/ixp4xx: Add DT bindings Date: Mon, 8 Apr 2019 08:28:12 +0200 Message-Id: <20190408062831.16422-13-linus.walleij@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190408062831.16422-1-linus.walleij@linaro.org> References: <20190408062831.16422-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds device tree bindings for the Intel IXP4xx timers. Cc: Daniel Lezcano Cc: Thomas Gleixner Cc: devicetree@vger.kernel.org Reviewed-by: Rob Herring Signed-off-by: Linus Walleij --- ChangeLog v2->v3: - Collect Rob's Review tag. ChangeLog v1->v2: - Switch to JSON YAML schema, why not. - Not collecting any review tags as this changed a bit. --- .../bindings/timer/intel,ixp4xx-timer.yaml | 42 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 43 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml -- 2.20.1 diff --git a/Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml b/Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml new file mode 100644 index 000000000000..a36a0746c056 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2018 Linaro Ltd. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/timer/intel-ixp4xx-timer.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel IXP4xx XScale Networking Processors Timers + +maintainers: + - Linus Walleij + +description: This timer is found in the Intel IXP4xx processors. + +properties: + compatible: + items: + - const: intel,ixp4xx-timer + + reg: + description: Should contain registers location and length + + interrupts: + minItems: 1 + maxItems: 2 + items: + - description: Timer 1 interrupt + - description: Timer 2 interrupt + +required: + - compatible + - reg + - interrupts + +examples: + - | + #include + timer@c8005000 { + compatible = "intel,ixp4xx-timer"; + reg = <0xc8005000 0x100>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index ad05704fbd68..78f50505a313 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1691,6 +1691,7 @@ M: Krzysztof Halasa L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml +F: Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml F: arch/arm/mach-ixp4xx/ F: drivers/clocksource/timer-ixp4xx.c F: drivers/gpio/gpio-ixp4xx.c From patchwork Mon Apr 8 06:28:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 161925 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3328516jan; Sun, 7 Apr 2019 23:29:06 -0700 (PDT) X-Google-Smtp-Source: APXvYqyc5sg76DlL1HPe7takjKqbWSQp8x0ZevQUziiUYsm/ldB6hNmrMAG7Bjkk1xjs02O9IMAT X-Received: by 2002:a62:1f92:: with SMTP id l18mr28479960pfj.180.1554704946289; Sun, 07 Apr 2019 23:29:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554704946; cv=none; d=google.com; s=arc-20160816; b=unzDElfdI7C1i3e7cExWikCh9N4PO520IK5Ru3kS5DvfaqFagQlhOsbCeHQoI1XmXB sb9RyRsbQeM6LirTW8PnmYfwyLo1Q+9WGXwlk8wC+TznukPvAMTg7+VutzRQp+SYM6d9 6m+ZbCsOJ3gL8REbbe1MeugWE0CTLvJR5r01LKlTLQY8t9zEaNKhvQaga5Hq3GqqHFcT CBL4NVSnKb5BBLuZfmRH/vk4VppbYO8X/WPh8CJKnKjO1j/oL8+iG/yX5HBWIUuAfJeC 5xvdnifr8qp20QgeHEKPHp0vavGOB/vTdjfeuFqgWX1BSMPFzNJKGicDrEiFe8QzhaPN jYJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=iljacqnFg4LmeBoXSrYKaNBp8P7wDLxY4AyH/8TV1jM=; b=sa6HDz914PGOTYCnEyHJ7qHDlFXc3Orq+8jaeUZAqqZctToE9hPe5fi3AwUd/qHjMi uZcsXn+EFsP54QxxqoG4ig+UCiay2bLMBoKzPuGUPIX9xPGzh81Wi4hQfu/T4Gk3C9gq a86KaQunVhsqoBWoesCYHR8GsZHkTQBkB3g7OAJYCXYFeaUUmz1ZhynVBkeIdZcR1R9c BpWIf5hM9WMpRTAXAvphSDW1eH2hrUc4IsA6I2YrM+uJX9sgq6KacOJwybJByX7XQJmD miZYYqp91tJ6SX7x1pA5L9hjSThCR9+fUhSRdEmP0AyXBML4H9O4k7xqp5c99CEDAegX 25Eg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="F/seV/ZB"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[213.113.123.174]) by smtp.gmail.com with ESMTPSA id v11sm5884443lfb.68.2019.04.07.23.29.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 07 Apr 2019 23:29:02 -0700 (PDT) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Imre Kaloz , Krzysztof Halasa Cc: Linus Walleij , devicetree@vger.kernel.org, Bartosz Golaszewski , Rob Herring Subject: [PATCH 14/31 v3] gpio: ixp4xx: Add DT bindings Date: Mon, 8 Apr 2019 08:28:14 +0200 Message-Id: <20190408062831.16422-15-linus.walleij@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190408062831.16422-1-linus.walleij@linaro.org> References: <20190408062831.16422-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds DT bindings for the IXP4xx GPIO controller. Cc: devicetree@vger.kernel.org Reviewed-by: Bartosz Golaszewski Reviewed-by: Rob Herring Signed-off-by: Linus Walleij --- ChangeLog v2->v3: - Rebase on v5.1-rc1 ChangeLog v1->v2: - Collect Bartosz and Rob's review tags. --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) -- 2.20.1 diff --git a/MAINTAINERS b/MAINTAINERS index 78f50505a313..0a8999c09764 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1690,6 +1690,7 @@ M: Imre Kaloz M: Krzysztof Halasa L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained +F: Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt F: Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml F: Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml F: arch/arm/mach-ixp4xx/ From patchwork Mon Apr 8 06:28:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 161926 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3328571jan; Sun, 7 Apr 2019 23:29:10 -0700 (PDT) X-Google-Smtp-Source: APXvYqw5V2lMlizX/G7lZwDxmSzJiZt05d4dlAtxa1mgC6V0YPt9yXgkf5bHmnYOhenD4Ur+QcLV X-Received: by 2002:a17:902:6b8c:: with SMTP id p12mr27691838plk.282.1554704950539; Sun, 07 Apr 2019 23:29:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554704950; cv=none; d=google.com; s=arc-20160816; b=rTfIWDYiRpd2K4JD2yMlJZhJMOkKoKzqvhyDlimSyhvHAOG0e7XEESU4ksBKxq3V3t TXZ1C6B7S4LIHODeWzpsXG5Qs8f+jqIvKk/96cBq9SegS88rCyoTtZ+wH3IJhTDWkhvR 7Kaxj92YQJfnGd0lzeUKs42OIwwbAbawohIebTFFPfyLmMw98azDmlPKZsvGAcUARElZ X/CdG9tWtGBLaNMM4cQhfmS2nATQSr1UZ0KpWidHxp5vbmsH1Jfw7VxSxPV237MhEPJM G37Z7WewtBxQnJ4rdurCzNCBfJDUG2Pq2oZs35l3hYVZvmeYOU6qorZ1b2Fm6kMrfphz dS/g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=gcdKxspfzyr8ZXvHVPMKJeLa2Vyl1YwHPiT+F16dCCg=; b=oN22uVwdeLvSqsjZ6MJfsfYXlwwDR/b7qYQAVRV1MtxeCxCLs6kO+DlL9KYIj7G0jG RNdbc8yFTZHGXKb4f2ThllSz/vrCJFxqJ3cKNnCcwrRz2yM+84MwbCvIogCUW2M/the1 CH4uN6Mge23V4zAL+QqtyQEJ+j3p4lQxEQ+0i9cfYWycNSO3WX3QyUhKodVJKQx9upex RKdVwlxG36RWzQmZOST9dMpfJewXof0FMPC22oGNWBcZj2strIUATc6ZcXWbNbyt7Tlt T2uCZarAvFPn7u2qZphLxlCkC4Cl3dlKhkJ5YmKSe4sbS66LszSju5xvRMYXnnnJE4y7 MMtA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="TWjrAbh/"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[213.113.123.174]) by smtp.gmail.com with ESMTPSA id v11sm5884443lfb.68.2019.04.07.23.29.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 07 Apr 2019 23:29:06 -0700 (PDT) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Imre Kaloz , Krzysztof Halasa Cc: Linus Walleij , devicetree@vger.kernel.org, Rob Herring Subject: [PATCH 16/31 v3] ARM: ixp4xx: Add DT bindings Date: Mon, 8 Apr 2019 08:28:16 +0200 Message-Id: <20190408062831.16422-17-linus.walleij@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190408062831.16422-1-linus.walleij@linaro.org> References: <20190408062831.16422-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds initial device tree bindings for the IXP4xx machines. This time I tried something wild and crazy and try to make proper JSON-style YAML bindings for the top level. Cc: devicetree@vger.kernel.org Reviewed-by: Rob Herring Signed-off-by: Linus Walleij --- ChangeLog v2->v3: - Rebased on v5.1-rc1 ChangeLog v1->v2: - Fix up the GW2358 compatible string. --- .../devicetree/bindings/arm/intel-ixp4xx.yaml | 22 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 23 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml -- 2.20.1 diff --git a/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml b/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml new file mode 100644 index 000000000000..f4f7451e5e8a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/intel-ixp4xx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel IXP4xx Device Tree Bindings + +maintainers: + - Linus Walleij + +properties: + compatible: + oneOf: + - items: + - enum: + - linksys,nslu2 + - const: intel,ixp42x + - items: + - enum: + - gateworks,gw2358 + - const: intel,ixp43x diff --git a/MAINTAINERS b/MAINTAINERS index 0a8999c09764..49052de0567b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1690,6 +1690,7 @@ M: Imre Kaloz M: Krzysztof Halasa L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained +F: Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml F: Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt F: Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml F: Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml From patchwork Mon Apr 8 06:28:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 161927 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3328841jan; Sun, 7 Apr 2019 23:29:31 -0700 (PDT) X-Google-Smtp-Source: APXvYqyv4HpttIbe56xX9GECvXo8RsI/4GBBzUV7pjdSoIzHezSWfbo1cE/Qxiv9M0XGSx/A/Zsa X-Received: by 2002:a17:902:e091:: with SMTP id cb17mr29022808plb.222.1554704971930; Sun, 07 Apr 2019 23:29:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554704971; cv=none; d=google.com; s=arc-20160816; b=KmmNpF9i24vWlH5qEQ1SCOI1x3Roxtqhr6xGcOC7mZtFjDBD/LTV1780ET7tUbK3lY txfFhvb9XKV6pOOsTiC0xfT61NSPXF5nOlsw5Qh+usPSdKkMC0YKCN6DejW6CNKj9S1u 2OypHsNJSA9roWIE4W2Xb4MvCK0kEXHbJCPpwZkI3LT88KFDgPfEpv/xXZpIag3/pQ39 JN4UpiHrzqtpfAsCWLi2U59cag1mE1zWc5pRlTIPdvj6mvEn7hHwbEmsmMNUWgWdLNqS ySnMe42LKVKRXljHryDB6iSbJvCTjOgfdidt12di9xYa7NRPiKk8UD73ZE62QzC6S8U0 0K9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ZK56vIDitGuvZv/uCdIi56mrFt1HuEuZ30xH6Lto5AE=; b=R6KjbXiRQC3DAdsIK459G/nVRWveqz+0i4XGifaXiNMgY49lXbMmUVkHjmkLnF2Yij 1wNnNQBprto6hZgtSioBRqjqSGysZ40MzzDvSbiwSKnH2drjW+zP9iFrz8Fn0r14y8BW Q0yDoIv1xWpTV/gbBHUWb1lly8yQamcsUYlfzdbJSy3nU5SL0I77b+vQFHNpkMZ/LBMv M1MibicApL8w5Le7GPe/b21nDJkPXxQd21fKueVmQ84/yM5vEpy1t2oWCTP6BA/J3keY ap+JHrAO0hTpi454B6H3hFMZdpSLIyWGvi5t/2PMHAugFrkglZmoD1WPgoWWHrvhR6iU 9HKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="WuxIn/lI"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[213.113.123.174]) by smtp.gmail.com with ESMTPSA id v11sm5884443lfb.68.2019.04.07.23.29.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 07 Apr 2019 23:29:28 -0700 (PDT) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Imre Kaloz , Krzysztof Halasa Cc: Linus Walleij , devicetree@vger.kernel.org Subject: [PATCH 27/31 v3] soc: ixp4xx: Add DT bindings for IXP4xx NPE Date: Mon, 8 Apr 2019 08:28:27 +0200 Message-Id: <20190408062831.16422-28-linus.walleij@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190408062831.16422-1-linus.walleij@linaro.org> References: <20190408062831.16422-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds DT bindings for the Intel IXP4xx Network Processing Engine (NPE). These are three firmware-executing units found in the IXP4xx SoC. These bindings use YAML. Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij --- ChangeLog v2->v3: - Rebased on v5.1-rc1 --- ...ntel,ixp4xx-network-processing-engine.yaml | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml -- 2.20.1 Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml b/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml new file mode 100644 index 000000000000..8cb136c376fb --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 Linaro Ltd. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/firmware/intel-ixp4xx-network-processing-engine.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel IXP4xx Network Processing Engine + +maintainers: + - Linus Walleij + +description: | + On the IXP4xx SoCs, the Network Processing Engine (NPE) is a small + processor that can load a firmware to perform offloading of networking + and crypto tasks. It also manages the MDIO bus to the ethernet PHYs + on the IXP4xx platform. All IXP4xx platforms have three NPEs at + consecutive memory locations. They are all included in the same + device node since they are not independent of each other. + +properties: + compatible: + oneOf: + - items: + - const: intel,ixp4xx-network-processing-engine + + reg: + minItems: 3 + maxItems: 3 + items: + - description: NPE0 register range + - description: NPE1 register range + - description: NPE2 register range + +required: + - compatible + - reg + +examples: + - | + npe@c8006000 { + compatible = "intel,ixp4xx-network-processing-engine"; + reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>; + }; From patchwork Mon Apr 8 06:28:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 161928 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3328908jan; Sun, 7 Apr 2019 23:29:35 -0700 (PDT) X-Google-Smtp-Source: APXvYqyTLHVWxAUpHekbBlul6ssuHv+Hsl28M31Qf6AXeOm4HkI23swJStmzi69a3aq629aSh/Lw X-Received: by 2002:a63:9a4a:: with SMTP id e10mr26485861pgo.366.1554704975642; Sun, 07 Apr 2019 23:29:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554704975; cv=none; d=google.com; s=arc-20160816; b=byqrJ8/jnocWCJbvDsH3MVUI1FZjl5LbGOfP9d3E+G9t2SxFAxNV9AEJ7Uftr6CPJk NNl66ueP9dIWWkREXateq3S7SSPfSTTQZaMM+PhXmfAatS3XbUqxjwTyl9vSgawTTjZu lOPARmCM99PPveK4hHW+JoqyAmbdqr28ORVCeMinFlcwM7GLiAaVjebEl25P/yKMqVcL ECnQBSt2+AxpYafy5kVvdyJ/EELerUI+Wyotz45apRxKuTJQZaY27rjWkHDf9yDdxmuj psz9v7QP3RU7Sycmlg8duplSxWYtpKuWdVGMowQihlyUQWD5SayukIpmeTXPiAm54ODM wPJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=e1cGCjrV1atVyw1TmC7u+KdhMh8hZ/hqXnNE39ae6Xw=; b=XRaoDP9GCb6tXOfxmeNMvC/xo5o9ZQPDQQdbtI3cZsT59kX35A7JBWAiYhF2q0lmIN Ytm+FOZXXfZvtvz/rSUWL071UIoLH2jFSR5/lqL1MQCeXW1GzlYvy8bnjOjHaBYC3Qb4 iBigNJbUwUTUpEaKaoDWJZNlyrO+6v1SeFFB4as5P9+U1v5m/aDcfJskcZeeDmjwK5nj E2MQnDrcwq1dL+UWEsF45acLsbKMoSFp5B6pcRItGiXy5Bdcb9NPvYl/wi6US577dkmo ow7NmBD9yCrbNWoK4DoTv5GiHFxaT94gghIZgUfSVbwA4RNmlkkCvlQa5zodIH3YCyx7 4dmg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=albykDCl; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[213.113.123.174]) by smtp.gmail.com with ESMTPSA id v11sm5884443lfb.68.2019.04.07.23.29.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 07 Apr 2019 23:29:31 -0700 (PDT) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Imre Kaloz , Krzysztof Halasa Cc: Linus Walleij , devicetree@vger.kernel.org Subject: [PATCH 29/31 v3] soc: ixp4xx: qmgr: Add DT bindings for IXP4xx qmgr Date: Mon, 8 Apr 2019 08:28:29 +0200 Message-Id: <20190408062831.16422-30-linus.walleij@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190408062831.16422-1-linus.walleij@linaro.org> References: <20190408062831.16422-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds device tree bindings for the Intel IXP4xx AHB Queue Manager. Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij --- ChangeLog v2->v3: - Rebased on v5.1-rc1 - Drop oneOf in compatible, just list items. - Drop description on reg, just use maxItems: 1 - Set '#queue-cells' as required --- .../misc/intel,ixp4xx-queue-manager.yaml | 54 +++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/intel,ixp4xx-queue-manager.yaml -- 2.20.1 diff --git a/Documentation/devicetree/bindings/misc/intel,ixp4xx-queue-manager.yaml b/Documentation/devicetree/bindings/misc/intel,ixp4xx-queue-manager.yaml new file mode 100644 index 000000000000..346707936a2f --- /dev/null +++ b/Documentation/devicetree/bindings/misc/intel,ixp4xx-queue-manager.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 Linaro Ltd. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/misc/intel-ixp4xx-ahb-queue-manager.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel IXP4xx AHB Queue Manager + +maintainers: + - Linus Walleij + +description: | + The IXP4xx AHB Queue Manager maintains queues as circular buffers in + an 8KB embedded SRAM along with hardware pointers. It is used by both + the XScale processor and the NPEs (Network Processing Units) in the + IXP4xx for accelerating queues, especially for networking. Clients pick + queues from the queue manager with foo-queue = <&qmgr N> where the + &qmgr is a phandle to the queue manager and N is the queue resource + number. The queue resources available and their specific purpose + on a certain IXP4xx system will vary. + +properties: + compatible: + items: + - const: intel,ixp4xx-ahb-queue-manager + + reg: + maxItems: 1 + + interrupts: + items: + - description: Interrupt for queues 0-31 + - description: Interrupt for queues 32-63 + + '#queue-cells': + const: 1 + +required: + - compatible + - reg + - interrupts + - '#queue-cells' + +examples: + - | + #include + + qmgr: queue-manager@60000000 { + compatible = "intel,ixp4xx-ahb-queue-manager"; + reg = <0x60000000 0x4000>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>; + #queue-cells = <1>; + };