From patchwork Wed Jun 1 12:31:22 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 102268 Delivered-To: patch@linaro.org Received: by 10.140.92.199 with SMTP id b65csp67085qge; Wed, 1 Jun 2016 05:32:27 -0700 (PDT) X-Received: by 10.36.25.83 with SMTP id b80mr19869244itb.29.1464784347544; Wed, 01 Jun 2016 05:32:27 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id bf10si11644394pab.204.2016.06.01.05.32.27; Wed, 01 Jun 2016 05:32:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757945AbcFAMcY (ORCPT + 30 others); Wed, 1 Jun 2016 08:32:24 -0400 Received: from mout.kundenserver.de ([217.72.192.73]:55976 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750822AbcFAMcW (ORCPT ); Wed, 1 Jun 2016 08:32:22 -0400 Received: from wuerfel.lan. ([78.42.132.4]) by mrelayeu.kundenserver.de (mreue102) with ESMTPA (Nemesis) id 0MMF1Z-1b9Rgn1VNN-007zhr; Wed, 01 Jun 2016 14:31:40 +0200 From: Arnd Bergmann To: Bjorn Helgaas Cc: Heiko Stuebner , Wenrui Li , Doug Anderson , linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Shawn Lin , Thomas Petazzoni , linux-arm-kernel@lists.infradead.org, Jingoo Han , Pratyush Anand , Arnd Bergmann , Hannes Reinecke , Alex Williamson Subject: [PATCH 1/3] pci: introduce read_bridge/write_bridge pci ops Date: Wed, 1 Jun 2016 14:31:22 +0200 Message-Id: <1464784332-3775650-1-git-send-email-arnd@arndb.de> X-Mailer: git-send-email 2.7.0 X-Provags-ID: V03:K0:qPwrFNAHQH1kgefT9t2KiEI77Co0M8t5FZ7Q+a1XHpwd52lZVI/ VyKVnJ17r1OWNzO+MA9rpHO6IXtmgd/EsPyhRRSzozUglkIjCm/t+mrs6eIEcSBkFRnYZma WkP1HjkE3Q4jVVUxzJs209TZ7E1ARLIOgpWPEzszImX0BbiMn/WBlG0yTlURFfCBumiHZDn TD7NPiRpCGONr327BLysA== X-UI-Out-Filterresults: notjunk:1; V01:K0:uPRHu++XmaI=:+g21yn/KiwY0/UShdH1Riz ZkVhvrtDjvZ6ovVUny7t2fHM7gWvEhaz18159iTWAhR7wMtB4SWkA71zFXA/draHfq/r0jvHY XChPFlzmm1luH+tKWCu0izLp36Li9Vx4daEdMjuYzt1qLGta/E6w9+9/+szYB/MN+NQ9+dH+k GUip43z12wqMl7AD9VoFYJcrfstkjpWiJJjZ31QEQSClS77N0lV9Iz+0fGNrkPSwXSuMHBLBJ agqBFo0NtMqzNM0+odGneFTqfQE+BLJjkskW3rOYYFxy8EYZXNiL+G2kpgxfaF8tMIdbDpRRX 81IU6DNlJd+wlDZNuLYv/vhBerX1mUH0MdJrtMft8Y85UOjtm6WHxdbgH+zDdiwmnsa+QMG8G Ckh7HIssdxTVgDfOlDIx+tDOyss5rke9xsEM999V1J02XCX66m/qIpAhZTI5oMulXMiUuGO3f lmklawQdu8GrCuR71/S+Caq3sran/NtFkfkvAFvZITTjwfY7IWRcFtks1ty2r3dDthRf1ykFQ 6DydP+dZ1AwDmtAbn+FTuingrrremQFIIt/Ed8MyCK0KIGrNl001LC6c4xo7r3SIlZariafPk JJpN+dvlLtrIBFWRoc69cTXM3f6FA91S78sjgSJKUxyZT765SG+bUZsHaVUk/A/V6dhi9E+Hx 6TV+ODmOfyHj3iQ8QeVcsUMQFI+QY0BiD6B/+swzVZbaDvjU5/dVqXWAi9DkmiELC/zM= Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org A lot of PCI host bridges require different methods for initiating type 0 and type 1 config space accesses, leading to duplication of code. This adds support for the two different kinds at the pci_ops level, with the newly added map_bridge/read_bridge/write_bridge operations for type 1 accesses. When these are not set, we fall back to the regular map_bus/read/write operations, so all existing drivers keep working, and bridges that have identical operations continue to only require one set. In most cases, a driver will only have to override either map_bridge or read_bridge/write_bridge but not both. Signed-off-by: Arnd Bergmann --- This is slightly refined over what I had in the "Add PCIe driver for Rockchip Soc" thread earlier, but probably not the final version yet, so I'd like to get more feedback on it. In particular, I think it may be useful to add a third set of functions for the config space of devices that are directly attached to the host bridge, as those are sometimes (designware, rcar, mvebu) yet again different from the host bridge itself and from all other devices. On the other hand, that adds further complexity that we may want to leave out of the common code, and I honestly can't seem to come up for a catchy name form the callbacks. drivers/pci/access.c | 35 +++++++++++++++++++++++++++-------- include/linux/pci.h | 3 +++ 2 files changed, 30 insertions(+), 8 deletions(-) -- 2.7.0 diff --git a/drivers/pci/access.c b/drivers/pci/access.c index d11cdbb8fba3..263606ece211 100644 --- a/drivers/pci/access.c +++ b/drivers/pci/access.c @@ -34,9 +34,12 @@ int pci_bus_read_config_##size \ u32 data = 0; \ if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \ raw_spin_lock_irqsave(&pci_lock, flags); \ - res = bus->ops->read(bus, devfn, pos, len, &data); \ + if (!bus->parent == 0 && bus->ops->read_bridge) \ + res = bus->ops->read_bridge(bus, devfn, pos, len, &data); \ + else \ + res = bus->ops->read(bus, devfn, pos, len, &data); \ *value = (type)data; \ - raw_spin_unlock_irqrestore(&pci_lock, flags); \ + raw_spin_unlock_irqrestore(&pci_lock, flags); \ return res; \ } @@ -48,8 +51,11 @@ int pci_bus_write_config_##size \ unsigned long flags; \ if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \ raw_spin_lock_irqsave(&pci_lock, flags); \ - res = bus->ops->write(bus, devfn, pos, len, value); \ - raw_spin_unlock_irqrestore(&pci_lock, flags); \ + if (!bus->parent && bus->ops->write_bridge) \ + res = bus->ops->write_bridge(bus, devfn, pos, len, value);\ + else \ + res = bus->ops->write(bus, devfn, pos, len, value); \ + raw_spin_unlock_irqrestore(&pci_lock, flags); \ return res; \ } @@ -72,7 +78,11 @@ int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, { void __iomem *addr; - addr = bus->ops->map_bus(bus, devfn, where); + if (!bus->parent && bus->ops->map_bridge) + addr = bus->ops->map_bridge(bus, devfn, where); + else + addr = bus->ops->map_bus(bus, devfn, where); + if (!addr) { *val = ~0; return PCIBIOS_DEVICE_NOT_FOUND; @@ -94,7 +104,10 @@ int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, { void __iomem *addr; - addr = bus->ops->map_bus(bus, devfn, where); + if (!bus->parent && bus->ops->map_bridge) + addr = bus->ops->map_bridge(bus, devfn, where); + else + addr = bus->ops->map_bus(bus, devfn, where); if (!addr) return PCIBIOS_DEVICE_NOT_FOUND; @@ -114,7 +127,10 @@ int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, { void __iomem *addr; - addr = bus->ops->map_bus(bus, devfn, where & ~0x3); + if (!bus->parent && bus->ops->map_bridge) + addr = bus->ops->map_bridge(bus, devfn, where); + else + addr = bus->ops->map_bus(bus, devfn, where & ~0x3); if (!addr) { *val = ~0; return PCIBIOS_DEVICE_NOT_FOUND; @@ -135,7 +151,10 @@ int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, void __iomem *addr; u32 mask, tmp; - addr = bus->ops->map_bus(bus, devfn, where & ~0x3); + if (!bus->parent && bus->ops->map_bridge) + addr = bus->ops->map_bridge(bus, devfn, where); + else + addr = bus->ops->map_bus(bus, devfn, where & ~0x3); if (!addr) return PCIBIOS_DEVICE_NOT_FOUND; diff --git a/include/linux/pci.h b/include/linux/pci.h index df41c4645911..2b1d08771b36 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -580,6 +580,9 @@ struct pci_ops { void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); + void __iomem *(*map_bridge)(struct pci_bus *bus, unsigned int devfn, int where); + int (*read_bridge)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); + int (*write_bridge)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); }; /* From patchwork Wed Jun 1 12:31:23 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 102266 Delivered-To: patch@linaro.org Received: by 10.140.92.199 with SMTP id b65csp67533qge; Wed, 1 Jun 2016 05:33:15 -0700 (PDT) X-Received: by 10.98.54.194 with SMTP id d185mr8443266pfa.34.1464784395256; Wed, 01 Jun 2016 05:33:15 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b63si50916091pfa.50.2016.06.01.05.33.15; Wed, 01 Jun 2016 05:33:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758088AbcFAMdG (ORCPT + 30 others); Wed, 1 Jun 2016 08:33:06 -0400 Received: from mout.kundenserver.de ([212.227.17.13]:64321 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757333AbcFAMdD (ORCPT ); Wed, 1 Jun 2016 08:33:03 -0400 Received: from wuerfel.lan. ([78.42.132.4]) by mrelayeu.kundenserver.de (mreue102) with ESMTPA (Nemesis) id 0M2MnE-1bONB51672-00s74U; Wed, 01 Jun 2016 14:32:02 +0200 From: Arnd Bergmann To: Bjorn Helgaas , Jingoo Han , Pratyush Anand Cc: Heiko Stuebner , Wenrui Li , Doug Anderson , linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Shawn Lin , Thomas Petazzoni , linux-arm-kernel@lists.infradead.org, Arnd Bergmann , Gabriele Paoloni , Zhou Wang , Lucas Stach , Jisheng Zhang , Lorenzo Pieralisi , Joao Pinto Subject: [PATCH 2/3] pci: dw: use new config space accessors Date: Wed, 1 Jun 2016 14:31:23 +0200 Message-Id: <1464784332-3775650-2-git-send-email-arnd@arndb.de> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1464784332-3775650-1-git-send-email-arnd@arndb.de> References: <1464784332-3775650-1-git-send-email-arnd@arndb.de> X-Provags-ID: V03:K0:89Phcbs/aUqx8tas5OStzRqGmPQ0Mv+Rs91Tq9NuCTYPwG6HKNN aZCXOrNB68CJDQegcJiZ6ENmAkHZnC5h94x3Fs2UbwbXWuREiblkwdRcARex5hBaKokWby9 WgJq0vDoWJ+Krmik9jUkmXhmVz3wMzqPM/M48AlOpItxk8jfm+J8fTo7VxQvPpuInhbZkOE LCEtaiOZ9XMQveAgAxlng== X-UI-Out-Filterresults: notjunk:1; V01:K0:mbfFkjdDVjU=:PkGBBUKbJDOnZrbKr9eG10 CjsX6QjaJIeqcryRsX/SDIIQfPmUi3s6Ki+3XkKSraPeT4dCk60L93zEjOpZHn+l1GAZf2XHD tGjNGATLpaV+vGLV6YgbnSh6e9FtdTPgu0SvpFWp4Bo45Fl4bjBMKUEfJsgRSeYAbbeplXeoY RK5hU9Wd0vJMFJW032tLG1nM3rsgPaUfKGV/t0kXK88VBmN43Wx0Kt6fMwCZWgi6N9/d2fuch w+sN8USTZ2m8R8qZUGSplIE6msD9PVTIeqt+Fq3AsGeDAXW4nKsHdjL43sU5rxywDNmUVuv3C 9C24rOwHqnIHyC35puRsuPebKUpadRvBp5Mf+yQstn1uFd3zWMe9dwotvl9zjrxDJbqoWfXtA wzVgtv/ntLQC2LFkLnJZDlmOVHKP/r8p+jPio2cH2mmLy1l1lM/3ha7mtlDbBne4m24P6Qahe ZUz46/YTPudBK6gxOp0d5lYzKOIY6N8Cfzifb+Gskqm1YV7yYtWeapPoLloedMbbKhbm+/vCX gSoJa/dnL1XL9JwerUKyOa5SHkQjMYh1ZW3bTLpEctukyf8EPZLlNZCbzpLJCnwIatDlfnGEK NX11JD+rYsBnRK7dTsu37boI98DhpLN5egBCkEZpA0WqjlUrDsAtuRtnMoYaSqTrQqtKPhyAO z4BSorbt9zDyc7WJhZnSUyYQFzORQHdcRvlGNCDhkDFDh5tlj38vwAARcrqIQ264wrnU= Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The PCI core can now use separate callbacks for type 1 config space accesses, so we can simplify the dw_pcie_wr_conf/dw_pcie_rd_conf logic that multiplexes between the two kinds. Signed-off-by: Arnd Bergmann --- drivers/pci/host/pcie-designware.c | 73 +++++++++++++++----------------------- 1 file changed, 28 insertions(+), 45 deletions(-) -- 2.7.0 diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index aafd766546f3..37e16c159719 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -573,13 +573,24 @@ int dw_pcie_host_init(struct pcie_port *pp) return 0; } -static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, +static int dw_pcie_rd_other_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) { int ret, type; u32 busdev, cfg_size; u64 cpu_addr; void __iomem *va_cfg_base; + struct pcie_port *pp = bus->sysdata; + + /* + * If there is no link, then there is no device. + * + * do not read more than one device on the bus directly attached + * to RC's (Virtual Bridge's) DS side. + */ + if (!dw_pcie_link_up(pp) || + (bus->primary == pp->root_bus_nr && PCI_SLOT(devfn) > 0)) + return PCIBIOS_DEVICE_NOT_FOUND; if (pp->ops->rd_other_conf) return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val); @@ -610,13 +621,18 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, return ret; } -static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, +static int dw_pcie_wr_other_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 val) { int ret, type; u32 busdev, cfg_size; u64 cpu_addr; void __iomem *va_cfg_base; + struct pcie_port *pp = bus->sysdata; + + if (!dw_pcie_link_up(pp) || + (bus->primary == pp->root_bus_nr && PCI_SLOT(devfn) > 0)) + return PCIBIOS_DEVICE_NOT_FOUND; if (pp->ops->wr_other_conf) return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val); @@ -647,62 +663,29 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, return ret; } -static int dw_pcie_valid_config(struct pcie_port *pp, - struct pci_bus *bus, int dev) -{ - /* If there is no link, then there is no device */ - if (bus->number != pp->root_bus_nr) { - if (!dw_pcie_link_up(pp)) - return 0; - } - - /* access only one slot on each root port */ - if (bus->number == pp->root_bus_nr && dev > 0) - return 0; - - /* - * do not read more than one device on the bus directly attached - * to RC's (Virtual Bridge's) DS side. - */ - if (bus->primary == pp->root_bus_nr && dev > 0) - return 0; - - return 1; -} - -static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, +static int dw_pcie_rd_bridge_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) { - struct pcie_port *pp = bus->sysdata; - - if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) { - *val = 0xffffffff; + if (PCI_SLOT(devfn) > 0) return PCIBIOS_DEVICE_NOT_FOUND; - } - - if (bus->number == pp->root_bus_nr) - return dw_pcie_rd_own_conf(pp, where, size, val); - return dw_pcie_rd_other_conf(pp, bus, devfn, where, size, val); + return dw_pcie_rd_own_conf(bus->sysdata, where, size, val); } -static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn, +static int dw_pcie_wr_bridge_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 val) { - struct pcie_port *pp = bus->sysdata; - - if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) + if (PCI_SLOT(devfn) > 0) return PCIBIOS_DEVICE_NOT_FOUND; - if (bus->number == pp->root_bus_nr) - return dw_pcie_wr_own_conf(pp, where, size, val); - - return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val); + return dw_pcie_wr_own_conf(bus->sysdata, where, size, val); } static struct pci_ops dw_pcie_ops = { - .read = dw_pcie_rd_conf, - .write = dw_pcie_wr_conf, + .read_bridge = dw_pcie_rd_bridge_conf, + .write_bridge = dw_pcie_wr_bridge_conf, + .read = dw_pcie_rd_other_conf, + .write = dw_pcie_wr_other_conf, }; void dw_pcie_setup_rc(struct pcie_port *pp) From patchwork Wed Jun 1 12:31:24 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 102267 Delivered-To: patch@linaro.org Received: by 10.140.92.199 with SMTP id b65csp67375qge; Wed, 1 Jun 2016 05:32:57 -0700 (PDT) X-Received: by 10.98.103.7 with SMTP id b7mr8042629pfc.19.1464784377651; Wed, 01 Jun 2016 05:32:57 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c196si50942660pfc.233.2016.06.01.05.32.57; Wed, 01 Jun 2016 05:32:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758044AbcFAMcx (ORCPT + 30 others); Wed, 1 Jun 2016 08:32:53 -0400 Received: from mout.kundenserver.de ([217.72.192.73]:53539 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757333AbcFAMcv (ORCPT ); Wed, 1 Jun 2016 08:32:51 -0400 Received: from wuerfel.lan. ([78.42.132.4]) by mrelayeu.kundenserver.de (mreue102) with ESMTPA (Nemesis) id 0MRknR-1axKjc3cKH-00Sz0R; Wed, 01 Jun 2016 14:32:14 +0200 From: Arnd Bergmann To: Bjorn Helgaas , Thomas Petazzoni , Jason Cooper Cc: Heiko Stuebner , Wenrui Li , Doug Anderson , linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Shawn Lin , linux-arm-kernel@lists.infradead.org, Jingoo Han , Pratyush Anand , Arnd Bergmann , Russell King , Jisheng Zhang Subject: [PATCH 3/3] pci: mvebu: use bridge config operations Date: Wed, 1 Jun 2016 14:31:24 +0200 Message-Id: <1464784332-3775650-3-git-send-email-arnd@arndb.de> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1464784332-3775650-1-git-send-email-arnd@arndb.de> References: <1464784332-3775650-1-git-send-email-arnd@arndb.de> X-Provags-ID: V03:K0:bG2N/SDSJosu73yUxgDBLxMJVicpA51P8eiQcfVXJyV4pD1mx9P weYnEdz0zEE6h7pG9e6Zb8mt3ISqhnSyQD5R1cesiPCNfb+wv1JbQ15TNoNoUeXyKZ0f69P X8zAEKO+QQIVqH9sw0cEKYqnvMItE8Lm5XsZzEmx7eQikbqBUSArbrXt3W2TBRd1p0aJTVz N4mFXACKmiiOGKGG56IAQ== X-UI-Out-Filterresults: notjunk:1; V01:K0:bfZA+ii+gO0=:SjSKjJCLbQ3B+0pbqyXs/2 mYI/Dhbv0Ksoug+GOgfY0UumPLncIDJciWxJW0GCdjQh/a9P9PcsPNHMVZXBohUAA+NISwe2C /HkMrU/Q9ZvfeYXna9jV5zH+7AQB0DgqsSODYkp4Yhk92+RO93It/0E+q6wVXEP6Qk4/Q+lcM bguUHaneZI2kXg2h5pn/U8NqGC/ElHVbCqZTeTHxCzGspo4Z1zgusz9iyOtQDIjgKsWRUOZu4 VpseqYTlFi/J2wxDxE+3dhTK9p04OJNXVJbsHhFgTmY8XCkGfjwfJ5TIu1M8WK5uLSgpuvuSc FQ97qLwjCDudbQC+qqot2QtZQydFoxShRLyeHhPCbormywS16M9i9bJmf/M/sLmByAJXxPIOK IUZ8yYtlNPX6lZTgg5/hAvp+53xRSrsmNLs8xETIbICRoxrnA6CccerXOju+K48J+/bu8WBOi pbBeIiVbLnINeaoTKvG7tWAG8opMAizg8TwD+hPlGJ8RzOIvbbA6AyMx0YQ+bJgFyaN5OPZLq O5vYXIcTG16R5gj8asGPYX6dG8T5z5oe0hN9doH4VPDqFrcdg/FVN3Dkg4ZfZWvmTzU+81/i5 uEQaRHmYFduAxT3lYwVj3WR20nBiKi5M5AP5SWktPXXjkQDPlN5p8oeEsXWtP36401bfJFSQe +6oGMIKC1swGo0Ol6zF/6e+hlAawJDgaEb/clO5wTeQj8+D2u7LRsSOf43XtrxN6PFg0= Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This converts the pci-mvebu host driver to use the newly added pci_ops callbacks for handling the host config space. After support for the emulator root bridge is removed, the normal operations can use pci_generic_config_read/pci_generic_config_write and we just need to provide a map_bus callback. Signed-off-by: Arnd Bergmann --- drivers/pci/host/pci-mvebu.c | 158 ++++++++++++------------------------------- 1 file changed, 42 insertions(+), 116 deletions(-) -- 2.7.0 diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c index 6b451df6502c..9dff177e32eb 100644 --- a/drivers/pci/host/pci-mvebu.c +++ b/drivers/pci/host/pci-mvebu.c @@ -155,6 +155,11 @@ struct mvebu_pcie_port { u32 saved_pcie_stat; }; +static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys) +{ + return sys->private_data; +} + static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg) { writel(val, port->base + reg); @@ -273,56 +278,6 @@ static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port) mvebu_writel(port, mask, PCIE_MASK_OFF); } -static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port, - struct pci_bus *bus, - u32 devfn, int where, int size, u32 *val) -{ - void __iomem *conf_data = port->base + PCIE_CONF_DATA_OFF; - - mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where), - PCIE_CONF_ADDR_OFF); - - switch (size) { - case 1: - *val = readb_relaxed(conf_data + (where & 3)); - break; - case 2: - *val = readw_relaxed(conf_data + (where & 2)); - break; - case 4: - *val = readl_relaxed(conf_data); - break; - } - - return PCIBIOS_SUCCESSFUL; -} - -static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port, - struct pci_bus *bus, - u32 devfn, int where, int size, u32 val) -{ - void __iomem *conf_data = port->base + PCIE_CONF_DATA_OFF; - - mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where), - PCIE_CONF_ADDR_OFF); - - switch (size) { - case 1: - writeb(val, conf_data + (where & 3)); - break; - case 2: - writew(val, conf_data + (where & 2)); - break; - case 4: - writel(val, conf_data); - break; - default: - return PCIBIOS_BAD_REGISTER_NUMBER; - } - - return PCIBIOS_SUCCESSFUL; -} - /* * Remove windows, starting from the largest ones to the smallest * ones. @@ -624,6 +579,19 @@ static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port, return PCIBIOS_SUCCESSFUL; } +static int mvebu_pcie_rd_bridge_conf(struct pci_bus *bus, u32 devfn, int where, + int size, u32 *val) +{ + struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata); + struct mvebu_pcie_port *port; + + for (port = pcie->ports; port < &pcie->ports[pcie->nports]; port++) + if (port->devfn == devfn) + return mvebu_sw_pci_bridge_read(port, where, size, val); + + return PCIBIOS_DEVICE_NOT_FOUND; +} + /* Write to the PCI-to-PCI bridge configuration space */ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port, unsigned int where, int size, u32 value) @@ -750,90 +718,48 @@ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port, return PCIBIOS_SUCCESSFUL; } -static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys) -{ - return sys->private_data; -} - -static struct mvebu_pcie_port *mvebu_pcie_find_port(struct mvebu_pcie *pcie, - struct pci_bus *bus, - int devfn) -{ - int i; - - for (i = 0; i < pcie->nports; i++) { - struct mvebu_pcie_port *port = &pcie->ports[i]; - - if (bus->number == 0 && port->devfn == devfn) - return port; - if (bus->number != 0 && - bus->number >= port->bridge.secondary_bus && - bus->number <= port->bridge.subordinate_bus) - return port; - } - - return NULL; -} - -/* PCI configuration space write function */ -static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn, - int where, int size, u32 val) +static int mvebu_pcie_wr_bridge_conf(struct pci_bus *bus, u32 devfn, + int where, int size, u32 val) { struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata); struct mvebu_pcie_port *port; - int ret; - - port = mvebu_pcie_find_port(pcie, bus, devfn); - if (!port) - return PCIBIOS_DEVICE_NOT_FOUND; - - /* Access the emulated PCI-to-PCI bridge */ - if (bus->number == 0) - return mvebu_sw_pci_bridge_write(port, where, size, val); - - if (!mvebu_pcie_link_up(port)) - return PCIBIOS_DEVICE_NOT_FOUND; - /* Access the real PCIe interface */ - ret = mvebu_pcie_hw_wr_conf(port, bus, devfn, - where, size, val); + for (port = pcie->ports; port < &pcie->ports[pcie->nports]; port++) + if (port->devfn == devfn) + return mvebu_sw_pci_bridge_write(port, where, size, val); - return ret; + return PCIBIOS_DEVICE_NOT_FOUND; } -/* PCI configuration space read function */ -static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, - int size, u32 *val) +/* find normal config registers */ +static void __iomem *mvebu_pcie_map_conf(struct pci_bus *bus, u32 devfn, int where) { struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata); struct mvebu_pcie_port *port; - int ret; + u32 addr; - port = mvebu_pcie_find_port(pcie, bus, devfn); - if (!port) { - *val = 0xffffffff; - return PCIBIOS_DEVICE_NOT_FOUND; - } + for (port = pcie->ports; port < &pcie->ports[pcie->nports]; port++) { + if (bus->number >= port->bridge.secondary_bus && + bus->number <= port->bridge.subordinate_bus) { + if (!mvebu_pcie_link_up(port)) + return NULL; - /* Access the emulated PCI-to-PCI bridge */ - if (bus->number == 0) - return mvebu_sw_pci_bridge_read(port, where, size, val); + addr = PCIE_CONF_ADDR(bus->number, devfn, where); + mvebu_writel(port, addr, PCIE_CONF_ADDR_OFF); - if (!mvebu_pcie_link_up(port)) { - *val = 0xffffffff; - return PCIBIOS_DEVICE_NOT_FOUND; + return port->base + PCIE_CONF_DATA_OFF + (where & 3); + } } - /* Access the real PCIe interface */ - ret = mvebu_pcie_hw_rd_conf(port, bus, devfn, - where, size, val); - - return ret; + return NULL; } static struct pci_ops mvebu_pcie_ops = { - .read = mvebu_pcie_rd_conf, - .write = mvebu_pcie_wr_conf, + .read_bridge = mvebu_pcie_rd_bridge_conf, + .write_bridge = mvebu_pcie_wr_bridge_conf, + .map_bus = mvebu_pcie_map_conf, + .read = pci_generic_config_read, + .write = pci_generic_config_write, }; static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys)