From patchwork Thu Apr 4 11:04:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 161768 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1450395jan; Thu, 4 Apr 2019 04:04:24 -0700 (PDT) X-Google-Smtp-Source: APXvYqxgus4xUM9efHxhwDzT8Cz8FScXETJ7m+WGymW9TjIdI3ZzYYS3eQSFGlbbQUoGY4xrxAMy X-Received: by 2002:a50:897b:: with SMTP id f56mr3441200edf.144.1554375864133; Thu, 04 Apr 2019 04:04:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554375864; cv=none; d=google.com; s=arc-20160816; b=NmASWt0ZgBSp2DoSaDrnmA6jCfGtOr8JVgmyxpmCwaE7W76UXSr7yx9oRDItHkouYq oEUbpWCXbyF3g3Ei431TWdXMhQlWDox3XrNOk8y1sGZUhxh5ZjRxMDwG7ye5++is0pMa Jje0YbSQmNskE2oBpeUj/MS4V2EzJM5xCqUpjoIc3ar4t8Gv1XnqrMAoOSlPzW/zbQQe kJXL8fq+VyOa+xp3Mhg+G121vEgjA9fpxIB88CbK/zH+zk8tx324HJm9gAmUApvMkIPx 8oXgeSkhm5I3PJJz81P774QPRk4upDKWsB+qkJj3ZoD2nIpAGD8pnIivdFtlYvdoPo+f XroQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:mime-version :content-transfer-encoding:content-language:accept-language :in-reply-to:references:message-id:date:thread-index:thread-topic:cc :to:from:dkim-signature; bh=2GERol+73EyH685QwhsCKospu1NMeBytmRUzh0SQYcA=; b=lP6UZWw9ZdrBSnqdH983b4tuTU5aPYla2UJgsWOZ5KbBudOgxr5LpzgQU1dKg93A76 d4thuBsGi9O1jt44pRwNpiUehukbmTDzxzNMKe6YZIhZ6y5kbiujmm3wFNuvUUl3Bkvl UQ94UCqMoLMkzH6yuKiBqDGmeaMqS0zfW9fR+DrwD0dujaA4ndNx1x+HBquYUCXQsR9p VYHojTXBBs7tq7QwskKsBEyoqhV8QM1gs/Yhs5lQVUZsqor9gE1zDbc5y3iHahZEWltC bIfqY0DJ3xnrxeKA2gg7MVJpr4jBQXAFy/QwG4BuZJi8ML3MWZLeTjIf2ZfUH80Os/tQ yeow== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@nxp.com header.s=selector1 header.b=dSaayGkX; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. [92.243.14.124]) by mx.google.com with ESMTP id m23si4846957eja.71.2019.04.04.04.04.23; Thu, 04 Apr 2019 04:04:24 -0700 (PDT) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; dkim=fail header.i=@nxp.com header.s=selector1 header.b=dSaayGkX; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 4A5F07CE2; Thu, 4 Apr 2019 13:04:22 +0200 (CEST) Received: from EUR01-DB5-obe.outbound.protection.outlook.com (mail-eopbgr150044.outbound.protection.outlook.com [40.107.15.44]) by dpdk.org (Postfix) with ESMTP id 69F0158EC for ; Thu, 4 Apr 2019 13:04:20 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=2GERol+73EyH685QwhsCKospu1NMeBytmRUzh0SQYcA=; b=dSaayGkXhvaOQEcxTfahcs+UhpSUbW8dWbh0sPHXkM4cxv0m7EbwQnURYBqq8JRgsJlq+QgkaAI3fUMd2PEqmxKK8ANTjCKvfwVYFuwO1OVjTo6ZVWQlqXW3b9OyqSUlY755iyGywMM0UHPIeM//PW8Q9SDGV1i89e2/nIzhuTU= Received: from VI1PR0401MB2541.eurprd04.prod.outlook.com (10.168.65.19) by VI1PR0401MB2543.eurprd04.prod.outlook.com (10.168.65.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1750.19; Thu, 4 Apr 2019 11:04:19 +0000 Received: from VI1PR0401MB2541.eurprd04.prod.outlook.com ([fe80::18e3:39b6:c61d:3f18]) by VI1PR0401MB2541.eurprd04.prod.outlook.com ([fe80::18e3:39b6:c61d:3f18%12]) with mapi id 15.20.1750.017; Thu, 4 Apr 2019 11:04:19 +0000 From: Hemant Agrawal To: "dev@dpdk.org" CC: "thomas@monjalon.net" , Shreyansh Jain Thread-Topic: [PATCH v2 1/7] config: increase the num of rawdev to be 64 Thread-Index: AQHU6tYmWQEk7/xkokWu9gV/5JcGxQ== Date: Thu, 4 Apr 2019 11:04:19 +0000 Message-ID: <20190404110215.14410-1-hemant.agrawal@nxp.com> References: <20190326121610.28024-1-hemant.agrawal@nxp.com> In-Reply-To: <20190326121610.28024-1-hemant.agrawal@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [92.120.1.72] x-mailer: git-send-email 2.17.1 x-clientproxiedby: BMXPR01CA0041.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:c::27) To VI1PR0401MB2541.eurprd04.prod.outlook.com (2603:10a6:800:56::19) authentication-results: spf=none (sender IP is ) smtp.mailfrom=hemant.agrawal@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 4b3d7fa8-705b-434d-0b40-08d6b8ed48c7 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(5600139)(711020)(4605104)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7193020); SRVR:VI1PR0401MB2543; x-ms-traffictypediagnostic: VI1PR0401MB2543: x-microsoft-antispam-prvs: x-forefront-prvs: 0997523C40 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(136003)(376002)(346002)(396003)(366004)(39860400002)(199004)(189003)(6916009)(6486002)(53936002)(50226002)(2906002)(8936002)(2616005)(86362001)(54906003)(7736002)(11346002)(44832011)(486006)(316002)(8676002)(6512007)(446003)(1076003)(66066001)(5640700003)(99286004)(3846002)(6116002)(478600001)(386003)(5660300002)(26005)(81166006)(25786009)(1730700003)(76176011)(68736007)(102836004)(476003)(14454004)(4326008)(71200400001)(4744005)(105586002)(81156014)(97736004)(256004)(14444005)(2501003)(186003)(2351001)(106356001)(6436002)(305945005)(71190400001)(52116002)(6506007)(36756003); DIR:OUT; SFP:1101; SCL:1; SRVR:VI1PR0401MB2543; H:VI1PR0401MB2541.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: TkzrvrWKdGsVfalBUUS8+8kAZKK3VJ1b+3clHjWCTlNZnVEr4l9YolBjrzoh6B/trndhF7jyGQOSEcHPfUC3mZrGdE/jO2e7dibiJeSVr9NGv/ppCRpkbh8Gpa07ro4d3I56mUz7BlUVjypAWAJm8LMXe7i1sJ2eMK7hap55n7C4T3j7gtokG9SLXv1q5H/eKxxSacjT6iU3I/2ntb3A5PHyPvR9mpvNieMuzhYOtLN4EjYHj+IaQDdY1BFE/DPYqi9us5AstmuTRC9XLIx/Zum2IXolbVnHBEWYv7jmiwpccFq7LTDuB8+11x5znFswQtjU81Zx/ZAYpLB5FAal8QICIWUAiNUiZ3u1pvMwbewRGW8h2Hbs6D9UDuye1Hicyn6golHqBmur0/kfB7ZndcUkpgB0UdkBMTpd5koAQXk= MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4b3d7fa8-705b-434d-0b40-08d6b8ed48c7 X-MS-Exchange-CrossTenant-originalarrivaltime: 04 Apr 2019 11:04:19.3793 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0401MB2543 Subject: [dpdk-dev] [PATCH v2 1/7] config: increase the num of rawdev to be 64 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The current value is 10, which is not sufficient for many use-cases. e.g. NXP LX2 with raw qdma devices can use 32-48 raw devices in some use-cases. So, making it to 64 to cover various cases. Signed-off-by: Hemant Agrawal --- config/common_base | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.1 diff --git a/config/common_base b/config/common_base index a0a9fe0c7..1e55c8076 100644 --- a/config/common_base +++ b/config/common_base @@ -709,7 +709,7 @@ CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV=n # EXPERIMENTAL: API may change without prior notice # CONFIG_RTE_LIBRTE_RAWDEV=y -CONFIG_RTE_RAWDEV_MAX_DEVS=10 +CONFIG_RTE_RAWDEV_MAX_DEVS=64 CONFIG_RTE_LIBRTE_PMD_SKELETON_RAWDEV=y # From patchwork Thu Apr 4 11:04:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 161769 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1450562jan; Thu, 4 Apr 2019 04:04:33 -0700 (PDT) X-Google-Smtp-Source: APXvYqwgmNKEIZ9GUyBwpcANmcMmNsaFmPj7Ewp3oPxOyTEvlcxjyoEgeUXDCRgK7Z6wcn1bpTHb X-Received: by 2002:aa7:cf18:: with SMTP id a24mr3345311edy.215.1554375873032; Thu, 04 Apr 2019 04:04:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554375873; cv=none; d=google.com; s=arc-20160816; b=j+/oqPA6Kn7MAxR6uCyPc68nkojhrxGYtfpuZBhNPE8K/3FxPg7qwsah74g19IBclj yfRYyxZpNRbnPDYDPHWcaF4mhun2r+LWcCyTcfVDWxjIHddgdSR1XRmRm+x0Hs5KB5wV irlBk6DI0d5roTpEsOn7N1tHfwDv8HupMgjS2JfutDCup4kU0Nydnf+Ydi8d064U9OmT vTqe3d/JMK77aGevuDfP+pefIqnnOmjbYel+62jFcw1Gf3JpUhIxRgzF8oW+NPLc5EPN tkq8h9HXTzm2arUkaRHAC0RW9NUlW/Q2oVXoaNMoQyUsP/uPN9EzYk6mk3d2UCbj0/H/ 2JoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:mime-version :content-transfer-encoding:content-language:accept-language :in-reply-to:references:message-id:date:thread-index:thread-topic:cc :to:from:dkim-signature; bh=6mlpZpPbew5OqixRCrTqt29MLaL7YjdUMaK37ZdGSgg=; b=IYKnTw9wlniOXLA6PxYNKxv98c4hH60qXP/Akl6aKDzwRwmAl5JxyQlreLRNJF7ibr H22xqRNfoEu5TCWcudC+LHF7MYCiw6EMqF+zmQ6EnJQ5bnErU63LlpSdXZp5I+dlRBav osA9xeNsy5jbro6R0BL/dC50RgX+N1ZmEl5fP03leHYyWZmjUpefeqofxkCa4Rhi8TMK CBuJEx/kc8oC3kwShECWVX5sX/KtXlSp6hT69XqF7hfYv6MJBR4SPHW7y/osm0ZeUxfz wDEg3/SQHMatyvyjb94Gwj5p4JG4ZS5+FYsAXgqsDHkcsqgO34GoxA1jppuQLZw4qDJ5 ZF5Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@nxp.com header.s=selector1 header.b=hkbxqGP1; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. 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bh=6mlpZpPbew5OqixRCrTqt29MLaL7YjdUMaK37ZdGSgg=; b=hkbxqGP13RWZ+zPsMtU5JtX/e1GREsDYMcuSP3RuDDBXk5tiCzQY44LBiaTJ1Zfo04yNNbHbrDEbSvoj+pvg42aTNTyvhSoHtiYautDptxqd2pbrJSOUB2MUUJQRQS2pLtiSm5OF1Uy/JpHx86j1Xz3XtyjBo/Bk4PTIufQ2Gg4= Received: from VI1PR0401MB2541.eurprd04.prod.outlook.com (10.168.65.19) by VI1PR0401MB2543.eurprd04.prod.outlook.com (10.168.65.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1750.19; Thu, 4 Apr 2019 11:04:20 +0000 Received: from VI1PR0401MB2541.eurprd04.prod.outlook.com ([fe80::18e3:39b6:c61d:3f18]) by VI1PR0401MB2541.eurprd04.prod.outlook.com ([fe80::18e3:39b6:c61d:3f18%12]) with mapi id 15.20.1750.017; Thu, 4 Apr 2019 11:04:20 +0000 From: Hemant Agrawal To: "dev@dpdk.org" CC: "thomas@monjalon.net" , Shreyansh Jain Thread-Topic: [PATCH v2 2/7] raw/dpaa2_qdma: remove experimental tag from APIs Thread-Index: AQHU6tYnTpO9Tls1XUSftQ4xqxAnog== Date: Thu, 4 Apr 2019 11:04:20 +0000 Message-ID: <20190404110215.14410-2-hemant.agrawal@nxp.com> References: <20190326121610.28024-1-hemant.agrawal@nxp.com> <20190404110215.14410-1-hemant.agrawal@nxp.com> In-Reply-To: <20190404110215.14410-1-hemant.agrawal@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [92.120.1.72] x-mailer: git-send-email 2.17.1 x-clientproxiedby: BMXPR01CA0041.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:c::27) To VI1PR0401MB2541.eurprd04.prod.outlook.com (2603:10a6:800:56::19) authentication-results: spf=none (sender IP is ) smtp.mailfrom=hemant.agrawal@nxp.com; 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DIR:OUT; SFP:1101; SCL:1; SRVR:VI1PR0401MB2543; H:VI1PR0401MB2541.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: /h9foFV1Ch/f8/cn5cnsqqst9ez/q00ITEbEn8cKjgzZkXz9Wb0oG81tBOAbVb0zPGYhnLuC9XQOVh4V43vAY2FD3cws4Hf1HvhvqF2YMBiIKG9Y9DE229D6KmN6ULzMz0Q0GdZ5TQ02mKgBpYw7frIe74CNRykmUdHNvz80YKN1gXDeGvwofg5rIkiKW69XcvE5Ux+pUfyu4nDRbezb2pW2BYX9UXGzJrnFMcn712PrMHWSQ+XD6BTPykAsC44J76hltX+ZbdkWOQdabnbAUTPjqW8dlkR3hh8sr0u+lzuo39w10HlZuAuLVWr3hXTJKCO4jN9lC33NcDDNLaLdMHwOQA3mbTh1sjG10KfOIlKj7gZvrp7O2Wg5HXqSeyaVWDuzJW3n1n2ClprmiGfRzAGVgMDqYfLsOPvfH8OB3RY= MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: c12b2e33-b94e-453e-41b8-08d6b8ed49ae X-MS-Exchange-CrossTenant-originalarrivaltime: 04 Apr 2019 11:04:20.8175 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0401MB2543 Subject: [dpdk-dev] [PATCH v2 2/7] raw/dpaa2_qdma: remove experimental tag from APIs X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" These APIs has been in the DPDK for few release now. This patch removes the experimental tags for the APIs. Signed-off-by: Hemant Agrawal --- drivers/raw/dpaa2_qdma/dpaa2_qdma.c | 20 ++++++------- drivers/raw/dpaa2_qdma/rte_pmd_dpaa2_qdma.h | 28 +++++++++---------- .../dpaa2_qdma/rte_pmd_dpaa2_qdma_version.map | 2 +- 3 files changed, 25 insertions(+), 25 deletions(-) -- 2.17.1 diff --git a/drivers/raw/dpaa2_qdma/dpaa2_qdma.c b/drivers/raw/dpaa2_qdma/dpaa2_qdma.c index 60621eb85..afa5e5a3d 100644 --- a/drivers/raw/dpaa2_qdma/dpaa2_qdma.c +++ b/drivers/raw/dpaa2_qdma/dpaa2_qdma.c @@ -143,7 +143,7 @@ put_hw_queue(struct qdma_hw_queue *queue) } } -int __rte_experimental +int rte_qdma_init(void) { DPAA2_QDMA_FUNC_TRACE(); @@ -153,7 +153,7 @@ rte_qdma_init(void) return 0; } -void __rte_experimental +void rte_qdma_attr_get(struct rte_qdma_attr *qdma_attr) { DPAA2_QDMA_FUNC_TRACE(); @@ -161,7 +161,7 @@ rte_qdma_attr_get(struct rte_qdma_attr *qdma_attr) qdma_attr->num_hw_queues = qdma_dev.num_hw_queues; } -int __rte_experimental +int rte_qdma_reset(void) { struct qdma_hw_queue *queue; @@ -215,7 +215,7 @@ rte_qdma_reset(void) return 0; } -int __rte_experimental +int rte_qdma_configure(struct rte_qdma_config *qdma_config) { int ret; @@ -274,7 +274,7 @@ rte_qdma_configure(struct rte_qdma_config *qdma_config) return 0; } -int __rte_experimental +int rte_qdma_start(void) { DPAA2_QDMA_FUNC_TRACE(); @@ -284,7 +284,7 @@ rte_qdma_start(void) return 0; } -int __rte_experimental +int rte_qdma_vq_create(uint32_t lcore_id, uint32_t flags) { char ring_name[32]; @@ -677,7 +677,7 @@ rte_qdma_vq_dequeue(uint16_t vq_id) return job; } -void __rte_experimental +void rte_qdma_vq_stats(uint16_t vq_id, struct rte_qdma_vq_stats *vq_status) { @@ -695,7 +695,7 @@ rte_qdma_vq_stats(uint16_t vq_id, } } -int __rte_experimental +int rte_qdma_vq_destroy(uint16_t vq_id) { struct qdma_virt_queue *qdma_vq = &qdma_vqs[vq_id]; @@ -724,7 +724,7 @@ rte_qdma_vq_destroy(uint16_t vq_id) return 0; } -void __rte_experimental +void rte_qdma_stop(void) { DPAA2_QDMA_FUNC_TRACE(); @@ -732,7 +732,7 @@ rte_qdma_stop(void) qdma_dev.state = 0; } -void __rte_experimental +void rte_qdma_destroy(void) { DPAA2_QDMA_FUNC_TRACE(); diff --git a/drivers/raw/dpaa2_qdma/rte_pmd_dpaa2_qdma.h b/drivers/raw/dpaa2_qdma/rte_pmd_dpaa2_qdma.h index 17fffcb74..c9697b4d7 100644 --- a/drivers/raw/dpaa2_qdma/rte_pmd_dpaa2_qdma.h +++ b/drivers/raw/dpaa2_qdma/rte_pmd_dpaa2_qdma.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright 2018 NXP + * Copyright 2018-2019 NXP */ #ifndef __RTE_PMD_DPAA2_QDMA_H__ @@ -113,7 +113,7 @@ struct rte_qdma_job { * - 0: Success. * - <0: Error code. */ -int __rte_experimental +int rte_qdma_init(void); /** @@ -122,7 +122,7 @@ rte_qdma_init(void); * @param qdma_attr * QDMA attributes providing total number of hw queues etc. */ -void __rte_experimental +void rte_qdma_attr_get(struct rte_qdma_attr *qdma_attr); /** @@ -134,7 +134,7 @@ rte_qdma_attr_get(struct rte_qdma_attr *qdma_attr); * - 0: Success. * - <0: Error code. */ -int __rte_experimental +int rte_qdma_reset(void); /** @@ -144,7 +144,7 @@ rte_qdma_reset(void); * - 0: Success. * - <0: Error code. */ -int __rte_experimental +int rte_qdma_configure(struct rte_qdma_config *qdma_config); /** @@ -154,7 +154,7 @@ rte_qdma_configure(struct rte_qdma_config *qdma_config); * - 0: Success. * - <0: Error code. */ -int __rte_experimental +int rte_qdma_start(void); /** @@ -171,7 +171,7 @@ rte_qdma_start(void); * - >= 0: Virtual queue ID. * - <0: Error code. */ -int __rte_experimental +int rte_qdma_vq_create(uint32_t lcore_id, uint32_t flags); /** @@ -190,7 +190,7 @@ rte_qdma_vq_create(uint32_t lcore_id, uint32_t flags); * - >=0: Number of jobs successfully submitted * - <0: Error code. */ -int __rte_experimental +int rte_qdma_vq_enqueue_multi(uint16_t vq_id, struct rte_qdma_job **job, uint16_t nb_jobs); @@ -209,7 +209,7 @@ rte_qdma_vq_enqueue_multi(uint16_t vq_id, * - >=0: Number of jobs successfully submitted * - <0: Error code. */ -int __rte_experimental +int rte_qdma_vq_enqueue(uint16_t vq_id, struct rte_qdma_job *job); @@ -227,7 +227,7 @@ rte_qdma_vq_enqueue(uint16_t vq_id, * @returns * Number of jobs actually dequeued. */ -int __rte_experimental +int rte_qdma_vq_dequeue_multi(uint16_t vq_id, struct rte_qdma_job **job, uint16_t nb_jobs); @@ -252,7 +252,7 @@ rte_qdma_vq_dequeue(uint16_t vq_id); * @param vq_stats * VQ statistics structure which will be filled in by the driver. */ -void __rte_experimental +void rte_qdma_vq_stats(uint16_t vq_id, struct rte_qdma_vq_stats *vq_stats); @@ -268,19 +268,19 @@ rte_qdma_vq_stats(uint16_t vq_id, * - 0: Success. * - <0: Error code. */ -int __rte_experimental +int rte_qdma_vq_destroy(uint16_t vq_id); /** * Stop QDMA device. */ -void __rte_experimental +void rte_qdma_stop(void); /** * Destroy the QDMA device. */ -void __rte_experimental +void rte_qdma_destroy(void); #endif /* __RTE_PMD_DPAA2_QDMA_H__*/ diff --git a/drivers/raw/dpaa2_qdma/rte_pmd_dpaa2_qdma_version.map b/drivers/raw/dpaa2_qdma/rte_pmd_dpaa2_qdma_version.map index fe42a2276..d16a136fc 100644 --- a/drivers/raw/dpaa2_qdma/rte_pmd_dpaa2_qdma_version.map +++ b/drivers/raw/dpaa2_qdma/rte_pmd_dpaa2_qdma_version.map @@ -1,4 +1,4 @@ -EXPERIMENTAL { +DPDK_19.05 { global: rte_qdma_attr_get; From patchwork Thu Apr 4 11:04:22 2019 Content-Type: text/plain; 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DIR:OUT; SFP:1101; SCL:1; SRVR:VI1PR0401MB2543; H:VI1PR0401MB2541.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: wnvdOO8q+eFOu4w6Ye63DjAtYXv//1eU40ibtg9etLc4+TJsT4gY4KPybT4LzE4/NuwwSdCBDHnRYvClnF+kjg02Ev1d4ru8eV7jW2fDkxLDrzbLGfF1dRflAnDhUPn6WRiqjTPzkBpSIDAFrmakS2Ar0ZuXJCjaMTohzTv7PBeRO7Hc4k8rdhDAXovipyoPWtZis9TpauGkxhc2YUdmrCf+FLvfXIJd4NtBtnLq4z5bj/FCLzHG+cFBoUIjOOmrCpgdpYe8zERoU4ImKMD2F2IvC0dOZx/3ggOFpKN6QsDMedfowhGaErohwZvkS46BDUpt1SJTVxKO7l7ClznI7TcXbkqBTgiwIEf81wpBElc9tgdTvRski3WCyraRVzl4Ismk0sNI30YO2sksOrhqFsBZykd1sj9yi+Ybe+bDMyU= MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7a1c54a1-44f9-4472-385c-08d6b8ed4ab7 X-MS-Exchange-CrossTenant-originalarrivaltime: 04 Apr 2019 11:04:22.4349 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0401MB2543 Subject: [dpdk-dev] [PATCH v2 3/7] raw/dpaa2_qdma: fix to support multiprocess execution X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shreyansh Jain Fixes: c22fab9a6c34 ("raw/dpaa2_qdma: support configuration APIs") Cc: nipun.gupta@nxp.com Cc: stable@dpdk.org Signed-off-by: Shreyansh Jain --- drivers/raw/dpaa2_qdma/dpaa2_qdma.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) -- 2.17.1 diff --git a/drivers/raw/dpaa2_qdma/dpaa2_qdma.c b/drivers/raw/dpaa2_qdma/dpaa2_qdma.c index afa5e5a3d..88c11a3d2 100644 --- a/drivers/raw/dpaa2_qdma/dpaa2_qdma.c +++ b/drivers/raw/dpaa2_qdma/dpaa2_qdma.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright 2018 NXP + * Copyright 2018-2019 NXP */ #include @@ -219,6 +219,7 @@ int rte_qdma_configure(struct rte_qdma_config *qdma_config) { int ret; + char fle_pool_name[32]; /* RTE_MEMZONE_NAMESIZE = 32 */ DPAA2_QDMA_FUNC_TRACE(); @@ -258,8 +259,12 @@ rte_qdma_configure(struct rte_qdma_config *qdma_config) } qdma_dev.max_vqs = qdma_config->max_vqs; - /* Allocate FLE pool */ - qdma_dev.fle_pool = rte_mempool_create("qdma_fle_pool", + /* Allocate FLE pool; just append PID so that in case of + * multiprocess, the pool's don't collide. + */ + snprintf(fle_pool_name, sizeof(fle_pool_name), "qdma_fle_pool%u", + getpid()); + qdma_dev.fle_pool = rte_mempool_create(fle_pool_name, qdma_config->fle_pool_count, QDMA_FLE_POOL_SIZE, QDMA_FLE_CACHE_SIZE(qdma_config->fle_pool_count), 0, NULL, NULL, NULL, NULL, SOCKET_ID_ANY, 0); @@ -303,6 +308,7 @@ rte_qdma_vq_create(uint32_t lcore_id, uint32_t flags) /* Return in case no VQ is free */ if (i == qdma_dev.max_vqs) { rte_spinlock_unlock(&qdma_dev.lock); + DPAA2_QDMA_ERR("Unable to get lock on QDMA device"); return -ENODEV; } @@ -793,9 +799,6 @@ dpaa2_dpdmai_dev_uninit(struct rte_rawdev *rawdev) DPAA2_QDMA_FUNC_TRACE(); - if (rte_eal_process_type() != RTE_PROC_PRIMARY) - return 0; - /* Remove HW queues from global list */ remove_hw_queues_from_list(dpdmai_dev); @@ -834,10 +837,6 @@ dpaa2_dpdmai_dev_init(struct rte_rawdev *rawdev, int dpdmai_id) DPAA2_QDMA_FUNC_TRACE(); - /* For secondary processes, the primary has done all the work */ - if (rte_eal_process_type() != RTE_PROC_PRIMARY) - return 0; - /* Open DPDMAI device */ dpdmai_dev->dpdmai_id = dpdmai_id; dpdmai_dev->dpdmai.regs = rte_mcp_ptr_list[MC_PORTAL_INDEX]; From patchwork Thu Apr 4 11:04:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 161771 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1451010jan; Thu, 4 Apr 2019 04:04:54 -0700 (PDT) X-Google-Smtp-Source: APXvYqxaj9ALqevpBPzo/lq89Axt0ISzM3IcmGPbPMBNwDnNc9fhdMihpS6AL+lN2pevHaf59QIT X-Received: by 2002:a50:90c9:: with SMTP id d9mr3449901eda.158.1554375894536; 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DIR:OUT; SFP:1101; SCL:1; SRVR:VI1PR0401MB2543; H:VI1PR0401MB2541.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: TY3KjL28fhQDLuLUyoBragjSE1cUaQaNRaGAzmPxCuN/ymc6Vg/WqwHxP+QptUzTlMdzg4hXvl3nng8mbHqRIFiaSzK9c3Sw5KX6QA6MESGPTWKZgKq8rzeS5YWOJ9WbTQyR8bZSQBMmpXZjIl2JIundOvmGRKsAG4ldTikn27100lIC1ZPSGRQf1y5fH7bB4rg91hgvkPcXFsSJCEq9/JvMSzuLWfQB4qqQLmGZqELpbE/bK9lVgcjSEAt9RpOvzT/aROe00OuGFhVXuBozXd87v1TstuVq0+nrGvwSzqUvzbzY0R3eCq0PrAeYC1XSKjYnYI8ApXbbUsfyptj0yuZHmKxv7mw+V3nIQinorbCw83Oa/69QQfWfs0Fkz4O/ns0EeMeHG1zWZLJ4UOSaiX7MQLNdX+fqYg8abnkBBS4= MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 17613a2c-3a31-4a70-ab34-08d6b8ed4b96 X-MS-Exchange-CrossTenant-originalarrivaltime: 04 Apr 2019 11:04:23.7443 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0401MB2543 Subject: [dpdk-dev] [PATCH v2 4/7] raw/dpaa2_qdma: add burst mode support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds support the batch processing for the qdma jobs Signed-off-by: Hemant Agrawal Signed-off-by: Yi Liu --- drivers/raw/dpaa2_qdma/dpaa2_qdma.c | 305 ++++++++++---------- drivers/raw/dpaa2_qdma/rte_pmd_dpaa2_qdma.h | 6 +- 2 files changed, 164 insertions(+), 147 deletions(-) -- 2.17.1 diff --git a/drivers/raw/dpaa2_qdma/dpaa2_qdma.c b/drivers/raw/dpaa2_qdma/dpaa2_qdma.c index 88c11a3d2..a1351e648 100644 --- a/drivers/raw/dpaa2_qdma/dpaa2_qdma.c +++ b/drivers/raw/dpaa2_qdma/dpaa2_qdma.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -395,21 +396,31 @@ dpaa2_qdma_populate_fle(struct qbman_fle *fle, DPAA2_SET_FLE_FIN(fle); } -static int -dpdmai_dev_enqueue(struct dpaa2_dpdmai_dev *dpdmai_dev, - uint16_t txq_id, - uint16_t vq_id, - struct rte_qdma_job *job) +int +rte_qdma_vq_enqueue_multi(uint16_t vq_id, + struct rte_qdma_job **job, + uint16_t nb_jobs) { + struct qdma_virt_queue *qdma_vq = &qdma_vqs[vq_id]; + struct qdma_hw_queue *qdma_pq = qdma_vq->hw_queue; + struct dpaa2_dpdmai_dev *dpdmai_dev = qdma_pq->dpdmai_dev; struct qdma_io_meta *io_meta; - struct qbman_fd fd; + struct qbman_fd fd_arr[MAX_TX_RING_SLOTS]; struct dpaa2_queue *txq; struct qbman_fle *fle; struct qbman_eq_desc eqdesc; struct qbman_swp *swp; int ret; + uint32_t num_to_send = 0; + uint16_t num_tx = 0; + uint16_t num_txed = 0; - DPAA2_QDMA_FUNC_TRACE(); + /* Return error in case of wrong lcore_id */ + if (rte_lcore_id() != qdma_vq->lcore_id) { + DPAA2_QDMA_ERR("QDMA enqueue for vqid %d on wrong core", + vq_id); + return -1; + } if (unlikely(!DPAA2_PER_LCORE_DPIO)) { ret = dpaa2_affine_qbman_swp(); @@ -420,7 +431,7 @@ dpdmai_dev_enqueue(struct dpaa2_dpdmai_dev *dpdmai_dev, } swp = DPAA2_PER_LCORE_PORTAL; - txq = &(dpdmai_dev->tx_queue[txq_id]); + txq = &(dpdmai_dev->tx_queue[qdma_pq->queue_id]); /* Prepare enqueue descriptor */ qbman_eq_desc_clear(&eqdesc); @@ -428,97 +439,86 @@ dpdmai_dev_enqueue(struct dpaa2_dpdmai_dev *dpdmai_dev, qbman_eq_desc_set_no_orp(&eqdesc, 0); qbman_eq_desc_set_response(&eqdesc, 0, 0); - /* - * Get an FLE/SDD from FLE pool. - * Note: IO metadata is before the FLE and SDD memory. - */ - ret = rte_mempool_get(qdma_dev.fle_pool, (void **)(&io_meta)); - if (ret) { - DPAA2_QDMA_DP_WARN("Memory alloc failed for FLE"); - return ret; - } - - /* Set the metadata */ - io_meta->cnxt = (size_t)job; - io_meta->id = vq_id; - - fle = (struct qbman_fle *)(io_meta + 1); - - /* populate Frame descriptor */ - memset(&fd, 0, sizeof(struct qbman_fd)); - DPAA2_SET_FD_ADDR(&fd, DPAA2_VADDR_TO_IOVA(fle)); - DPAA2_SET_FD_COMPOUND_FMT(&fd); - DPAA2_SET_FD_FRC(&fd, QDMA_SER_CTX); + while (nb_jobs > 0) { + uint32_t loop; + + num_to_send = (nb_jobs > dpaa2_eqcr_size) ? + dpaa2_eqcr_size : nb_jobs; + + for (loop = 0; loop < num_to_send; loop++) { + /* + * Get an FLE/SDD from FLE pool. + * Note: IO metadata is before the FLE and SDD memory. + */ + ret = rte_mempool_get(qdma_dev.fle_pool, + (void **)(&io_meta)); + if (ret) { + DPAA2_QDMA_DP_WARN("Me alloc failed for FLE"); + return ret; + } - /* Populate FLE */ - memset(fle, 0, QDMA_FLE_POOL_SIZE); - dpaa2_qdma_populate_fle(fle, job->src, job->dest, job->len, job->flags); + /* Set the metadata */ + io_meta->cnxt = (size_t)job[num_tx]; + io_meta->id = vq_id; - /* Enqueue the packet to the QBMAN */ - do { - ret = qbman_swp_enqueue_multiple(swp, &eqdesc, &fd, NULL, 1); - if (ret < 0 && ret != -EBUSY) - DPAA2_QDMA_ERR("Transmit failure with err: %d", ret); - } while (ret == -EBUSY); + fle = (struct qbman_fle *)(io_meta + 1); - DPAA2_QDMA_DP_DEBUG("Successfully transmitted a packet"); + /* populate Frame descriptor */ + memset(&fd_arr[loop], 0, sizeof(struct qbman_fd)); + DPAA2_SET_FD_ADDR(&fd_arr[loop], + DPAA2_VADDR_TO_IOVA(fle)); + DPAA2_SET_FD_COMPOUND_FMT(&fd_arr[loop]); + DPAA2_SET_FD_FRC(&fd_arr[loop], QDMA_SER_CTX); - return ret; -} + /* Populate FLE */ + memset(fle, 0, QDMA_FLE_POOL_SIZE); + dpaa2_qdma_populate_fle(fle, job[num_tx]->src, + job[num_tx]->dest, + job[num_tx]->len, + job[num_tx]->flags); -int __rte_experimental -rte_qdma_vq_enqueue_multi(uint16_t vq_id, - struct rte_qdma_job **job, - uint16_t nb_jobs) -{ - int i, ret; + num_tx++; + } - DPAA2_QDMA_FUNC_TRACE(); + /* Enqueue the packet to the QBMAN */ + uint32_t enqueue_loop = 0; + while (enqueue_loop < num_to_send) { + enqueue_loop += qbman_swp_enqueue_multiple(swp, + &eqdesc, + &fd_arr[enqueue_loop], + NULL, + num_to_send - enqueue_loop); + } - for (i = 0; i < nb_jobs; i++) { - ret = rte_qdma_vq_enqueue(vq_id, job[i]); - if (ret < 0) - break; + num_txed += num_to_send; + nb_jobs -= num_to_send; } - - return i; + qdma_vq->num_enqueues += num_txed; + return num_txed; } -int __rte_experimental +int rte_qdma_vq_enqueue(uint16_t vq_id, struct rte_qdma_job *job) { - struct qdma_virt_queue *qdma_vq = &qdma_vqs[vq_id]; - struct qdma_hw_queue *qdma_pq = qdma_vq->hw_queue; - struct dpaa2_dpdmai_dev *dpdmai_dev = qdma_pq->dpdmai_dev; int ret; - DPAA2_QDMA_FUNC_TRACE(); - - /* Return error in case of wrong lcore_id */ - if (rte_lcore_id() != qdma_vq->lcore_id) { - DPAA2_QDMA_ERR("QDMA enqueue for vqid %d on wrong core", - vq_id); - return -EINVAL; - } - - ret = dpdmai_dev_enqueue(dpdmai_dev, qdma_pq->queue_id, vq_id, job); + ret = rte_qdma_vq_enqueue_multi(vq_id, &job, 1); if (ret < 0) { DPAA2_QDMA_ERR("DPDMAI device enqueue failed: %d", ret); return ret; } - qdma_vq->num_enqueues++; - return 1; } /* Function to receive a QDMA job for a given device and queue*/ static int -dpdmai_dev_dequeue(struct dpaa2_dpdmai_dev *dpdmai_dev, +dpdmai_dev_dequeue_multijob(struct dpaa2_dpdmai_dev *dpdmai_dev, uint16_t rxq_id, uint16_t *vq_id, - struct rte_qdma_job **job) + struct rte_qdma_job **job, + uint16_t nb_jobs) { struct qdma_io_meta *io_meta; struct dpaa2_queue *rxq; @@ -531,8 +531,6 @@ dpdmai_dev_dequeue(struct dpaa2_dpdmai_dev *dpdmai_dev, uint8_t status; int ret; - DPAA2_QDMA_FUNC_TRACE(); - if (unlikely(!DPAA2_PER_LCORE_DPIO)) { ret = dpaa2_affine_qbman_swp(); if (ret) { @@ -541,7 +539,6 @@ dpdmai_dev_dequeue(struct dpaa2_dpdmai_dev *dpdmai_dev, } } swp = DPAA2_PER_LCORE_PORTAL; - rxq = &(dpdmai_dev->rx_queue[rxq_id]); dq_storage = rxq->q_storage->dq_storage[0]; fqid = rxq->fqid; @@ -551,7 +548,10 @@ dpdmai_dev_dequeue(struct dpaa2_dpdmai_dev *dpdmai_dev, qbman_pull_desc_set_fq(&pulldesc, fqid); qbman_pull_desc_set_storage(&pulldesc, dq_storage, (uint64_t)(DPAA2_VADDR_TO_IOVA(dq_storage)), 1); - qbman_pull_desc_set_numframes(&pulldesc, 1); + if (nb_jobs > dpaa2_dqrr_size) + qbman_pull_desc_set_numframes(&pulldesc, dpaa2_dqrr_size); + else + qbman_pull_desc_set_numframes(&pulldesc, nb_jobs); while (1) { if (qbman_swp_pull(swp, &pulldesc)) { @@ -561,125 +561,138 @@ dpdmai_dev_dequeue(struct dpaa2_dpdmai_dev *dpdmai_dev, break; } - /* Check if previous issued command is completed. */ + rte_prefetch0((void *)((size_t)(dq_storage + 1))); + /* Check if the previous issued command is completed. */ while (!qbman_check_command_complete(dq_storage)) ; - /* Loop until dq_storage is updated with new token by QBMAN */ - while (!qbman_check_new_result(dq_storage)) - ; - /* Check for valid frame. */ - status = qbman_result_DQ_flags(dq_storage); - if (unlikely((status & QBMAN_DQ_STAT_VALIDFRAME) == 0)) { - DPAA2_QDMA_DP_DEBUG("No frame is delivered"); - return 0; - } + int num_pulled = 0; + int pending = 1; + do { + /* Loop until the dq_storage is updated with + * new token by QBMAN + */ + while (!qbman_check_new_result(dq_storage)) + ; - /* Get the FD */ - fd = qbman_result_DQ_fd(dq_storage); + rte_prefetch0((void *)((size_t)(dq_storage + 2))); + /* Check whether Last Pull command is Expired and + * setting Condition for Loop termination + */ + if (qbman_result_DQ_is_pull_complete(dq_storage)) { + pending = 0; + /* Check for valid frame. */ + status = qbman_result_DQ_flags(dq_storage); + if (unlikely((status & + QBMAN_DQ_STAT_VALIDFRAME) == 0)) + continue; + } + fd = qbman_result_DQ_fd(dq_storage); - /* - * Fetch metadata from FLE. job and vq_id were set - * in metadata in the enqueue operation. - */ - fle = (struct qbman_fle *)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)); - io_meta = (struct qdma_io_meta *)(fle) - 1; - if (vq_id) - *vq_id = io_meta->id; + /* + * Fetch metadata from FLE. job and vq_id were set + * in metadata in the enqueue operation. + */ + fle = (struct qbman_fle *) + DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)); + io_meta = (struct qdma_io_meta *)(fle) - 1; + if (vq_id) + vq_id[num_pulled] = io_meta->id; - *job = (struct rte_qdma_job *)(size_t)io_meta->cnxt; - (*job)->status = DPAA2_GET_FD_ERR(fd); + job[num_pulled] = (struct rte_qdma_job *)(size_t)io_meta->cnxt; + job[num_pulled]->status = DPAA2_GET_FD_ERR(fd); - /* Free FLE to the pool */ - rte_mempool_put(qdma_dev.fle_pool, io_meta); + /* Free FLE to the pool */ + rte_mempool_put(qdma_dev.fle_pool, io_meta); - DPAA2_QDMA_DP_DEBUG("packet received"); + dq_storage++; + num_pulled++; + } while (pending && (num_pulled <= dpaa2_dqrr_size)); - return 1; + return num_pulled; } -int __rte_experimental +int rte_qdma_vq_dequeue_multi(uint16_t vq_id, struct rte_qdma_job **job, uint16_t nb_jobs) -{ - int i; - - DPAA2_QDMA_FUNC_TRACE(); - - for (i = 0; i < nb_jobs; i++) { - job[i] = rte_qdma_vq_dequeue(vq_id); - if (!job[i]) - break; - } - - return i; -} - -struct rte_qdma_job * __rte_experimental -rte_qdma_vq_dequeue(uint16_t vq_id) { struct qdma_virt_queue *qdma_vq = &qdma_vqs[vq_id]; struct qdma_hw_queue *qdma_pq = qdma_vq->hw_queue; - struct dpaa2_dpdmai_dev *dpdmai_dev = qdma_pq->dpdmai_dev; - struct rte_qdma_job *job = NULL; struct qdma_virt_queue *temp_qdma_vq; - int dequeue_budget = QDMA_DEQUEUE_BUDGET; - int ring_count, ret, i; - uint16_t temp_vq_id; - - DPAA2_QDMA_FUNC_TRACE(); + struct dpaa2_dpdmai_dev *dpdmai_dev = qdma_pq->dpdmai_dev; + int ring_count, ret = 0, i; /* Return error in case of wrong lcore_id */ if (rte_lcore_id() != (unsigned int)(qdma_vq->lcore_id)) { - DPAA2_QDMA_ERR("QDMA dequeue for vqid %d on wrong core", + DPAA2_QDMA_WARN("QDMA dequeue for vqid %d on wrong core", vq_id); - return NULL; + return -1; } /* Only dequeue when there are pending jobs on VQ */ if (qdma_vq->num_enqueues == qdma_vq->num_dequeues) - return NULL; + return 0; + + if (qdma_vq->num_enqueues < (qdma_vq->num_dequeues + nb_jobs)) + nb_jobs = (qdma_vq->num_enqueues - qdma_vq->num_dequeues); if (qdma_vq->exclusive_hw_queue) { /* In case of exclusive queue directly fetch from HW queue */ - ret = dpdmai_dev_dequeue(dpdmai_dev, qdma_pq->queue_id, - NULL, &job); + ret = dpdmai_dev_dequeue_multijob(dpdmai_dev, qdma_pq->queue_id, + NULL, job, nb_jobs); if (ret < 0) { DPAA2_QDMA_ERR( "Dequeue from DPDMAI device failed: %d", ret); - return NULL; + return ret; } + qdma_vq->num_dequeues += ret; } else { + uint16_t temp_vq_id[RTE_QDMA_BURST_NB_MAX]; /* * Get the QDMA completed jobs from the software ring. * In case they are not available on the ring poke the HW * to fetch completed jobs from corresponding HW queues */ ring_count = rte_ring_count(qdma_vq->status_ring); - if (ring_count == 0) { + if (ring_count < nb_jobs) { /* TODO - How to have right budget */ - for (i = 0; i < dequeue_budget; i++) { - ret = dpdmai_dev_dequeue(dpdmai_dev, - qdma_pq->queue_id, &temp_vq_id, &job); - if (ret == 0) - break; - temp_qdma_vq = &qdma_vqs[temp_vq_id]; + ret = dpdmai_dev_dequeue_multijob(dpdmai_dev, + qdma_pq->queue_id, + temp_vq_id, job, nb_jobs); + for (i = 0; i < ret; i++) { + temp_qdma_vq = &qdma_vqs[temp_vq_id[i]]; rte_ring_enqueue(temp_qdma_vq->status_ring, - (void *)(job)); + (void *)(job[i])); ring_count = rte_ring_count( qdma_vq->status_ring); - if (ring_count) - break; } } - /* Dequeue job from the software ring to provide to the user */ - rte_ring_dequeue(qdma_vq->status_ring, (void **)&job); - if (job) - qdma_vq->num_dequeues++; + if (ring_count) { + /* Dequeue job from the software ring + * to provide to the user + */ + ret = rte_ring_dequeue_bulk(qdma_vq->status_ring, + (void **)job, ring_count, NULL); + if (ret) + qdma_vq->num_dequeues += ret; + } } + return ret; +} + +struct rte_qdma_job * +rte_qdma_vq_dequeue(uint16_t vq_id) +{ + int ret; + struct rte_qdma_job *job = NULL; + + ret = rte_qdma_vq_dequeue_multi(vq_id, &job, 1); + if (ret < 0) + DPAA2_QDMA_DP_WARN("DPDMAI device dequeue failed: %d", ret); + return job; } diff --git a/drivers/raw/dpaa2_qdma/rte_pmd_dpaa2_qdma.h b/drivers/raw/dpaa2_qdma/rte_pmd_dpaa2_qdma.h index c9697b4d7..e1ccc19e8 100644 --- a/drivers/raw/dpaa2_qdma/rte_pmd_dpaa2_qdma.h +++ b/drivers/raw/dpaa2_qdma/rte_pmd_dpaa2_qdma.h @@ -12,6 +12,9 @@ * */ +/** Maximum qdma burst size */ +#define RTE_QDMA_BURST_NB_MAX 32 + /** Determines the mode of operation */ enum { /** @@ -225,7 +228,8 @@ rte_qdma_vq_enqueue(uint16_t vq_id, * Number of QDMA jobs requested for dequeue by the user. * * @returns - * Number of jobs actually dequeued. + * - >=0: Number of jobs successfully received + * - <0: Error code. */ int rte_qdma_vq_dequeue_multi(uint16_t vq_id, From patchwork Thu Apr 4 11:04:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 161772 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1451315jan; Thu, 4 Apr 2019 04:05:09 -0700 (PDT) X-Google-Smtp-Source: APXvYqxEiza6Ty2wbzXjqbuK1pWjVCupSpGeYzFl174SP2ZlMXRaDcVZJc7lFjizJ07a22XN4AfW X-Received: by 2002:a50:a90d:: with SMTP id l13mr3387984edc.45.1554375909617; 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Lian" , Sachin Saxena Thread-Topic: [PATCH v2 5/7] raw/dpaa2_qdma: add rbp mode support Thread-Index: AQHU6tYqL3Nc9aAEeku9SWvztCm+jg== Date: Thu, 4 Apr 2019 11:04:25 +0000 Message-ID: <20190404110215.14410-5-hemant.agrawal@nxp.com> References: <20190326121610.28024-1-hemant.agrawal@nxp.com> <20190404110215.14410-1-hemant.agrawal@nxp.com> In-Reply-To: <20190404110215.14410-1-hemant.agrawal@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [92.120.1.72] x-mailer: git-send-email 2.17.1 x-clientproxiedby: BMXPR01CA0041.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:c::27) To VI1PR0401MB2541.eurprd04.prod.outlook.com (2603:10a6:800:56::19) authentication-results: spf=none (sender IP is ) smtp.mailfrom=hemant.agrawal@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 03969632-3fa4-43c0-484f-08d6b8ed4c7a x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(5600139)(711020)(4605104)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7193020); SRVR:VI1PR0401MB2543; x-ms-traffictypediagnostic: VI1PR0401MB2543: x-microsoft-antispam-prvs: x-forefront-prvs: 0997523C40 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(136003)(376002)(346002)(396003)(366004)(39860400002)(199004)(189003)(6916009)(6486002)(53936002)(50226002)(2906002)(8936002)(2616005)(86362001)(54906003)(7736002)(11346002)(44832011)(53946003)(486006)(316002)(8676002)(6512007)(446003)(1076003)(66066001)(5640700003)(99286004)(3846002)(6116002)(478600001)(386003)(5660300002)(26005)(81166006)(25786009)(1730700003)(76176011)(68736007)(102836004)(476003)(14454004)(4326008)(71200400001)(105586002)(81156014)(97736004)(256004)(14444005)(2501003)(186003)(2351001)(106356001)(30864003)(6436002)(305945005)(71190400001)(52116002)(6506007)(36756003)(579004); DIR:OUT; SFP:1101; SCL:1; SRVR:VI1PR0401MB2543; H:VI1PR0401MB2541.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: pMK337ClpTIN7cbMp1/EBse3Q2eNA795RcshqVm2UJVAmWUoGZcCMo52grjPMGrLW67SEfTcrDmpbP2XtHCyTiwo/AOXqU+4eyTFlocHKvp6Lea+bIc3EKIswiG5RoPPwrtJcJm+6dM11pB7tqjoRnSKVon6QCB94q9M2FXerfazidBPDmsn+BR0kVYRT/udi7mlAPulbm4fs3LJO5BA9KsJRjPSb5vzGIl8gQXI/4+3KsuAfOJQ4QsSxxly0v9+jG5p78ZpE+oAPCNBWyVfH4zAlg/ZU41hDT5AZaOObJpuILlwpQEKHxJ3DTqLAFNO1ayCbIviMsWbI4s1ZvtSdZn1nz2otwf+xUscoJUChLss21YK6w+ovebT46zDBjAqfgqLYGbA6DgWIuzpmvC26N0aokQDxwx+9pOBEQd5ABM= MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 03969632-3fa4-43c0-484f-08d6b8ed4c7a X-MS-Exchange-CrossTenant-originalarrivaltime: 04 Apr 2019 11:04:25.3449 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0401MB2543 Subject: [dpdk-dev] [PATCH v2 5/7] raw/dpaa2_qdma: add rbp mode support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for route by port mode. The route by port feature in HW helps in translating the PCI address of connected device. Signed-off-by: Minghuan Lian Signed-off-by: Sachin Saxena Signed-off-by: Hemant Agrawal --- drivers/raw/dpaa2_qdma/Makefile | 2 +- drivers/raw/dpaa2_qdma/dpaa2_qdma.c | 403 +++++++++++++------- drivers/raw/dpaa2_qdma/dpaa2_qdma.h | 65 +++- drivers/raw/dpaa2_qdma/rte_pmd_dpaa2_qdma.h | 60 ++- 4 files changed, 383 insertions(+), 147 deletions(-) -- 2.17.1 diff --git a/drivers/raw/dpaa2_qdma/Makefile b/drivers/raw/dpaa2_qdma/Makefile index 5c75f5fa0..ee95662f1 100644 --- a/drivers/raw/dpaa2_qdma/Makefile +++ b/drivers/raw/dpaa2_qdma/Makefile @@ -26,7 +26,7 @@ LDLIBS += -lrte_common_dpaax EXPORT_MAP := rte_pmd_dpaa2_qdma_version.map -LIBABIVER := 2 +LIBABIVER := 3 # # all source are stored in SRCS-y diff --git a/drivers/raw/dpaa2_qdma/dpaa2_qdma.c b/drivers/raw/dpaa2_qdma/dpaa2_qdma.c index a1351e648..cf1a1aaa6 100644 --- a/drivers/raw/dpaa2_qdma/dpaa2_qdma.c +++ b/drivers/raw/dpaa2_qdma/dpaa2_qdma.c @@ -19,13 +19,16 @@ #include #include +#include "rte_pmd_dpaa2_qdma.h" #include "dpaa2_qdma.h" #include "dpaa2_qdma_logs.h" -#include "rte_pmd_dpaa2_qdma.h" /* Dynamic log type identifier */ int dpaa2_qdma_logtype; +uint32_t dpaa2_coherent_no_alloc_cache; +uint32_t dpaa2_coherent_alloc_cache; + /* QDMA device */ static struct qdma_device qdma_dev; @@ -345,14 +348,29 @@ rte_qdma_vq_create(uint32_t lcore_id, uint32_t flags) qdma_vqs[i].in_use = 1; qdma_vqs[i].lcore_id = lcore_id; - + memset(&qdma_vqs[i].rbp, 0, sizeof(struct rte_qdma_rbp)); rte_spinlock_unlock(&qdma_dev.lock); return i; } +/*create vq for route-by-port*/ +int +rte_qdma_vq_create_rbp(uint32_t lcore_id, uint32_t flags, + struct rte_qdma_rbp *rbp) +{ + int i; + + i = rte_qdma_vq_create(lcore_id, flags); + + memcpy(&qdma_vqs[i].rbp, rbp, sizeof(struct rte_qdma_rbp)); + + return i; +} + static void dpaa2_qdma_populate_fle(struct qbman_fle *fle, + struct rte_qdma_rbp *rbp, uint64_t src, uint64_t dest, size_t len, uint32_t flags) { @@ -368,10 +386,36 @@ dpaa2_qdma_populate_fle(struct qbman_fle *fle, DPAA2_SET_FLE_LEN(fle, (2 * (sizeof(struct qdma_sdd)))); /* source and destination descriptor */ - DPAA2_SET_SDD_RD_COHERENT(sdd); /* source descriptor CMD */ - sdd++; - DPAA2_SET_SDD_WR_COHERENT(sdd); /* dest descriptor CMD */ + if (rbp && rbp->enable) { + /* source */ + sdd->read_cmd.portid = rbp->sportid; + sdd->rbpcmd_simple.pfid = rbp->spfid; + sdd->rbpcmd_simple.vfid = rbp->svfid; + + if (rbp->srbp) { + sdd->read_cmd.rbp = rbp->srbp; + sdd->read_cmd.rdtype = DPAA2_RBP_MEM_RW; + } else { + sdd->read_cmd.rdtype = dpaa2_coherent_no_alloc_cache; + } + sdd++; + /* destination */ + sdd->write_cmd.portid = rbp->dportid; + sdd->rbpcmd_simple.pfid = rbp->dpfid; + sdd->rbpcmd_simple.vfid = rbp->dvfid; + + if (rbp->drbp) { + sdd->write_cmd.rbp = rbp->drbp; + sdd->write_cmd.wrttype = DPAA2_RBP_MEM_RW; + } else { + sdd->write_cmd.wrttype = dpaa2_coherent_alloc_cache; + } + } else { + sdd->read_cmd.rdtype = dpaa2_coherent_no_alloc_cache; + sdd++; + sdd->write_cmd.wrttype = dpaa2_coherent_alloc_cache; + } fle++; /* source frame list to source buffer */ if (flags & RTE_QDMA_JOB_SRC_PHY) { @@ -396,31 +440,57 @@ dpaa2_qdma_populate_fle(struct qbman_fle *fle, DPAA2_SET_FLE_FIN(fle); } -int -rte_qdma_vq_enqueue_multi(uint16_t vq_id, - struct rte_qdma_job **job, - uint16_t nb_jobs) +static inline uint16_t dpdmai_dev_set_fd(struct qbman_fd *fd, + struct rte_qdma_job *job, + struct rte_qdma_rbp *rbp, + uint16_t vq_id) { - struct qdma_virt_queue *qdma_vq = &qdma_vqs[vq_id]; - struct qdma_hw_queue *qdma_pq = qdma_vq->hw_queue; - struct dpaa2_dpdmai_dev *dpdmai_dev = qdma_pq->dpdmai_dev; struct qdma_io_meta *io_meta; - struct qbman_fd fd_arr[MAX_TX_RING_SLOTS]; - struct dpaa2_queue *txq; struct qbman_fle *fle; + int ret = 0; + /* + * Get an FLE/SDD from FLE pool. + * Note: IO metadata is before the FLE and SDD memory. + */ + ret = rte_mempool_get(qdma_dev.fle_pool, (void **)(&io_meta)); + if (ret) { + DPAA2_QDMA_DP_DEBUG("Memory alloc failed for FLE"); + return ret; + } + + /* Set the metadata */ + io_meta->cnxt = (size_t)job; + io_meta->id = vq_id; + + fle = (struct qbman_fle *)(io_meta + 1); + + DPAA2_SET_FD_ADDR(fd, DPAA2_VADDR_TO_IOVA(fle)); + DPAA2_SET_FD_COMPOUND_FMT(fd); + DPAA2_SET_FD_FRC(fd, QDMA_SER_CTX); + + /* Populate FLE */ + memset(fle, 0, QDMA_FLE_POOL_SIZE); + dpaa2_qdma_populate_fle(fle, rbp, job->src, job->dest, + job->len, job->flags); + + return 0; +} + +static int +dpdmai_dev_enqueue_multi(struct dpaa2_dpdmai_dev *dpdmai_dev, + uint16_t txq_id, + uint16_t vq_id, + struct rte_qdma_rbp *rbp, + struct rte_qdma_job **job, + uint16_t nb_jobs) +{ + struct qbman_fd fd[RTE_QDMA_BURST_NB_MAX]; + struct dpaa2_queue *txq; struct qbman_eq_desc eqdesc; struct qbman_swp *swp; int ret; uint32_t num_to_send = 0; uint16_t num_tx = 0; - uint16_t num_txed = 0; - - /* Return error in case of wrong lcore_id */ - if (rte_lcore_id() != qdma_vq->lcore_id) { - DPAA2_QDMA_ERR("QDMA enqueue for vqid %d on wrong core", - vq_id); - return -1; - } if (unlikely(!DPAA2_PER_LCORE_DPIO)) { ret = dpaa2_affine_qbman_swp(); @@ -431,7 +501,7 @@ rte_qdma_vq_enqueue_multi(uint16_t vq_id, } swp = DPAA2_PER_LCORE_PORTAL; - txq = &(dpdmai_dev->tx_queue[qdma_pq->queue_id]); + txq = &(dpdmai_dev->tx_queue[txq_id]); /* Prepare enqueue descriptor */ qbman_eq_desc_clear(&eqdesc); @@ -439,6 +509,8 @@ rte_qdma_vq_enqueue_multi(uint16_t vq_id, qbman_eq_desc_set_no_orp(&eqdesc, 0); qbman_eq_desc_set_response(&eqdesc, 0, 0); + memset(fd, 0, RTE_QDMA_BURST_NB_MAX * sizeof(struct qbman_fd)); + while (nb_jobs > 0) { uint32_t loop; @@ -446,73 +518,100 @@ rte_qdma_vq_enqueue_multi(uint16_t vq_id, dpaa2_eqcr_size : nb_jobs; for (loop = 0; loop < num_to_send; loop++) { - /* - * Get an FLE/SDD from FLE pool. - * Note: IO metadata is before the FLE and SDD memory. - */ - ret = rte_mempool_get(qdma_dev.fle_pool, - (void **)(&io_meta)); - if (ret) { - DPAA2_QDMA_DP_WARN("Me alloc failed for FLE"); - return ret; + ret = dpdmai_dev_set_fd(&fd[loop], + job[num_tx], rbp, vq_id); + if (ret < 0) { + /* Set nb_jobs to loop, so outer while loop + * breaks out. + */ + nb_jobs = loop; + break; } - /* Set the metadata */ - io_meta->cnxt = (size_t)job[num_tx]; - io_meta->id = vq_id; - - fle = (struct qbman_fle *)(io_meta + 1); - - /* populate Frame descriptor */ - memset(&fd_arr[loop], 0, sizeof(struct qbman_fd)); - DPAA2_SET_FD_ADDR(&fd_arr[loop], - DPAA2_VADDR_TO_IOVA(fle)); - DPAA2_SET_FD_COMPOUND_FMT(&fd_arr[loop]); - DPAA2_SET_FD_FRC(&fd_arr[loop], QDMA_SER_CTX); - - /* Populate FLE */ - memset(fle, 0, QDMA_FLE_POOL_SIZE); - dpaa2_qdma_populate_fle(fle, job[num_tx]->src, - job[num_tx]->dest, - job[num_tx]->len, - job[num_tx]->flags); - num_tx++; } /* Enqueue the packet to the QBMAN */ uint32_t enqueue_loop = 0; - while (enqueue_loop < num_to_send) { + while (enqueue_loop < loop) { enqueue_loop += qbman_swp_enqueue_multiple(swp, &eqdesc, - &fd_arr[enqueue_loop], + &fd[enqueue_loop], NULL, - num_to_send - enqueue_loop); + loop - enqueue_loop); } - - num_txed += num_to_send; - nb_jobs -= num_to_send; + nb_jobs -= loop; } - qdma_vq->num_enqueues += num_txed; - return num_txed; + return num_tx; } int -rte_qdma_vq_enqueue(uint16_t vq_id, - struct rte_qdma_job *job) +rte_qdma_vq_enqueue_multi(uint16_t vq_id, + struct rte_qdma_job **job, + uint16_t nb_jobs) { + struct qdma_virt_queue *qdma_vq = &qdma_vqs[vq_id]; + struct qdma_hw_queue *qdma_pq = qdma_vq->hw_queue; + struct dpaa2_dpdmai_dev *dpdmai_dev = qdma_pq->dpdmai_dev; int ret; - ret = rte_qdma_vq_enqueue_multi(vq_id, &job, 1); + DPAA2_QDMA_FUNC_TRACE(); + + /* Return error in case of wrong lcore_id */ + if (rte_lcore_id() != qdma_vq->lcore_id) { + DPAA2_QDMA_ERR("QDMA enqueue for vqid %d on wrong core", + vq_id); + return -EINVAL; + } + + ret = dpdmai_dev_enqueue_multi(dpdmai_dev, + qdma_pq->queue_id, + vq_id, + &qdma_vq->rbp, + job, + nb_jobs); if (ret < 0) { DPAA2_QDMA_ERR("DPDMAI device enqueue failed: %d", ret); return ret; } - return 1; + qdma_vq->num_enqueues += ret; + + return ret; +} + +int +rte_qdma_vq_enqueue(uint16_t vq_id, + struct rte_qdma_job *job) +{ + return rte_qdma_vq_enqueue_multi(vq_id, &job, 1); +} + +static inline uint16_t dpdmai_dev_get_job(const struct qbman_fd *fd, + struct rte_qdma_job **job) +{ + struct qbman_fle *fle; + struct qdma_io_meta *io_meta; + uint16_t vqid; + /* + * Fetch metadata from FLE. job and vq_id were set + * in metadata in the enqueue operation. + */ + fle = (struct qbman_fle *)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)); + io_meta = (struct qdma_io_meta *)(fle) - 1; + + *job = (struct rte_qdma_job *)(size_t)io_meta->cnxt; + (*job)->status = (DPAA2_GET_FD_ERR(fd) << 8) | + (DPAA2_GET_FD_FRC(fd) & 0xFF); + + vqid = io_meta->id; + + /* Free FLE to the pool */ + rte_mempool_put(qdma_dev.fle_pool, io_meta); + + return vqid; } -/* Function to receive a QDMA job for a given device and queue*/ static int dpdmai_dev_dequeue_multijob(struct dpaa2_dpdmai_dev *dpdmai_dev, uint16_t rxq_id, @@ -520,16 +619,18 @@ dpdmai_dev_dequeue_multijob(struct dpaa2_dpdmai_dev *dpdmai_dev, struct rte_qdma_job **job, uint16_t nb_jobs) { - struct qdma_io_meta *io_meta; struct dpaa2_queue *rxq; struct qbman_result *dq_storage; struct qbman_pull_desc pulldesc; - const struct qbman_fd *fd; struct qbman_swp *swp; - struct qbman_fle *fle; uint32_t fqid; - uint8_t status; - int ret; + uint8_t status, pending; + uint8_t num_rx = 0; + const struct qbman_fd *fd; + uint16_t vqid; + int ret, next_pull = nb_jobs, num_pulled = 0; + + DPAA2_QDMA_FUNC_TRACE(); if (unlikely(!DPAA2_PER_LCORE_DPIO)) { ret = dpaa2_affine_qbman_swp(); @@ -539,77 +640,75 @@ dpdmai_dev_dequeue_multijob(struct dpaa2_dpdmai_dev *dpdmai_dev, } } swp = DPAA2_PER_LCORE_PORTAL; + rxq = &(dpdmai_dev->rx_queue[rxq_id]); - dq_storage = rxq->q_storage->dq_storage[0]; fqid = rxq->fqid; - /* Prepare dequeue descriptor */ - qbman_pull_desc_clear(&pulldesc); - qbman_pull_desc_set_fq(&pulldesc, fqid); - qbman_pull_desc_set_storage(&pulldesc, dq_storage, - (uint64_t)(DPAA2_VADDR_TO_IOVA(dq_storage)), 1); - if (nb_jobs > dpaa2_dqrr_size) - qbman_pull_desc_set_numframes(&pulldesc, dpaa2_dqrr_size); - else - qbman_pull_desc_set_numframes(&pulldesc, nb_jobs); - - while (1) { - if (qbman_swp_pull(swp, &pulldesc)) { - DPAA2_QDMA_DP_WARN("VDQ command not issued. QBMAN busy"); - continue; + do { + dq_storage = rxq->q_storage->dq_storage[0]; + /* Prepare dequeue descriptor */ + qbman_pull_desc_clear(&pulldesc); + qbman_pull_desc_set_fq(&pulldesc, fqid); + qbman_pull_desc_set_storage(&pulldesc, dq_storage, + (uint64_t)(DPAA2_VADDR_TO_IOVA(dq_storage)), 1); + + if (next_pull > dpaa2_dqrr_size) { + qbman_pull_desc_set_numframes(&pulldesc, + dpaa2_dqrr_size); + next_pull -= dpaa2_dqrr_size; + } else { + qbman_pull_desc_set_numframes(&pulldesc, next_pull); + next_pull = 0; } - break; - } - rte_prefetch0((void *)((size_t)(dq_storage + 1))); - /* Check if the previous issued command is completed. */ - while (!qbman_check_command_complete(dq_storage)) - ; + while (1) { + if (qbman_swp_pull(swp, &pulldesc)) { + DPAA2_QDMA_DP_WARN("VDQ command not issued. QBMAN busy"); + /* Portal was busy, try again */ + continue; + } + break; + } - int num_pulled = 0; - int pending = 1; - do { - /* Loop until the dq_storage is updated with - * new token by QBMAN - */ - while (!qbman_check_new_result(dq_storage)) + rte_prefetch0((void *)((size_t)(dq_storage + 1))); + /* Check if the previous issued command is completed. */ + while (!qbman_check_command_complete(dq_storage)) ; - rte_prefetch0((void *)((size_t)(dq_storage + 2))); - /* Check whether Last Pull command is Expired and - * setting Condition for Loop termination - */ - if (qbman_result_DQ_is_pull_complete(dq_storage)) { - pending = 0; - /* Check for valid frame. */ - status = qbman_result_DQ_flags(dq_storage); - if (unlikely((status & - QBMAN_DQ_STAT_VALIDFRAME) == 0)) - continue; - } - fd = qbman_result_DQ_fd(dq_storage); + num_pulled = 0; + pending = 1; - /* - * Fetch metadata from FLE. job and vq_id were set - * in metadata in the enqueue operation. - */ - fle = (struct qbman_fle *) - DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)); - io_meta = (struct qdma_io_meta *)(fle) - 1; - if (vq_id) - vq_id[num_pulled] = io_meta->id; + do { + /* Loop until dq_storage is updated + * with new token by QBMAN + */ + while (!qbman_check_new_result(dq_storage)) + ; + rte_prefetch0((void *)((size_t)(dq_storage + 2))); + + if (qbman_result_DQ_is_pull_complete(dq_storage)) { + pending = 0; + /* Check for valid frame. */ + status = qbman_result_DQ_flags(dq_storage); + if (unlikely((status & + QBMAN_DQ_STAT_VALIDFRAME) == 0)) + continue; + } + fd = qbman_result_DQ_fd(dq_storage); - job[num_pulled] = (struct rte_qdma_job *)(size_t)io_meta->cnxt; - job[num_pulled]->status = DPAA2_GET_FD_ERR(fd); + vqid = dpdmai_dev_get_job(fd, &job[num_rx]); + if (vq_id) + vq_id[num_rx] = vqid; - /* Free FLE to the pool */ - rte_mempool_put(qdma_dev.fle_pool, io_meta); + dq_storage++; + num_rx++; + num_pulled++; - dq_storage++; - num_pulled++; - } while (pending && (num_pulled <= dpaa2_dqrr_size)); + } while (pending); + /* Last VDQ provided all packets and more packets are requested */ + } while (next_pull && num_pulled == dpaa2_dqrr_size); - return num_pulled; + return num_rx; } int @@ -664,9 +763,9 @@ rte_qdma_vq_dequeue_multi(uint16_t vq_id, temp_qdma_vq = &qdma_vqs[temp_vq_id[i]]; rte_ring_enqueue(temp_qdma_vq->status_ring, (void *)(job[i])); - ring_count = rte_ring_count( - qdma_vq->status_ring); } + ring_count = rte_ring_count( + qdma_vq->status_ring); } if (ring_count) { @@ -743,6 +842,35 @@ rte_qdma_vq_destroy(uint16_t vq_id) return 0; } +int +rte_qdma_vq_destroy_rbp(uint16_t vq_id) +{ + struct qdma_virt_queue *qdma_vq = &qdma_vqs[vq_id]; + + DPAA2_QDMA_FUNC_TRACE(); + + /* In case there are pending jobs on any VQ, return -EBUSY */ + if (qdma_vq->num_enqueues != qdma_vq->num_dequeues) + return -EBUSY; + + rte_spinlock_lock(&qdma_dev.lock); + + if (qdma_vq->exclusive_hw_queue) { + free_hw_queue(qdma_vq->hw_queue); + } else { + if (qdma_vqs->status_ring) + rte_ring_free(qdma_vqs->status_ring); + + put_hw_queue(qdma_vq->hw_queue); + } + + memset(qdma_vq, 0, sizeof(struct qdma_virt_queue)); + + rte_spinlock_lock(&qdma_dev.lock); + + return 0; +} + void rte_qdma_stop(void) { @@ -939,6 +1067,21 @@ dpaa2_dpdmai_dev_init(struct rte_rawdev *rawdev, int dpdmai_id) DPAA2_QDMA_ERR("Adding H/W queue to list failed"); goto init_err; } + + if (!dpaa2_coherent_no_alloc_cache) { + if (dpaa2_svr_family == SVR_LX2160A) { + dpaa2_coherent_no_alloc_cache = + DPAA2_LX2_COHERENT_NO_ALLOCATE_CACHE; + dpaa2_coherent_alloc_cache = + DPAA2_LX2_COHERENT_ALLOCATE_CACHE; + } else { + dpaa2_coherent_no_alloc_cache = + DPAA2_COHERENT_NO_ALLOCATE_CACHE; + dpaa2_coherent_alloc_cache = + DPAA2_COHERENT_ALLOCATE_CACHE; + } + } + DPAA2_QDMA_DEBUG("Initialized dpdmai object successfully"); return 0; diff --git a/drivers/raw/dpaa2_qdma/dpaa2_qdma.h b/drivers/raw/dpaa2_qdma/dpaa2_qdma.h index 0cbe90255..f15dda694 100644 --- a/drivers/raw/dpaa2_qdma/dpaa2_qdma.h +++ b/drivers/raw/dpaa2_qdma/dpaa2_qdma.h @@ -22,28 +22,24 @@ struct qdma_io_meta; /** Notification by FQD_CTX[fqid] */ #define QDMA_SER_CTX (1 << 8) - +#define DPAA2_RBP_MEM_RW 0x0 /** * Source descriptor command read transaction type for RBP=0: * coherent copy of cacheable memory */ -#define DPAA2_SET_SDD_RD_COHERENT(sdd) ((sdd)->cmd = (0xb << 28)) +#define DPAA2_COHERENT_NO_ALLOCATE_CACHE 0xb +#define DPAA2_LX2_COHERENT_NO_ALLOCATE_CACHE 0x7 /** * Destination descriptor command write transaction type for RBP=0: * coherent copy of cacheable memory */ -#define DPAA2_SET_SDD_WR_COHERENT(sdd) ((sdd)->cmd = (0x6 << 28)) +#define DPAA2_COHERENT_ALLOCATE_CACHE 0x6 +#define DPAA2_LX2_COHERENT_ALLOCATE_CACHE 0xb /** Maximum possible H/W Queues on each core */ #define MAX_HW_QUEUE_PER_CORE 64 -/** - * In case of Virtual Queue mode, this specifies the number of - * dequeue the 'qdma_vq_dequeue/multi' API does from the H/W Queue - * in case there is no job present on the Virtual Queue ring. - */ -#define QDMA_DEQUEUE_BUDGET 64 - +#define QDMA_RBP_UPPER_ADDRESS_MASK (0xfff0000000000) /** * Represents a QDMA device. * A single QDMA device exists which is combination of multiple DPDMAI rawdev's. @@ -90,6 +86,8 @@ struct qdma_virt_queue { struct rte_ring *status_ring; /** Associated hw queue */ struct qdma_hw_queue *hw_queue; + /** Route by port */ + struct rte_qdma_rbp rbp; /** Associated lcore id */ uint32_t lcore_id; /** States if this vq is in use or not */ @@ -118,7 +116,7 @@ struct qdma_io_meta { */ uint64_t cnxt; /** VQ ID is stored as a part of metadata of the enqueue command */ - uint64_t id; + uint64_t id; }; /** Source/Destination Descriptor */ @@ -127,9 +125,48 @@ struct qdma_sdd { /** Stride configuration */ uint32_t stride; /** Route-by-port command */ - uint32_t rbpcmd; - uint32_t cmd; -} __attribute__((__packed__)); + union { + uint32_t rbpcmd; + struct rbpcmd_st { + uint32_t vfid:6; + uint32_t rsv4:2; + uint32_t pfid:1; + uint32_t rsv3:7; + uint32_t attr:3; + uint32_t rsv2:1; + uint32_t at:2; + uint32_t vfa:1; + uint32_t ca:1; + uint32_t tc:3; + uint32_t rsv1:5; + } rbpcmd_simple; + }; + union { + uint32_t cmd; + struct rcmd_simple { + uint32_t portid:4; + uint32_t rsv1:14; + uint32_t rbp:1; + uint32_t ssen:1; + uint32_t rthrotl:4; + uint32_t sqos:3; + uint32_t ns:1; + uint32_t rdtype:4; + } read_cmd; + struct wcmd_simple { + uint32_t portid:4; + uint32_t rsv3:10; + uint32_t rsv2:2; + uint32_t lwc:2; + uint32_t rbp:1; + uint32_t dsen:1; + uint32_t rsv1:4; + uint32_t dqos:3; + uint32_t ns:1; + uint32_t wrttype:4; + } write_cmd; + }; +} __attribute__ ((__packed__)); /** Represents a DPDMAI raw device */ struct dpaa2_dpdmai_dev { diff --git a/drivers/raw/dpaa2_qdma/rte_pmd_dpaa2_qdma.h b/drivers/raw/dpaa2_qdma/rte_pmd_dpaa2_qdma.h index e1ccc19e8..bbc66a286 100644 --- a/drivers/raw/dpaa2_qdma/rte_pmd_dpaa2_qdma.h +++ b/drivers/raw/dpaa2_qdma/rte_pmd_dpaa2_qdma.h @@ -13,7 +13,7 @@ */ /** Maximum qdma burst size */ -#define RTE_QDMA_BURST_NB_MAX 32 +#define RTE_QDMA_BURST_NB_MAX 256 /** Determines the mode of operation */ enum { @@ -73,6 +73,40 @@ struct rte_qdma_config { int fle_pool_count; }; +struct rte_qdma_rbp { + uint32_t use_ultrashort:1; + uint32_t enable:1; + /** + * dportid: + * 0000 PCI-Express 1 + * 0001 PCI-Express 2 + * 0010 PCI-Express 3 + * 0011 PCI-Express 4 + * 0100 PCI-Express 5 + * 0101 PCI-Express 6 + */ + uint32_t dportid:4; + uint32_t dpfid:2; + uint32_t dvfid:6; + /*using route by port for destination */ + uint32_t drbp:1; + /** + * sportid: + * 0000 PCI-Express 1 + * 0001 PCI-Express 2 + * 0010 PCI-Express 3 + * 0011 PCI-Express 4 + * 0100 PCI-Express 5 + * 0101 PCI-Express 6 + */ + uint32_t sportid:4; + uint32_t spfid:2; + uint32_t svfid:6; + /* using route by port for source */ + uint32_t srbp:1; + uint32_t rsv:4; +}; + /** Provides QDMA device statistics */ struct rte_qdma_vq_stats { /** States if this vq has exclusively associated hw queue */ @@ -105,8 +139,10 @@ struct rte_qdma_job { /** * Status of the transaction. * This is filled in the dequeue operation by the driver. + * upper 8bits acc_err for route by port. + * lower 8bits fd error */ - uint8_t status; + uint16_t status; }; /** @@ -177,6 +213,11 @@ rte_qdma_start(void); int rte_qdma_vq_create(uint32_t lcore_id, uint32_t flags); +/*create vq for route-by-port*/ +int +rte_qdma_vq_create_rbp(uint32_t lcore_id, uint32_t flags, + struct rte_qdma_rbp *rbp); + /** * Enqueue multiple jobs to a Virtual Queue. * If the enqueue is successful, the H/W will perform DMA operations @@ -275,6 +316,21 @@ rte_qdma_vq_stats(uint16_t vq_id, int rte_qdma_vq_destroy(uint16_t vq_id); +/** + * Destroy the RBP specific Virtual Queue specified by vq_id. + * This API can be called from any thread/core. User can create/destroy + * VQ's at runtime. + * + * @param vq_id + * RBP based Virtual Queue ID which needs to be deinialized. + * + * @returns + * - 0: Success. + * - <0: Error code. + */ + +int __rte_experimental +rte_qdma_vq_destroy_rbp(uint16_t vq_id); /** * Stop QDMA device. */ From patchwork Thu Apr 4 11:04:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 161773 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1451501jan; Thu, 4 Apr 2019 04:05:17 -0700 (PDT) X-Google-Smtp-Source: APXvYqx5HIA0SfUS1UUeCoiijGoh2Zka9Icd8xCJ3IEyJ1dICzDhMmJv9Q+IfX0fRQ/0auGwzKVE X-Received: by 2002:aa7:dd0e:: with SMTP id i14mr3410330edv.172.1554375917508; Thu, 04 Apr 2019 04:05:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554375917; cv=none; d=google.com; s=arc-20160816; b=aMItRv12AEK8NInztNd+5jlNZKJ4SYzBEnnUfu/FxfzGAfBkQLerF750+yq7xxfSrf 08ckrs4LdYwukFFaiV7b03s5TSeVSIg+Fo+iXAab5aQ76VK4IUlsSiClW98iqZTPONhT bCPUE7fsne3FnLg9OEP3hvFhafZQcxCHEWMo96oUc8GDe9lhxdvLnFvwlFK2Zf5MCWDL EyWfwOp+ukcJ8jSl0nQBcC6aVndEIaH/uEWBnTbbW+hTlSPpdi+AM5bQ+onq1f7uiyyE NATa6n1+52er1/DkCEEFy3QkVgASAC0EttM2Xi+/q8hQ6uD3mOgvLtAvnuatqiZJclH3 6PXw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:mime-version :content-transfer-encoding:content-language:accept-language :in-reply-to:references:message-id:date:thread-index:thread-topic:cc :to:from:dkim-signature; bh=4blpbpeN4gKgz34zi4opeZg8VSXnbdF/YKsymUyQbOc=; b=vIs1hnc8kNC41a5bLkUKfXOSuso6hYHcPAC8A/PYbILnkeqkpKRfwyzye2/13eF5RX qGkAbClm0ADEfIqEgYv3LHEOBBGXNeGKfWeaFrN7FIJrfjMdcg7+gPYr03CkH5Fe3FK3 eQoWqSwhUb/I2z+Q+matcb6KnIeF2iAF2s9FjCL82RwuYw1xrrutb8FplJ43CiVnToO9 6oeDVINqoqS9giTBRPdvahnWwKnqIeKy3cA0NUbkMlSM4DP0TYcJNGEBGk4JDwZJneAo Pxs3H1xjk41zlVwA/Kx+GI0a+tynrFDqifXQoHd1Hxr06qUMVVaOroww8pK3JFy/dfjy /KEA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@nxp.com header.s=selector1 header.b=EEHgcDbc; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. 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DIR:OUT; SFP:1101; SCL:1; SRVR:VI1PR0401MB2543; H:VI1PR0401MB2541.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: g1s2p1WlaMG72ll2N0PtmN57BUx+QAZU4McFsZ5CCUVmuTiqbdG8o0z0b8eAiIXbG8SzO2ctAN6A2DXHQmr4Yw70Igkq8lg3wILCBR3I2ilXvh+InU6ILampIup4D4ke81GmoNw3YXH4GcIou5zKNk5UDBRY7OJTSCZ4ZrBk2Z1x6zuxJB58L7Z67uDFUwCorPv/bA/JIm9+Sw2bf9XRntMojWaLTHJinPTxiXa85pddVw3hdkdLfnOnsr08NSQAzo9SIDhPmXnrrj1FW70nd1XCU485eOKXpDgGKyjGObI8OBcQixNWvvrgYSKWNDvcGizyjSDehcmpgzrPImu5YEyHKw7R2tSZFk+iRB/CLE5PwIuLQB80onBB7tpl2CJeG8JhuNPpAxMQZedVRN205vU5W+y+GNZONmbs/J0Heo8= MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3e7b2bb5-f6bf-496e-71ff-08d6b8ed4d53 X-MS-Exchange-CrossTenant-originalarrivaltime: 04 Apr 2019 11:04:26.7341 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0401MB2543 Subject: [dpdk-dev] [PATCH v2 6/7] raw/dpaa2x: remove rte logs from data path X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Nipun Gupta The runtime traces shall not be present in datapath Signed-off-by: Nipun Gupta --- drivers/raw/dpaa2_cmdif/dpaa2_cmdif.c | 4 ---- drivers/raw/dpaa2_qdma/dpaa2_qdma.c | 8 -------- drivers/raw/dpaa2_qdma/rte_pmd_dpaa2_qdma.h | 2 +- 3 files changed, 1 insertion(+), 13 deletions(-) -- 2.17.1 diff --git a/drivers/raw/dpaa2_cmdif/dpaa2_cmdif.c b/drivers/raw/dpaa2_cmdif/dpaa2_cmdif.c index 469960a3e..7d311b2ee 100644 --- a/drivers/raw/dpaa2_cmdif/dpaa2_cmdif.c +++ b/drivers/raw/dpaa2_cmdif/dpaa2_cmdif.c @@ -67,8 +67,6 @@ dpaa2_cmdif_enqueue_bufs(struct rte_rawdev *dev, struct qbman_swp *swp; int ret; - DPAA2_CMDIF_FUNC_TRACE(); - RTE_SET_USED(count); if (unlikely(!DPAA2_PER_LCORE_DPIO)) { @@ -128,8 +126,6 @@ dpaa2_cmdif_dequeue_bufs(struct rte_rawdev *dev, uint8_t status; int ret; - DPAA2_CMDIF_FUNC_TRACE(); - RTE_SET_USED(count); if (unlikely(!DPAA2_PER_LCORE_DPIO)) { diff --git a/drivers/raw/dpaa2_qdma/dpaa2_qdma.c b/drivers/raw/dpaa2_qdma/dpaa2_qdma.c index cf1a1aaa6..38f329a50 100644 --- a/drivers/raw/dpaa2_qdma/dpaa2_qdma.c +++ b/drivers/raw/dpaa2_qdma/dpaa2_qdma.c @@ -376,8 +376,6 @@ dpaa2_qdma_populate_fle(struct qbman_fle *fle, { struct qdma_sdd *sdd; - DPAA2_QDMA_FUNC_TRACE(); - sdd = (struct qdma_sdd *)((uint8_t *)(fle) + (DPAA2_QDMA_MAX_FLE * sizeof(struct qbman_fle))); @@ -555,8 +553,6 @@ rte_qdma_vq_enqueue_multi(uint16_t vq_id, struct dpaa2_dpdmai_dev *dpdmai_dev = qdma_pq->dpdmai_dev; int ret; - DPAA2_QDMA_FUNC_TRACE(); - /* Return error in case of wrong lcore_id */ if (rte_lcore_id() != qdma_vq->lcore_id) { DPAA2_QDMA_ERR("QDMA enqueue for vqid %d on wrong core", @@ -630,8 +626,6 @@ dpdmai_dev_dequeue_multijob(struct dpaa2_dpdmai_dev *dpdmai_dev, uint16_t vqid; int ret, next_pull = nb_jobs, num_pulled = 0; - DPAA2_QDMA_FUNC_TRACE(); - if (unlikely(!DPAA2_PER_LCORE_DPIO)) { ret = dpaa2_affine_qbman_swp(); if (ret) { @@ -801,8 +795,6 @@ rte_qdma_vq_stats(uint16_t vq_id, { struct qdma_virt_queue *qdma_vq = &qdma_vqs[vq_id]; - DPAA2_QDMA_FUNC_TRACE(); - if (qdma_vq->in_use) { vq_status->exclusive_hw_queue = qdma_vq->exclusive_hw_queue; vq_status->lcore_id = qdma_vq->lcore_id; diff --git a/drivers/raw/dpaa2_qdma/rte_pmd_dpaa2_qdma.h b/drivers/raw/dpaa2_qdma/rte_pmd_dpaa2_qdma.h index bbc66a286..ce491d5d4 100644 --- a/drivers/raw/dpaa2_qdma/rte_pmd_dpaa2_qdma.h +++ b/drivers/raw/dpaa2_qdma/rte_pmd_dpaa2_qdma.h @@ -329,7 +329,7 @@ rte_qdma_vq_destroy(uint16_t vq_id); * - <0: Error code. */ -int __rte_experimental +int rte_qdma_vq_destroy_rbp(uint16_t vq_id); /** * Stop QDMA device. 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DIR:OUT; SFP:1101; SCL:1; SRVR:VI1PR0401MB2493; H:VI1PR0401MB2541.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: j6gY/zt4hveZ0KfoWGOdoI61RLAEHiq60sfrjc0v8IGzwQozmcJnrvjlqY5xbuqSYDr4XCiXrVsANEEbp4/8WqD6Gsb1wpRBnFm35PLKOhFAnfTjCk0LXDuvFT+Po2BXMC1E71Yd4AMorqqlviOkQUgYOIEBUpBLysnG2gTi5YKeRdDCnAwXkZnUxyGPF/8zj+EL2NH6W3auadcJ5tq7QxCEP8fSN/ZvxN8YjpVu3Mbs25ZgjpTYA9h7+01oLtVy98UjSW7J0RsL71LsvxRh2UXyloG6sHz04pqOxlYshZ+Kimvh9lhREdeOuWANt3KaWRDfCj4uCEJ1Q+KJl45AdZpIQ8q39XtlBC1nZDeSxk90qgxRDyWe6rdw0UIQshy0ePMyTUIK6NCOIVh4XhUc9vZN+3Q3XHFqflnoHlN/jMw= MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: a4e43030-c885-4cc0-f76a-08d6b8ed4e10 X-MS-Exchange-CrossTenant-originalarrivaltime: 04 Apr 2019 11:04:28.0162 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0401MB2493 Subject: [dpdk-dev] [PATCH v2 7/7] raw/dpaa2_qdma: add support for non prefetch mode X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch add support for non prefetch mode in Rx functions. Signed-off-by: Hemant Agrawal --- drivers/raw/dpaa2_qdma/Makefile | 1 + drivers/raw/dpaa2_qdma/dpaa2_qdma.c | 215 +++++++++++++++++++++++++++- drivers/raw/dpaa2_qdma/meson.build | 2 +- 3 files changed, 212 insertions(+), 6 deletions(-) -- 2.17.1 diff --git a/drivers/raw/dpaa2_qdma/Makefile b/drivers/raw/dpaa2_qdma/Makefile index ee95662f1..450c76e76 100644 --- a/drivers/raw/dpaa2_qdma/Makefile +++ b/drivers/raw/dpaa2_qdma/Makefile @@ -21,6 +21,7 @@ LDLIBS += -lrte_eal LDLIBS += -lrte_mempool LDLIBS += -lrte_mempool_dpaa2 LDLIBS += -lrte_rawdev +LDLIBS += -lrte_kvargs LDLIBS += -lrte_ring LDLIBS += -lrte_common_dpaax diff --git a/drivers/raw/dpaa2_qdma/dpaa2_qdma.c b/drivers/raw/dpaa2_qdma/dpaa2_qdma.c index 38f329a50..a41c1e385 100644 --- a/drivers/raw/dpaa2_qdma/dpaa2_qdma.c +++ b/drivers/raw/dpaa2_qdma/dpaa2_qdma.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -23,6 +24,8 @@ #include "dpaa2_qdma.h" #include "dpaa2_qdma_logs.h" +#define DPAA2_QDMA_NO_PREFETCH "no_prefetch" + /* Dynamic log type identifier */ int dpaa2_qdma_logtype; @@ -43,6 +46,14 @@ static struct qdma_virt_queue *qdma_vqs; /* QDMA per core data */ static struct qdma_per_core_info qdma_core_info[RTE_MAX_LCORE]; +typedef int (dpdmai_dev_dequeue_multijob_t)(struct dpaa2_dpdmai_dev *dpdmai_dev, + uint16_t rxq_id, + uint16_t *vq_id, + struct rte_qdma_job **job, + uint16_t nb_jobs); + +dpdmai_dev_dequeue_multijob_t *dpdmai_dev_dequeue_multijob; + static struct qdma_hw_queue * alloc_hw_queue(uint32_t lcore_id) { @@ -608,12 +619,156 @@ static inline uint16_t dpdmai_dev_get_job(const struct qbman_fd *fd, return vqid; } +/* Function to receive a QDMA job for a given device and queue*/ static int -dpdmai_dev_dequeue_multijob(struct dpaa2_dpdmai_dev *dpdmai_dev, - uint16_t rxq_id, - uint16_t *vq_id, - struct rte_qdma_job **job, - uint16_t nb_jobs) +dpdmai_dev_dequeue_multijob_prefetch( + struct dpaa2_dpdmai_dev *dpdmai_dev, + uint16_t rxq_id, + uint16_t *vq_id, + struct rte_qdma_job **job, + uint16_t nb_jobs) +{ + struct dpaa2_queue *rxq; + struct qbman_result *dq_storage, *dq_storage1 = NULL; + struct qbman_pull_desc pulldesc; + struct qbman_swp *swp; + struct queue_storage_info_t *q_storage; + uint32_t fqid; + uint8_t status, pending; + uint8_t num_rx = 0; + const struct qbman_fd *fd; + uint16_t vqid; + int ret, pull_size; + + if (unlikely(!DPAA2_PER_LCORE_DPIO)) { + ret = dpaa2_affine_qbman_swp(); + if (ret) { + DPAA2_QDMA_ERR("Failure in affining portal"); + return 0; + } + } + swp = DPAA2_PER_LCORE_PORTAL; + + pull_size = (nb_jobs > dpaa2_dqrr_size) ? dpaa2_dqrr_size : nb_jobs; + rxq = &(dpdmai_dev->rx_queue[rxq_id]); + fqid = rxq->fqid; + q_storage = rxq->q_storage; + + if (unlikely(!q_storage->active_dqs)) { + q_storage->toggle = 0; + dq_storage = q_storage->dq_storage[q_storage->toggle]; + q_storage->last_num_pkts = pull_size; + qbman_pull_desc_clear(&pulldesc); + qbman_pull_desc_set_numframes(&pulldesc, + q_storage->last_num_pkts); + qbman_pull_desc_set_fq(&pulldesc, fqid); + qbman_pull_desc_set_storage(&pulldesc, dq_storage, + (size_t)(DPAA2_VADDR_TO_IOVA(dq_storage)), 1); + if (check_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index)) { + while (!qbman_check_command_complete( + get_swp_active_dqs( + DPAA2_PER_LCORE_DPIO->index))) + ; + clear_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index); + } + while (1) { + if (qbman_swp_pull(swp, &pulldesc)) { + DPAA2_QDMA_DP_WARN( + "VDQ command not issued.QBMAN busy\n"); + /* Portal was busy, try again */ + continue; + } + break; + } + q_storage->active_dqs = dq_storage; + q_storage->active_dpio_id = DPAA2_PER_LCORE_DPIO->index; + set_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index, + dq_storage); + } + + dq_storage = q_storage->active_dqs; + rte_prefetch0((void *)(size_t)(dq_storage)); + rte_prefetch0((void *)(size_t)(dq_storage + 1)); + + /* Prepare next pull descriptor. This will give space for the + * prefething done on DQRR entries + */ + q_storage->toggle ^= 1; + dq_storage1 = q_storage->dq_storage[q_storage->toggle]; + qbman_pull_desc_clear(&pulldesc); + qbman_pull_desc_set_numframes(&pulldesc, pull_size); + qbman_pull_desc_set_fq(&pulldesc, fqid); + qbman_pull_desc_set_storage(&pulldesc, dq_storage1, + (size_t)(DPAA2_VADDR_TO_IOVA(dq_storage1)), 1); + + /* Check if the previous issued command is completed. + * Also seems like the SWP is shared between the Ethernet Driver + * and the SEC driver. + */ + while (!qbman_check_command_complete(dq_storage)) + ; + if (dq_storage == get_swp_active_dqs(q_storage->active_dpio_id)) + clear_swp_active_dqs(q_storage->active_dpio_id); + + pending = 1; + + do { + /* Loop until the dq_storage is updated with + * new token by QBMAN + */ + while (!qbman_check_new_result(dq_storage)) + ; + rte_prefetch0((void *)((size_t)(dq_storage + 2))); + /* Check whether Last Pull command is Expired and + * setting Condition for Loop termination + */ + if (qbman_result_DQ_is_pull_complete(dq_storage)) { + pending = 0; + /* Check for valid frame. */ + status = qbman_result_DQ_flags(dq_storage); + if (unlikely((status & QBMAN_DQ_STAT_VALIDFRAME) == 0)) + continue; + } + fd = qbman_result_DQ_fd(dq_storage); + + vqid = dpdmai_dev_get_job(fd, &job[num_rx]); + if (vq_id) + vq_id[num_rx] = vqid; + + dq_storage++; + num_rx++; + } while (pending); + + if (check_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index)) { + while (!qbman_check_command_complete( + get_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index))) + ; + clear_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index); + } + /* issue a volatile dequeue command for next pull */ + while (1) { + if (qbman_swp_pull(swp, &pulldesc)) { + DPAA2_QDMA_DP_WARN("VDQ command is not issued." + "QBMAN is busy (2)\n"); + continue; + } + break; + } + + q_storage->active_dqs = dq_storage1; + q_storage->active_dpio_id = DPAA2_PER_LCORE_DPIO->index; + set_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index, dq_storage1); + + return num_rx; +} + +static int +dpdmai_dev_dequeue_multijob_no_prefetch( + struct dpaa2_dpdmai_dev *dpdmai_dev, + uint16_t rxq_id, + uint16_t *vq_id, + struct rte_qdma_job **job, + uint16_t nb_jobs) { struct dpaa2_queue *rxq; struct qbman_result *dq_storage; @@ -958,6 +1113,43 @@ dpaa2_dpdmai_dev_uninit(struct rte_rawdev *rawdev) return 0; } +static int +check_devargs_handler(__rte_unused const char *key, const char *value, + __rte_unused void *opaque) +{ + if (strcmp(value, "1")) + return -1; + + return 0; +} + +static int +dpaa2_get_devargs(struct rte_devargs *devargs, const char *key) +{ + struct rte_kvargs *kvlist; + + if (!devargs) + return 0; + + kvlist = rte_kvargs_parse(devargs->args, NULL); + if (!kvlist) + return 0; + + if (!rte_kvargs_count(kvlist, key)) { + rte_kvargs_free(kvlist); + return 0; + } + + if (rte_kvargs_process(kvlist, key, + check_devargs_handler, NULL) < 0) { + rte_kvargs_free(kvlist); + return 0; + } + rte_kvargs_free(kvlist); + + return 1; +} + static int dpaa2_dpdmai_dev_init(struct rte_rawdev *rawdev, int dpdmai_id) { @@ -1060,6 +1252,17 @@ dpaa2_dpdmai_dev_init(struct rte_rawdev *rawdev, int dpdmai_id) goto init_err; } + if (dpaa2_get_devargs(rawdev->device->devargs, + DPAA2_QDMA_NO_PREFETCH)) { + /* If no prefetch is configured. */ + dpdmai_dev_dequeue_multijob = + dpdmai_dev_dequeue_multijob_no_prefetch; + DPAA2_QDMA_INFO("No Prefetch RX Mode enabled"); + } else { + dpdmai_dev_dequeue_multijob = + dpdmai_dev_dequeue_multijob_prefetch; + } + if (!dpaa2_coherent_no_alloc_cache) { if (dpaa2_svr_family == SVR_LX2160A) { dpaa2_coherent_no_alloc_cache = @@ -1139,6 +1342,8 @@ static struct rte_dpaa2_driver rte_dpaa2_qdma_pmd = { }; RTE_PMD_REGISTER_DPAA2(dpaa2_qdma, rte_dpaa2_qdma_pmd); +RTE_PMD_REGISTER_PARAM_STRING(dpaa2_qdma, + "no_prefetch= "); RTE_INIT(dpaa2_qdma_init_log) { diff --git a/drivers/raw/dpaa2_qdma/meson.build b/drivers/raw/dpaa2_qdma/meson.build index 2a4b69c16..1577946fa 100644 --- a/drivers/raw/dpaa2_qdma/meson.build +++ b/drivers/raw/dpaa2_qdma/meson.build @@ -4,7 +4,7 @@ version = 2 build = dpdk_conf.has('RTE_LIBRTE_DPAA2_MEMPOOL') -deps += ['rawdev', 'mempool_dpaa2', 'ring'] +deps += ['rawdev', 'mempool_dpaa2', 'ring', 'kvargs'] sources = files('dpaa2_qdma.c') allow_experimental_apis = true