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[209.132.180.67]) by mx.google.com with ESMTP id k24si16269162pgf.294.2019.04.03.22.10.49; Wed, 03 Apr 2019 22:10:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TVrlYzkJ; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727057AbfDDFKs (ORCPT + 7 others); Thu, 4 Apr 2019 01:10:48 -0400 Received: from mail-pf1-f195.google.com ([209.85.210.195]:34201 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727053AbfDDFKs (ORCPT ); Thu, 4 Apr 2019 01:10:48 -0400 Received: by mail-pf1-f195.google.com with SMTP id b3so746881pfd.1 for ; Wed, 03 Apr 2019 22:10:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KklAnXYLBcaWUwOXv3w+NPnCSqij3vKIBVWvRjd2T1M=; b=TVrlYzkJah4xdZ0w8EvrnSm/BK2kbCUs+gYrh4qHXuTB+9XfnOKDUijzhXIOhYcCQ1 lMWLSiwQm+HBmQ8e4X8RqpPvj65Nem5N7MMVM86i766VY6p6IXLsPIDlRbHoOoXhjrkM i41Ogs62ITdcsCP4H3olAyjjOUko92YbM/gLAPKf3PBVt/OaCvR34FNNUfU/GGNzxrDt 4dK87LDFQXJLL/EefUGM7xmBQ9sKFFy/Np27g9F+KAJFqgzDyy3t5QGS+0VMhXbPKQwv Dkb9xcd4wT7vQL5n7o1j4Ra+ue6z78MoWYjjfcBc4E1tnEXZ3IG9Y1v+bcdpW/aD3CTf rdPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KklAnXYLBcaWUwOXv3w+NPnCSqij3vKIBVWvRjd2T1M=; b=GmTIXdXfM4Nzr4bP9mHb0bUDN5o+gHMQ7WBe1zNSfzTlniQD4R7MftpSzLEbty8JWJ lP+K3XgHJvSCJgYqB10SI+o5tB28UqApbIJWA7NaGF2DZ8z/rtjwKCBfuKT22xru2ObJ ntmpdPVu2xFkjuCupsVB1kaOqBpOR/3qXEGQYKGL4oSQ7ibuFyJN60JbO0HIxePfp8H5 86Ri6sBCkfFNhzpOMo6RPyYsnM6mrPPV9HGzOcw+D6t47wQw5j9/Dw/VZHuePFX+kGOa CvCN5/RO12YZdJz/AB2thGSDInIGlRWHzjZuB6KlOWN86Q4eYmPZ5Zgx+7Uh3qkm7St4 uzZQ== X-Gm-Message-State: APjAAAWwoNr+4jyuyDKzBxFqm7kndHDcFa0MTuVqqnRPe2/oqAZP2lh8 40SZggRZ4SfzWqCVT4HUpXZjlg== X-Received: by 2002:a62:1318:: with SMTP id b24mr3620039pfj.201.1554354647500; Wed, 03 Apr 2019 22:10:47 -0700 (PDT) Received: from centauri.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id g64sm43254361pfg.13.2019.04.03.22.10.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 Apr 2019 22:10:46 -0700 (PDT) From: Niklas Cassel To: Rob Herring , Mark Rutland , Jorge Ramirez-Ortiz , Niklas Cassel Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 7/9] dt-bindings: power: avs: Add support for CPR (Core Power Reduction) Date: Thu, 4 Apr 2019 07:09:28 +0200 Message-Id: <20190404050931.9812-8-niklas.cassel@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190404050931.9812-1-niklas.cassel@linaro.org> References: <20190404050931.9812-1-niklas.cassel@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT bindings to describe the CPR HW found on certain Qualcomm SoCs. Co-developed-by: Jorge Ramirez-Ortiz Signed-off-by: Jorge Ramirez-Ortiz Signed-off-by: Niklas Cassel --- .../bindings/power/avs/qcom,cpr.txt | 119 ++++++++++++++++++ 1 file changed, 119 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/avs/qcom,cpr.txt -- 2.20.1 diff --git a/Documentation/devicetree/bindings/power/avs/qcom,cpr.txt b/Documentation/devicetree/bindings/power/avs/qcom,cpr.txt new file mode 100644 index 000000000000..541c9b31cd3b --- /dev/null +++ b/Documentation/devicetree/bindings/power/avs/qcom,cpr.txt @@ -0,0 +1,119 @@ +QCOM CPR (Core Power Reduction) + +CPR (Core Power Reduction) is a technology to reduce core power on a CPU +or other device. Each OPP of a device corresponds to a "corner" that has +a range of valid voltages for a particular frequency. While the device is +running at a particular frequency, CPR monitors dynamic factors such as +temperature, etc. and suggests adjustments to the voltage to save power +and meet silicon characteristic requirements. + +- compatible: + Usage: required + Value type: + Definition: must be "qcom,cpr" + +- reg: + Usage: required + Value type: + Definition: base address and size of the rbcpr register region + +- interrupts: + Usage: required + Value type: + Definition: list of three interrupts in order of irq0, irq1, irq2 + +- acc-syscon: + Usage: optional + Value type: + Definition: phandle to syscon for writing ACC settings + +- nvmem: + Usage: required + Value type: + Definition: phandle to nvmem provider containing efuse settings + +- nvmem-names: + Usage: required + Value type: + Definition: must be "qfprom" + +vdd-mx-supply = <&pm8916_l3>; + +- qcom,cpr-ref-clk: + Usage: required + Value type: + Definition: rate of reference clock in kHz + +- qcom,cpr-timer-delay-us: + Usage: required + Value type: + Definition: delay in uS for the timer interval + +- qcom,cpr-timer-cons-up: + Usage: required + Value type: + Definition: Consecutive number of timer intervals, or units of + qcom,cpr-timer-delay-us, that occur before issuing an up + interrupt + +- qcom,cpr-timer-cons-down: + Usage: required + Value type: + Definition: Consecutive number of timer intervals, or units of + qcom,cpr-timer-delay-us, that occur before issuing a down + interrupt + +- qcom,cpr-up-threshold: + Usage: optional + Value type: + Definition: The threshold for CPR to issue interrupt when error_steps + is greater than it when stepping up + +- qcom,cpr-down-threshold: + Usage: optional + Value type: + Definition: The threshold for CPR to issue interrdownt when error_steps + is greater than it when stepping down + +- qcom,cpr-down-threshold: + Usage: optional + Value type: + Definition: Idle clock cycles ring oscillator can be in + +- qcom,cpr-gcnt-us: + Usage: required + Value type: + Definition: The time for gate count in uS + +- qcom,vdd-apc-step-up-limit: + Usage: required + Value type: + Definition: Limit of vdd-apc-supply steps for scaling up + +- qcom,vdd-apc-step-down-limit: + Usage: required + Value type: + Definition: Limit of vdd-apc-supply steps for scaling down + +Example: + + avs@b018000 { + compatible = "qcom,cpr"; + reg = <0xb018000 0x1000>; + interrupts = <0 15 1>, <0 16 1>, <0 17 1>; + vdd-mx-supply = <&pm8916_l3>; + acc-syscon = <&tcsr>; + nvmem = <&qfprom>; + nvmem-names = "qfprom"; + + qcom,cpr-ref-clk = <19200>; + qcom,cpr-timer-delay-us = <5000>; + qcom,cpr-timer-cons-up = <0>; + qcom,cpr-timer-cons-down = <2>; + qcom,cpr-up-threshold = <0>; + qcom,cpr-down-threshold = <2>; + qcom,cpr-idle-clocks = <15>; + qcom,cpr-gcnt-us = <1>; + qcom,vdd-apc-step-up-limit = <1>; + qcom,vdd-apc-step-down-limit = <1>; + };