From patchwork Thu Apr 4 05:09:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 161742 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1155565jan; Wed, 3 Apr 2019 22:09:55 -0700 (PDT) X-Google-Smtp-Source: APXvYqzaxXQlKDrqvJ92DXHFcgSd9LfTbxSf5HYYEfwID01p4afEY+imSqRcz2oXjtTZqushzcPf X-Received: by 2002:aa7:86ce:: with SMTP id h14mr3786984pfo.84.1554354594968; Wed, 03 Apr 2019 22:09:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554354594; cv=none; d=google.com; s=arc-20160816; b=yxTMkA91cCUiIfZmS9CHMkzH9JCfmZJgWI78pD0DBlP4u9s3TUoyINTxY8BjyXbnl6 YHPOKEMm+pk8uG8u7HQhGdOqpXhMPPH7bj+yZO7vFSco0aagdRwpU/C9lK5aIvAUVCCF 7u0r9fOjsdNLpSC4tZztn4RSvsYTl0r5DHUqRR4pTIzbMkNeEMt+ZKH8/V7E5Sr4oEZa OkunxSDT8WzddRYAcOuHoRl4AkC8XPUzkpyyFNH7WAW4J2x8z9o1FkzAV6DxMNqvCvPC k0Qf9ZbbUxngkD52Z4R9+O27OivirEl1xfeB7AVnCobfyaPFJ4FjlLz5Mq9MedZH3GO+ EMvA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=fMDysyCfwc+hqRyd1PaEzIvcoRjPHOAd89SSQWs92AE=; b=G2VKXYOMJHW2nM6LArtGKhWSHBxuYYLfU0Ya6oX0o7pVfdvbfcWZeo3YEnuyzujq/Y N+dmNTCFuQkug5YeWzePY8Wy1P3x6qFzS93rgb9TG9l/HzmOlFrkFQT1N5XdECcPUSvt wZINwdKW0U3of5nx0+3CN0fVSFUr6R7T8RtMdviG5v10lUtdpOzXq2xdNgWeXHj7F6aU HvKmfNdRA2li2AmL2CyagjCvXPuMAn2VQIzJF0QZ+/gsZOS6FawM7knKSDsMXcYoz/s6 Juqwto76zSj+W5XLdpfHf3cYnF08Es+PrQYQ9vKGLD5SBmNFEgnYL93TVxDC9gBSOm2N iETA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=j4VCF7jN; spf=pass (google.com: best guess record for domain of linux-pm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-pm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t26si15227330pgu.504.2019.04.03.22.09.54; Wed, 03 Apr 2019 22:09:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-pm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=j4VCF7jN; spf=pass (google.com: best guess record for domain of linux-pm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-pm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726735AbfDDFJx (ORCPT + 11 others); Thu, 4 Apr 2019 01:09:53 -0400 Received: from mail-pl1-f195.google.com ([209.85.214.195]:41142 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726702AbfDDFJx (ORCPT ); Thu, 4 Apr 2019 01:09:53 -0400 Received: by mail-pl1-f195.google.com with SMTP id d1so541956plj.8 for ; Wed, 03 Apr 2019 22:09:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fMDysyCfwc+hqRyd1PaEzIvcoRjPHOAd89SSQWs92AE=; b=j4VCF7jNaQuAIxsT208+FINDEMJxnPuSDb2EXPaui8Zl+KIldPJ1m+9v5OSffLiBkJ DFwz0eOr11NO5R96lmrYaqbN/6hoXyDFZYi/lyg4DVBVvFHviraL9nY3nEUt7HtS6Hex 40wdw1A1hfeChUp4PqbtD8tmurgivN0Tb8Dyh8tYjMtTno8XkKJjBHudK+XAqlw/I6uf IhORxDw//DYuN4yngj92UaaRGEFH0MQ7PBTFz26MueqwbPP78cIVO3XdYVQ3DzOXh9LK 5+rbh+8uB1jcA6LxPCTniS16BqxP4nQ35Rw7EUSo19I1LsheNDhQy391LHVTYwRpRmL7 rUxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fMDysyCfwc+hqRyd1PaEzIvcoRjPHOAd89SSQWs92AE=; b=WWwclduR5BhoZe+D3VgCMncUkRGkCP+jUhNSc2hRV2+RvPxyqRlYU9aGayWi4KZTEg 2YOpS03G1i9rJBX2EROpBhDw4jMDb14LQqzeoIQDNMA3MDXvE0tEy9GYDGkC3Fl95vVj /Gd5vNv6Wm3A3b6PKx+a6fjeQvpsWfkBnj5tvRaL6cy2DBzezd2aux3MFRdPhpDA20u8 OWaPTFL0RQMYWs7SBZUy+SK5hF+dWPMMiwBJyplHpTWFijU6rBBe5cbKTX+6+cRrAjdN MvEODIe+qx2IMN2rY9ttSDv/sfeJaV7XmgOXZjfaLuLoIXthZCnFhasIInmhc2+MIZYL ZIUA== X-Gm-Message-State: APjAAAXFFeXyHqSRbM+K4DKTkqTL/aKSibYmeyJqQoff7ZbgkBr85rXx /MRDOSO2SQNsD+dzBKv7+HNreg== X-Received: by 2002:a17:902:54f:: with SMTP id 73mr4154967plf.210.1554354592375; Wed, 03 Apr 2019 22:09:52 -0700 (PDT) Received: from centauri.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id a129sm50589089pfa.152.2019.04.03.22.09.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 Apr 2019 22:09:51 -0700 (PDT) From: Niklas Cassel To: Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Rob Herring , Mark Rutland , Andy Gross , David Brown , "Rafael J. Wysocki" Cc: linux-arm-msm@vger.kernel.org, jorge.ramirez-ortiz@linaro.org, Sricharan R , Niklas Cassel , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 2/9] cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem based qcom socs Date: Thu, 4 Apr 2019 07:09:23 +0200 Message-Id: <20190404050931.9812-3-niklas.cassel@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190404050931.9812-1-niklas.cassel@linaro.org> References: <20190404050931.9812-1-niklas.cassel@linaro.org> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Sricharan R The kryo cpufreq driver reads the nvmem cell and uses that data to populate the opps. There are other qcom cpufreq socs like krait which does similar thing. Except for the interpretation of the read data, rest of the driver is same for both the cases. So pull the common things out for reuse. Signed-off-by: Sricharan R Signed-off-by: Niklas Cassel --- ...ryo-cpufreq.txt => qcom-nvmem-cpufreq.txt} | 16 +-- drivers/cpufreq/Kconfig.arm | 4 +- drivers/cpufreq/Makefile | 2 +- ...om-cpufreq-kryo.c => qcom-cpufreq-nvmem.c} | 124 +++++++++++------- 4 files changed, 85 insertions(+), 61 deletions(-) rename Documentation/devicetree/bindings/opp/{kryo-cpufreq.txt => qcom-nvmem-cpufreq.txt} (97%) rename drivers/cpufreq/{qcom-cpufreq-kryo.c => qcom-cpufreq-nvmem.c} (69%) -- 2.20.1 diff --git a/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt similarity index 97% rename from Documentation/devicetree/bindings/opp/kryo-cpufreq.txt rename to Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt index c2127b96805a..f4a7123730c3 100644 --- a/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt +++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt @@ -1,13 +1,13 @@ -Qualcomm Technologies, Inc. KRYO CPUFreq and OPP bindings +Qualcomm Technologies, Inc. NVMEM CPUFreq and OPP bindings =================================== -In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996 -that have KRYO processors, the CPU ferequencies subset and voltage value -of each OPP varies based on the silicon variant in use. +In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996, +the CPU frequencies subset and voltage value of each OPP varies based on +the silicon variant in use. Qualcomm Technologies, Inc. Process Voltage Scaling Tables defines the voltage and frequency value based on the msm-id in SMEM and speedbin blown in the efuse combination. -The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC +The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC to provide the OPP framework with required information (existing HW bitmap). This is used to determine the voltage and frequency value for each OPP of operating-points-v2 table when it is parsed by the OPP framework. @@ -19,7 +19,7 @@ In 'cpus' nodes: In 'operating-points-v2' table: - compatible: Should be - - 'operating-points-v2-kryo-cpu' for apq8096 and msm8996. + - 'operating-points-v2-qcom-cpu' for apq8096 and msm8996. - nvmem-cells: A phandle pointing to a nvmem-cells node representing the efuse registers that has information about the speedbin that is used to select the right frequency/voltage @@ -127,7 +127,7 @@ Example 1: }; cluster0_opp: opp_table0 { - compatible = "operating-points-v2-kryo-cpu"; + compatible = "operating-points-v2-qcom-cpu"; nvmem-cells = <&speedbin_efuse>; opp-shared; @@ -338,7 +338,7 @@ Example 1: }; cluster1_opp: opp_table1 { - compatible = "operating-points-v2-kryo-cpu"; + compatible = "operating-points-v2-qcom-cpu"; nvmem-cells = <&speedbin_efuse>; opp-shared; diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index 179a1d302f48..2e4aefa0f34d 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -110,8 +110,8 @@ config ARM_OMAP2PLUS_CPUFREQ depends on ARCH_OMAP2PLUS default ARCH_OMAP2PLUS -config ARM_QCOM_CPUFREQ_KRYO - tristate "Qualcomm Kryo based CPUFreq" +config ARM_QCOM_CPUFREQ_NVMEM + tristate "Qualcomm nvmem based CPUFreq" depends on ARM64 depends on QCOM_QFPROM depends on QCOM_SMEM diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile index 689b26c6f949..8e83fd73bd2d 100644 --- a/drivers/cpufreq/Makefile +++ b/drivers/cpufreq/Makefile @@ -63,7 +63,7 @@ obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o obj-$(CONFIG_ARM_QCOM_CPUFREQ_HW) += qcom-cpufreq-hw.o -obj-$(CONFIG_ARM_QCOM_CPUFREQ_KRYO) += qcom-cpufreq-kryo.o +obj-$(CONFIG_ARM_QCOM_CPUFREQ_NVMEM) += qcom-cpufreq-nvmem.o obj-$(CONFIG_ARM_S3C2410_CPUFREQ) += s3c2410-cpufreq.o obj-$(CONFIG_ARM_S3C2412_CPUFREQ) += s3c2412-cpufreq.o obj-$(CONFIG_ARM_S3C2416_CPUFREQ) += s3c2416-cpufreq.o diff --git a/drivers/cpufreq/qcom-cpufreq-kryo.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c similarity index 69% rename from drivers/cpufreq/qcom-cpufreq-kryo.c rename to drivers/cpufreq/qcom-cpufreq-nvmem.c index dd64dcf89c74..652a1de2a5d4 100644 --- a/drivers/cpufreq/qcom-cpufreq-kryo.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -9,7 +9,7 @@ * based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables * defines the voltage and frequency value based on the msm-id in SMEM * and speedbin blown in the efuse combination. - * The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC + * The qcom-cpufreq driver reads the msm-id and efuse value from the SoC * to provide the OPP framework with required information. * This is used to determine the voltage and frequency value for each OPP of * operating-points-v2 table when it is parsed by the OPP framework. @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -42,9 +43,9 @@ enum _msm8996_version { NUM_OF_MSM8996_VERSIONS, }; -static struct platform_device *cpufreq_dt_pdev, *kryo_cpufreq_pdev; +static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev; -static enum _msm8996_version qcom_cpufreq_kryo_get_msm_id(void) +static enum _msm8996_version qcom_cpufreq_get_msm_id(void) { size_t len; u32 *msm_id; @@ -73,34 +74,68 @@ static enum _msm8996_version qcom_cpufreq_kryo_get_msm_id(void) return version; } -static int qcom_cpufreq_kryo_probe(struct platform_device *pdev) +static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev, + struct nvmem_cell *speedbin_nvmem, + u32 *versions) { - struct opp_table **opp_tables; + size_t len; + u8 *speedbin; enum _msm8996_version msm8996_version; + + msm8996_version = qcom_cpufreq_get_msm_id(); + if (NUM_OF_MSM8996_VERSIONS == msm8996_version) { + dev_err(cpu_dev, "Not Snapdragon 820/821!"); + return -ENODEV; + } + + speedbin = nvmem_cell_read(speedbin_nvmem, &len); + if (IS_ERR(speedbin)) + return PTR_ERR(speedbin); + + switch (msm8996_version) { + case MSM8996_V3: + *versions = 1 << (unsigned int)(*speedbin); + break; + case MSM8996_SG: + *versions = 1 << ((unsigned int)(*speedbin) + 4); + break; + default: + BUG(); + break; + } + + kfree(speedbin); + return 0; +} + +static int qcom_cpufreq_probe(struct platform_device *pdev) +{ + struct opp_table **opp_tables; + int (*get_version)(struct device *cpu_dev, + struct nvmem_cell *speedbin_nvmem, + u32 *versions); struct nvmem_cell *speedbin_nvmem; struct device_node *np; struct device *cpu_dev; unsigned cpu; - u8 *speedbin; u32 versions; - size_t len; + const struct of_device_id *match; int ret; cpu_dev = get_cpu_device(0); if (!cpu_dev) return -ENODEV; - msm8996_version = qcom_cpufreq_kryo_get_msm_id(); - if (NUM_OF_MSM8996_VERSIONS == msm8996_version) { - dev_err(cpu_dev, "Not Snapdragon 820/821!"); + match = pdev->dev.platform_data; + get_version = match->data; + if (!get_version) return -ENODEV; - } np = dev_pm_opp_of_get_opp_desc_node(cpu_dev); if (!np) return -ENOENT; - ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu"); + ret = of_device_is_compatible(np, "operating-points-v2-qcom-cpu"); if (!ret) { of_node_put(np); return -ENOENT; @@ -115,23 +150,10 @@ static int qcom_cpufreq_kryo_probe(struct platform_device *pdev) return PTR_ERR(speedbin_nvmem); } - speedbin = nvmem_cell_read(speedbin_nvmem, &len); + ret = get_version(cpu_dev, speedbin_nvmem, &versions); nvmem_cell_put(speedbin_nvmem); - if (IS_ERR(speedbin)) - return PTR_ERR(speedbin); - - switch (msm8996_version) { - case MSM8996_V3: - versions = 1 << (unsigned int)(*speedbin); - break; - case MSM8996_SG: - versions = 1 << ((unsigned int)(*speedbin) + 4); - break; - default: - BUG(); - break; - } - kfree(speedbin); + if (ret) + return ret; opp_tables = kcalloc(num_possible_cpus(), sizeof(*opp_tables), GFP_KERNEL); if (!opp_tables) @@ -174,7 +196,7 @@ static int qcom_cpufreq_kryo_probe(struct platform_device *pdev) return ret; } -static int qcom_cpufreq_kryo_remove(struct platform_device *pdev) +static int qcom_cpufreq_remove(struct platform_device *pdev) { struct opp_table **opp_tables = platform_get_drvdata(pdev); unsigned int cpu; @@ -189,18 +211,20 @@ static int qcom_cpufreq_kryo_remove(struct platform_device *pdev) return 0; } -static struct platform_driver qcom_cpufreq_kryo_driver = { - .probe = qcom_cpufreq_kryo_probe, - .remove = qcom_cpufreq_kryo_remove, +static struct platform_driver qcom_cpufreq_driver = { + .probe = qcom_cpufreq_probe, + .remove = qcom_cpufreq_remove, .driver = { - .name = "qcom-cpufreq-kryo", + .name = "qcom-cpufreq", }, }; -static const struct of_device_id qcom_cpufreq_kryo_match_list[] __initconst = { - { .compatible = "qcom,apq8096", }, - { .compatible = "qcom,msm8996", }, - {} +static const struct of_device_id qcom_cpufreq_match_list[] __initconst = { + { .compatible = "qcom,apq8096", + .data = qcom_cpufreq_kryo_name_version }, + { .compatible = "qcom,msm8996", + .data = qcom_cpufreq_kryo_name_version }, + {}, }; /* @@ -209,7 +233,7 @@ static const struct of_device_id qcom_cpufreq_kryo_match_list[] __initconst = { * which may be defered as well. The init here is only registering * the driver and the platform device. */ -static int __init qcom_cpufreq_kryo_init(void) +static int __init qcom_cpufreq_init(void) { struct device_node *np = of_find_node_by_path("/"); const struct of_device_id *match; @@ -218,32 +242,32 @@ static int __init qcom_cpufreq_kryo_init(void) if (!np) return -ENODEV; - match = of_match_node(qcom_cpufreq_kryo_match_list, np); + match = of_match_node(qcom_cpufreq_match_list, np); of_node_put(np); if (!match) return -ENODEV; - ret = platform_driver_register(&qcom_cpufreq_kryo_driver); + ret = platform_driver_register(&qcom_cpufreq_driver); if (unlikely(ret < 0)) return ret; - kryo_cpufreq_pdev = platform_device_register_simple( - "qcom-cpufreq-kryo", -1, NULL, 0); - ret = PTR_ERR_OR_ZERO(kryo_cpufreq_pdev); + cpufreq_pdev = platform_device_register_data(NULL, "qcom-cpufreq", + -1, match, sizeof(*match)); + ret = PTR_ERR_OR_ZERO(cpufreq_pdev); if (0 == ret) return 0; - platform_driver_unregister(&qcom_cpufreq_kryo_driver); + platform_driver_unregister(&qcom_cpufreq_driver); return ret; } -module_init(qcom_cpufreq_kryo_init); +module_init(qcom_cpufreq_init); -static void __exit qcom_cpufreq_kryo_exit(void) +static void __exit qcom_cpufreq_exit(void) { - platform_device_unregister(kryo_cpufreq_pdev); - platform_driver_unregister(&qcom_cpufreq_kryo_driver); + platform_device_unregister(cpufreq_pdev); + platform_driver_unregister(&qcom_cpufreq_driver); } -module_exit(qcom_cpufreq_kryo_exit); +module_exit(qcom_cpufreq_exit); -MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Kryo CPUfreq driver"); +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. CPUfreq driver"); MODULE_LICENSE("GPL v2"); From patchwork Thu Apr 4 05:09:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 161744 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1155955jan; Wed, 3 Apr 2019 22:10:18 -0700 (PDT) X-Google-Smtp-Source: APXvYqze/C5+zgEwpux3YABwYFEQX/oCkxrcImLlubXflV92yqLAH4qFU8AC4TrDxN+j71WMSoDh X-Received: by 2002:a17:902:e912:: with SMTP id cs18mr4233610plb.130.1554354618339; Wed, 03 Apr 2019 22:10:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554354618; cv=none; d=google.com; s=arc-20160816; b=SDgMxXFK/qDM+zV4VnBUoIvsKJcIm5unHrnCo26MjRcUoWIadnRyoY08EYKi0RB/K3 5FAhWVyxvR3AG5AWfn3NSyY8d2zIwUoXXIgbiO4h61xR9jDGwSrac83zViLrNrduQdcU JMgk30hs3gVzUFr4FhyLdGuTT/rlbRc4YA9un6VExZUwcO2zXhwM2hur5FZS7guyNlpf NyJ98E4oCxM8XhL9TRmyIrn+C7gRjl6XwcKrFZQR6vXcgdG7ouEcDrgsxrIVesdl5TUT 39TL13ijOEffYhqpTgeJ1/FJlP9ZvHBqvDrAXGipP6PVoafSAJGdTGscxoEsNF3DCPpP xuyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=mdOJYDtANreHncbeef90zrWtNG5DJsKAdH3zS7ujZ1U=; b=l2b3YN9d5rpGGivqh65bzcy4LHb81rRCN9a6rnpk7XBcTR2C9Nt2T6hKPf/eMEwwBn Zs2DCTArGIMNayqQbSp7Upn8hql3CJTqFu8ZueZbLmsQWu8s24oQejM4DIgP+9SDGU9b TIk+6zRyoubfpF1PAcwH+dAcsgY3Vr+lyzJH8ngsQN87VAV2/cjqpQ0KYq4xvYjp8YS4 4PlBNHvMVTEYvtKpC3wDz5VjUSbSxStBEqcTiHDPSQoSHWGGoZVhyVcv5FRNk4WGVKYC 2Gi7b9mHyBDXNM3L1C1nnJrz085ZwzCGKpxVSDBq+wW7VC6L7FlVUL0qyV0Rkksbd6O4 BYUQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=I3r7GRr+; spf=pass (google.com: best guess record for domain of linux-pm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-pm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g6si15003567pgq.506.2019.04.03.22.10.18; Wed, 03 Apr 2019 22:10:18 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-pm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=I3r7GRr+; spf=pass (google.com: best guess record for domain of linux-pm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-pm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726902AbfDDFKR (ORCPT + 11 others); Thu, 4 Apr 2019 01:10:17 -0400 Received: from mail-pf1-f196.google.com ([209.85.210.196]:45878 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726827AbfDDFKQ (ORCPT ); Thu, 4 Apr 2019 01:10:16 -0400 Received: by mail-pf1-f196.google.com with SMTP id e24so717172pfi.12 for ; Wed, 03 Apr 2019 22:10:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mdOJYDtANreHncbeef90zrWtNG5DJsKAdH3zS7ujZ1U=; b=I3r7GRr+snPvFd86Mi8jhruOQUNWmdQmm7b7ecIcS4EHj+oanQWssoHtBXIkn+SnYs 0w73rCjZadVrqKxbWQAnB/YE8hVEXIEYZBybv5CJ+9iP5+xbfx4F/G5Yih5yIEJhu+uQ twbx3KiZqUOw30D/xSZ/Ry7bQwQ6y72jCZZ/2NCipPOAbkr1JOr0Bazn0lybvp5H34aZ T0XlScQ5jVShxh+p6UdaUhudPIJ9nIIwGOMd7HYJOpIsZCmzxD3yQY63DukRrvyplI5X mJev8i1yZg9q2PAox8OImn78RPANFXIEPBDJp4pi3QvnN1s9nChyPuxt6We/gHlQoKO5 U7Sg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mdOJYDtANreHncbeef90zrWtNG5DJsKAdH3zS7ujZ1U=; b=iOI2WfhXFkF+1IfJSMBq6lRPWBHt5mCLSFhNMqG/2/juqqSJrnsp+uHYrWBhIrKFMo mLmldzg2hqgv51RaRj+wbwi/V59uYfUc+EssFxz4zUA62j6Vj2IYMByuj+J7Ys0/6vxF hWkujA9PZLMWweNPQoyc/pXyV1+UchDQboaAkJUib8pzJ1IfWGptMEGMn179RjavGhx4 jomYdLwe8+4vLGDmAs1wBGSKEQ9v+lGfx6wBTnTICM/UePXjwZ1ovudvm2eaeBMO0qES 423xhsoYaq5GeRIxoa8Hje0cOizM7RtsK5YxWCsb8WZgp9c0FBNLh0g/jmACcSQN07ol 8BcA== X-Gm-Message-State: APjAAAVrffC8mGgBcBjpuMe7H5KTj0+J4vJanQBFc1aiXYC97OqTfJJh 7yONT9m8nreuxhVS3H2/LcZMCg== X-Received: by 2002:a63:6fcd:: with SMTP id k196mr3772020pgc.238.1554354616065; Wed, 03 Apr 2019 22:10:16 -0700 (PDT) Received: from centauri.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id q80sm27623011pfa.66.2019.04.03.22.10.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 Apr 2019 22:10:15 -0700 (PDT) From: Niklas Cassel To: Andy Gross , David Brown , "Rafael J. Wysocki" , Viresh Kumar Cc: linux-arm-msm@vger.kernel.org, jorge.ramirez-ortiz@linaro.org, Niklas Cassel , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 4/9] cpufreq: qcom: support qcs404 on nvmem driver Date: Thu, 4 Apr 2019 07:09:25 +0200 Message-Id: <20190404050931.9812-5-niklas.cassel@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190404050931.9812-1-niklas.cassel@linaro.org> References: <20190404050931.9812-1-niklas.cassel@linaro.org> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Jorge Ramirez-Ortiz Signed-off-by: Jorge Ramirez-Ortiz Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel --- drivers/cpufreq/qcom-cpufreq-nvmem.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) -- 2.20.1 diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c index 366c65a7132a..7fdc38218390 100644 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -79,6 +80,13 @@ static enum _msm8996_version qcom_cpufreq_get_msm_id(void) return version; } +static int qcom_cpufreq_qcs404_name_version(struct device *cpu_dev, + struct nvmem_cell *speedbin_nvmem, + struct qcom_cpufreq_drv *drv) +{ + return 0; +} + static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev, struct nvmem_cell *speedbin_nvmem, struct qcom_cpufreq_drv *drv) @@ -191,6 +199,14 @@ static int qcom_cpufreq_probe(struct platform_device *pdev) dev_err(cpu_dev, "Failed to set supported hardware\n"); goto free_opp; } + + ret = dev_pm_domain_attach(cpu_dev, false); + if (ret) { + if (ret == -EPROBE_DEFER) + goto free_opp; + dev_err(cpu_dev, "Could not attach to pm_domain: %d\n", + ret); + } } cpufreq_dt_pdev = platform_device_register_simple("cpufreq-dt", -1, @@ -247,6 +263,8 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst = { .data = qcom_cpufreq_kryo_name_version }, { .compatible = "qcom,msm8996", .data = qcom_cpufreq_kryo_name_version }, + { .compatible = "qcom,qcs404", + .data = qcom_cpufreq_qcs404_name_version }, {}, }; From patchwork Thu Apr 4 05:09:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 161746 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1156294jan; Wed, 3 Apr 2019 22:10:42 -0700 (PDT) X-Google-Smtp-Source: APXvYqze7ZwrFUyJwdO58QcIsWbj6JzyyXVsey2FaSHDPUrBoeN6jtoAit8CsSfOfrmDz2u8gBTa X-Received: by 2002:a63:fd07:: with SMTP id d7mr3796959pgh.199.1554354642128; Wed, 03 Apr 2019 22:10:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554354642; cv=none; d=google.com; s=arc-20160816; b=bHVOxUw+zfGrcvtMpv9UGlKEac2yfCP9/RxZFCOpUpLzQZhAYP9u6aEZfqsddfKzmQ srOvE3PIvZdw56T3p1v33PXy5K4PNyXZeSyuSwhoWGClhRWDmVjKfGYU64dlqaodR8pD Bt3XKhPQS9PUL4vObcjPD4VL+NyR1fH0Df9tVqYZmdhvI2H4fPXfpHh7a7SbalSiTZ29 9WcwNax49BnujVplbv1Gjfj6c28NX+Du6klqVHLhq8bnkt57tsn3l9vxQ6ajOwLG7cqh p8uTVleEBzryi+hvx6zBuAjZRy9VOPMtmnynZi2X0WcH506eFFGER/lLTJMrMj7NaSZb zeJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=5f+kkMUgvOOpOd6cTF9Ie+6FOr6453kj1E1ya/v5Za8=; b=t3HfH+nDPhFQ1I2iHB12Qq+cNYDjs+meSZ6SOahM+zZaOJxsM5XzRqKT/vG2CaWImR +EqMJu6Sf1SPgTn2oN5kbE0wHLGX1y8oMjVd6TKPwZj5EqENPd450ZVhJmoYnl2mRxy/ j03jvPG+G9S8LPxnMi3avJf/Hf/pnDKS0GCHzwx/RShhQ8aLaQtvohkkSbaVw+V4DPHt nJYkM2l81xaIB/fKg/35UhmB7+KWN7qF7DFhWYqm8+8VJL7JlnJdTiMnVRILJC+hYIU0 7PLz5k8eAEgaKEWjh8ndiwigw3rLYoDWfA00X9tkFa630xGdkVXblZ0wuSwEX+PsZqpR YuKQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OQusTV+s; spf=pass (google.com: best guess record for domain of linux-pm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-pm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j25si15509246pgb.531.2019.04.03.22.10.41; Wed, 03 Apr 2019 22:10:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-pm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OQusTV+s; spf=pass (google.com: best guess record for domain of linux-pm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-pm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727021AbfDDFKl (ORCPT + 11 others); Thu, 4 Apr 2019 01:10:41 -0400 Received: from mail-pf1-f194.google.com ([209.85.210.194]:34191 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726693AbfDDFKl (ORCPT ); Thu, 4 Apr 2019 01:10:41 -0400 Received: by mail-pf1-f194.google.com with SMTP id b3so746737pfd.1 for ; Wed, 03 Apr 2019 22:10:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5f+kkMUgvOOpOd6cTF9Ie+6FOr6453kj1E1ya/v5Za8=; b=OQusTV+sLzBgbuQim/aJBTk/xjcBPTqYlFT9scR6O8fYzA0i29sdhhV5Jnxg81dPHL MwAFl+bs31OrLE9iQXLisbdttm0uhX7lBVJOLlI3joGVjmPJ6uPi0qF4Tt8gAR7JbWdZ SvVAnPMZu0ZxSSXF9Ap7xv/YSNby0tIJIqwSeSjlSl6zskXvNpgv5CAofOoQf3BRztZ+ y+LYNuu4+wmQ32CfLWWUzCnFzLJPWclgKOPHXyxiwJitkTI8+9f8jv37IfGfhgQLMUIV k+yDCnbs4xXT2c2ttyqaycOFf5Kt5efXpoxaXHPnnFSUnBRN+2LZ034sjgPgD3U0wydF FwOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5f+kkMUgvOOpOd6cTF9Ie+6FOr6453kj1E1ya/v5Za8=; b=Nzr0ptJHHfu7m75sXCywyhmu5OBM+lqHw2TszYWr5aAwB2kGt7V6mbeQF3Toz9RFr/ +6KArM/o/E0ncDk3ZLnbGUGrGUVnn/Pt2w7tOQdf63UPZeyjL5JccilLaUcVycG6OKG4 QiuuJRg+D5FsvJn1BCw2PYXs7RWJGdLtZpknz0bYnRv6Tn4LXcc8xgC39bbuybfIjBuu dhYA7CssCuQ7pLHPRMgzgeZl0x2ycdQ0ZQdWSEKEr+abIRPOTSe9OD0dooh1uA0LzyM0 dVmlmOdCGVt83BQsK6gQWKiHzV1xBwZZYX4HmCZklByzCDTIBX2l/oMhH3mh755SKjRt YgIw== X-Gm-Message-State: APjAAAVQB0NM5NBK6MC67BkmGrf0CKNMby9xhtbOCzg4XclSBW0dCU6W WnwPn5y+Gbz2dV6Rbecav672Dg== X-Received: by 2002:a63:1064:: with SMTP id 36mr3772475pgq.155.1554354640554; Wed, 03 Apr 2019 22:10:40 -0700 (PDT) Received: from centauri.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id g64sm43254361pfg.13.2019.04.03.22.10.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 Apr 2019 22:10:40 -0700 (PDT) From: Niklas Cassel To: Andy Gross , David Brown , Viresh Kumar , Nishanth Menon , Stephen Boyd , Rob Herring , Mark Rutland Cc: linux-arm-msm@vger.kernel.org, jorge.ramirez-ortiz@linaro.org, Niklas Cassel , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 6/9] dt-bindings: opp: Add qcom-opp bindings with properties needed for CPR Date: Thu, 4 Apr 2019 07:09:27 +0200 Message-Id: <20190404050931.9812-7-niklas.cassel@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190404050931.9812-1-niklas.cassel@linaro.org> References: <20190404050931.9812-1-niklas.cassel@linaro.org> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add qcom-opp bindings with properties needed for Core Power Reduction (CPR). CPR is included in a great variety of Qualcomm SoC, e.g. msm8916 and msm8996, and was first introduced in msm8974. Co-developed-by: Jorge Ramirez-Ortiz Signed-off-by: Jorge Ramirez-Ortiz Signed-off-by: Niklas Cassel --- .../devicetree/bindings/opp/qcom-opp.txt | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/opp/qcom-opp.txt -- 2.20.1 diff --git a/Documentation/devicetree/bindings/opp/qcom-opp.txt b/Documentation/devicetree/bindings/opp/qcom-opp.txt new file mode 100644 index 000000000000..d24280467db7 --- /dev/null +++ b/Documentation/devicetree/bindings/opp/qcom-opp.txt @@ -0,0 +1,24 @@ +Qualcomm OPP bindings to describe OPP nodes + +The bindings are based on top of the operating-points-v2 bindings +described in Documentation/devicetree/bindings/opp/opp.txt +Additional properties are described below. + +* OPP Table Node + +Required properties: +- compatible: Allow OPPs to express their compatibility. It should be: + "operating-points-v2-qcom-level" + +* OPP Node + +Optional properties: +- opp-hz: Frequency in Hz, expressed as a 64-bit big-endian integer. Even + though a power domain doesn't need a opp-hz, there can be devices in the + power domain that need to know the highest supported frequency for each + corner/level (e.g. CPR), in order to properly initialize the hardware. + +- qcom,opp-fuse-level: A positive value representing the fuse corner/level + associated with this OPP node. Sometimes several corners/levels shares + a certain fuse corner/level. A fuse corner/level contains e.g. ref uV, + min uV, and max uV.