From patchwork Thu Apr 4 03:35:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 161720 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1086944jan; Wed, 3 Apr 2019 20:35:55 -0700 (PDT) X-Google-Smtp-Source: APXvYqxU+ARPFdcYo9ls2hZ4xz8sn4lNlz7fwYUIuINZlMAgp/+V9UHi9SA5nYnxrOHemmQ9dt0E X-Received: by 2002:a62:4558:: with SMTP id s85mr3310847pfa.171.1554348955838; Wed, 03 Apr 2019 20:35:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554348955; cv=none; d=google.com; s=arc-20160816; b=CQ/mKGY/FToUPTJ+rGaVpCY+eafMAtaMwOxonVnpdyMCI5AE4YCOgjTYgZILFm63CO HNC9T6nu5KL8LybRBmuwQ6IPv/qKg/xIlJ8NuXg+fYbqOJYve7LyiynT4GJryrR9mluz yeZsW1OuIoN8WHuChW/QG3FRvg3BCUNXbtiPgjk3P73FayVS16uHhvllNszckw63LpO4 vjDjBDLq9H/Yst2mfjFt/092jx33KsalpCmPLq2MEh8rOqgGEqZqRgtH2Ew7EUJGQWSQ 8yiNnwWnk/u8hrFvJhU0G5xouELvPmj+qtB8LScDJTixsgyrEK8ZrJqZAa8FzFsrHgwS Ejgw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=pQJCMdAOcoU1qu2khwRxnoxNDPS67R2CoUeniO+PC88=; b=n/3DgIbyH/dLWEKLNJJ26kUDTGl8ZrcPKYE/l97GJqr+8PUskPvz9Jr70tr2ws4Vy0 0RZwYUn2SgNGG4Y3PEgzT7CVwLyilHWFPmjLgA0iozQqlMONruBnmEUpUkwMmT4lJjPf bBMTBfzjo7oEZidySDwv1SC6WBANrCRSUTlclE6aML3Kvwhw80qn7pyirfEEjT8aNovo /4gR3V+14iE7Q0WNQtGZuQbf1w9eyMzTx/s93S8xacKyNw1OUVUfMqLK7WdHyekpCIJV 5+nYSzUaGXvWs0+jBDBVmkaiE/fJ5ZCwn6XOvqRCbo1DINeKtg2ucxMrDBdsbUJgDP0i /b9A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JG7qosCg; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a64si15856627pge.592.2019.04.03.20.35.55; Wed, 03 Apr 2019 20:35:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JG7qosCg; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726862AbfDDDfy (ORCPT + 31 others); Wed, 3 Apr 2019 23:35:54 -0400 Received: from mail-pf1-f196.google.com ([209.85.210.196]:42264 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726167AbfDDDfx (ORCPT ); Wed, 3 Apr 2019 23:35:53 -0400 Received: by mail-pf1-f196.google.com with SMTP id r15so613974pfn.9 for ; Wed, 03 Apr 2019 20:35:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pQJCMdAOcoU1qu2khwRxnoxNDPS67R2CoUeniO+PC88=; b=JG7qosCgIljTpyMPcpMLIF001Mci7KhIhDxzZNrpV/i1kcDTXgjJ6kbJSb2Dvemp3n Ga8GciIaVKWkZBJCrEsTGGKZGocGG4jFQirf7ktsTDhKh3FYLyA80Rs4go2DlpEXZpiz RlZmzMcetNrU1fLoBHkNkWsMIBNmljfmvCH3x45TM9DA6sC+/bAV1wSrp+88U28W6TlM c3vWSTPz15/4FTtdoodb6FlC95ap7dVUKQp79ClVhkuJj2eZCtGvKB/6HnLirkJTX1z4 iL1aw6pnDdpmLvbsWmMyD98wNnyKfyVsYgEtVrje+1TPi2y+sVF6RuyD5wVlnJm23Lff acuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pQJCMdAOcoU1qu2khwRxnoxNDPS67R2CoUeniO+PC88=; b=q8pT9pgp8UmjoZPmKdHla8UjcNQol7/OnXPoCwDlnPdfltOrVRWX3AP/77CFQKMGZ3 gyajM/sa/xb8jtcWWV1BJGbBUppeud+W2C0Dk8JIS0iYBEXZb1P94cH//quhOqmUVEm/ j3mDeZH0COPkgi8WPBlai2MFnAu6eP6pKw5roCgW8FRZHH+vACzDQ//gA4glLldnKD99 4yP9X5wm+IlL2MSBqsR/fuYxiY3Js4IgP9Ov3ErnhA60bi/jBU0rc1+hxKdMKXYqY3xm aBjdkpQHbkxbUsNC72NbR9tfRiEEQmuC6xZIiXsmolZEZFS5Mr83pmgVGWQfsuR2hEBp N7QA== X-Gm-Message-State: APjAAAX2UAyhOFa94AUlWWXjZR/+zg/VYkV4UXg7TH0TwlMHfFNK2+lV Os87K1y3GPmzw28KX/knE7ymew== X-Received: by 2002:a62:458a:: with SMTP id n10mr3321188pfi.136.1554348952475; Wed, 03 Apr 2019 20:35:52 -0700 (PDT) Received: from xps15.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id u5sm12212780pfm.121.2019.04.03.20.35.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 03 Apr 2019 20:35:51 -0700 (PDT) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org Cc: alexander.shishkin@linux.intel.com, peterz@infradead.org, suzuki.poulose@arm.com, mike.leach@arm.com, leo.yan@linaro.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 01/20] coresight: pmu: Adding ITRACE property to cs_etm PMU Date: Wed, 3 Apr 2019 21:35:22 -0600 Message-Id: <20190404033541.14072-2-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190404033541.14072-1-mathieu.poirier@linaro.org> References: <20190404033541.14072-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add to the capabilities the ITRACE property so that ITRACE START events are generated when the PMU is switched on by the core. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm-perf.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.17.1 Acked-by: Suzuki K Poulose diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index 4d5a2b9f9d6a..25ae56e924bb 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -566,7 +566,8 @@ static int __init etm_perf_init(void) { int ret; - etm_pmu.capabilities = PERF_PMU_CAP_EXCLUSIVE; + etm_pmu.capabilities = (PERF_PMU_CAP_EXCLUSIVE | + PERF_PMU_CAP_ITRACE); etm_pmu.attr_groups = etm_pmu_attr_groups; etm_pmu.task_ctx_nr = perf_sw_context; From patchwork Thu Apr 4 03:35:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 161721 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1086993jan; Wed, 3 Apr 2019 20:36:00 -0700 (PDT) X-Google-Smtp-Source: APXvYqydrzOIB4CTiUkFvqe753IYUijo78OzOrfqSeE5H38y3cXF8iHe1EU/YY03pQqhloH+tAjv X-Received: by 2002:a17:902:9a4c:: with SMTP id x12mr3897275plv.157.1554348960667; Wed, 03 Apr 2019 20:36:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554348960; cv=none; d=google.com; s=arc-20160816; b=Y3fRfMYIcpxdi/Wx8Vw2N5Q41unDerKHw+rdVehvpx0LuR03TeQACz0hmhdKaw9o4G L59mhm9sNkAZS3UoEZs1+Jd0Bs3VP+eYekPbJIEmmMxVUQwr2/9v0Mwx9DkUCVmy/szW 0Xd6r3ZcOrzFPPSpLhflt3ftHVitqkPQ7GgXfbwYfWnY/wIFVo1R6m3yjFICZX0x/niR y3w99EFfwbURzVG63MGDWd9W3dXhQIO9bx3QZxctH8NuSpNicw6PjiR3sW3FXVShQCW7 BonTjGsffXq10mQzmOE5llCA5A5C35A6xP+VLKrzMiGjJ0p4IRIAtpnvYUzjxVBAjtSw KdSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=PWODwCYQDDzzbPW6Achm9IFb7pPJ4tsTqEyeFjus50Q=; b=SSjH51baQOYlVpV+6Bw48VgzeaAhLbl4j2yZ5T6NeuB0Hk1EU2RyqS4ujv13I6wVfs hVnK/8aRI9xJSwEshyDFvqkisXrrioVmDbk72a9Sh2DLnKDOdcFANz3HUUJv1jBvqs9p aUnwtoy167vTXeBd1eQilLnNw8Kgnif1P/op15mAFGCEr+VhIqTTV6Pzz9KP1XD2ZKiu rndtZIAJBSYxIS1zyul+DHfkUXj/D2vIGrgpJ1SE4X7h7WLSmVJmfwBJDpYOfC8gwElV PxmQEj6h7QNeaprPQv+g5yoMcZO5KWGsK5DAGlR8ZgrJNsIEAnP6rIxXFacG/GXGpz5I 7Qzw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qiT6ObVV; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f9si6620237plo.101.2019.04.03.20.36.00; Wed, 03 Apr 2019 20:36:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qiT6ObVV; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726930AbfDDDf6 (ORCPT + 31 others); Wed, 3 Apr 2019 23:35:58 -0400 Received: from mail-pl1-f196.google.com ([209.85.214.196]:35469 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726167AbfDDDf5 (ORCPT ); Wed, 3 Apr 2019 23:35:57 -0400 Received: by mail-pl1-f196.google.com with SMTP id w24so446244plp.2 for ; Wed, 03 Apr 2019 20:35:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PWODwCYQDDzzbPW6Achm9IFb7pPJ4tsTqEyeFjus50Q=; b=qiT6ObVVNr3Ag9oPswoT6G7Cx8iqiCsE6UmCVZbRHZCc3e7ACYSYOrZGcSaaXvLaUU UMN7QnaPCcDT+FbETiRyczLquxSHirJorI0xwJym4b+c3ZFBEhJHZnH890/fDF7+MG71 9oHnHCO9KlgT4IzJjJjmPTJO3Tm3YJq9DA07FvpOf+nob8IIlOnXt9zUqb52ef3SMNto 9VqxYGbWcujjNzGK+i7D93Z/BFRxRofteY03vvmlZcjNGC4pcOvRUu/iVO6i4tqQXzw1 +gnrIEf2urnZzYvTdPaoDPakZSK9onlqHI4EaKX8DAx9AOzafZlcyf9jYUiyna0+5BaU yBwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PWODwCYQDDzzbPW6Achm9IFb7pPJ4tsTqEyeFjus50Q=; b=OJCib52KyHP/172fMYQ6EzddWGrNHva+oP2vzwF8z1lCSXZB7m8yACyhKo2UjRGynR F34Nbdr11pTiXjRUsjBtfG2rAeBqnD6D+NH5G9qde9pzS2Pf7lxlimzhwMP2RyKl8//9 UcFFHzvoOfa5WsM/aMYQUv2MQ0fU+2v32kckbkouCVkLF5Dl2L3RmhYXpsSmaKAjry4F ntejrZLJP23YPK0ijyr3k3Q8dGrxChi8akkn+r6Pencpk3HXzmXTrrk869X0czBvcSf8 Vd4Hv4wH4tjnlRV0iCvLV1jOI/7euBssCJoCRaX51R2XDMws7Lm5a5yAu4MJVGoGf/BI OMBQ== X-Gm-Message-State: APjAAAU9shl5QKftuDjTPiojmeAKbQJqrEbc4ajZpsLI8XqYNsLR5+jI 5RrF3S3Ty6/TNTwnrqvS9dkGtQ== X-Received: by 2002:a17:902:4681:: with SMTP id p1mr3884423pld.42.1554348956257; Wed, 03 Apr 2019 20:35:56 -0700 (PDT) Received: from xps15.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id u5sm12212780pfm.121.2019.04.03.20.35.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 03 Apr 2019 20:35:55 -0700 (PDT) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org Cc: alexander.shishkin@linux.intel.com, peterz@infradead.org, suzuki.poulose@arm.com, mike.leach@arm.com, leo.yan@linaro.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 02/20] coresight: etm4x: Add kernel configuration for CONTEXTID Date: Wed, 3 Apr 2019 21:35:23 -0600 Message-Id: <20190404033541.14072-3-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190404033541.14072-1-mathieu.poirier@linaro.org> References: <20190404033541.14072-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Set the proper bit in the configuration register when contextID tracing has been requested by user space. That way PE_CONTEXT elements are generated by the tracers when a process is installed on a CPU. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/Kconfig | 1 + drivers/hwtracing/coresight/coresight-etm-perf.c | 2 ++ drivers/hwtracing/coresight/coresight-etm4x.c | 5 +++++ include/linux/coresight-pmu.h | 2 ++ tools/include/linux/coresight-pmu.h | 2 ++ 5 files changed, 12 insertions(+) -- 2.17.1 Reviewed-by: Suzuki K Poulose diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index ad34380cac49..44d1650f398e 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -75,6 +75,7 @@ config CORESIGHT_SOURCE_ETM4X bool "CoreSight Embedded Trace Macrocell 4.x driver" depends on ARM64 select CORESIGHT_LINKS_AND_SINKS + select PID_IN_CONTEXTIDR help This driver provides support for the ETM4.x tracer module, tracing the instructions that a processor is executing. This is primarily useful diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index 25ae56e924bb..bbfed70b3402 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -29,6 +29,7 @@ static DEFINE_PER_CPU(struct coresight_device *, csdev_src); /* ETMv3.5/PTM's ETMCR is 'config' */ PMU_FORMAT_ATTR(cycacc, "config:" __stringify(ETM_OPT_CYCACC)); +PMU_FORMAT_ATTR(contextid, "config:" __stringify(ETM_OPT_CTXTID)); PMU_FORMAT_ATTR(timestamp, "config:" __stringify(ETM_OPT_TS)); PMU_FORMAT_ATTR(retstack, "config:" __stringify(ETM_OPT_RETSTK)); /* Sink ID - same for all ETMs */ @@ -36,6 +37,7 @@ PMU_FORMAT_ATTR(sinkid, "config2:0-31"); static struct attribute *etm_config_formats_attr[] = { &format_attr_cycacc.attr, + &format_attr_contextid.attr, &format_attr_timestamp.attr, &format_attr_retstack.attr, &format_attr_sinkid.attr, diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 08ce37c9475d..732ae12fca9b 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -239,6 +239,11 @@ static int etm4_parse_event_config(struct etmv4_drvdata *drvdata, if (attr->config & BIT(ETM_OPT_TS)) /* bit[11], Global timestamp tracing bit */ config->cfg |= BIT(11); + + if (attr->config & BIT(ETM_OPT_CTXTID)) + /* bit[6], Context ID tracing bit */ + config->cfg |= BIT(ETM4_CFG_BIT_CTXTID); + /* return stack - enable if selected and supported */ if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack) /* bit[12], Return stack enable bit */ diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h index a1a959ba24ff..b0e35eec6499 100644 --- a/include/linux/coresight-pmu.h +++ b/include/linux/coresight-pmu.h @@ -12,11 +12,13 @@ /* ETMv3.5/PTM's ETMCR config bit */ #define ETM_OPT_CYCACC 12 +#define ETM_OPT_CTXTID 14 #define ETM_OPT_TS 28 #define ETM_OPT_RETSTK 29 /* ETMv4 CONFIGR programming bits for the ETM OPTs */ #define ETM4_CFG_BIT_CYCACC 4 +#define ETM4_CFG_BIT_CTXTID 6 #define ETM4_CFG_BIT_TS 11 #define ETM4_CFG_BIT_RETSTK 12 diff --git a/tools/include/linux/coresight-pmu.h b/tools/include/linux/coresight-pmu.h index a1a959ba24ff..b0e35eec6499 100644 --- a/tools/include/linux/coresight-pmu.h +++ b/tools/include/linux/coresight-pmu.h @@ -12,11 +12,13 @@ /* ETMv3.5/PTM's ETMCR config bit */ #define ETM_OPT_CYCACC 12 +#define ETM_OPT_CTXTID 14 #define ETM_OPT_TS 28 #define ETM_OPT_RETSTK 29 /* ETMv4 CONFIGR programming bits for the ETM OPTs */ #define ETM4_CFG_BIT_CYCACC 4 +#define ETM4_CFG_BIT_CTXTID 6 #define ETM4_CFG_BIT_TS 11 #define ETM4_CFG_BIT_RETSTK 12 From patchwork Thu Apr 4 03:35:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 161722 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1087026jan; Wed, 3 Apr 2019 20:36:03 -0700 (PDT) X-Google-Smtp-Source: APXvYqykP/upHKrR2IGKAy3BsBaaVrR2T+1KM4T9uXqNFmUiUG4gmLzdPUpt8o0CRUqkVW1B6sl/ X-Received: by 2002:a63:6942:: with SMTP id e63mr3531656pgc.102.1554348963162; Wed, 03 Apr 2019 20:36:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554348963; cv=none; d=google.com; s=arc-20160816; b=F2OidLzF9E865jh3hBWbgc5JXH0uzs1rmewEk676EXsjywZ/k1AZsELQ45aCUMuoyG 1bOYdET48HS+JddRQ9z3p0xi+DP02F+UF41lSeekylataqFcb217l10dhFU1m7BxEqFf iOFLadMdeG7BNnchryyZiTqVqEm/VkasuIISRm//+EkdvkMFSed9LCUW6n1JSQexZW41 x4pHcaxvJxyFJbuD3seA6VS6shNEUDLRbxT0nUM3/CFOtuPGjb4zwdMXmnNakMGkbbis xl+yq6ffbZoZOnesjNZ83hT/kmbN1J/ub7SmYW+x7PG6efWLA/SrbDAz6/DGr+zKanYL q6ug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=rHFVznWd3K/zryT+Tds7l4sZTdfDnutsgyti8B8Scew=; b=wf+V08CA0WfPde0c2RczeXeBxC4R+SCFyyG5tz9mzzXOQYmjuRraw5D+3MP5EKrGDq JHm3zYXcA6mLFxERA4hoYIx6WJAQq9fdzfiwHgQTlih7Qf4996OXPSOpuSV4KcgRc2Mp jsVcngpn+nLt0/PqKqh4GmiYBloDydP2l2W0VRMnTEdBPy1Pry+vgqAUaXuIt9paWtj4 iEjy7IVoUVNtZwvQ2bfZCqGIwy4DxqXObog+WJrmPHFckdNl8+BpXVD3o2aMUBR0p4Qi hFppXrml/F2FVmeeJRNYvOs9miVQn1J56qbFZUDqKXuJvTfY1ZbTRKiTHntqMGcDB2J6 vXlg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TRzKh2vO; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f9si6620237plo.101.2019.04.03.20.36.02; Wed, 03 Apr 2019 20:36:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TRzKh2vO; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726994AbfDDDgC (ORCPT + 31 others); Wed, 3 Apr 2019 23:36:02 -0400 Received: from mail-pl1-f195.google.com ([209.85.214.195]:45221 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726791AbfDDDgA (ORCPT ); Wed, 3 Apr 2019 23:36:00 -0400 Received: by mail-pl1-f195.google.com with SMTP id bf11so420734plb.12 for ; Wed, 03 Apr 2019 20:36:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rHFVznWd3K/zryT+Tds7l4sZTdfDnutsgyti8B8Scew=; b=TRzKh2vOPOa2ZvsJuRkYqzZnXGyMeGuX67tGMNah46Ls86ESxy2T98bYlcFr3XX5Pk DKraZC1Md0//SeUaIhNQnCiQN2gQL4PFWNCaADEOZP4LpbFIACrY3Acn17x1LBbF85uw HJ3Cnm5HyTQErLC5YJqMSvvMdallW1tG/HC4NlV/b49PYn5ywYQ+mjNIGNciTAfGPbzn AdAhdAvw0pcWhT2TwZEbx6PnamyEkghvns7tqXOixdD5VKZRFqFwm1QLStM8JKC1ikfB ayyaufqpk1qc4Zwd7fF977eZdwWMGhCjNXb8jVSHrNQps8slJQw0rHTS7BEzsgZGhcQJ NVeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rHFVznWd3K/zryT+Tds7l4sZTdfDnutsgyti8B8Scew=; b=EHFboj9AcYGqMwv3dcSO0Urav/JaIlHgsRVI12Av6O2VM23iyvINbozH/N+4joUUMl +c0Sff9oWL2hEnp420E3mQNjKntlRFOeuqmBfhgcCItS6ls1Qb+y2vznHA+rr0vKEGbi HIkABimTMYp9DYl3+ep3GaTPES+OFbRYe+1qNjyH3zI+hFmvJ28OjLYyucoJP0ecr9aE 29p+h+QO0/DDWfibs5WfXvB81wFysz62S3JS8hYnJX+DR3feavL0IPB8J2x5yUxK24TY Glo6vzoWBhi03DCJZxoTI+EkifJu2qP8P87kqLWOqaZQwxdcmVbXQP3oMmvShRueXydU 006Q== X-Gm-Message-State: APjAAAWlHjf2RjP3pSKvJON7Sks+kR0W/vfAF0cqErBmvpZspWuz9zTz gCQlsMbjnTwUu5n9oVKbVpcVHA== X-Received: by 2002:a17:902:403:: with SMTP id 3mr3816530ple.48.1554348960246; Wed, 03 Apr 2019 20:36:00 -0700 (PDT) Received: from xps15.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id u5sm12212780pfm.121.2019.04.03.20.35.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 03 Apr 2019 20:35:59 -0700 (PDT) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org Cc: alexander.shishkin@linux.intel.com, peterz@infradead.org, suzuki.poulose@arm.com, mike.leach@arm.com, leo.yan@linaro.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 03/20] coresight: etm4x: Skip selector pair 0 Date: Wed, 3 Apr 2019 21:35:24 -0600 Message-Id: <20190404033541.14072-4-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190404033541.14072-1-mathieu.poirier@linaro.org> References: <20190404033541.14072-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Resource selector pair 0 is always implemented and reserved. As such it should not be explicitly programmed. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm4x.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) -- 2.17.1 Reviewed-by: Suzuki K Poulose diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 732ae12fca9b..d64192c29860 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -138,8 +138,11 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) drvdata->base + TRCCNTVRn(i)); } - /* Resource selector pair 0 is always implemented and reserved */ - for (i = 0; i < drvdata->nr_resource * 2; i++) + /* + * Resource selector pair 0 is always implemented and reserved. As + * such start at 2. + */ + for (i = 2; i < drvdata->nr_resource * 2; i++) writel_relaxed(config->res_ctrl[i], drvdata->base + TRCRSCTLRn(i)); From patchwork Thu Apr 4 03:35:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 161723 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1087090jan; Wed, 3 Apr 2019 20:36:07 -0700 (PDT) X-Google-Smtp-Source: APXvYqzXLk7BIX0YP4fUqmTCIZNT1TzKJ8VmTGH6RDY1ZddY0mMvPg295wFWBIpFcfw7jKJgTdhP X-Received: by 2002:a63:945:: with SMTP id 66mr3317412pgj.128.1554348967756; Wed, 03 Apr 2019 20:36:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554348967; cv=none; d=google.com; s=arc-20160816; b=EMxqQQHvZm+aiFHXZBC/8BsDGcoCvIS1cwZxcJWPH3QoJQUSSOItkvk1wSgL0/y4EB 7edKv8qWaPKuSyPF7E7MI7gN5M8OOc78IfhWTFrAyHzhJS0SmYZ2B97Rgn6o7j+MHCQm vVnyFd1LmGCZkDfFKzG9dNJ9EqOYSifgBSHGxP/B/z+++uUY8NO7Szb6IS8hY+sfR+n3 JnAQT2wza+jJDZnpPtPJcVTZ3mys4oU7G/+he9pXIl7OvzHz2kFBYG6JlbAyFzDxG6H1 avzv8Wj9EYQNCdk0za7tK/OLqCLJg8Yit9IQbEQVUsW5MnAkpAztKT0viWmOtM9cW43Q SrWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=ATVaL0BIcRrddkftI6sh9Xp4gw4NfYBuCJEK93HbLeU=; b=zwuJAdkUtzYxUwTp3pSA6CZ2yRzaEN/9/gtrjwFQfzBfcg0cK0aKI/s/jjdqRQWivL EXhJUPvsdmp6YRpdN64Q8J/mF9BS8x94UCSl/V9g26rkn5RHc4pIJP3szhNQfxfja10d FHlqMJHIdZNBeT3c4GFnlbUjwAqCfxkqvImLeviNfYAcrG5xCgQMYjSXI88Wq4PXSOva /rZUrwHMTpq21yYhT/2fn29MXH4t0JaxAVqu1/TesndkxAudRkCi/rycD3ffJYLFiZGN uWW00GToGQtTjHxgsdsPej7RcyLCfv0plLdoxYOjZgnoxfhj/gSitaMzCuVuRW+YO2an RzgQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rKmCBzs5; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm4x.c | 101 +++++++++++++++++- 1 file changed, 100 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index d64192c29860..46d337fd8442 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -204,6 +204,90 @@ static void etm4_enable_hw_smp_call(void *info) arg->rc = etm4_enable_hw(arg->drvdata); } +/* + * The goal of function etm4_config_timestamp_event() is to configure a + * counter that will tell the tracer to emit a timestamp packet when it + * reaches zero. This is done in order to get a more fine grained idea + * of when instructions are executed so that they can be correlated + * with execution on other CPUs. + * + * To do this the counter itself is configured to self reload and + * TRCRSCTLR1 (always true) used to get the counter to decrement. From + * there a resource selector is configured with the counter and the + * timestamp control register to use the resource selector to trigger the + * event that will insert a timestamp packet in the stream. + */ +static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata) +{ + int ctridx, ret = -EINVAL; + int counter, rselector; + u32 val = 0; + struct etmv4_config *config = &drvdata->config; + + /* No point in trying if we don't have at least one counter */ + if (!drvdata->nr_cntr) + goto out; + + /* Find a counter that hasn't been initialised */ + for (ctridx = 0; ctridx < drvdata->nr_cntr; ctridx++) + if (config->cntr_val[ctridx] == 0) + break; + + /* All the counters have been configured already, bail out */ + if (ctridx == drvdata->nr_cntr) { + pr_debug("%s: no available counter found\n", __func__); + ret = -ENOSPC; + goto out; + } + + /* + * Searching for an available resource selector to use, starting at + * '2' since every implementation has at least 2 resource selector. + * ETMIDR4 gives the number of resource selector _pairs_, + * hence multiply by 2. + */ + for (rselector = 2; rselector < drvdata->nr_resource * 2; rselector++) + if (!config->res_ctrl[rselector]) + break; + + if (rselector == drvdata->nr_resource * 2) { + pr_debug("%s: no available resource selector found\n", __func__); + ret = -ENOSPC; + goto out; + } + + /* Remember what counter we used */ + counter = 1 << ctridx; + + /* + * Initialise original and reload counter value to the smallest + * possible value in order to get as much precision as we can. + */ + config->cntr_val[ctridx] = 1; + config->cntrldvr[ctridx] = 1; + + /* Set the trace counter control register */ + val = 0x1 << 16 | /* Bit 16, reload counter automatically */ + 0x0 << 7 | /* Select single resource selector */ + 0x1; /* Resource selector 1, i.e always true */ + + config->cntr_ctrl[ctridx] = val; + + val = 0x2 << 16 | /* Group 0b0010 - Counter and sequencers */ + counter << 0; /* Counter to use */ + + config->res_ctrl[rselector] = val; + + val = 0x0 << 7 | /* Select single resource selector */ + rselector; /* Resource selector */ + + config->ts_ctrl = val; + + ret = 0; +out: + return ret; +} + static int etm4_parse_event_config(struct etmv4_drvdata *drvdata, struct perf_event *event) { @@ -239,9 +323,24 @@ static int etm4_parse_event_config(struct etmv4_drvdata *drvdata, /* TRM: Must program this for cycacc to work */ config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT; } - if (attr->config & BIT(ETM_OPT_TS)) + if (attr->config & BIT(ETM_OPT_TS)) { + /* + * Configure timestamps to be emitted at regular intervals in + * order to correlate instructions executed on different CPUs + * (CPU-wide trace scenarios). + */ + ret = etm4_config_timestamp_event(drvdata); + + /* + * No need to go further if timestamp intervals can't + * be configured. + */ + if (ret) + goto out; + /* bit[11], Global timestamp tracing bit */ config->cfg |= BIT(11); + } if (attr->config & BIT(ETM_OPT_CTXTID)) /* bit[6], Context ID tracing bit */ From patchwork Thu Apr 4 03:35:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 161724 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1087124jan; 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Signed-off-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-etb10.c | 3 ++- drivers/hwtracing/coresight/coresight-tmc-etf.c | 5 +++-- drivers/hwtracing/coresight/coresight-tmc-etr.c | 5 +++-- drivers/hwtracing/coresight/coresight-tpiu.c | 3 ++- drivers/hwtracing/coresight/coresight.c | 6 +++++- include/linux/coresight.h | 2 +- 6 files changed, 16 insertions(+), 8 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 105782ea64c7..71c2a3cdb866 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -325,7 +325,7 @@ static void etb_disable_hw(struct etb_drvdata *drvdata) coresight_disclaim_device(drvdata->base); } -static void etb_disable(struct coresight_device *csdev) +static int etb_disable(struct coresight_device *csdev) { struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); unsigned long flags; @@ -340,6 +340,7 @@ static void etb_disable(struct coresight_device *csdev) spin_unlock_irqrestore(&drvdata->spinlock, flags); dev_dbg(drvdata->dev, "ETB disabled\n"); + return 0; } static void *etb_alloc_buffer(struct coresight_device *csdev, int cpu, diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index a5f053f2db2c..d4213e7c2c45 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -273,7 +273,7 @@ static int tmc_enable_etf_sink(struct coresight_device *csdev, return 0; } -static void tmc_disable_etf_sink(struct coresight_device *csdev) +static int tmc_disable_etf_sink(struct coresight_device *csdev) { unsigned long flags; struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); @@ -281,7 +281,7 @@ static void tmc_disable_etf_sink(struct coresight_device *csdev) spin_lock_irqsave(&drvdata->spinlock, flags); if (drvdata->reading) { spin_unlock_irqrestore(&drvdata->spinlock, flags); - return; + return -EBUSY; } /* Disable the TMC only if it needs to */ @@ -293,6 +293,7 @@ static void tmc_disable_etf_sink(struct coresight_device *csdev) spin_unlock_irqrestore(&drvdata->spinlock, flags); dev_dbg(drvdata->dev, "TMC-ETB/ETF disabled\n"); + return 0; } static int tmc_enable_etf_link(struct coresight_device *csdev, diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index f684283890d3..33501777038a 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1392,7 +1392,7 @@ static int tmc_enable_etr_sink(struct coresight_device *csdev, return -EINVAL; } -static void tmc_disable_etr_sink(struct coresight_device *csdev) +static int tmc_disable_etr_sink(struct coresight_device *csdev) { unsigned long flags; struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); @@ -1400,7 +1400,7 @@ static void tmc_disable_etr_sink(struct coresight_device *csdev) spin_lock_irqsave(&drvdata->spinlock, flags); if (drvdata->reading) { spin_unlock_irqrestore(&drvdata->spinlock, flags); - return; + return -EBUSY; } /* Disable the TMC only if it needs to */ @@ -1412,6 +1412,7 @@ static void tmc_disable_etr_sink(struct coresight_device *csdev) spin_unlock_irqrestore(&drvdata->spinlock, flags); dev_dbg(drvdata->dev, "TMC-ETR disabled\n"); + return 0; } static const struct coresight_ops_sink tmc_etr_sink_ops = { diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/hwtracing/coresight/coresight-tpiu.c index b2f72a1fa402..0d13da1b9df1 100644 --- a/drivers/hwtracing/coresight/coresight-tpiu.c +++ b/drivers/hwtracing/coresight/coresight-tpiu.c @@ -94,13 +94,14 @@ static void tpiu_disable_hw(struct tpiu_drvdata *drvdata) CS_LOCK(drvdata->base); } -static void tpiu_disable(struct coresight_device *csdev) +static int tpiu_disable(struct coresight_device *csdev) { struct tpiu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); tpiu_disable_hw(drvdata); dev_dbg(drvdata->dev, "TPIU disabled\n"); + return 0; } static const struct coresight_ops_sink tpiu_sink_ops = { diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c index 29cef898afba..13eda4693f81 100644 --- a/drivers/hwtracing/coresight/coresight.c +++ b/drivers/hwtracing/coresight/coresight.c @@ -239,9 +239,13 @@ static int coresight_enable_sink(struct coresight_device *csdev, static void coresight_disable_sink(struct coresight_device *csdev) { + int ret; + if (atomic_dec_return(csdev->refcnt) == 0) { if (sink_ops(csdev)->disable) { - sink_ops(csdev)->disable(csdev); + ret = sink_ops(csdev)->disable(csdev); + if (ret) + return; csdev->enable = false; } } diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 7b87965f7a65..189cc6ddc92b 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -192,7 +192,7 @@ struct coresight_device { */ struct coresight_ops_sink { int (*enable)(struct coresight_device *csdev, u32 mode, void *data); - void (*disable)(struct coresight_device *csdev); + int (*disable)(struct coresight_device *csdev); void *(*alloc_buffer)(struct coresight_device *csdev, int cpu, void **pages, int nr_pages, bool overwrite); void (*free_buffer)(void *config); From patchwork Thu Apr 4 03:35:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 161725 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1087157jan; Wed, 3 Apr 2019 20:36:14 -0700 (PDT) X-Google-Smtp-Source: APXvYqzOrYJ1vLFFNNCzHWFvzQG5t8EE0cZWMl+1Z8Tdw0lFTb05shab0eqKMErn+qPx9gNDELPQ X-Received: by 2002:a63:5150:: with SMTP id r16mr3246775pgl.307.1554348974464; Wed, 03 Apr 2019 20:36:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554348974; cv=none; d=google.com; s=arc-20160816; b=sx5Gq9hjCQAMv71S3h3PsfUdggj+fOa19TrzL0tJ2zn0ULCgaVlObuD77XPFTRbV4Q 1aG4RlIW1xaFJZg+SaTOYiMfIa9e6mvV0ZI7NMeC2JnUhLSqQG8x4C05I5EZDNupadRL vf4Uu8w4P/V+OGEcbvabtMa7ipYWBT/ZSIW5+BOkIAx/G3VQ95MJw5q3M8z5Xm8EktRF JB7nNIH+Aot/atUXVFBjWQdIlHScdz6FHCMQYDh/7/nCx6COGEgWnyo2rv+v6tqOV9o4 aThFGDMSkfd9Sm2nSJopYdVIRQYj17Eke+dEyB7IK9oXczoiA5zqwVb9PhyRhF4rxgSW eoXA== ARC-Message-Signature: i=1; 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As such reference counting needs to happen when the device's spinlock is held to avoid racing with other operations (start(), update(), stop()), such as: session A Session B ----- ------- enable_sink atomic_inc(refcount) = 1 ... atomic_dec(refcount) = 0 enable_sink if (refcount == 0) disable_sink atomic_inc() Signed-off-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-etb10.c | 21 ++++++++++---- .../hwtracing/coresight/coresight-tmc-etf.c | 21 +++++++++++--- .../hwtracing/coresight/coresight-tmc-etr.c | 19 +++++++++++-- drivers/hwtracing/coresight/coresight-tpiu.c | 6 +++- drivers/hwtracing/coresight/coresight.c | 28 +++++++++---------- 5 files changed, 66 insertions(+), 29 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 71c2a3cdb866..5af50a852e87 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -5,6 +5,7 @@ * Description: CoreSight Embedded Trace Buffer driver */ +#include #include #include #include @@ -159,14 +160,15 @@ static int etb_enable_sysfs(struct coresight_device *csdev) goto out; } - /* Nothing to do, the tracer is already enabled. */ - if (drvdata->mode == CS_MODE_SYSFS) - goto out; + if (drvdata->mode == CS_MODE_DISABLED) { + ret = etb_enable_hw(drvdata); + if (ret) + goto out; - ret = etb_enable_hw(drvdata); - if (!ret) drvdata->mode = CS_MODE_SYSFS; + } + atomic_inc(csdev->refcnt); out: spin_unlock_irqrestore(&drvdata->spinlock, flags); return ret; @@ -196,8 +198,10 @@ static int etb_enable_perf(struct coresight_device *csdev, void *data) goto out; ret = etb_enable_hw(drvdata); - if (!ret) + if (!ret) { drvdata->mode = CS_MODE_PERF; + atomic_inc(csdev->refcnt); + } out: spin_unlock_irqrestore(&drvdata->spinlock, flags); @@ -332,6 +336,11 @@ static int etb_disable(struct coresight_device *csdev) spin_lock_irqsave(&drvdata->spinlock, flags); + if (atomic_dec_return(csdev->refcnt)) { + spin_unlock_irqrestore(&drvdata->spinlock, flags); + return -EBUSY; + } + /* Disable the ETB only if it needs to */ if (drvdata->mode != CS_MODE_DISABLED) { etb_disable_hw(drvdata); diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index d4213e7c2c45..d50a608a60f1 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -4,6 +4,7 @@ * Author: Mathieu Poirier */ +#include #include #include #include @@ -180,8 +181,10 @@ static int tmc_enable_etf_sink_sysfs(struct coresight_device *csdev) * sink is already enabled no memory is needed and the HW need not be * touched. */ - if (drvdata->mode == CS_MODE_SYSFS) + if (drvdata->mode == CS_MODE_SYSFS) { + atomic_inc(csdev->refcnt); goto out; + } /* * If drvdata::buf isn't NULL, memory was allocated for a previous @@ -200,11 +203,13 @@ static int tmc_enable_etf_sink_sysfs(struct coresight_device *csdev) } ret = tmc_etb_enable_hw(drvdata); - if (!ret) + if (!ret) { drvdata->mode = CS_MODE_SYSFS; - else + atomic_inc(csdev->refcnt); + } else { /* Free up the buffer if we failed to enable */ used = false; + } out: spin_unlock_irqrestore(&drvdata->spinlock, flags); @@ -239,8 +244,10 @@ static int tmc_enable_etf_sink_perf(struct coresight_device *csdev, void *data) if (ret) break; ret = tmc_etb_enable_hw(drvdata); - if (!ret) + if (!ret) { drvdata->mode = CS_MODE_PERF; + atomic_inc(csdev->refcnt); + } } while (0); spin_unlock_irqrestore(&drvdata->spinlock, flags); @@ -279,11 +286,17 @@ static int tmc_disable_etf_sink(struct coresight_device *csdev) struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); spin_lock_irqsave(&drvdata->spinlock, flags); + if (drvdata->reading) { spin_unlock_irqrestore(&drvdata->spinlock, flags); return -EBUSY; } + if (atomic_dec_return(csdev->refcnt)) { + spin_unlock_irqrestore(&drvdata->spinlock, flags); + return -EBUSY; + } + /* Disable the TMC only if it needs to */ if (drvdata->mode != CS_MODE_DISABLED) { tmc_etb_disable_hw(drvdata); diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 33501777038a..f90bca971367 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -4,6 +4,7 @@ * Author: Mathieu Poirier */ +#include #include #include #include @@ -1124,8 +1125,10 @@ static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev) * sink is already enabled no memory is needed and the HW need not be * touched, even if the buffer size has changed. */ - if (drvdata->mode == CS_MODE_SYSFS) + if (drvdata->mode == CS_MODE_SYSFS) { + atomic_inc(csdev->refcnt); goto out; + } /* * If we don't have a buffer or it doesn't match the requested size, @@ -1138,8 +1141,10 @@ static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev) } ret = tmc_etr_enable_hw(drvdata, drvdata->sysfs_buf); - if (!ret) + if (!ret) { drvdata->mode = CS_MODE_SYSFS; + atomic_inc(csdev->refcnt); + } out: spin_unlock_irqrestore(&drvdata->spinlock, flags); @@ -1370,8 +1375,10 @@ static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, void *data) etr_perf->head = PERF_IDX2OFF(handle->head, etr_perf); drvdata->perf_data = etr_perf; rc = tmc_etr_enable_hw(drvdata, etr_perf->etr_buf); - if (!rc) + if (!rc) { drvdata->mode = CS_MODE_PERF; + atomic_inc(csdev->refcnt); + } unlock_out: spin_unlock_irqrestore(&drvdata->spinlock, flags); @@ -1398,11 +1405,17 @@ static int tmc_disable_etr_sink(struct coresight_device *csdev) struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); spin_lock_irqsave(&drvdata->spinlock, flags); + if (drvdata->reading) { spin_unlock_irqrestore(&drvdata->spinlock, flags); return -EBUSY; } + if (atomic_dec_return(csdev->refcnt)) { + spin_unlock_irqrestore(&drvdata->spinlock, flags); + return -EBUSY; + } + /* Disable the TMC only if it needs to */ if (drvdata->mode != CS_MODE_DISABLED) { tmc_etr_disable_hw(drvdata); diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/hwtracing/coresight/coresight-tpiu.c index 0d13da1b9df1..7acbeffcc137 100644 --- a/drivers/hwtracing/coresight/coresight-tpiu.c +++ b/drivers/hwtracing/coresight/coresight-tpiu.c @@ -5,6 +5,7 @@ * Description: CoreSight Trace Port Interface Unit driver */ +#include #include #include #include @@ -73,7 +74,7 @@ static int tpiu_enable(struct coresight_device *csdev, u32 mode, void *__unused) struct tpiu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); tpiu_enable_hw(drvdata); - + atomic_inc(csdev->refcnt); dev_dbg(drvdata->dev, "TPIU enabled\n"); return 0; } @@ -98,6 +99,9 @@ static int tpiu_disable(struct coresight_device *csdev) { struct tpiu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + if (atomic_dec_return(csdev->refcnt)) + return -EBUSY; + tpiu_disable_hw(drvdata); dev_dbg(drvdata->dev, "TPIU disabled\n"); diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c index 13eda4693f81..19ba121d7451 100644 --- a/drivers/hwtracing/coresight/coresight.c +++ b/drivers/hwtracing/coresight/coresight.c @@ -225,14 +225,13 @@ static int coresight_enable_sink(struct coresight_device *csdev, * We need to make sure the "new" session is compatible with the * existing "mode" of operation. */ - if (sink_ops(csdev)->enable) { - ret = sink_ops(csdev)->enable(csdev, mode, data); - if (ret) - return ret; - csdev->enable = true; - } + if (!sink_ops(csdev)->enable) + return -EINVAL; - atomic_inc(csdev->refcnt); + ret = sink_ops(csdev)->enable(csdev, mode, data); + if (ret) + return ret; + csdev->enable = true; return 0; } @@ -241,14 +240,13 @@ static void coresight_disable_sink(struct coresight_device *csdev) { int ret; - if (atomic_dec_return(csdev->refcnt) == 0) { - if (sink_ops(csdev)->disable) { - ret = sink_ops(csdev)->disable(csdev); - if (ret) - return; - csdev->enable = false; - } - } + if (!sink_ops(csdev)->disable) + return; + + ret = sink_ops(csdev)->disable(csdev); + if (ret) + return; + csdev->enable = false; } static int coresight_enable_link(struct coresight_device *csdev, From patchwork Thu Apr 4 03:35:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 161726 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1087202jan; Wed, 3 Apr 2019 20:36:18 -0700 (PDT) X-Google-Smtp-Source: APXvYqyFmwZq7TY9bm/US41qLh1MNTQyxVk2OYIfkNNRfFguuTZPNA5z/+Y+MPOLpxVg4AgDK8rt X-Received: by 2002:a63:554b:: with SMTP id f11mr3415764pgm.77.1554348978179; Wed, 03 Apr 2019 20:36:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554348978; cv=none; d=google.com; s=arc-20160816; b=SU8pz25h1Mb8v5s2Y0RGaH2NaHrJlWpgDBQwzz/h0rCyp1CEslQVTKuNV8xBq1AvnP Mcc62s1Ns1ebKl6fr6fGZyrX2gkZDY3foTag/pasEftE5uRqDW3HSCTBFQ0OxcdzrHuv on3R14ff63zekTzS8fsGsklNkNq8JVZ/T63ubp9jLx/0YzsNC1NuAoPshnVp5qBE6PaG E1fAVz/6RvZgrPD4YLADvnlyCwncMpj7Ot4YdFpJk/Z/FsJ2AhABUWVeUsnC0x0ewSeM jUOmOUcV4TlmsvvltFcEbAovSWORCZs1rB737zEa+wZkjuJTA4028M5IQ9mgsMfHgrOO DqEQ== ARC-Message-Signature: i=1; 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As such if drvdata::mode is already set do CS_MODE_DISABLED, it is an error and should be reported as such. Signed-off-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-etb10.c | 9 ++++----- drivers/hwtracing/coresight/coresight-tmc-etf.c | 9 ++++----- drivers/hwtracing/coresight/coresight-tmc-etr.c | 9 ++++----- 3 files changed, 12 insertions(+), 15 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 5af50a852e87..52b7d95ab498 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -341,11 +341,10 @@ static int etb_disable(struct coresight_device *csdev) return -EBUSY; } - /* Disable the ETB only if it needs to */ - if (drvdata->mode != CS_MODE_DISABLED) { - etb_disable_hw(drvdata); - drvdata->mode = CS_MODE_DISABLED; - } + /* Complain if we (somehow) got out of sync */ + WARN_ON_ONCE(drvdata->mode == CS_MODE_DISABLED); + etb_disable_hw(drvdata); + drvdata->mode = CS_MODE_DISABLED; spin_unlock_irqrestore(&drvdata->spinlock, flags); dev_dbg(drvdata->dev, "ETB disabled\n"); diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index d50a608a60f1..30f868676540 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -297,11 +297,10 @@ static int tmc_disable_etf_sink(struct coresight_device *csdev) return -EBUSY; } - /* Disable the TMC only if it needs to */ - if (drvdata->mode != CS_MODE_DISABLED) { - tmc_etb_disable_hw(drvdata); - drvdata->mode = CS_MODE_DISABLED; - } + /* Complain if we (somehow) got out of sync */ + WARN_ON_ONCE(drvdata->mode == CS_MODE_DISABLED); + tmc_etb_disable_hw(drvdata); + drvdata->mode = CS_MODE_DISABLED; spin_unlock_irqrestore(&drvdata->spinlock, flags); diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index f90bca971367..86e748d09dc3 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1416,11 +1416,10 @@ static int tmc_disable_etr_sink(struct coresight_device *csdev) return -EBUSY; } - /* Disable the TMC only if it needs to */ - if (drvdata->mode != CS_MODE_DISABLED) { - tmc_etr_disable_hw(drvdata); - drvdata->mode = CS_MODE_DISABLED; - } + /* Complain if we (somehow) got out of sync */ + WARN_ON_ONCE(drvdata->mode == CS_MODE_DISABLED); + tmc_etr_disable_hw(drvdata); + drvdata->mode = CS_MODE_DISABLED; spin_unlock_irqrestore(&drvdata->spinlock, flags); From patchwork Thu Apr 4 03:35:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 161727 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1087276jan; Wed, 3 Apr 2019 20:36:23 -0700 (PDT) X-Google-Smtp-Source: APXvYqxxXU1OKLmQ8VD04MomSaYw28zcyvp+vEEw1YZH4ew5Br2c7omdEXnhpNzTGYfjMpCwFt6h X-Received: by 2002:a17:902:b60d:: with SMTP id b13mr3944197pls.100.1554348983858; Wed, 03 Apr 2019 20:36:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554348983; cv=none; d=google.com; s=arc-20160816; b=VBpYUpOfcb/hjNUB54WwI1hv5v+AW8WBBUNh9rV1y700uAafd/n9tS8frU6adMaFoK 5szrwIWXeMjjmr5TDtTYZTDjkYEHszznsgsQl+t1XpowHchB9tOPZ49iOwEWnlTlJSXY 0SLMjOtY/uAe63GG1Sy/7aGjypzUHBDP5PdT8C7wqADttuoFi2WR8Tg2yYYFxA/cJDwV gBwODlfmic19cZAS7iBAUUxa9VD852yTOmFWMJAxaT+jozh6VkILzlfKiWRf0yrIk/m/ p5oMm0xYnUsiIL3x1uvIgW9QDApD2W9t0aw3v5ZdkmIrvy1KsXrpl6Slx6mlQNBbRHHv H3Tg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=Rp82OG+X/1qzhxgu7Opyhu1qYPCsjQeQJx+i+wMOyCE=; b=Ut4s+ApaPKA2yi3fvCVsIyhhfNMjyc8zxwPqDytX/1dF2+C2HMDns54QfKMb14WGjK RYiOoNbG3amicT6d+n1SsETbIBGbPduhSGqi7XbEpj8qyzy6zr7qDP4NK9E+cZDiOc3S 8V6L+BoPMx3GD9UsQdp46OHoOCTVLba2bwUiYClJcNf1aNFDgJ0vr+ZCpk1/VrSyDLHF O3aB+e+RoyjZmMWrzJbHF3ai9scyRBPEODVpUEoTkw2WBfa0wcQX1BK8NxO1xgs3nMQb PcUl/N4HfwJNy/YEOu3h6tin5iNZZvmtlRUF2OZDLOn7TI+NNOf45LU7FYaFfP09c6WW tf4Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uWXgpbR5; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-etb10.c | 4 +++- drivers/hwtracing/coresight/coresight-tmc-etf.c | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 52b7d95ab498..6b50e781dc57 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -413,7 +413,7 @@ static unsigned long etb_update_buffer(struct coresight_device *csdev, const u32 *barrier; u32 read_ptr, write_ptr, capacity; u32 status, read_data; - unsigned long offset, to_read; + unsigned long offset, to_read, flags; struct cs_buffers *buf = sink_config; struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); @@ -422,6 +422,7 @@ static unsigned long etb_update_buffer(struct coresight_device *csdev, capacity = drvdata->buffer_depth * ETB_FRAME_SIZE_WORDS; + spin_lock_irqsave(&drvdata->spinlock, flags); __etb_disable_hw(drvdata); CS_UNLOCK(drvdata->base); @@ -532,6 +533,7 @@ static unsigned long etb_update_buffer(struct coresight_device *csdev, } __etb_enable_hw(drvdata); CS_LOCK(drvdata->base); + spin_unlock_irqrestore(&drvdata->spinlock, flags); return to_read; } diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index 30f868676540..a38ad2b0d95a 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -413,7 +413,7 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev, u32 *buf_ptr; u64 read_ptr, write_ptr; u32 status; - unsigned long offset, to_read; + unsigned long offset, to_read, flags; struct cs_buffers *buf = sink_config; struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); @@ -424,6 +424,7 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev, if (WARN_ON_ONCE(drvdata->mode != CS_MODE_PERF)) return 0; + spin_lock_irqsave(&drvdata->spinlock, flags); CS_UNLOCK(drvdata->base); tmc_flush_and_stop(drvdata); @@ -517,6 +518,7 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev, to_read = buf->nr_pages << PAGE_SHIFT; } CS_LOCK(drvdata->base); + spin_unlock_irqrestore(&drvdata->spinlock, flags); return to_read; } From patchwork Thu Apr 4 03:35:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 161728 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1087290jan; Wed, 3 Apr 2019 20:36:25 -0700 (PDT) X-Google-Smtp-Source: APXvYqwiRQPXOQkE7RjmZaQxKzmm3VnfvQpn7wT9WFYzYs1r6XguybGlQER0qa7SP3cGOwuGdC+s X-Received: by 2002:a17:902:3e3:: with SMTP id d90mr3830577pld.271.1554348985194; Wed, 03 Apr 2019 20:36:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554348985; cv=none; d=google.com; s=arc-20160816; b=BL68DB+y1NWKMyyzX7zBZNqfqWihSsgcqaGOO3cyG9J6YRCbZIvSDF4jkdkiqx7P2J 8o0My0K073cRnxrU3uhyd6djJdLTC4L6udV735taydaP8bQDotCxbwJmM9/Sc8Efbu0R FEDINrNGYk5keNOsZU88fdsyplrgFheABIQpSJ01JAhCoCUsPVfv/iAUgZzIv19r71iF yLs0xfUsH/Im9SCHNXThj2NA6RxyxEBGhP0WQJ8ek8eF7nCYUr3K2Lxuq/Jnmgd66Bpr qei9S5095H47Gy7QEdPPJsP9EE0lAZDwyyc5Sdks6RS+1QtwG2paUCndl8hKUdZMzp8Q kgxA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=Rs0Mz9KrYOZgcBXADVGIV6b2w07we0qLU/jBgiUTV9k=; b=QO373npHxRQbdCOicTOfiQwodCm2AxkqOzHwpuU6kEBQUoLtEVlViOH0JaJFi7QFG0 Z4mKImSDhmJaHjgitMeJhrsSyqCwK1+NUeaz/rWyIJWhFNCoVZ6SE+ZHj/tptVy6jDVL 9Y6XWQYanrgBoq02R2a84RJ0J1RbAElkr3sPNGLQ5zIoS9rQ8LJORSRj6d7QgT2IpMgE pdO9lIJpVPpEo0NCxn+h17NObFShZbOBskVNXcbzx49BLOCgZp9xRabVHOU0VnEBDW/j eUo1SU1TvI3zZEOd+LgGnxSGCRDOKcixM+MpG7rvHYOPOfksjUrQhTBSZDngf4awWfl4 hFmw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gdec1QIX; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i14si6795375pgb.0.2019.04.03.20.36.24; Wed, 03 Apr 2019 20:36:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gdec1QIX; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728409AbfDDDgX (ORCPT + 31 others); Wed, 3 Apr 2019 23:36:23 -0400 Received: from mail-pl1-f193.google.com ([209.85.214.193]:39268 "EHLO mail-pl1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728019AbfDDDgW (ORCPT ); Wed, 3 Apr 2019 23:36:22 -0400 Received: by mail-pl1-f193.google.com with SMTP id b65so438476plb.6 for ; Wed, 03 Apr 2019 20:36:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Rs0Mz9KrYOZgcBXADVGIV6b2w07we0qLU/jBgiUTV9k=; b=gdec1QIXZeSLFtCBGpLGPuiGmrxIPSimppb5U9XDlVghC5LgWVcBP9Mfa1xbFdUOOa l1phJ6Y5zBrTHa1fsbSTWLx0aEUcvu+5wuDUvJsKjAQpPDubxp7PS5AckgUnZoy8ZdFr b9akJJhz8tIkZZYpFAKr/D1chofAiyvy2oQrMZzAJ/LLLPYi/6Q229+vkpgY55rW/qbg hFRkQ38/Y9VIQHBOanauk/GszRrMZEkZqKroxY37IkekTpk/BuKy2/ypZ5RjlVgtT74e XW2uePefexh0xccalxM9sn8/l2Qyjwidmxlq1V6meE53dP6Y5ghM3LNtY/7HVREco18R g0Fw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Rs0Mz9KrYOZgcBXADVGIV6b2w07we0qLU/jBgiUTV9k=; b=LTggfbc/6a8si8Iml1JtRDdPp7uoZ/8v1kcp+NJbOtT9+bHLRCJGLGw7myaZtpaK4F szqemr1LkL535vlyTAD2RL1XQ0BnWryUKF1EU0bGr/RpONND4ISDPb9mNAD5vt40KvLx SS5LJQNtw8v+0LgFylN0z9uug/odK7rLcV0TaGdsJUIVJBHa2VNwzff5U75mNtwuLwEF GQ38kYIEaZPMjO0ZBATYSRvy2EzMpKZ0tCg6lNhFCcofdnS8JmKjPjXFPGzpUFtSKNqE jThc22MfF/K6+UUb5phC0qH6V/Ll8mPSsOFVNI1XUmc9DxjOF2E/qMxlPbRkFBXTQH0N nbVw== X-Gm-Message-State: APjAAAWpByQ1eWG0yBgHQ2Z9zW4tHv6dsYpceazxlHTgVEjemZo0rt5e n4cJJCNhaEP9tqbE7q6Sp+q7aQ== X-Received: by 2002:a17:902:f01:: with SMTP id 1mr3828458ply.41.1554348981813; Wed, 03 Apr 2019 20:36:21 -0700 (PDT) Received: from xps15.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id u5sm12212780pfm.121.2019.04.03.20.36.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 03 Apr 2019 20:36:21 -0700 (PDT) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org Cc: alexander.shishkin@linux.intel.com, peterz@infradead.org, suzuki.poulose@arm.com, mike.leach@arm.com, leo.yan@linaro.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 09/20] coresight: perf: Clean up function etm_setup_aux() Date: Wed, 3 Apr 2019 21:35:30 -0600 Message-Id: <20190404033541.14072-10-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190404033541.14072-1-mathieu.poirier@linaro.org> References: <20190404033541.14072-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org There is no point in allocating sink memory for a trace session if there is not a way to free it once it is no longer needed. As such make sure the sink API function to allocate and free memory have been implemented before moving ahead with the establishment of a trace session. Signed-off-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-etm-perf.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index bbfed70b3402..b8ca3800b56b 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -134,8 +134,7 @@ static void free_event_data(struct work_struct *work) if (event_data->snk_config && !WARN_ON(cpumask_empty(mask))) { cpu = cpumask_first(mask); sink = coresight_get_sink(etm_event_cpu_path(event_data, cpu)); - if (sink_ops(sink)->free_buffer) - sink_ops(sink)->free_buffer(event_data->snk_config); + sink_ops(sink)->free_buffer(event_data->snk_config); } for_each_cpu(cpu, mask) { @@ -215,7 +214,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, sink = coresight_get_enabled_sink(true); } - if (!sink || !sink_ops(sink)->alloc_buffer) + if (!sink) goto err; mask = &event_data->mask; @@ -261,6 +260,9 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, if (cpu >= nr_cpu_ids) goto err; + if (!sink_ops(sink)->alloc_buffer || !sink_ops(sink)->free_buffer) + goto err; + /* Allocate the sink buffer for this session */ event_data->snk_config = sink_ops(sink)->alloc_buffer(sink, cpu, pages, From patchwork Thu Apr 4 03:35:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 161729 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1087331jan; Wed, 3 Apr 2019 20:36:29 -0700 (PDT) X-Google-Smtp-Source: APXvYqz9WcbPIO+UKTmuh1cUuto6bqf9xcO+ucNXsNOIGjpxL7nHtJGN3Tq8/Lk7RPR9Oy5kcKiB X-Received: by 2002:a65:6489:: with SMTP id e9mr3426142pgv.364.1554348989333; Wed, 03 Apr 2019 20:36:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554348989; cv=none; d=google.com; s=arc-20160816; b=lYgiDCq9cMiEgPOIW7GBxc4w4dtPOvaW2Q4zSfE+/F6egepEwjOPXJz9pk+HrhB/5T BccgtRhCWk6m8dDzfZJlq12sTg/0tFZYDOcDXVgSGcVI6IhB7ks4AT6XY0S26x4oHlOQ po+iGdFDt42S43LTaVtEwVMbGJktdVWg/fPdu5Dsms/ivPo46elH08QsA4iu928/Mb9m 8b0id8JBHpqD956V1wKebr9HETyrGaJNg5UtsOKGkEKBcU48RV7OgAXgGlKP0EiEDeV7 PXI/mzAsSU9dny3R5kivX0juN1ZmUt1gD7LiNdaCNPuFMXFnIlVeUct7URhdtONbSFvp ypPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=Dv9y6a52f07gLfeGg5bt9mu9Q1KVd8oRTBa2/L6JdcE=; b=K9YBdyWfKuVlM3j+14UiHo0gYm3/kTcV4Cv5ksBkjVY6+sxtksNaOMPL77TXkSWDJj xm9gUIk6w+drfciV5guzLQl00KJgwVzN3gtZptpvMWFOnho3QDjPR6E2lqU00ehpm0NH 8P12EG90G0B/sMwWamRaIjxTBuHIMgL88YUCIcouuBjbY5LL1sKa/grlvur3Orf1MlPo smlL3rR3HcxymNAoIbydd802+JFqWxiBxZpZgWjSJVhqHjRkbm4WzyOjzcghQTrCVaaB 1ypI65Ibx3b1OCACsO4lWnWNFVvOx8C1OPg6y/hEVsMXREsbRPW86bQSbwMVVYqqxwIP rkCg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nd7rhGJL; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f66si16431083plb.261.2019.04.03.20.36.29; Wed, 03 Apr 2019 20:36:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nd7rhGJL; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728552AbfDDDg1 (ORCPT + 31 others); Wed, 3 Apr 2019 23:36:27 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:34288 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728412AbfDDDg0 (ORCPT ); Wed, 3 Apr 2019 23:36:26 -0400 Received: by mail-pg1-f194.google.com with SMTP id v12so515448pgq.1 for ; Wed, 03 Apr 2019 20:36:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Dv9y6a52f07gLfeGg5bt9mu9Q1KVd8oRTBa2/L6JdcE=; b=nd7rhGJLp6uakVyfCcVqzS4ysrJlCjbe5qVHJ8WFBTutz45kQj0T1EKbTNqXsJ4Xo1 MXdii2+cyi0GnFyuX1/98yRAyZ81XFHh9Cn5e9yNLFJ+FZnJUsIFz1r5MvKX4LDeJLpl NQGj7G0eT5J/HCL/rF3/hj/YNYFac8nBgUNFebnX5wdf86aZjZ6yqabOO1Xeh8CHikcl 1TH+dgxG4SOYPB5wxYiwoJC26THS5CCeXcyqpeM+Vxk1gwZVsmTJlNOENdWtUyHT7w1O 4JL1IUaXgTJgBCvBxLnEAQRBDyVxzYBvlCx0el9OyYb8y7U4Ft5agX32zwYeEgjMSkiY chjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Dv9y6a52f07gLfeGg5bt9mu9Q1KVd8oRTBa2/L6JdcE=; b=OXsosUB9LB3skzHVTgjQ0Z+8nZsNX/IpSgUstuY0tBA+my6fyXwLEtJUhH9S4Y5A3N P2jAhwlSE3jbmpz44X+TmXCsE0H0fehaW2I95HZB4kHBX9DjfGyxBdd2mZo+KGk1K8kE Yp/OQ/FDSlzVpMztbhi/2cYsH1niVS/QKDorCeMeKl5mm8TynSDRIFn0zv3gL8dJcwuE 9Zp2Zwxqjj8cPbcyeeIVn1P2DYCDa/LSxBJ1bsqU3AIEsiubVsYILH9QJAYBPGxzVeXx SkM6yKzp8SowIk/7O9o5J0vAdQG6dH3/KIKaM3EzKdDjSVP2MENXWsZ05RaEPE++fpWg okCw== X-Gm-Message-State: APjAAAWrvbIdy2NrCebSukoqoutz5HO0sSbKzXhW+HlOA3AJs7+9uGNv PWMtAlB2cTDbPUWByFUad4Mggg== X-Received: by 2002:a62:e50a:: with SMTP id n10mr3324246pff.55.1554348985691; Wed, 03 Apr 2019 20:36:25 -0700 (PDT) Received: from xps15.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id u5sm12212780pfm.121.2019.04.03.20.36.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 03 Apr 2019 20:36:24 -0700 (PDT) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org Cc: alexander.shishkin@linux.intel.com, peterz@infradead.org, suzuki.poulose@arm.com, mike.leach@arm.com, leo.yan@linaro.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 10/20] coresight: perf: Refactor function free_event_data() Date: Wed, 3 Apr 2019 21:35:31 -0600 Message-Id: <20190404033541.14072-11-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190404033541.14072-1-mathieu.poirier@linaro.org> References: <20190404033541.14072-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Function free_event_data() is already busy and is bound to become worse with the addition of CPU-wide trace scenarios. As such spin off a new function to strickly take care of the sink buffers. Signed-off-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose --- .../hwtracing/coresight/coresight-etm-perf.c | 24 ++++++++++++++----- 1 file changed, 18 insertions(+), 6 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index b8ca3800b56b..806b3dd5872d 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -120,22 +120,34 @@ static int etm_event_init(struct perf_event *event) return ret; } +static void free_sink_buffer(struct etm_event_data *event_data) +{ + int cpu; + cpumask_t *mask = &event_data->mask; + struct coresight_device *sink; + + if (WARN_ON(cpumask_empty(mask))) + return; + + if (!event_data->snk_config) + return; + + cpu = cpumask_first(mask); + sink = coresight_get_sink(etm_event_cpu_path(event_data, cpu)); + sink_ops(sink)->free_buffer(event_data->snk_config); +} + static void free_event_data(struct work_struct *work) { int cpu; cpumask_t *mask; struct etm_event_data *event_data; - struct coresight_device *sink; event_data = container_of(work, struct etm_event_data, work); mask = &event_data->mask; /* Free the sink buffers, if there are any */ - if (event_data->snk_config && !WARN_ON(cpumask_empty(mask))) { - cpu = cpumask_first(mask); - sink = coresight_get_sink(etm_event_cpu_path(event_data, cpu)); - sink_ops(sink)->free_buffer(event_data->snk_config); - } + free_sink_buffer(event_data); for_each_cpu(cpu, mask) { struct list_head **ppath; From patchwork Thu Apr 4 03:35:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 161730 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1087401jan; Wed, 3 Apr 2019 20:36:34 -0700 (PDT) X-Google-Smtp-Source: APXvYqxcWN6cr6mvPmTBnMO1R7opbAiJsAZml+/uR09PX8ofqvTw3iUgpVtxSYFmcw3AAJEwO0/E X-Received: by 2002:a62:b612:: with SMTP id j18mr3429381pff.124.1554348994818; Wed, 03 Apr 2019 20:36:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554348994; cv=none; d=google.com; s=arc-20160816; b=Ts+UJ4d3yYiYSTbQ+7w3XIcErFuHkhh3mb1cfvCZv7A8S3rVv3wpYiMgKHtvROn7J2 2uWfLxk1xbp4IalbtSGalka11Vv5fmeh/79k1PUvdzhk1G9ImJoLEjctiTEGmxFGK255 qsxGFrFcyhYremd0tWb7LzQ8jI5iXjVx1TgjGg5XDOVW6OGQG2r/2ZPIANSxuCV9aA48 5mXyqY7XRpc3xJ+FR9OdPH2ONtnpMUF8Wkyzu/mM/YwV2p8AEnQutXdLc5wDbJNucMBP aJOn2Su33vROFSHPZo0iqWosnUKK6frobxbPXmh7PaAEyI3Vwxt/K6j+JVl5VDXXlDUZ 8a9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=ednxYZuT+oA8hxh6HD6VGiDDQ3dBG66DPU7JCj5TchU=; b=RjhGEgOS4TxjFrg/3ZdMVN3SO4K3dqHbttavXdCK6ayARAh2UsQCQppg/h3cK+swoz 9Azjk/p4fbI9DDVC25/+IiU36I+W+5LNroMlWeiiA/lj/9i9aa4LWZDUeybHeCtRMl4Q +qT+xZf2y+2QmDUtSjZeZEXzVjvuES+wG+3GnJhvlCXcmrVKVW4+LyEL7C298QPAWZTL 9GNtvsrBadX/QWB1GDbNip4j5/ZcKtNMmV3NPezE1/+Qj60MFfoURbrnDMfPo7KZBjin xCCuu88QwvIED5kSnBbiVBgXy+boRxK6Vy2IfoKh17vISkqOydyiowzdtJPT5RVDLo9t tVFQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CyJzb0Uj; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f32si16064956plf.24.2019.04.03.20.36.34; Wed, 03 Apr 2019 20:36:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CyJzb0Uj; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728594AbfDDDgd (ORCPT + 31 others); Wed, 3 Apr 2019 23:36:33 -0400 Received: from mail-pg1-f196.google.com ([209.85.215.196]:33519 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728553AbfDDDga (ORCPT ); Wed, 3 Apr 2019 23:36:30 -0400 Received: by mail-pg1-f196.google.com with SMTP id k19so519277pgh.0 for ; Wed, 03 Apr 2019 20:36:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ednxYZuT+oA8hxh6HD6VGiDDQ3dBG66DPU7JCj5TchU=; b=CyJzb0UjFCPMfiNKnar/GdUSuGYeNSF22bfv4yi9xlJKYV8z5MahFDaHXDlOExNlcQ EHps+jWEkCsiIAHi0j9u7oKr7KoOqK5YTAqGcmYsxPLU5wk0xzjfhbPlEqpA3avNcdk4 aI4hKBiD0YTTB3hYeKD/KdFV61/HHq7VyRikeOjxfbocQh3jw4bFWCFJWK6FXb9rOO5k 9O/NZYxgEhOCIfYtecRElXvFs2GoFMzq2yGZKoOH2tdi87lJk8FjDf8pEEe2ja8MAGlr RkYJOee6rvZrrkmg3ZIGeVIAgB0ZLGCTmuGGwTQIUkpqw+EkqalUfRptOoohaUS19epF xX4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ednxYZuT+oA8hxh6HD6VGiDDQ3dBG66DPU7JCj5TchU=; b=pvBQzlUjrHVd81ncNapTRV4WIfrh0B05vWFhN45nbnTfEZqApcoCf9F50X5sJPyVxl Q6y4nYv8tRUqqOT6fJVmzHmb7vpdRZbyZ/CL+vi/4aoZMbkSHD3OBR9tuC5X00rQdVi0 lxBynNifl8jq0pHvBGtYrGHQGvo0Pr67uUqW7vYQzoMgFx32jl9NYT93JKgMjocPRYES iWo47UpPpcggzhye34ZTOpDHDn3JDACRNh35qZEJgdN+Cad3P0yW7y0NVdNqT3N6AfJ8 a2GdYYKtFHq6bK548EZ+S2RbFF/pk2I64gHCWzZ9HrwkV+UFGSaq2b6HLJVBaaSIEQXe wr0w== X-Gm-Message-State: APjAAAXRZ2ssOUkQTzq8doI9mj/JmYJ4qnnSDKsnYpV1JnMRSfwGb0Fz r/wA26ipwJIk12Ni6rC3hhPOUg== X-Received: by 2002:a63:5150:: with SMTP id r16mr3247658pgl.307.1554348989515; Wed, 03 Apr 2019 20:36:29 -0700 (PDT) Received: from xps15.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id u5sm12212780pfm.121.2019.04.03.20.36.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 03 Apr 2019 20:36:28 -0700 (PDT) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org Cc: alexander.shishkin@linux.intel.com, peterz@infradead.org, suzuki.poulose@arm.com, mike.leach@arm.com, leo.yan@linaro.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 11/20] coresight: Communicate perf event to sink buffer allocation functions Date: Wed, 3 Apr 2019 21:35:32 -0600 Message-Id: <20190404033541.14072-12-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190404033541.14072-1-mathieu.poirier@linaro.org> References: <20190404033541.14072-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Make struct perf_event available to sink buffer allocation functions in order to use the pid they carry to allocate and free buffer memory along with regimenting access to what source a sink can collect data for. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etb10.c | 7 ++++--- .../hwtracing/coresight/coresight-etm-perf.c | 2 +- .../hwtracing/coresight/coresight-tmc-etf.c | 7 ++++--- .../hwtracing/coresight/coresight-tmc-etr.c | 18 ++++++++++-------- include/linux/coresight.h | 5 +++-- 5 files changed, 22 insertions(+), 17 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 6b50e781dc57..7d64c41cd8ac 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -351,10 +351,11 @@ static int etb_disable(struct coresight_device *csdev) return 0; } -static void *etb_alloc_buffer(struct coresight_device *csdev, int cpu, - void **pages, int nr_pages, bool overwrite) +static void *etb_alloc_buffer(struct coresight_device *csdev, + struct perf_event *event, void **pages, + int nr_pages, bool overwrite) { - int node; + int node, cpu = event->cpu; struct cs_buffers *buf; if (cpu == -1) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index 806b3dd5872d..3c6294432748 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -277,7 +277,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, /* Allocate the sink buffer for this session */ event_data->snk_config = - sink_ops(sink)->alloc_buffer(sink, cpu, pages, + sink_ops(sink)->alloc_buffer(sink, event, pages, nr_pages, overwrite); if (!event_data->snk_config) goto err; diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index a38ad2b0d95a..1df1f8fade71 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -350,10 +350,11 @@ static void tmc_disable_etf_link(struct coresight_device *csdev, dev_dbg(drvdata->dev, "TMC-ETF disabled\n"); } -static void *tmc_alloc_etf_buffer(struct coresight_device *csdev, int cpu, - void **pages, int nr_pages, bool overwrite) +static void *tmc_alloc_etf_buffer(struct coresight_device *csdev, + struct perf_event *event, void **pages, + int nr_pages, bool overwrite) { - int node; + int node, cpu = event->cpu; struct cs_buffers *buf; if (cpu == -1) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 86e748d09dc3..00db6a6ce23f 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1166,13 +1166,18 @@ static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev) * reaches a minimum limit (1M), beyond which we give up. */ static struct etr_perf_buffer * -tmc_etr_setup_perf_buf(struct tmc_drvdata *drvdata, int node, int nr_pages, - void **pages, bool snapshot) +tmc_etr_setup_perf_buf(struct tmc_drvdata *drvdata, struct perf_event *event, + int nr_pages, void **pages, bool snapshot) { + int node, cpu = event->cpu; struct etr_buf *etr_buf; struct etr_perf_buffer *etr_perf; unsigned long size; + if (cpu == -1) + cpu = smp_processor_id(); + node = cpu_to_node(cpu); + etr_perf = kzalloc_node(sizeof(*etr_perf), GFP_KERNEL, node); if (!etr_perf) return ERR_PTR(-ENOMEM); @@ -1210,16 +1215,13 @@ tmc_etr_setup_perf_buf(struct tmc_drvdata *drvdata, int node, int nr_pages, static void *tmc_alloc_etr_buffer(struct coresight_device *csdev, - int cpu, void **pages, int nr_pages, - bool snapshot) + struct perf_event *event, void **pages, + int nr_pages, bool snapshot) { struct etr_perf_buffer *etr_perf; struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - if (cpu == -1) - cpu = smp_processor_id(); - - etr_perf = tmc_etr_setup_perf_buf(drvdata, cpu_to_node(cpu), + etr_perf = tmc_etr_setup_perf_buf(drvdata, event, nr_pages, pages, snapshot); if (IS_ERR(etr_perf)) { dev_dbg(drvdata->dev, "Unable to allocate ETR buffer\n"); diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 189cc6ddc92b..62a520df8add 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -193,8 +193,9 @@ struct coresight_device { struct coresight_ops_sink { int (*enable)(struct coresight_device *csdev, u32 mode, void *data); int (*disable)(struct coresight_device *csdev); - void *(*alloc_buffer)(struct coresight_device *csdev, int cpu, - void **pages, int nr_pages, bool overwrite); + void *(*alloc_buffer)(struct coresight_device *csdev, + struct perf_event *event, void **pages, + int nr_pages, bool overwrite); void (*free_buffer)(void *config); unsigned long (*update_buffer)(struct coresight_device *csdev, struct perf_output_handle *handle, From patchwork Thu Apr 4 03:35:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 161731 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1087427jan; Wed, 3 Apr 2019 20:36:37 -0700 (PDT) X-Google-Smtp-Source: APXvYqzw8QP8n7HF8VNG/V36GF6o2s+dEkJXbX7SbSOCUYLAyyRnW8Sj+4kBz2cxVX2tMoPti4sI X-Received: by 2002:a62:1318:: with SMTP id b24mr3255584pfj.201.1554348997724; Wed, 03 Apr 2019 20:36:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554348997; 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[209.132.180.67]) by mx.google.com with ESMTP id f32si16064956plf.24.2019.04.03.20.36.37; Wed, 03 Apr 2019 20:36:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qXhOlJqP; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728641AbfDDDgg (ORCPT + 31 others); Wed, 3 Apr 2019 23:36:36 -0400 Received: from mail-pf1-f195.google.com ([209.85.210.195]:38157 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728553AbfDDDgd (ORCPT ); Wed, 3 Apr 2019 23:36:33 -0400 Received: by mail-pf1-f195.google.com with SMTP id 10so625567pfo.5 for ; Wed, 03 Apr 2019 20:36:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dOOzJONg42NBLUevdjidfidJoqrClGTmFfG3kUUzoxQ=; b=qXhOlJqPUARfaFRhk52W+mdWfLOuctMZRZL+W/w7PkoTzwJehVfu/CSbnqE7KuHEbG wEqDswYmao+uuJ55P/SNTWJ2q+VHF7M3zbj5UnFBy2rn8iq/LS2lKxzff5g/qcxYZIw3 qdgM5FuaS/DEGzMCy8RiTbrxYmNRZzKx5Jh/QwJ0GUQQoCRa4YBuph91rmXfm3W2FiZY tW09b3cejjCN2nmCbToB8Gfg0i28XiA6P+IbyAUWekRyrMpimXCB92W44kpgi6+kZFES umLywbqC2ssdNYBrLJseCl3SdmPWBGzZmWZnY1ptvETPAi2wGf1xB7Vwzs1EehjWIHi+ en2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dOOzJONg42NBLUevdjidfidJoqrClGTmFfG3kUUzoxQ=; b=khigKKWzZQNOD6B2BAySzUrXcs4eXqupQzayQVwp3C63QxVKXNlct3kTXN+jGGp4Jy 6TEnf8SNcg8PfkHkFPwwHmbQyxeO0WDvNGoEjHI1hs+Pw7lU9w/HXbGZV5Q4LxRVSVJa Y7BhjQ+0NiR3OHsOzmeOAe/Vqpid9QWE3hGZLek6a5DVSUdIfXhXX3dNep+nwZuxO12Z PsQqTa/tTt4ijYsxuG1dSV5CCjz2swFybINB/d9cpvbiMEsh/tTDHGQcYUa4HbhxGQBC DKTbqsMkDXaKUNbt7V6l886qI8js2TKmAWxk7mASmNSpgdhIa48iLs0DsEjAYe8U81VW KunQ== X-Gm-Message-State: APjAAAUfH3fVCM8BQO51yzd38c3BXVs1l8jwvvlRZuuPE9feelTAmaVc ekwR3yp8UX5R+VsbYtU1/jrb8w== X-Received: by 2002:a63:8143:: with SMTP id t64mr3341387pgd.301.1554348993093; Wed, 03 Apr 2019 20:36:33 -0700 (PDT) Received: from xps15.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id u5sm12212780pfm.121.2019.04.03.20.36.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 03 Apr 2019 20:36:32 -0700 (PDT) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org Cc: alexander.shishkin@linux.intel.com, peterz@infradead.org, suzuki.poulose@arm.com, mike.leach@arm.com, leo.yan@linaro.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 12/20] coresight: tmc-etr: Refactor function tmc_etr_setup_perf_buf() Date: Wed, 3 Apr 2019 21:35:33 -0600 Message-Id: <20190404033541.14072-13-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190404033541.14072-1-mathieu.poirier@linaro.org> References: <20190404033541.14072-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Refactoring function tmc_etr_setup_perf_buf() so that it only deals with the high level etr_perf_buffer, leaving the allocation of the backend buffer (i.e etr_buf) to another function. That way the backend buffer allocation function can decide if it wants to reuse an existing buffer (CPU-wide trace scenarios) or simply create a new one. Signed-off-by: Mathieu Poirier --- .../hwtracing/coresight/coresight-tmc-etr.c | 39 ++++++++++++++----- 1 file changed, 30 insertions(+), 9 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 00db6a6ce23f..e9c77009188a 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1159,29 +1159,24 @@ static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev) } /* - * tmc_etr_setup_perf_buf: Allocate ETR buffer for use by perf. + * alloc_etr_buf: Allocate ETR buffer for use by perf. * The size of the hardware buffer is dependent on the size configured * via sysfs and the perf ring buffer size. We prefer to allocate the * largest possible size, scaling down the size by half until it * reaches a minimum limit (1M), beyond which we give up. */ -static struct etr_perf_buffer * -tmc_etr_setup_perf_buf(struct tmc_drvdata *drvdata, struct perf_event *event, - int nr_pages, void **pages, bool snapshot) +static struct etr_buf * +alloc_etr_buf(struct tmc_drvdata *drvdata, struct perf_event *event, + int nr_pages, void **pages, bool snapshot) { int node, cpu = event->cpu; struct etr_buf *etr_buf; - struct etr_perf_buffer *etr_perf; unsigned long size; if (cpu == -1) cpu = smp_processor_id(); node = cpu_to_node(cpu); - etr_perf = kzalloc_node(sizeof(*etr_perf), GFP_KERNEL, node); - if (!etr_perf) - return ERR_PTR(-ENOMEM); - /* * Try to match the perf ring buffer size if it is larger * than the size requested via sysfs. @@ -1205,6 +1200,32 @@ tmc_etr_setup_perf_buf(struct tmc_drvdata *drvdata, struct perf_event *event, size /= 2; } while (size >= TMC_ETR_PERF_MIN_BUF_SIZE); + return ERR_PTR(-ENOMEM); + +done: + return etr_buf; +} + +static struct etr_perf_buffer * +tmc_etr_setup_perf_buf(struct tmc_drvdata *drvdata, struct perf_event *event, + int nr_pages, void **pages, bool snapshot) +{ + int node, cpu = event->cpu; + struct etr_buf *etr_buf; + struct etr_perf_buffer *etr_perf; + + if (cpu == -1) + cpu = smp_processor_id(); + node = cpu_to_node(cpu); + + etr_perf = kzalloc_node(sizeof(*etr_perf), GFP_KERNEL, node); + if (!etr_perf) + return ERR_PTR(-ENOMEM); + + etr_buf = alloc_etr_buf(drvdata, event, nr_pages, pages, snapshot); + if (!IS_ERR(etr_buf)) + goto done; + kfree(etr_perf); return ERR_PTR(-ENOMEM); From patchwork Thu Apr 4 03:35:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 161732 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1087486jan; Wed, 3 Apr 2019 20:36:42 -0700 (PDT) X-Google-Smtp-Source: APXvYqztDDiuLuGjYRsmGXiSy2dIQwIH0BnyVt4e2BrQ8FTm7h8nyUKC5jT7012477GpBwe4OzZx X-Received: by 2002:aa7:8092:: with SMTP id v18mr3257950pff.35.1554349002355; Wed, 03 Apr 2019 20:36:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554349002; cv=none; d=google.com; s=arc-20160816; b=IP7+kwrNuJlpacAAr7YIvLcEjx8PaSmA2jVflbhb3+ya2sUjm/XcHFPxxHdUXYq8pQ DgSNxT+aG/BGT8+D0u4uSbC7vSoqhltmyVhyeD7hlUBGjUM0uaYIai5y1e6PxV2mV6Kf go2RnBRVr4xBUc6dPhSxY7e1AnFZgndwhryysqQZdZc/ocxmp3dgH0HbN5ONpu5bm8df +bxiC7w9O0Tit5V/tuaOaSRKZD3vuOj8tc3OaYVDd2YJlpnDipCAyYlC6s0Zgu21Ajc1 DeuoCLMvheqLB+W6U+WEfDQ4zaKwM8oBPCB+LuiRuohPw7N9D3z28/AfF6WQWBohWiRp HtRw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=3HdOcyQCq9wrU1AdvtM6R2lHiYyKElGkieSf9jn2Q7c=; b=F5Ts18t5PuEgCr3mJYVbGyA+2x2yLF1VYbHztedo+C667fxrQmn7PvAoEn8UOsNqpe 2qLg4YabGwbHZLdynd8qV0nJx3qJgkztmgEMw7Jjlinnp/hBv3v0L75gliEtCuHeqlOW d/PphvFktQbPtRAgRjgYYxF8XAc/PFqQv41VVvgap1C/9Uz75Czh903c3jB9WH0QKigJ k3FE+xHcPEPku2flGhG1itDxOydFrjBt/T9V8IRdZSZi5vJ3enmBZg8WS6O9mqq2HdIq +h2lFbLWN0DXClgVtHlv4s+S1eAdgXrdEpXNbJU1DmoL3DN7Lcm8VrkS4DGACKdttu/+ HW0g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=slFc+tqc; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m2si5350508pgm.258.2019.04.03.20.36.42; Wed, 03 Apr 2019 20:36:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=slFc+tqc; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728658AbfDDDgk (ORCPT + 31 others); Wed, 3 Apr 2019 23:36:40 -0400 Received: from mail-pf1-f193.google.com ([209.85.210.193]:38159 "EHLO mail-pf1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728553AbfDDDgh (ORCPT ); Wed, 3 Apr 2019 23:36:37 -0400 Received: by mail-pf1-f193.google.com with SMTP id 10so625638pfo.5 for ; Wed, 03 Apr 2019 20:36:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3HdOcyQCq9wrU1AdvtM6R2lHiYyKElGkieSf9jn2Q7c=; b=slFc+tqcLXHYhCkIxgtfmG/A+C0SXJdQV/GnM6Oqifk9ED1Eb60jGCl5ehaz7kum9f /zzsI+zMaS64QEk6OeKJbO9qcb/orb7/xJSHlQTFmSoO32iuFd/gtifKgQiWwjEWAw+6 pa6GUmvQyLt3tUY8/QjNRxSLmNSas0E/Vo+nPOcrBRcyZs+DpdNZqr8OqkDEwiGMwzfI Nt1zrt4RMmEeVYi0JspPGlerBrJ5vgpDHQm5WSpokzXHsTwI0k4oGUWbnJmADATo1Rer zBYu9x1qeJzwAjdBEnorMU8S20jXoX2i/GxSjd69q//Voh0psQhboexDaqx5hpCqCiP2 Hfow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3HdOcyQCq9wrU1AdvtM6R2lHiYyKElGkieSf9jn2Q7c=; b=nuiKpkIvz6mT6WTvzZcCY+4e1Hmf4SzhBUf9BvIZ4vqc9BnTiZd6cVk2MpG40HZkX/ Fn3XfjIeyQetEpjWcrocgmG7awlzqp72sybUCFQ31/Jxk0XjXz14Tp0DgKLjthER5ZZm yNntY/+09lMvMJN/j1bVn1HnEuiLgQyK6uEw11XVCdZyOWbyax1V8zJQV2HckOnF2btC WznIVoKxICMMTpROYJ7ZjgLpN2GNq11BlQIxyxqTBR58+2KGtT7aKUzz2cnt4PzQw24l A82roVTrcYMMdfm0SMXdR+sCy5CkPk4lIeOBVgJotBiB0lR/svGLuB25AB276AwnGoiq g++w== X-Gm-Message-State: APjAAAWEGiLSlNNvZDHxeCSAfqYsf+Wo6SHBjApZxVC2MqPJ5i2hvqYH PH/YXXEuQKh8qRZulff0ORRvlw== X-Received: by 2002:a63:b64:: with SMTP id a36mr3487712pgl.58.1554348996718; Wed, 03 Apr 2019 20:36:36 -0700 (PDT) Received: from xps15.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id u5sm12212780pfm.121.2019.04.03.20.36.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 03 Apr 2019 20:36:36 -0700 (PDT) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org Cc: alexander.shishkin@linux.intel.com, peterz@infradead.org, suzuki.poulose@arm.com, mike.leach@arm.com, leo.yan@linaro.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 13/20] coresight: tmc-etr: Create per-thread buffer allocation function Date: Wed, 3 Apr 2019 21:35:34 -0600 Message-Id: <20190404033541.14072-14-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190404033541.14072-1-mathieu.poirier@linaro.org> References: <20190404033541.14072-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Buffer allocation is different when dealing with per-thread and CPU-wide sessions. In preparation to support CPU-wide trace scenarios simplify things by keeping allocation functions for both type separate. Signed-off-by: Mathieu Poirier --- .../hwtracing/coresight/coresight-tmc-etr.c | 29 ++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index e9c77009188a..ac1efdfc0d07 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1206,6 +1206,33 @@ alloc_etr_buf(struct tmc_drvdata *drvdata, struct perf_event *event, return etr_buf; } +static struct etr_buf * +get_perf_etr_buf_per_thread(struct tmc_drvdata *drvdata, + struct perf_event *event, int nr_pages, + void **pages, bool snapshot) +{ + struct etr_buf *etr_buf; + + /* + * In per-thread mode the etr_buf isn't shared, so just go ahead + * with memory allocation. + */ + etr_buf = alloc_etr_buf(drvdata, event, nr_pages, pages, snapshot); + + return etr_buf; +} + +static struct etr_buf * +get_perf_etr_buf(struct tmc_drvdata *drvdata, struct perf_event *event, + int nr_pages, void **pages, bool snapshot) +{ + if (event->cpu == -1) + return get_perf_etr_buf_per_thread(drvdata, event, nr_pages, + pages, snapshot); + + return ERR_PTR(-ENOENT); +} + static struct etr_perf_buffer * tmc_etr_setup_perf_buf(struct tmc_drvdata *drvdata, struct perf_event *event, int nr_pages, void **pages, bool snapshot) @@ -1222,7 +1249,7 @@ tmc_etr_setup_perf_buf(struct tmc_drvdata *drvdata, struct perf_event *event, if (!etr_perf) return ERR_PTR(-ENOMEM); - etr_buf = alloc_etr_buf(drvdata, event, nr_pages, pages, snapshot); + etr_buf = get_perf_etr_buf(drvdata, event, nr_pages, pages, snapshot); if (!IS_ERR(etr_buf)) goto done; From patchwork Thu Apr 4 03:35:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 161733 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1087533jan; Wed, 3 Apr 2019 20:36:46 -0700 (PDT) X-Google-Smtp-Source: APXvYqwuxIqDteNKwHDuyAqQH31ouB6RYo9MZhAIsiNeapibCu2IW9GVXdGjSX/aLrzpVyaqmBPQ X-Received: by 2002:aa7:9294:: with SMTP id j20mr3384223pfa.64.1554349006081; Wed, 03 Apr 2019 20:36:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554349006; cv=none; d=google.com; s=arc-20160816; b=CBa7oECt8JZnSR70396KmGfSvRydw7Pszz9iRJ4duBBGZJ6bsnISX2tpvYv7AM92uq Oh/ZzYabM2MjKwMX6uNSeS0Nc9VMoi0SPlLo2Jyk0NthZXS/HFbrF4oyrmt9w0cJzXau nopHrECJ8TVRnVvjMM6kOUZ2G3Tx2x+Aa2bJoaftrrJRLzrB5AOWALhSduPOWgYTXKFr hewVW8d6Ev+cBlhJIe4yIl5eIyfDy/zZpHbjAqd5kNYPBcVaaRrGAKTcpHPtU1FV+sTw fXjMQ6jIa+Il2+u4NCjiVgYFe+/aWPvCUeHA35QwDaLvNe40z2czjY1zVMMv91SmWFC2 yUhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=SAt54gusO22M7wlCjXKs+Y6DbEbN3JCXkJVbAiVcyrQ=; b=vC9+1BUpzR4ktrYKXFNAnpp5cRf1clE8ON8QuYo+V2ZhS5rcBOFEjB0zlybDezKPDY j+caSGjMKvtbXG/0Yd6/48E7q89RzQ1eRYgZqizcITqWQeGB6KgV4NL2M3Y/cdErQZdl H8CdbDM9bOVBG8dcT2yvTExTr3ynI24HWAuDQIOAucOFHUrrWLC+DZPkxSI4+VSGhvj+ DR75tPVrdXm7N44tBVZsXc3fHk6l0nNdAywggc0Ogm/ujYU9qSr0ZIMIvb/EInGYooTj 32kCxbQhPcMDsGnbqCwrlvf85HQXFoDEwZX19dJlaYiBp0g+pPHVaPmfnIRXHjhsIfoM Tslw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=U6yFsd+6; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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That way events monitoring the same process can use the same etr_buf, allowing multiple CPUs to use the same sink. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-tmc-etr.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index ac1efdfc0d07..e1774d4bb5f3 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include "coresight-catu.h" #include "coresight-etm-perf.h" @@ -25,6 +26,7 @@ struct etr_flat_buf { /* * etr_perf_buffer - Perf buffer used for ETR * @etr_buf - Actual buffer used by the ETR + * @pid - The PID this etr_perf_buffer belongs to. * @snaphost - Perf session mode * @head - handle->head at the beginning of the session. * @nr_pages - Number of pages in the ring buffer. @@ -32,6 +34,7 @@ struct etr_flat_buf { */ struct etr_perf_buffer { struct etr_buf *etr_buf; + pid_t pid; bool snapshot; unsigned long head; int nr_pages; @@ -1276,6 +1279,7 @@ static void *tmc_alloc_etr_buffer(struct coresight_device *csdev, return NULL; } + etr_perf->pid = task_pid_nr(event->owner); etr_perf->snapshot = snapshot; etr_perf->nr_pages = nr_pages; etr_perf->pages = pages; From patchwork Thu Apr 4 03:35:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 161734 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1087557jan; Wed, 3 Apr 2019 20:36:48 -0700 (PDT) X-Google-Smtp-Source: APXvYqyW7Y7Vb6MzEwpPsCicHwcRYlhIgnnqxxiavAqnVsKxoQhp5HjEv8uZjJQzxLLWG2/zq2du X-Received: by 2002:aa7:914d:: with SMTP id 13mr3318283pfi.149.1554349008732; Wed, 03 Apr 2019 20:36:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554349008; cv=none; d=google.com; s=arc-20160816; b=Hoa5TLKgogvE7o7rnO+0as25aaVrwyyVt3xHxBaIb+MRaJxdT+JQh1ogplg6ntC3yI 8F5sIuti6HTEauTeMaVwnTL9Pheb0JbnMemsacroJOyuhy4I3dPv3B7rfT5AQOrZCVr1 qPbBfU2wfMNLoEdKDuEZU2Ng9NREsGqjIt8oRdvqx+p9UC2xPTfPkCTdy1miDnblR/Nh RJxfKlx3sz/Lkr86ySkYH96cq9+TxbucZ8afY/p+lNfOIRCvg6xiV64BzsNOCKjdelKQ DZ2213lP+J1b0axW2wKopxtdXFHwDHJBvpBratxFvbZeS32N/WSnzuFzGl3Cgcp1oUZ0 wJ2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=H9+OTr1OpfrOYtthYPTeqD/UZckEAYj6DoPWjl6ycEY=; b=Dp1wcS7BSvcDgzosSclk+Ot0aGbG/OsP2uVNL1iDGlb1cv/NJQew/NzKyw7rRcZJox RwNQxHmjEXhd0SdHJCq/ei/cW2Syc+RzLFlFxTuYebXtiaThYnsQ2/wRUvhloUO5tZSl 1Hkma79NaRikqbeixaQjLUHI+HoyvtyWJS4D9nAbSSgfLc91Ti1fJiRk/ixNWQmakYzi OwaOzboXs17cQn5lrWa2LEHzZ4T0J7oZufkYJVCfq3Five1jqYwqGxihMovKjw+uTtxb ba9TG4O/8AFHAdk+NhseE9G10Vpj/k8mn1pLf8xdNGo3p2BOO4wRGrFJv0buQkt1fAyn RTpQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=K68wBhJE; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z31si15750482plb.333.2019.04.03.20.36.48; Wed, 03 Apr 2019 20:36:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=K68wBhJE; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728688AbfDDDgr (ORCPT + 31 others); Wed, 3 Apr 2019 23:36:47 -0400 Received: from mail-pl1-f196.google.com ([209.85.214.196]:36615 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728671AbfDDDgo (ORCPT ); Wed, 3 Apr 2019 23:36:44 -0400 Received: by mail-pl1-f196.google.com with SMTP id ck15so445031plb.3 for ; Wed, 03 Apr 2019 20:36:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=H9+OTr1OpfrOYtthYPTeqD/UZckEAYj6DoPWjl6ycEY=; b=K68wBhJEME7fnO0jZ2eonmNB3GuHTmOF7iCsl8xEsvaPBFjiqFF+5Nx8BZrytnDPl4 3ozNLTYUVmxGm8C7sKWtJhEIGbZhe66ILZqt6EtA7ZjECx29SvjbtRXGGqJ442bA5G1w BwhJWUbLlnX6r0ICNZfbFN2SPI2NnE78gkpzd1kUmAMVCzEynsjygMDbu3t32CV0Yl2H bTtaXq5um59sufHwsYirJ5SP4nC6Nsmgm5IgRzCjRTgVy3dQiF1qWGETfMRMC27MqUmr 2Xfz3DXGVArX2qERcU4h3xJCG9AmO1yGqUOAqw+rkQLkVf7xlMbf2lP2pMlBrUIjk2tK izsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=H9+OTr1OpfrOYtthYPTeqD/UZckEAYj6DoPWjl6ycEY=; b=I3pxA0U7Cf2jlbfN9ykQUiwxZvLDJS9JFJMeebHzSgRvG0NzSeNy4c+/41KwTiCsiH Ll08ihj6h8kY+mROnKzm9iQFJtMlrII0WhnTXWef9xqNAlGiWiXdCQ8q8jI+2xiXnKhP QR+6p+wOWx0Dh8QN4FRTeVa4Z36RKysOmNtbfOoffvoWvwJg+sHNouOytS0+DhgntRkS MlqvxLKImj9vq5uRz7TqB52M6pZ7YGbBfFfxofo6Y10nYFTg4KWOtEOFjzrATpoXs80d Yv1v6qNM3+mlR1wNj+e8pbfJJNvgJVzTDRI7ywRrb4f4nJw7wWb6v8B66yoaeuUGzMgt gdDQ== X-Gm-Message-State: APjAAAX54eWntwVQy7xBykH0aMyJlz81g7VoDAdiFtZpk0B6nVYnhHUX SgWFQPrggfsD0/T3weNGdxqToA== X-Received: by 2002:a17:902:3283:: with SMTP id z3mr3762736plb.236.1554349003815; Wed, 03 Apr 2019 20:36:43 -0700 (PDT) Received: from xps15.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id u5sm12212780pfm.121.2019.04.03.20.36.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 03 Apr 2019 20:36:43 -0700 (PDT) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org Cc: alexander.shishkin@linux.intel.com, peterz@infradead.org, suzuki.poulose@arm.com, mike.leach@arm.com, leo.yan@linaro.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 15/20] coresight: tmc-etr: Introduce the notion of reference counting to ETR devices Date: Wed, 3 Apr 2019 21:35:36 -0600 Message-Id: <20190404033541.14072-16-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190404033541.14072-1-mathieu.poirier@linaro.org> References: <20190404033541.14072-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds reference counting to struct etr_buf so that, in CPU-wide trace scenarios, shared buffers can be disposed of when no longer used. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-tmc-etr.c | 5 +++++ drivers/hwtracing/coresight/coresight-tmc.h | 3 +++ 2 files changed, 8 insertions(+) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index e1774d4bb5f3..1346474ac019 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -1221,7 +1222,11 @@ get_perf_etr_buf_per_thread(struct tmc_drvdata *drvdata, * with memory allocation. */ etr_buf = alloc_etr_buf(drvdata, event, nr_pages, pages, snapshot); + if (IS_ERR(etr_buf)) + goto out; + refcount_set(&etr_buf->refcount, 1); +out: return etr_buf; } diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index 487c53701e9c..ee44906dffe8 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -9,6 +9,7 @@ #include #include +#include #define TMC_RSZ 0x004 #define TMC_STS 0x00c @@ -133,6 +134,7 @@ struct etr_buf_operations; /** * struct etr_buf - Details of the buffer used by ETR + * refcount ; Number of sources currently using this etr_buf. * @mode : Mode of the ETR buffer, contiguous, Scatter Gather etc. * @full : Trace data overflow * @size : Size of the buffer. @@ -143,6 +145,7 @@ struct etr_buf_operations; * @private : Backend specific information for the buf */ struct etr_buf { + refcount_t refcount; enum etr_mode mode; bool full; ssize_t size; From patchwork Thu Apr 4 03:35:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 161735 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1087584jan; Wed, 3 Apr 2019 20:36:51 -0700 (PDT) X-Google-Smtp-Source: APXvYqwRHBVQGHiYWdyluux08VOW3BcAedb4gAPJdY6DzC+5OdUMF5CiFNFj5Fhaqjk6e9yVOTSg X-Received: by 2002:a63:e653:: with SMTP id p19mr3401908pgj.284.1554349011827; Wed, 03 Apr 2019 20:36:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554349011; cv=none; d=google.com; s=arc-20160816; b=Ozqgrgfx4OqbzAXGOGVYDAfgQ5dYSy5bp08zrlkRlXSsC6tdAlyJpbG/ffSdFOT067 qtBkKfTvNBfaaS/s3fm5zOoT1VjibY8lCqXSybYpNQ3D0fnFLehAz26UCY7p+iIIeRGj IbW1Eqv5dHtjh1z4lhUBZXpCzDAXsJph9BvClRv189lJzWuv20YCnPdWEg5FSL4gLTxQ E8qWLM4bdmW5lR32AY/HUTIvbnOm81fkvtQm3cy6NUQERdjH2Sb+K/h7HUnXHLReSAa7 0m7lV2Xsu4woVIBAuOlpAjXGTUPT3tpcPHVFrrSZ7PwnuT5Hcunj2Usy2L3ZQS2I0o2s QdMQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=G1pTCL1CVW1J8+zqGHl3aMQK3cea75KFYLLVGa3aTuo=; b=gWymcUHwZAqx5kOC1/CL2AQ0DvNZf4o7l1XnPIvYDgj77AHROG47YPObeh+2jCACGP iqUNkd95SydLxr5CNv7DmtfcPAO5MzGUZ+lpQpdUlBCgJmz8xC3HiRi73636EBFklb6i iTjZGh9hCcmgbg4+oLQc3M7gKa4gsCDLoTBJzb8X7vlM2w3VcSCTNvt4LgdBjAZl6njX 0kSEzb2K7wuasRRBPLUXye0wARnkndJr4CudzDdyuvIUxnx4Df7KXVIlvITGg7tKEEzK UUPqMCaNSx2IgBZvTnMt/IywfAoD4PYIC0ZCwDYSuVUY9xwgIrvo5jFA44mCHysmtlz7 cs6g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KIHCnaFt; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z31si15750482plb.333.2019.04.03.20.36.51; Wed, 03 Apr 2019 20:36:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KIHCnaFt; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728708AbfDDDgu (ORCPT + 31 others); Wed, 3 Apr 2019 23:36:50 -0400 Received: from mail-pg1-f196.google.com ([209.85.215.196]:40485 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728671AbfDDDgs (ORCPT ); Wed, 3 Apr 2019 23:36:48 -0400 Received: by mail-pg1-f196.google.com with SMTP id u9so498995pgo.7 for ; Wed, 03 Apr 2019 20:36:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=G1pTCL1CVW1J8+zqGHl3aMQK3cea75KFYLLVGa3aTuo=; b=KIHCnaFtf0a36bnPS1J+zRFSumqsRdPPbVoWXwkeL1HXNwKWYsPasnJusJSH03de+g YrYEb2wJ/Xo+H/vWqEJdTjnFc4lejO+cXoI+Ur4SJwyNlqjDUm26N/hW4Lc7A7IRI8XE lHKqxmC/Fw69ZTS80V/oH5wYXxLlRR0MPw/3FbSQ9ivbTy8Z4M8ymHbgmxsEl+IAQ1Si DMF/oFhJMU8DXvkAC6SIB3Or8Rn+q4B0tTvNwmHYpT9Mx2TGfPWV5EUCbVNwyMyoWydI +XOQuiUO6i0q0zajwu3HaZNsiGLbgW9TWBgLUVMYb6u2i8Su233iQdtMSbCoZOVjHzgL hA8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=G1pTCL1CVW1J8+zqGHl3aMQK3cea75KFYLLVGa3aTuo=; b=K5I1D0owCinwDeKj0PbsLxMh6tAuKiO6ckDGCzvDpQdcVRGqpC9D3TI+FjaP01Jd9H 0YaNsOe6jt9P+m9wmcC33sZjeeFcanb8k02NWkDB+dgSh3Vv3qUrhFcbxcrqgKI5OZxp V5mrn8+dRz+xJAKX3JUssfkjFpIXfy3D83lGRxO9sjkmIJhE4FFA5d40hllBA9OBwsUA 98lX7GQMQ1PUHH1RgkRXm4Rg5ZPgnjy3asayEiOOIvyGDy2dcORlFejPZk5Kn7K6qp59 k0bC98e7HJTDCzwwIUCKU6MA1BunFinQIU1E7ILM/jLNrgSZgXF0nOzT/IG7okV0fU4y VXTA== X-Gm-Message-State: APjAAAWZVRunQ2yHGQuemktnsT27nPCA60L95Rt+hYPBFZnLitnAhxFb PdHs7ZG23I/qk2Nsvxe3DDlF4g== X-Received: by 2002:a63:c204:: with SMTP id b4mr3346998pgd.335.1554349007439; Wed, 03 Apr 2019 20:36:47 -0700 (PDT) Received: from xps15.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id u5sm12212780pfm.121.2019.04.03.20.36.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 03 Apr 2019 20:36:46 -0700 (PDT) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org Cc: alexander.shishkin@linux.intel.com, peterz@infradead.org, suzuki.poulose@arm.com, mike.leach@arm.com, leo.yan@linaro.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 16/20] coresight: tmc-etr: Introduce the notion of IDR to ETR devices Date: Wed, 3 Apr 2019 21:35:37 -0600 Message-Id: <20190404033541.14072-17-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190404033541.14072-1-mathieu.poirier@linaro.org> References: <20190404033541.14072-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In CPU-wide scenarios with an N:1 source/sink topology, sources share the same sink. In order to reuse the same sink for all sources an IDR is needed to archive events that have already been accounted for. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-tmc.c | 4 ++++ drivers/hwtracing/coresight/coresight-tmc.h | 6 ++++++ 2 files changed, 10 insertions(+) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c index 2a02da3d630f..71c86cffc021 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.c +++ b/drivers/hwtracing/coresight/coresight-tmc.c @@ -8,10 +8,12 @@ #include #include #include +#include #include #include #include #include +#include #include #include #include @@ -447,6 +449,8 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id) coresight_get_uci_data(id)); if (ret) goto out; + idr_init(&drvdata->idr); + mutex_init(&drvdata->idr_mutex); break; case TMC_CONFIG_TYPE_ETF: desc.type = CORESIGHT_DEV_TYPE_LINKSINK; diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index ee44906dffe8..c1b1700b2df7 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -8,7 +8,9 @@ #define _CORESIGHT_TMC_H #include +#include #include +#include #include #define TMC_RSZ 0x004 @@ -173,6 +175,8 @@ struct etr_buf { * @trigger_cntr: amount of words to store after a trigger. * @etr_caps: Bitmask of capabilities of the TMC ETR, inferred from the * device configuration register (DEVID) + * @idr: Holds etr_bufs allocated for this ETR. + * @idr_mutex: Access serialisation for idr. * @perf_data: PERF buffer for ETR. * @sysfs_data: SYSFS buffer for ETR. */ @@ -194,6 +198,8 @@ struct tmc_drvdata { enum tmc_mem_intf_width memwidth; u32 trigger_cntr; u32 etr_caps; + struct idr idr; + struct mutex idr_mutex; struct etr_buf *sysfs_buf; void *perf_data; }; From patchwork Thu Apr 4 03:35:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 161736 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1087619jan; Wed, 3 Apr 2019 20:36:55 -0700 (PDT) X-Google-Smtp-Source: APXvYqwKjN20EOEgYFhSNIeGsJXAKfVMiPfbRnkxlOoByKJQNKER6q5TjnOV0fG8aoPHrI5OYk+B X-Received: by 2002:a62:524e:: with SMTP id g75mr3311601pfb.106.1554349015329; Wed, 03 Apr 2019 20:36:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554349015; cv=none; d=google.com; s=arc-20160816; b=ZfponEod0KO4dJPcse8VfYmEqgAE8no3UFVaiwPyCeuHUTTyvekwUNP/38iU2Ui2Xq 95173CMizjy40O+hq61CZH9T1nIo3Ws+DLU83kJh928hfu2HdBjKdpeQJ0g/qvRoZoxs YX+K9WLlENERKmZJSZZRrYD0oCWYr/yH9gssHHl2G3oDdjkTbOOaIpjHLBNF8uN3Na+o P1C5TIKLE+/wn4rYp3kSUgLit+Uu2XrJs+vWs5BgfT8yrEZpuzKMeVfq7O+HJyHdPPVi AZxxUwUOrH28UXWJ+Xf2mD22bJHac9CZAOM32whnVUUURIo+J1BTlXQ/0ouoCi2pNoAE IJ6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=kFYUPXqDT+4NKa1uTQaXULpv7Y+YefzCDvbN138zMnI=; b=orFbVNLE7rVLSVLbIsEH1sx9U1YIKh3ya8Qq3g9yWwES6nemrfd/OmM3HnUBTZVQDN cZ7oT4dd4tgZzHUOU//5Lkw2Wul9uchDBnWfbMWr7WSiUpysF6hUYFz7fMo8dVwh8qz+ zN7FYNfFDj2fW2OGnUe6OPesecFyFkeclafnrFlLblbtueuy/Dccgd2q5VJVgdcKsG/D EDkYTJahVEweOLTSbkr4XdpBn+p8PgKePGpnX1BGbgwyTd1GrRsOUnp1DifX7LIF47FF SWbSLo+LhahN43KwxL8kyzzHsSYJQm7+DaDabHfiAbhURQOhuoSP8ttW+VgNhB2Gef5J DTLA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LTWy3uKH; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h65si15972948pfd.232.2019.04.03.20.36.55; Wed, 03 Apr 2019 20:36:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LTWy3uKH; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728727AbfDDDgx (ORCPT + 31 others); Wed, 3 Apr 2019 23:36:53 -0400 Received: from mail-pf1-f196.google.com ([209.85.210.196]:40741 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728671AbfDDDgw (ORCPT ); Wed, 3 Apr 2019 23:36:52 -0400 Received: by mail-pf1-f196.google.com with SMTP id c207so619257pfc.7 for ; Wed, 03 Apr 2019 20:36:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kFYUPXqDT+4NKa1uTQaXULpv7Y+YefzCDvbN138zMnI=; b=LTWy3uKHie6dKXq48SuUSLDOFWqCbGplQB45KxnD/vCJcF5L/sa/6SJCsJfosIpCPl vKFmCf6HgO8KQKoD1jtzcVSjz7N+SN/Vumg/EhLmnN98dw6WYr3+RXOJrXl5KlF3LOO/ ggUt2/E4oD0dsHEWIQ8WZTik71totE9jL6xSGHHwC+3bR7dOnPQTVaHHz7PcMHHdAzp8 iHehk1++FQ943S5EtIOSoTJKk6P+ZEKkjpaSMak+FOY7m8refm9ZzDNl+7bnuAwwmmK1 YBNM9mtRz+VTcMmRuCg7nFKbz6ofMXDes8uQJykGMOlO1RKxwfW1K62fR75y1GMZEIrv Oo2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kFYUPXqDT+4NKa1uTQaXULpv7Y+YefzCDvbN138zMnI=; b=bBSbF7giFF8ZKMQHcoPiJcYXVPz24Oa9+AEIwfZ/1Yu7fYuIO95k53k0j+gdnAVtHR YpFvm/GAY0qmmnlOqQo2SJOGoVjmoRb8yWv5TCcsVUf/xSJscsb6oD6Gt5P8RKbx4hsi nqP5msSMMuwSoHobJRoFS4r8ahpcCrNIo6MjubwqSvoIRIjcNYNoglzRAT6wnFdeU0EY y8teCwRxZaNuexWqLEjxG3HkNNSqenzGiVaUhZRsOll17PpyBSoWW9PizmTIfEGikm3X 7pmKJUnQd0/6/b3C1gdYVn7q00lrJCkpNLm5wEbrrRparEdv9D+1e++V4DlbwfBeCba3 6nNw== X-Gm-Message-State: APjAAAWanZwQ9lb/WLlmHdevsST8Xhi2dMF0yk+Izpao2f4bNKJ4tpT4 NuncdTWROPnknL8IFZQgJ6W3bA== X-Received: by 2002:a63:4e57:: with SMTP id o23mr3467140pgl.368.1554349011296; Wed, 03 Apr 2019 20:36:51 -0700 (PDT) Received: from xps15.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id u5sm12212780pfm.121.2019.04.03.20.36.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 03 Apr 2019 20:36:50 -0700 (PDT) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org Cc: alexander.shishkin@linux.intel.com, peterz@infradead.org, suzuki.poulose@arm.com, mike.leach@arm.com, leo.yan@linaro.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 17/20] coresight: tmc-etr: Allocate and free ETR memory buffers for CPU-wide scenarios Date: Wed, 3 Apr 2019 21:35:38 -0600 Message-Id: <20190404033541.14072-18-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190404033541.14072-1-mathieu.poirier@linaro.org> References: <20190404033541.14072-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch uses the PID of the process being traced to allocate and free ETR memory buffers for CPU-wide scenarios. The implementation is tailored to handle both N:1 and 1:1 source/sink HW topologies. Signed-off-by: Mathieu Poirier --- .../hwtracing/coresight/coresight-tmc-etr.c | 107 +++++++++++++++++- 1 file changed, 104 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 1346474ac019..61110ef41d00 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -8,6 +8,8 @@ #include #include #include +#include +#include #include #include #include @@ -26,6 +28,7 @@ struct etr_flat_buf { /* * etr_perf_buffer - Perf buffer used for ETR + * @drvdata - The ETR drvdaga this buffer has been allocated for. * @etr_buf - Actual buffer used by the ETR * @pid - The PID this etr_perf_buffer belongs to. * @snaphost - Perf session mode @@ -34,6 +37,7 @@ struct etr_flat_buf { * @pages - Array of Pages in the ring buffer. */ struct etr_perf_buffer { + struct tmc_drvdata *drvdata; struct etr_buf *etr_buf; pid_t pid; bool snapshot; @@ -1210,6 +1214,72 @@ alloc_etr_buf(struct tmc_drvdata *drvdata, struct perf_event *event, return etr_buf; } +static struct etr_buf * +get_perf_etr_buf_cpu_wide(struct tmc_drvdata *drvdata, + struct perf_event *event, int nr_pages, + void **pages, bool snapshot) +{ + int ret; + pid_t pid = task_pid_nr(event->owner); + struct etr_buf *etr_buf; + +retry: + /* + * An etr_perf_buffer is associated with an event and holds a reference + * to the AUX ring buffer that was created for that event. In CPU-wide + * N:1 mode multiple events (one per CPU), each with its own AUX ring + * buffer, share a sink. As such an etr_perf_buffer is created for each + * event but a single etr_buf associated with the ETR is shared between + * them. The last event in a trace session will copy the content of the + * etr_buf to its AUX ring buffer. Ring buffer associated to other + * events are simply not used an freed as events are destoyed. We still + * need to allocate a ring buffer for each event since we don't know + * which event will be last. + */ + + /* + * The first thing to do here is check if an etr_buf has already been + * allocated for this session. If so it is shared with this event, + * otherwise it is created. + */ + mutex_lock(&drvdata->idr_mutex); + etr_buf = idr_find(&drvdata->idr, pid); + if (etr_buf) { + refcount_inc(&etr_buf->refcount); + mutex_unlock(&drvdata->idr_mutex); + return etr_buf; + } + + /* If we made it here no buffer has been allocated, do so now. */ + mutex_unlock(&drvdata->idr_mutex); + + etr_buf = alloc_etr_buf(drvdata, event, nr_pages, pages, snapshot); + if (IS_ERR(etr_buf)) + return etr_buf; + + refcount_set(&etr_buf->refcount, 1); + + /* Now that we have a buffer, add it to the IDR. */ + mutex_lock(&drvdata->idr_mutex); + ret = idr_alloc(&drvdata->idr, etr_buf, pid, pid + 1, GFP_KERNEL); + mutex_unlock(&drvdata->idr_mutex); + + /* Another event with this session ID has allocated this buffer. */ + if (ret == -ENOSPC) { + tmc_free_etr_buf(etr_buf); + goto retry; + } + + /* The IDR can't allocate room for a new session, abandon ship. */ + if (ret == -ENOMEM) { + tmc_free_etr_buf(etr_buf); + return ERR_PTR(ret); + } + + + return etr_buf; +} + static struct etr_buf * get_perf_etr_buf_per_thread(struct tmc_drvdata *drvdata, struct perf_event *event, int nr_pages, @@ -1238,7 +1308,8 @@ get_perf_etr_buf(struct tmc_drvdata *drvdata, struct perf_event *event, return get_perf_etr_buf_per_thread(drvdata, event, nr_pages, pages, snapshot); - return ERR_PTR(-ENOENT); + return get_perf_etr_buf_cpu_wide(drvdata, event, nr_pages, + pages, snapshot); } static struct etr_perf_buffer * @@ -1265,7 +1336,13 @@ tmc_etr_setup_perf_buf(struct tmc_drvdata *drvdata, struct perf_event *event, return ERR_PTR(-ENOMEM); done: + /* + * Keep a reference to the ETR this buffer has been allocated for + * in order to have access to the IDR in tmc_free_etr_buffer(). + */ + etr_perf->drvdata = drvdata; etr_perf->etr_buf = etr_buf; + return etr_perf; } @@ -1295,9 +1372,33 @@ static void *tmc_alloc_etr_buffer(struct coresight_device *csdev, static void tmc_free_etr_buffer(void *config) { struct etr_perf_buffer *etr_perf = config; + struct tmc_drvdata *drvdata = etr_perf->drvdata; + struct etr_buf *buf, *etr_buf = etr_perf->etr_buf; + + if (!etr_buf) + goto free_etr_perf_buffer; + + mutex_lock(&drvdata->idr_mutex); + /* If we are not the last one to use the buffer, don't touch it. */ + if (!refcount_dec_and_test(&etr_buf->refcount)) { + mutex_unlock(&drvdata->idr_mutex); + goto free_etr_perf_buffer; + } + + /* We are the last one, remove from the IDR and free the buffer. */ + buf = idr_remove(&drvdata->idr, etr_perf->pid); + mutex_unlock(&drvdata->idr_mutex); + + /* + * Something went very wrong if the buffer associated with this ID + * is not the same in the IDR. Leak to avoid use after free. + */ + if (buf && WARN_ON(buf != etr_buf)) + goto free_etr_perf_buffer; + + tmc_free_etr_buf(etr_perf->etr_buf); - if (etr_perf->etr_buf) - tmc_free_etr_buf(etr_perf->etr_buf); +free_etr_perf_buffer: kfree(etr_perf); } From patchwork Thu Apr 4 03:35:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 161737 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1087655jan; Wed, 3 Apr 2019 20:36:58 -0700 (PDT) X-Google-Smtp-Source: APXvYqwfWbUZ5r1HNJj6/9LJIeO6U9aN58gT1teIKQHKauLAbOFFHt33vMRBauZOLeI7+FVV8iRE X-Received: by 2002:a17:902:9006:: with SMTP id a6mr3728300plp.259.1554349018860; Wed, 03 Apr 2019 20:36:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554349018; cv=none; d=google.com; s=arc-20160816; b=WtaRyO4zIpT/NqXAt4I82jskH4pYOcn5AGUFxV3vUIwgx3dNIbWeM0QeyxNtFiCTkk ETPTNoixWXmdi060MQdTpibFAc0ompT8TnE/9HCiQrDrjtwmKhH5p3KstAtj+PGDJfyg A7mxhwrV4vpoFDrywH1C4ASgdoforfm/fy55cTcXF88TThD7XNs8QMYHBYb6dJLRpWH0 q41uf4/XrqW0oOkTa7nFyCOn8MaifZCiM2KVM9bICjR6Ilm9E3GmfJP3m1IzQ0kmtW3E x6o5j5yh4XsNWWHeCPr+6UpbKrDCH5qqSc6CT4roBkmdJ2JSUOLh8eZBXIl/UuScJk3p bX6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=LudRC9TQK4HNLvQvknqLAVG3xxx86t5omiW1jcpQn7M=; b=yzqhodalVtMtkYpDViNiBf0wRotBQ/nk+xmuoqy/qKhO5eW5bULODeQ++MYdn92vRO D8wjqaZazlm5kBnveicD+vTbWbJUHYb1UWGPO53JciwDkSeU+wcieFQYuS59fFLJ9PAR 5WuhBhtJ+MzN2GTFUf2aA2MrU8QqfOVU6we/XyIL6hoNXRZtW4+hsaIj7C2miz/bBlyk uylvbYLO4pB6yi72pcXGoRODI11PmQ6YGM+DtY47cJyAdonu0oeNzrz9ZpFgFQiNGEIp j5UVCj9Iwne3n5gUyBVBl80YNzSUWoF7KkoqGwyTp1n+BhLUbi9KNecFWeLd/pEcSuxB WX6g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=p5ap4iba; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h65si15972948pfd.232.2019.04.03.20.36.58; Wed, 03 Apr 2019 20:36:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=p5ap4iba; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728743AbfDDDg5 (ORCPT + 31 others); Wed, 3 Apr 2019 23:36:57 -0400 Received: from mail-pf1-f193.google.com ([209.85.210.193]:33881 "EHLO mail-pf1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728671AbfDDDg4 (ORCPT ); Wed, 3 Apr 2019 23:36:56 -0400 Received: by mail-pf1-f193.google.com with SMTP id b3so636348pfd.1 for ; Wed, 03 Apr 2019 20:36:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LudRC9TQK4HNLvQvknqLAVG3xxx86t5omiW1jcpQn7M=; b=p5ap4ibaWa2YMJgeLjUNn2YMG/1OP1OdJICTAiBIXN8oy4cPKJ51Jd9kOgaA4wY3/x pp3Du9fIrKogx0dYSHz5wkHkBeWvIOYrNJ54wwWHiCwo2AnCRQjvV5L/oKWlTrL6M06e sxquML1M0yOl5NfRz5fQN0Vn6538pwN+786rBqo2JJfOmVE5vnbYdWrvPE7CEvmdFtQE Y3iyYDLa+rQV5dsqGUtO+VzodR7R6CZVjq+sIlhfMLNwv1HzYaFmkH5KS4WvPROLmDGV IowW/KPSopknMq0CmQGY1mEsq5R+0/V2HD/eFxOSPS/dJWA6bWk/d94S+RwISxwbZp+E yJwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LudRC9TQK4HNLvQvknqLAVG3xxx86t5omiW1jcpQn7M=; b=cOhPwQFtd3KUtiplxqXjV20z0zKCWVxkiGHLQWtVz20V4m2vlWQuKFfjazdOYR1wM2 sjl6QBF0E4gSbsOONMY8nXK3O6TZpfkYpTNQnK2/r2lg7qxyqCt1oYJQUS6FzYc7Lp0R JOOyfyDjqJb/jsAWrkeWK9w6LWli1ML+2Pf94J7x3CUrzQkqLcOitcWVF31LxPeOim2S kwTPmlyRHIrCov0HKf7/fTDtfmzv2UgWDHvteOq0B8Qnwb1tqKzrcDhZmEQKIXleoGDx S1cYPBUJgUXVZxGc2/iA4QaMTG5WZGTsm/thCV7y5Heck3zOw4vfxtphWJI9D0TEl+nI veNQ== X-Gm-Message-State: APjAAAWZQNOiPFMfMjst6nVyWi7XFaDSIN0c8yX8EgxZbWkJChMH6bt7 aWjApW9ge74VZN/hNx7pZUsEAQ== X-Received: by 2002:a65:47c6:: with SMTP id f6mr3400010pgs.173.1554349014940; Wed, 03 Apr 2019 20:36:54 -0700 (PDT) Received: from xps15.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id u5sm12212780pfm.121.2019.04.03.20.36.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 03 Apr 2019 20:36:54 -0700 (PDT) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org Cc: alexander.shishkin@linux.intel.com, peterz@infradead.org, suzuki.poulose@arm.com, mike.leach@arm.com, leo.yan@linaro.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 18/20] coresight: tmc-etr: Add support for CPU-wide trace scenarios Date: Wed, 3 Apr 2019 21:35:39 -0600 Message-Id: <20190404033541.14072-19-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190404033541.14072-1-mathieu.poirier@linaro.org> References: <20190404033541.14072-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds support for CPU-wide trace scenarios by making sure that only the sources monitoring the same process have access to a common sink. Because the sink is shared between sources, the first source to use the sink switches it on while the last one does the cleanup. Any attempt to modify the HW is overlooked for as long as more than one source is using a sink. Signed-off-by: Mathieu Poirier --- .../hwtracing/coresight/coresight-tmc-etr.c | 38 ++++++++++++++++--- drivers/hwtracing/coresight/coresight-tmc.c | 2 + drivers/hwtracing/coresight/coresight-tmc.h | 3 ++ 3 files changed, 38 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 61110ef41d00..a91c1bc17e2d 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1473,6 +1473,13 @@ tmc_update_etr_buffer(struct coresight_device *csdev, struct etr_buf *etr_buf = etr_perf->etr_buf; spin_lock_irqsave(&drvdata->spinlock, flags); + + /* Don't do anything if another tracer is using this sink */ + if (atomic_read(csdev->refcnt) != 1) { + spin_unlock_irqrestore(&drvdata->spinlock, flags); + goto out; + } + if (WARN_ON(drvdata->perf_data != etr_perf)) { lost = true; spin_unlock_irqrestore(&drvdata->spinlock, flags); @@ -1512,17 +1519,15 @@ tmc_update_etr_buffer(struct coresight_device *csdev, static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, void *data) { int rc = 0; + pid_t pid; unsigned long flags; struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); struct perf_output_handle *handle = data; struct etr_perf_buffer *etr_perf = etm_perf_sink_config(handle); spin_lock_irqsave(&drvdata->spinlock, flags); - /* - * There can be only one writer per sink in perf mode. If the sink - * is already open in SYSFS mode, we can't use it. - */ - if (drvdata->mode != CS_MODE_DISABLED || WARN_ON(drvdata->perf_data)) { + /* Don't use this sink if it is already claimed by sysFS */ + if (drvdata->mode == CS_MODE_SYSFS) { rc = -EBUSY; goto unlock_out; } @@ -1532,10 +1537,31 @@ static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, void *data) goto unlock_out; } + /* Get a handle on the pid of the process to monitor */ + pid = etr_perf->pid; + + /* Do not proceed if this device is associated with another session */ + if (drvdata->pid != -1 && drvdata->pid != pid) { + rc = -EBUSY; + goto unlock_out; + } + etr_perf->head = PERF_IDX2OFF(handle->head, etr_perf); drvdata->perf_data = etr_perf; + + /* + * No HW configuration is needed if the sink is already in + * use for this session. + */ + if (drvdata->pid == pid) { + atomic_inc(csdev->refcnt); + goto unlock_out; + } + rc = tmc_etr_enable_hw(drvdata, etr_perf->etr_buf); if (!rc) { + /* Associate with monitored process. */ + drvdata->pid = pid; drvdata->mode = CS_MODE_PERF; atomic_inc(csdev->refcnt); } @@ -1579,6 +1605,8 @@ static int tmc_disable_etr_sink(struct coresight_device *csdev) /* Complain if we (somehow) got out of sync */ WARN_ON_ONCE(drvdata->mode == CS_MODE_DISABLED); tmc_etr_disable_hw(drvdata); + /* Dissociate from monitored process. */ + drvdata->pid = -1; drvdata->mode = CS_MODE_DISABLED; spin_unlock_irqrestore(&drvdata->spinlock, flags); diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c index 71c86cffc021..fd8267fd8e6b 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.c +++ b/drivers/hwtracing/coresight/coresight-tmc.c @@ -417,6 +417,8 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id) devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID); drvdata->config_type = BMVAL(devid, 6, 7); drvdata->memwidth = tmc_get_memwidth(devid); + /* This device is not associated with a session */ + drvdata->pid = -1; if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) { if (np) diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index c1b1700b2df7..503f1b3a3741 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -165,6 +165,8 @@ struct etr_buf { * @csdev: component vitals needed by the framework. * @miscdev: specifics to handle "/dev/xyz.tmc" entry. * @spinlock: only one at a time pls. + * @pid: Process ID of the process being monitored by the session + * that is using this component. * @buf: Snapshot of the trace data for ETF/ETB. * @etr_buf: details of buffer used in TMC-ETR * @len: size of the available trace for ETF/ETB. @@ -186,6 +188,7 @@ struct tmc_drvdata { struct coresight_device *csdev; struct miscdevice miscdev; spinlock_t spinlock; + pid_t pid; bool reading; union { char *buf; /* TMC ETB */ From patchwork Thu Apr 4 03:35:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 161738 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1087696jan; Wed, 3 Apr 2019 20:37:02 -0700 (PDT) X-Google-Smtp-Source: APXvYqz1wGYyuykvAD7R/uXNfB9VNnrZqft45jgSXWDZIC6Tq+3AL1CgWZk6VFxuqxIcCGfgGM6g X-Received: by 2002:aa7:87c5:: with SMTP id i5mr3480017pfo.20.1554349022518; Wed, 03 Apr 2019 20:37:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554349022; cv=none; d=google.com; s=arc-20160816; b=xpuj5CPCn6wM3UxFXMFdYW40AUH3qQ+dMWoGke5m3mDlYsGx9y/Dyzz099ESUL9IVk FhL42xwsgdQBvlvJu5j5XXo5qcycs1TwOzVjLxFb+vtDB/d0szu0VcK1cbf257k4nITW TFQb3PeRc3QI9w9gMKv1X7v72IOf0t8L4taJVxwZnijiFfoZgK1lilI+JqVBGlknS6I2 ukEfYNKAw61H6zN73sWJLkztlgn/WW9fmWxbJhzFq8PhZa9dMtPeZsyYDD0dN3WpiP2N w7MYTrMZ75Jpj8uaJlTNwnhbrLS+BtBFk+cnOUSANTjrO3OT0Tiukwe5rv87fgWW+5b5 Z92w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=sdDt/HRF6MLGkuxtGtaVQsmhDK4+MNWevaRbT+jK8kU=; b=o3MfKktKfm4o+yPjQpwNVtxhomq5g903MSLpPhf4jNQbxnkO2nZQNEa/OYwZV95p3i XJlAeeMf0kgjvi0RbJjECMt1cQY8nIrJj8ff8CYP0Yb6xVGPk/7IXpApMAuGp2uXmj4u 8LROslSljsjMonOtr2550KcUxvirB3WKNHe3suCRn2YsglXhOqaZUIosxSU1pBzlwkzR /quKIpI86uIHtKBlsRSFuXXl+rd95cZJw2ngzFvePwXXnxdfotVo91AuEtT6RsXsVWXI 35wEJaraM42Gw/QDDrLDJlE9dkVfqOv3Pua0PxqsyewroqwhNuyv6XQkLDIkB0ruf6OP 2FEw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=me0reGUH; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h65si15972948pfd.232.2019.04.03.20.37.02; Wed, 03 Apr 2019 20:37:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=me0reGUH; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728754AbfDDDhB (ORCPT + 31 others); Wed, 3 Apr 2019 23:37:01 -0400 Received: from mail-pl1-f196.google.com ([209.85.214.196]:38479 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728737AbfDDDg7 (ORCPT ); Wed, 3 Apr 2019 23:36:59 -0400 Received: by mail-pl1-f196.google.com with SMTP id g37so439190plb.5 for ; Wed, 03 Apr 2019 20:36:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sdDt/HRF6MLGkuxtGtaVQsmhDK4+MNWevaRbT+jK8kU=; b=me0reGUHzjAiArUnM1m+8nwEBbmaHHIkK5QeHwjSxqEanx5sievn47DGQJOzluk7Yz K/wE+zAXLVZX25JzVwlb8I5DF7VoNep4JqOUhiEF6tKVxTglGMTWSx/2kOtKMRZGWWtU rWrGYYloH9wHtFC95pVDFDURHy5sWe5YpMK8noldYig6bHLwrX28/gnwoCfxbTPWKZrV wvLOpaiEh2v2HCbgfAr3HILmumCUA+Ur6oXsqnZO+uqgtmQBQ9+rFGJkjfHkdk6fJUoF LbkT9VmGoSqTCA7EQzoUYilV+6+7HCrBzOEMvWLp0f/vqap4uXJOqY7/b1erSZv/7/jN VgsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sdDt/HRF6MLGkuxtGtaVQsmhDK4+MNWevaRbT+jK8kU=; b=TPysirmqNSjkSAlAisOgwddkvGFh5Jjyk+qmY89r9jLPUbDjX4dlyxaTkw0Fm5rtfJ 8bs8n6rLLh477jCeSbTMREtbfEceHrK/EZLrDOQgOdlPW1E/2ZsTopymcirYLMjuAVK2 78mk0O6BP98S6G1iorqRf9GYCPxZtqtCcB5T7FRMHjrh5yek0vX/rge5kzcOPqFv9uls lR5IslUcbpYLg9Ly5hcGY9E5Zj+gS3klSDC5i4ixmS7DOAGJQW9Wq9t2nMSXIdzOeOTR SXr9R106OmiLULAV2bwD4E/4apLBP/s7EPfY34GjKZIHc4RciXe6sBNmm2hW5C3kuMF/ vDDg== X-Gm-Message-State: APjAAAVa1PVGXM7D5gprMGoBJPsSrNPvsIsYwp13StIAVn2LRMGIBhu8 dzP2EaJtGhTPQ4F2JWIMhdvnnA== X-Received: by 2002:a17:902:7c8c:: with SMTP id y12mr3808185pll.209.1554349018449; Wed, 03 Apr 2019 20:36:58 -0700 (PDT) Received: from xps15.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id u5sm12212780pfm.121.2019.04.03.20.36.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 03 Apr 2019 20:36:57 -0700 (PDT) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org Cc: alexander.shishkin@linux.intel.com, peterz@infradead.org, suzuki.poulose@arm.com, mike.leach@arm.com, leo.yan@linaro.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 19/20] coresight: tmc-etf: Add support for CPU-wide trace scenarios Date: Wed, 3 Apr 2019 21:35:40 -0600 Message-Id: <20190404033541.14072-20-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190404033541.14072-1-mathieu.poirier@linaro.org> References: <20190404033541.14072-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds support for CPU-wide trace scenarios by making sure that only the sources monitoring the same process have access to a common sink. Because the sink is shared between sources, the first source to use the sink switches it on while the last one does the cleanup. Any attempt to modify the HW is overlooked for as long as more than one source is using a sink. Signed-off-by: Mathieu Poirier --- .../hwtracing/coresight/coresight-tmc-etf.c | 40 ++++++++++++++++--- 1 file changed, 35 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index 1df1f8fade71..2527b5d3b65e 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -223,6 +223,7 @@ static int tmc_enable_etf_sink_sysfs(struct coresight_device *csdev) static int tmc_enable_etf_sink_perf(struct coresight_device *csdev, void *data) { int ret = 0; + pid_t pid; unsigned long flags; struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); struct perf_output_handle *handle = data; @@ -233,18 +234,39 @@ static int tmc_enable_etf_sink_perf(struct coresight_device *csdev, void *data) if (drvdata->reading) break; /* - * In Perf mode there can be only one writer per sink. There - * is also no need to continue if the ETB/ETF is already - * operated from sysFS. + * No need to continue if the ETB/ETF is already operated + * from sysFS. */ - if (drvdata->mode != CS_MODE_DISABLED) + if (drvdata->mode == CS_MODE_SYSFS) { + ret = -EBUSY; break; + } + + /* Get a handle on the pid of the process to monitor */ + pid = task_pid_nr(handle->event->owner); + + if (drvdata->pid != -1 && drvdata->pid != pid) { + ret = -EBUSY; + break; + } ret = tmc_set_etf_buffer(csdev, handle); if (ret) break; + + /* + * No HW configuration is needed if the sink is already in + * use for this session. + */ + if (drvdata->pid == pid) { + atomic_inc(csdev->refcnt); + break; + } + ret = tmc_etb_enable_hw(drvdata); if (!ret) { + /* Associate with monitored process. */ + drvdata->pid = pid; drvdata->mode = CS_MODE_PERF; atomic_inc(csdev->refcnt); } @@ -300,6 +322,8 @@ static int tmc_disable_etf_sink(struct coresight_device *csdev) /* Complain if we (somehow) got out of sync */ WARN_ON_ONCE(drvdata->mode == CS_MODE_DISABLED); tmc_etb_disable_hw(drvdata); + /* Dissociate from monitored process. */ + drvdata->pid = -1; drvdata->mode = CS_MODE_DISABLED; spin_unlock_irqrestore(&drvdata->spinlock, flags); @@ -414,7 +438,7 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev, u32 *buf_ptr; u64 read_ptr, write_ptr; u32 status; - unsigned long offset, to_read, flags; + unsigned long offset, to_read = 0, flags; struct cs_buffers *buf = sink_config; struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); @@ -426,6 +450,11 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev, return 0; spin_lock_irqsave(&drvdata->spinlock, flags); + + /* Don't do anything if another tracer is using this sink */ + if (atomic_read(csdev->refcnt) != 1) + goto out; + CS_UNLOCK(drvdata->base); tmc_flush_and_stop(drvdata); @@ -519,6 +548,7 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev, to_read = buf->nr_pages << PAGE_SHIFT; } CS_LOCK(drvdata->base); +out: spin_unlock_irqrestore(&drvdata->spinlock, flags); return to_read; From patchwork Thu Apr 4 03:35:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 161739 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1087753jan; Wed, 3 Apr 2019 20:37:07 -0700 (PDT) X-Google-Smtp-Source: APXvYqx1Qaje0AcO4YtiwVwpKxRn2BTPvPh/0rryHLuVZJV/6+VN+ktw/zPrZkmzl30p7ji/47FT X-Received: by 2002:a63:2ec6:: with SMTP id u189mr3568869pgu.170.1554349027456; Wed, 03 Apr 2019 20:37:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554349027; cv=none; d=google.com; s=arc-20160816; b=z2vDirrF3cwvgAIXNhYXv5rpX92Zyj+ZHvCgOQURoDP+qYyuUTFFyoTkWlv0Uenr3F gq2kOWj5PaTCtr9Zc63xF/mhX0T4T2fIgSEMwmmhslZu31Cp0gq5VkzAOcX1ZIVL6oGw zRd1DGk0B+seG5bvWpc7oU840US/if+9rZt3QSjuDfEwcL+mhF0utkDHEib1niKopCvR JxXb3wnL+Ch9X1ZG/NN7DVmJtGSopjVFptWAy9ozEY1aVuhV5gnuT8wwJOAEF4nI2Dvk ub6zTKWRGbKLXvH2EQZPEK10oYhDjwc9XJXqxfFOv2LGETymj3UMvoFuceVyDrYFaH83 ZQnw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=DXJXs+4knPk/tA7or7zclZmTtg+ioeh357GrnSar9kA=; b=cKGGSlQDSbW+lPIQ0eeiIBSKV5BIoAblCBOdD16efiQj7AqLW6wC/5+MUltdFdLbaO 1dn6AQUTFQHPUrlKIZyM5tiuARmkHtsHwEbZh+k2k/XvLtRB4XbTygsENZzyZSsyXpRG 7bDcSYM8JPVPeoWczGVCW0umXeLWs1S79hwpp2W3dAFGmtuOR1jWRKZuksSrv0J9iCPb OZRyje2oLzrc335jbHD9Wf+sbgd+5EDnFUSoeM6dp3PelgJ1G7x7LzTaXpDaPb+JhG8b nAq/T0Gpnabfeu0dececrvvPPqFMZH35jQhD9tWrcPBInzdgZfxM9S94kVVgWQVw6Q0R jjKA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ue49eOPx; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f18si15694567pgg.361.2019.04.03.20.37.07; Wed, 03 Apr 2019 20:37:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ue49eOPx; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728766AbfDDDhF (ORCPT + 31 others); Wed, 3 Apr 2019 23:37:05 -0400 Received: from mail-pl1-f196.google.com ([209.85.214.196]:38484 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726931AbfDDDhD (ORCPT ); Wed, 3 Apr 2019 23:37:03 -0400 Received: by mail-pl1-f196.google.com with SMTP id g37so439266plb.5 for ; Wed, 03 Apr 2019 20:37:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=DXJXs+4knPk/tA7or7zclZmTtg+ioeh357GrnSar9kA=; b=Ue49eOPxZ/b1NIUrbk6DsAPnbtiZDLB+YR+tD0AKaa/fHQhyekBCugfgGTfQML9J8e MQvFErB7hxKiVViwohCnahFYv8cpLq9Lz4ID9etGYngPzS0j8uPnWnd1HHIDcUM0LIL4 /J/Lcrl1xQ1SgJGqLRlPyiIShR6WlvTD+GTfO3Jhj17F7C7dE5uR/bNv1nr/dA57RRuJ C2w80m9Wi18ElVMtAc6zFUi0+dOg36L0BIt8KueCIMwydRYuqAk70YhtlJrniZ2HANfa qD77URjCiBDYx0o+HpE+jzUk/Vq/SqOgFEb/RhQAwOTo33qo1Sxy62jDoy1cCqQg/LHd 3Jyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=DXJXs+4knPk/tA7or7zclZmTtg+ioeh357GrnSar9kA=; b=kR7OEW6JAKGZu6LFY/GrA3t57TVBRv4y5kw+f44Dwto3DmfKy3RlOuNPIwlx8ETiMo srRRTwYItbYOP2OS4bT9mpuJOuHg37duxgwF2Pkh4pnhlHLdpXOJyLEKlbIfoosqoCzg h02jQ2b8ZPxms3ggGTEM4cBRaGmi3acI7SLEC/bpjZQUi3QIrzhpK3Zk3VnVxwfEC6Ww XIQDIMWywam0eU630J9HlxU647ql3/Wv/4IGeKWyjMzRekqJJfVm1I1Pdf9d2EjuiZSH n99tbkRUXl16bFMKN60Qho0sQsFtf8WHwIfYXx3gOeOW570ondIMOiUymlKw+iX7eLKn lavQ== X-Gm-Message-State: APjAAAXiU0TTSkENHwoAcS2AUv16U+8eoJi3XbI/oWHPaUqF0Ma1wVt+ VzwWzzXqQl9mW08y5ysR8z7DSg== X-Received: by 2002:a17:902:be04:: with SMTP id r4mr3949596pls.218.1554349022282; Wed, 03 Apr 2019 20:37:02 -0700 (PDT) Received: from xps15.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id u5sm12212780pfm.121.2019.04.03.20.36.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 03 Apr 2019 20:37:01 -0700 (PDT) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org Cc: alexander.shishkin@linux.intel.com, peterz@infradead.org, suzuki.poulose@arm.com, mike.leach@arm.com, leo.yan@linaro.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 20/20] coresight: etb10: Add support for CPU-wide trace scenarios Date: Wed, 3 Apr 2019 21:35:41 -0600 Message-Id: <20190404033541.14072-21-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190404033541.14072-1-mathieu.poirier@linaro.org> References: <20190404033541.14072-1-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds support for CPU-wide trace scenarios by making sure that only the sources monitoring the same process have access to a common sink. Because the sink is shared between sources, the first source to use the sink switches it on while the last one does the cleanup. Any attempt to modify the HW is overlooked for as long as more than one source is using a sink. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etb10.c | 43 +++++++++++++++++-- 1 file changed, 39 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 7d64c41cd8ac..a2379c00d635 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -72,6 +72,8 @@ * @miscdev: specifics to handle "/dev/xyz.etb" entry. * @spinlock: only one at a time pls. * @reading: synchronise user space access to etb buffer. + * @pid: Process ID of the process being monitored by the session + * that is using this component. * @buf: area of memory where ETB buffer content gets sent. * @mode: this ETB is being used. * @buffer_depth: size of @buf. @@ -85,6 +87,7 @@ struct etb_drvdata { struct miscdevice miscdev; spinlock_t spinlock; local_t reading; + pid_t pid; u8 *buf; u32 mode; u32 buffer_depth; @@ -177,28 +180,49 @@ static int etb_enable_sysfs(struct coresight_device *csdev) static int etb_enable_perf(struct coresight_device *csdev, void *data) { int ret = 0; + pid_t pid; unsigned long flags; struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + struct perf_output_handle *handle = data; spin_lock_irqsave(&drvdata->spinlock, flags); - /* No need to continue if the component is already in use. */ - if (drvdata->mode != CS_MODE_DISABLED) { + /* No need to continue if the component is already in used by sysFS. */ + if (drvdata->mode == CS_MODE_SYSFS) { + ret = -EBUSY; + goto out; + } + + /* Get a handle on the pid of the process to monitor */ + pid = task_pid_nr(handle->event->owner); + + if (drvdata->pid != -1 && drvdata->pid != pid) { ret = -EBUSY; goto out; } + /* + * No HW configuration is needed if the sink is already in + * use for this session. + */ + if (drvdata->pid == pid) { + atomic_inc(csdev->refcnt); + goto out; + } + /* * We don't have an internal state to clean up if we fail to setup * the perf buffer. So we can perform the step before we turn the * ETB on and leave without cleaning up. */ - ret = etb_set_buffer(csdev, (struct perf_output_handle *)data); + ret = etb_set_buffer(csdev, handle); if (ret) goto out; ret = etb_enable_hw(drvdata); if (!ret) { + /* Associate with monitored process. */ + drvdata->pid = pid; drvdata->mode = CS_MODE_PERF; atomic_inc(csdev->refcnt); } @@ -344,6 +368,8 @@ static int etb_disable(struct coresight_device *csdev) /* Complain if we (somehow) got out of sync */ WARN_ON_ONCE(drvdata->mode == CS_MODE_DISABLED); etb_disable_hw(drvdata); + /* Dissociate from monitored process. */ + drvdata->pid = -1; drvdata->mode = CS_MODE_DISABLED; spin_unlock_irqrestore(&drvdata->spinlock, flags); @@ -414,7 +440,7 @@ static unsigned long etb_update_buffer(struct coresight_device *csdev, const u32 *barrier; u32 read_ptr, write_ptr, capacity; u32 status, read_data; - unsigned long offset, to_read, flags; + unsigned long offset, to_read = 0, flags; struct cs_buffers *buf = sink_config; struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); @@ -424,6 +450,11 @@ static unsigned long etb_update_buffer(struct coresight_device *csdev, capacity = drvdata->buffer_depth * ETB_FRAME_SIZE_WORDS; spin_lock_irqsave(&drvdata->spinlock, flags); + + /* Don't do anything if another tracer is using this sink */ + if (atomic_read(csdev->refcnt) != 1) + goto out; + __etb_disable_hw(drvdata); CS_UNLOCK(drvdata->base); @@ -534,6 +565,7 @@ static unsigned long etb_update_buffer(struct coresight_device *csdev, } __etb_enable_hw(drvdata); CS_LOCK(drvdata->base); +out: spin_unlock_irqrestore(&drvdata->spinlock, flags); return to_read; @@ -742,6 +774,9 @@ static int etb_probe(struct amba_device *adev, const struct amba_id *id) if (!drvdata->buf) return -ENOMEM; + /* This device is not associated with a session */ + drvdata->pid = -1; + desc.type = CORESIGHT_DEV_TYPE_SINK; desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; desc.ops = &etb_cs_ops;