From patchwork Mon Dec 26 03:10:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 637036 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48A97C4708E for ; Mon, 26 Dec 2022 03:11:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231487AbiLZDLJ (ORCPT ); Sun, 25 Dec 2022 22:11:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41760 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231488AbiLZDLH (ORCPT ); Sun, 25 Dec 2022 22:11:07 -0500 Received: from mail-lj1-x22f.google.com (mail-lj1-x22f.google.com [IPv6:2a00:1450:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C8C553884 for ; Sun, 25 Dec 2022 19:11:02 -0800 (PST) Received: by mail-lj1-x22f.google.com with SMTP id x37so3500243ljq.1 for ; Sun, 25 Dec 2022 19:11:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MoziaF3+JG1vdH+ZGDVTm5fAOdEswU4poKDpL3BeKds=; b=KeVdeFAleANwajo1Cftf1wg1iX2zrzHvtlSR0xe3FcXZHgvLjJ4S8I0eg6SaXzBsnz 8GOrE0iMfUHs6mp9MYKU+dfMgZVOm7+x2rYBA9Von/Ad2Fgl44Kf3tU2tAjuTS7mT2Oh MhDLm6kBiVV8AZaLpVHRTguGBQro61LLzwXvXTl7XlDFLm+lIhexRPUKRgx6AinndcjR KPuR7dMitmhKgDNDAHVO5b9Yk8/DnRa6RVR0T5hr+E8Uf1N5ha3nW+TSCi2XtdS8Cvil ldoKyRoVBE6RtUaimxuzhHk24vwQnXsLxNvq6/cSWmJTyd9Gn9xUXgnmbJ9Ct53PhFOs dP6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MoziaF3+JG1vdH+ZGDVTm5fAOdEswU4poKDpL3BeKds=; b=3ipBuUVyZC9/X64bIRTEsgRgnL2bOhbDB1I4LNT945UySGZqRH3XIjlP/oJF8QHUvS j7VLl8zL1EVo+VPRgw1Q3ybW7C9K2QwvLI9EWNXaLgZ4uF7CnKmUE7z27aK/AZa0WkSD XmOrImOUe9W9x4bI3zRp1DGbeOctnZw0R5S63GHjMO1vk8s48YulDlfTQvrxDDDvDx+Y /Ixbc+dr5/KElzI4lF0s4lgl42xnVP+kO5Y4oLxn78iL75G+jqlahj5DtqIqfR7aQhGX xA2Os6JPS2fuRBi+BEw7+5zZRIBmDNZU+ZRKI3zbLMuq3+0xrKK6qWXXrEZI6yT8FHCb 0SuA== X-Gm-Message-State: AFqh2koYjXAfXletiiEeuJVTZEXqATIocid+dnsOxYaH7BnMyIVIu7gL gGwPRWwReVrzn1HD333RyD/347eOaohp7ZO2HnMhSg== X-Google-Smtp-Source: AMrXdXvnSiGapyHJLfrnI/KvG+XBOvgt4oh+HNf2lHZ1Wgmt+amf6CEPryuzzpYQCU+6XBBzvBALAw== X-Received: by 2002:a2e:60a:0:b0:27f:b41f:602a with SMTP id 10-20020a2e060a000000b0027fb41f602amr3102372ljg.30.1672024261054; Sun, 25 Dec 2022 19:11:01 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id a12-20020a2e860c000000b0027f770526ebsm1165388lji.75.2022.12.25.19.11.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Dec 2022 19:11:00 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski Cc: Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v2 1/3] dt-bindings: phy: qcom,pcie2-phy: convert to YAML format Date: Mon, 26 Dec 2022 05:10:57 +0200 Message-Id: <20221226031059.2563165-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221226031059.2563165-1-dmitry.baryshkov@linaro.org> References: <20221226031059.2563165-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Convert the bindings for the Qualcomm PCIe2 PHY into the YAML format from the text description. Signed-off-by: Dmitry Baryshkov --- .../bindings/phy/qcom,pcie2-phy.yaml | 87 +++++++++++++++++++ .../bindings/phy/qcom-pcie2-phy.txt | 42 --------- 2 files changed, 87 insertions(+), 42 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml delete mode 100644 Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt diff --git a/Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml new file mode 100644 index 000000000000..672035199c19 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,pcie2-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm PCIe2 PHY controller + +maintainers: + - Vinod Koul + +description: + The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm + platforms. + +properties: + compatible: + items: + - const: qcom,qcs404-pcie2-phy + - const: qcom,pcie2-phy + + reg: + items: + - description: PHY register set + + clocks: + items: + - description: a clock-specifier pair for the "pipe" clock + + clock-output-names: + maxItems: 1 + + "#clock-cells": + const: 0 + + "#phy-cells": + const: 0 + + vdda-vp-supply: + description: low voltage regulator + + vdda-vph-supply: + description: high voltage regulator + + resets: + maxItems: 2 + + reset-names: + items: + - const: phy + - const: pipe + +required: + - compatible + - reg + - clocks + - clock-output-names + - "#clock-cells" + - "#phy-cells" + - vdda-vp-supply + - vdda-vph-supply + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include + phy@7786000 { + compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; + reg = <0x07786000 0xb8>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, + <&gcc GCC_PCIE_0_PIPE_ARES>; + reset-names = "phy", "pipe"; + + vdda-vp-supply = <&vreg_l3_1p05>; + vdda-vph-supply = <&vreg_l5_1p8>; + + clock-output-names = "pcie_0_pipe_clk"; + #clock-cells = <0>; + #phy-cells = <0>; + }; +... diff --git a/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt b/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt deleted file mode 100644 index 30064253f290..000000000000 --- a/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt +++ /dev/null @@ -1,42 +0,0 @@ -Qualcomm PCIe2 PHY controller -============================= - -The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm -platforms. - -Required properties: - - compatible: compatible list, should be: - "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy" - - - reg: offset and length of the PHY register set. - - #phy-cells: must be 0. - - - clocks: a clock-specifier pair for the "pipe" clock - - - vdda-vp-supply: phandle to low voltage regulator - - vdda-vph-supply: phandle to high voltage regulator - - - resets: reset-specifier pairs for the "phy" and "pipe" resets - - reset-names: list of resets, should contain: - "phy" and "pipe" - - - clock-output-names: name of the outgoing clock signal from the PHY PLL - - #clock-cells: must be 0 - -Example: - phy@7786000 { - compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; - reg = <0x07786000 0xb8>; - - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; - resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, - <&gcc GCC_PCIE_0_PIPE_ARES>; - reset-names = "phy", "pipe"; - - vdda-vp-supply = <&vreg_l3_1p05>; - vdda-vph-supply = <&vreg_l5_1p8>; - - clock-output-names = "pcie_0_pipe_clk"; - #clock-cells = <0>; - #phy-cells = <0>; - }; From patchwork Mon Dec 26 03:10:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 636857 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8737EC53210 for ; Mon, 26 Dec 2022 03:11:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231491AbiLZDLL (ORCPT ); Sun, 25 Dec 2022 22:11:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41766 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231504AbiLZDLH (ORCPT ); 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id a12-20020a2e860c000000b0027f770526ebsm1165388lji.75.2022.12.25.19.11.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Dec 2022 19:11:01 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski Cc: Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v2 2/3] phy: qualcomm: pcie2: register as clock provider Date: Mon, 26 Dec 2022 05:10:58 +0200 Message-Id: <20221226031059.2563165-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221226031059.2563165-1-dmitry.baryshkov@linaro.org> References: <20221226031059.2563165-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Register pcie2 PHY as a clock provider to enable using it in the DT-based clock lookup. Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-pcie2.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-pcie2.c b/drivers/phy/qualcomm/phy-qcom-pcie2.c index 5407e59bb185..11a2bb958681 100644 --- a/drivers/phy/qualcomm/phy-qcom-pcie2.c +++ b/drivers/phy/qualcomm/phy-qcom-pcie2.c @@ -243,7 +243,11 @@ static int phy_pipe_clksrc_register(struct qcom_phy *qphy) fixed->fixed_rate = 250000000; fixed->hw.init = &init; - return devm_clk_hw_register(qphy->dev, &fixed->hw); + ret = devm_clk_hw_register(qphy->dev, &fixed->hw); + if (ret < 0) + return ret; + + return devm_of_clk_add_hw_provider(qphy->dev, of_clk_hw_simple_get, &fixed->hw); } static int qcom_pcie2_phy_probe(struct platform_device *pdev) From patchwork Mon Dec 26 03:10:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 637035 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42173C4167B for ; Mon, 26 Dec 2022 03:11:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231504AbiLZDLM (ORCPT ); Sun, 25 Dec 2022 22:11:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41768 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231515AbiLZDLH (ORCPT ); Sun, 25 Dec 2022 22:11:07 -0500 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 403E038A4 for ; Sun, 25 Dec 2022 19:11:04 -0800 (PST) Received: by mail-lf1-x134.google.com with SMTP id o6so14581863lfi.5 for ; Sun, 25 Dec 2022 19:11:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VOPpZXvnhHa1qoac0B6bfJrnDF8l/HQwHQJha2WAMcA=; b=y7lqmFF3DN7ZzcnjrZcCIKEy5NIzn3LtLpYfgOLj5NCFH7NPqM06Sr9ue+RsXUUfww WKddBkBrRKhOCA5jVj7GHpMKjNFG4mesBWtyIGd+cIN743WPB6tnqjFiWw+vI/MnV89i ba4MbTeur7yWp9Wh5IRa3UUjF2T+SHdwRiYHy8BT1UD4PEWN/hk3nQqudTn8wrQUT3zY jo0zpyv6y3KbbmZsr3Z+sjh2N5Ni5LV7SV5VJeWQgp7mqFCitHI7lbiy5Ny/AmhF02YN OkTJlKb6hmR1ZOX3MCGbfruKrm1Y1JJD297bI76EUA5HFSew+356g82t/Rs6I34BiNzq 86Ug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VOPpZXvnhHa1qoac0B6bfJrnDF8l/HQwHQJha2WAMcA=; b=gHB6dErT1CRmx/mxGzVQ6GfhRjtalbxi+J2tw7dd7/4GauzlbYOzmhwi3yfMDJW4c/ FSrOrC6wBV7xACI3HWufTxjbsVLjFZbAiNyx8UV8HTvgUZX6hw2nI5hKRgH0xftyjnB7 o7S2W5lvwGUHKrL5av3S2vxGAvNV0cFpSibeS2Zs1ekkTeAy1dT51ej8CqIRASMF4H9H QUxD/HMwn1+be2ZwnP1be/CttxIuIai7K3nTyqSCQQERoCUq/KGDy0mKbp9WLtgNTYFi SEI17Bu9HmzejwcUwCe/FyCbgaMmeyeIxEAVD9/Bf5RB7Cl1cTMeNEWq265GkZSpmFzk MsHw== X-Gm-Message-State: AFqh2kqWmVYL+DnRzQhDBaJzfjErR3KzFOxzkKjmTxLxpDji9gfH3A0p TzFkeptcnfBtqFslyD2RdSA57A== X-Google-Smtp-Source: AMrXdXtLlyh5s3oI5dEvX7d8RshePPPEHXE+yeeNY0V3rN/FmbaNibWHOrZql6Nag1Q2lYJ/KZamNg== X-Received: by 2002:a05:6512:31d1:b0:4b5:7925:8707 with SMTP id j17-20020a05651231d100b004b579258707mr5763777lfe.26.1672024262594; Sun, 25 Dec 2022 19:11:02 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id a12-20020a2e860c000000b0027f770526ebsm1165388lji.75.2022.12.25.19.11.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Dec 2022 19:11:02 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski Cc: Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v2 3/3] arm64: dts: qcom: qcs404: register PCIe PHY as a clock provider Date: Mon, 26 Dec 2022 05:10:59 +0200 Message-Id: <20221226031059.2563165-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221226031059.2563165-1-dmitry.baryshkov@linaro.org> References: <20221226031059.2563165-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add #clock-cells to the pcie_phy node. It provides a PCIe PIPE clock. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index a5324eecb50a..ffffaa7507cf 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -810,6 +810,7 @@ pcie_phy: phy@7786000 { reset-names = "phy", "pipe"; clock-output-names = "pcie_0_pipe_clk"; + #clock-cells = <0>; #phy-cells = <0>; status = "disabled";