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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id o9-20020ac25e29000000b004b4b5da5f80sm1641129lfg.219.2022.12.25.20.21.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Dec 2022 20:21:55 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v2 01/16] dt-bindings: clock: qcom: gcc-qcs404: add two GDSC entries Date: Mon, 26 Dec 2022 06:21:39 +0200 Message-Id: <20221226042154.2666748-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221226042154.2666748-1-dmitry.baryshkov@linaro.org> References: <20221226042154.2666748-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On QCS404 platform the Global Clock Controller supports two GDSCs: MDSS (display) and OXILI (GPU). Add corresponding indices. Acked-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov --- include/dt-bindings/clock/qcom,gcc-qcs404.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h index bc3051543347..126a51898571 100644 --- a/include/dt-bindings/clock/qcom,gcc-qcs404.h +++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h @@ -177,4 +177,8 @@ #define GCC_PCIE_0_PIPE_ARES 21 #define GCC_WDSP_RESTART 22 +/* Indexes for GDSCs */ +#define MDSS_GDSC 0 +#define OXILI_GDSC 1 + #endif From patchwork Mon Dec 26 04:21:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 636855 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A077C3DA79 for ; Mon, 26 Dec 2022 04:22:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231594AbiLZEWC (ORCPT ); Sun, 25 Dec 2022 23:22:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55156 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231571AbiLZEV7 (ORCPT ); Sun, 25 Dec 2022 23:21:59 -0500 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ADF102641 for ; Sun, 25 Dec 2022 20:21:58 -0800 (PST) Received: by mail-lf1-x12c.google.com with SMTP id o6so14703573lfi.5 for ; Sun, 25 Dec 2022 20:21:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3GhZ0FxfbIH4v+WIvD3ap4QIpyJbfOnvuvRt1i73wJk=; b=q23UOK9rcJEw6EbkKbpPAexJCjdG39R4jB+sOnwU/ySIcq4XAjm60ou+pHCDL13duX 3JN6nhB+Ng6iZ5mGrg+dezc5bs9X6grVB7z5c0vYHCu4RFcUCZ56zKgO+lGSA0s3ucek VTWjdz3wDRFdJEnEPJBAkhqWAlBM5lzeUHvYREFmN+pQA1SV3G/x5CVjWRckhjOb7yvn 9RPHdhI2M3NwT8e3BhlcmUmDCIKfSZaXJUv3MXDArkcBxKA0f4svt9/ipAAMAY0Za5ev ba8AN96MBZmXgXe40BEbdn68bnrW9Jv5guSj6sD6B/VB5cDXKzbJC32l0Z8k7B2L+179 I6wA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3GhZ0FxfbIH4v+WIvD3ap4QIpyJbfOnvuvRt1i73wJk=; b=xBG7XZHzHbY3hudPXEEGI/7W19RD/3AoUFFZ8mqyPrV/VmxFPKUXzFPfvajiP7HZVP O6zl3WjpruP/e0JSNy8x5yU68hNWEOW889bhCovlGUBxoFldNvMl7XWlt9GKPWNPqb8z El3OMit1SrNrzsknLB6/IT5e0e2tM7Zb1hyV2N9ZzEhS2R8vxmfUF3NmpXBeX5nU9Hyx jc9KfQFKFrp111PgCdOOg2J8xBcvJR1L9Lpi2Ijkw0VnRXb7pEOKDHJOVoWr+OCfrvKK MKhkcLcLdMJZn+OTwo90+4Nkyw2sTcCE+vEElTta1OwiV++1GCE/QgTmWiYDgqixj1U6 h1Uw== X-Gm-Message-State: AFqh2krwBGa6wbguNOwMnO75pUUnfoOm5QvdjmIncRgZAXsV11suHSPN sjhrds9YR5gGwlHP+qxzh5WZyg== X-Google-Smtp-Source: AMrXdXvNTP18ugelgVDKpsYtWXxt3JIhpq5vlfHPFgxIKtehlis9TOU7PI3dXS5mUd32lLGXdbsrpg== X-Received: by 2002:a19:6508:0:b0:4bc:8c94:82f7 with SMTP id z8-20020a196508000000b004bc8c9482f7mr4149328lfb.13.1672028517105; Sun, 25 Dec 2022 20:21:57 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id o9-20020ac25e29000000b004b4b5da5f80sm1641129lfg.219.2022.12.25.20.21.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Dec 2022 20:21:56 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v2 02/16] dt-bindings: clock: qcom: gcc-qcs404: switch to gcc.yaml Date: Mon, 26 Dec 2022 06:21:40 +0200 Message-Id: <20221226042154.2666748-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221226042154.2666748-1-dmitry.baryshkov@linaro.org> References: <20221226042154.2666748-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Now as the gcc-qcs404 gained support for GDSC and requires using the #power-domain-cells property, switch the qcom,gcc-qcs404.yaml schema to use common gcc.yaml. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov --- .../bindings/clock/qcom,gcc-qcs404.yaml | 22 +++++-------------- 1 file changed, 5 insertions(+), 17 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml index dca5775f79a4..b70901e0d5cf 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml @@ -20,26 +20,13 @@ properties: compatible: const: qcom,gcc-qcs404 - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - reg: - maxItems: 1 - - protected-clocks: - description: - Protected clock specifier list as per common clock binding. - required: - compatible - - reg - - '#clock-cells' - - '#reset-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | @@ -48,5 +35,6 @@ examples: reg = <0x01800000 0x80000>; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; }; ... 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id o9-20020ac25e29000000b004b4b5da5f80sm1641129lfg.219.2022.12.25.20.21.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Dec 2022 20:21:57 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v2 03/16] dt-bindings: clock: qcom: gcc-qcs404: define clocks/clock-names for QCS404 Date: Mon, 26 Dec 2022 06:21:41 +0200 Message-Id: <20221226042154.2666748-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221226042154.2666748-1-dmitry.baryshkov@linaro.org> References: <20221226042154.2666748-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Define clock/clock-names properties of the GCC device node to be used on QCS404 platform. Acked-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov --- .../bindings/clock/qcom,gcc-qcs404.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml index b70901e0d5cf..b2256f81b265 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml @@ -20,6 +20,24 @@ properties: compatible: const: qcom,gcc-qcs404 + clocks: + items: + - description: XO source + - description: Sleep clock source + - description: PCIe 0 PIPE clock (optional) + - description: DSI phy instance 0 dsi clock + - description: DSI phy instance 0 byte clock + - description: HDMI phy PLL clock + + clock-names: + items: + - const: cxo + - const: sleep_clk + - const: pcie_0_pipe_clk_src + - const: dsi0pll + - const: dsi0pllbyte + - const: hdmi_pll + required: - compatible From patchwork Mon Dec 26 04:21:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 636854 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A362AC3DA79 for ; Mon, 26 Dec 2022 04:22:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231622AbiLZEWG (ORCPT ); Sun, 25 Dec 2022 23:22:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55190 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231586AbiLZEWB (ORCPT ); Sun, 25 Dec 2022 23:22:01 -0500 Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 06F1A2AE6 for ; Sun, 25 Dec 2022 20:21:59 -0800 (PST) Received: by mail-lf1-x129.google.com with SMTP id j17so5171667lfr.3 for ; Sun, 25 Dec 2022 20:21:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sOHWJtUfoQ7+BWYnDhcajg+BQh/X9B1s4iIGNOeLfGE=; b=nJFZ+CYgag9566j6NkRuicRoLT9aDC2ov0M+cZileZkyYjFjU//G4oE/EIxnht1y39 AjLXpPQ/JS2ToPDCXVjfPiw6QTW2Bq1QQ+6btOZthGH8JxVd307bjt3+Oaz/KgB1iPJU LrO1CgrJdr8DRfPgPdqqtAaRknBKxGHqgbe2m3Swx8bsH8JzoTk491ajVCuO+kr/BJkH LQWz7WbFHNKN0zXQ9JeTdpmnfNXHGimK7qIlp1nwJArQXWrtRYbu/W/jRwMMli14wfg4 227kphGgy7/z3t1RSvNqkDWJ6/iNbKQAKTwpgqch4eORRoW7xcOb4/JE7camfuOV4R/I +44Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sOHWJtUfoQ7+BWYnDhcajg+BQh/X9B1s4iIGNOeLfGE=; b=gokacx7YZ6gmyjtvE1BEY0H+2tW9y7YzsE7v3OdZNsJjmwaOR4aO4mRBKornTjzTpg Rg9zgp+ETR/21hJaAs257mdplkydFHPZxlNuBaG11uOdHwgFjRDHhJwigsgj/nE1QH/E TqN6jNy9GepPtGDc0dSWJYc+ISZxd7Sh37ZBuMD1LvlclCmCD3KW7+hJFG9IxX3HolwQ fA6rRHRTAp+WI1kTZ7e9zWXmPD0uSw89EFMiiHUYuDKxtXF3+OxSl6n0i0oCzmgdJdc0 gl8XgX7d29QzkN/8idZRs291I8/nZv4nwK/w+BdvxdjGLEoMx+QUajkgcvE+R0Y6JJNd v3iA== X-Gm-Message-State: AFqh2krcsUhERtWrWcjDGNMu/ZUn9d/V35aLk7npY4Xx3cop1dI7hZlY s9INGkj8v49VrRmFoGIPjHj3glkPkRXIhRTrHellLw== X-Google-Smtp-Source: AMrXdXtPkBNsW/fzcGr+kL+zpoC5bnSOzy0hwko6earAlYsF1VfWBxpT2EOIx9ITwsa6jjg3BzWw+w== X-Received: by 2002:a05:6512:224a:b0:4b4:c0c:899a with SMTP id i10-20020a056512224a00b004b40c0c899amr5504438lfu.37.1672028518531; Sun, 25 Dec 2022 20:21:58 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id o9-20020ac25e29000000b004b4b5da5f80sm1641129lfg.219.2022.12.25.20.21.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Dec 2022 20:21:58 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 04/16] clk: qcom: gcc-qcs404: use ARRAY_SIZE instead of specifying num_parents Date: Mon, 26 Dec 2022 06:21:42 +0200 Message-Id: <20221226042154.2666748-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221226042154.2666748-1-dmitry.baryshkov@linaro.org> References: <20221226042154.2666748-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data/names/hws easy and errorproof. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-qcs404.c | 86 +++++++++++++++++------------------ 1 file changed, 43 insertions(+), 43 deletions(-) diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c index 46d314d69250..f60a0ab42da1 100644 --- a/drivers/clk/qcom/gcc-qcs404.c +++ b/drivers/clk/qcom/gcc-qcs404.c @@ -440,7 +440,7 @@ static struct clk_rcg2 apss_ahb_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "apss_ahb_clk_src", .parent_names = gcc_parent_names_ao_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_ao_0), .flags = CLK_IS_CRITICAL, .ops = &clk_rcg2_ops, }, @@ -461,7 +461,7 @@ static struct clk_rcg2 blsp1_qup0_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup0_i2c_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -486,7 +486,7 @@ static struct clk_rcg2 blsp1_qup0_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup0_spi_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -500,7 +500,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup1_i2c_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -525,7 +525,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup1_spi_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -539,7 +539,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup2_i2c_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -565,7 +565,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup2_spi_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -579,7 +579,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup3_i2c_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -593,7 +593,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup3_spi_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -607,7 +607,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup4_i2c_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -621,7 +621,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup4_spi_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -655,7 +655,7 @@ static struct clk_rcg2 blsp1_uart0_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart0_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -669,7 +669,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart1_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -683,7 +683,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart2_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -698,7 +698,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart3_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -712,7 +712,7 @@ static struct clk_rcg2 blsp2_qup0_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup0_i2c_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -726,7 +726,7 @@ static struct clk_rcg2 blsp2_qup0_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup0_spi_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -740,7 +740,7 @@ static struct clk_rcg2 blsp2_uart0_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart0_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -753,7 +753,7 @@ static struct clk_rcg2 byte0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "byte0_clk_src", .parent_names = gcc_parent_names_5, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_names_5), .flags = CLK_SET_RATE_PARENT, .ops = &clk_byte2_ops, }, @@ -776,7 +776,7 @@ static struct clk_rcg2 emac_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "emac_clk_src", .parent_names = gcc_parent_names_4, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_4), .ops = &clk_rcg2_ops, }, }; @@ -797,7 +797,7 @@ static struct clk_rcg2 emac_ptp_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "emac_ptp_clk_src", .parent_names = gcc_parent_names_4, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_4), .ops = &clk_rcg2_ops, }, }; @@ -816,7 +816,7 @@ static struct clk_rcg2 esc0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "esc0_clk_src", .parent_names = gcc_parent_names_6, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_names_6), .ops = &clk_rcg2_ops, }, }; @@ -850,7 +850,7 @@ static struct clk_rcg2 gfx3d_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gfx3d_clk_src", .parent_names = gcc_parent_names_7, - .num_parents = 6, + .num_parents = ARRAY_SIZE(gcc_parent_names_7), .ops = &clk_rcg2_ops, }, }; @@ -871,7 +871,7 @@ static struct clk_rcg2 gp1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gp1_clk_src", .parent_names = gcc_parent_names_2, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_names_2), .ops = &clk_rcg2_ops, }, }; @@ -885,7 +885,7 @@ static struct clk_rcg2 gp2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gp2_clk_src", .parent_names = gcc_parent_names_2, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_names_2), .ops = &clk_rcg2_ops, }, }; @@ -899,7 +899,7 @@ static struct clk_rcg2 gp3_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gp3_clk_src", .parent_names = gcc_parent_names_2, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_names_2), .ops = &clk_rcg2_ops, }, }; @@ -913,7 +913,7 @@ static struct clk_rcg2 hdmi_app_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "hdmi_app_clk_src", .parent_names = gcc_parent_names_1, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parent_names_1), .ops = &clk_rcg2_ops, }, }; @@ -927,7 +927,7 @@ static struct clk_rcg2 hdmi_pclk_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "hdmi_pclk_clk_src", .parent_names = gcc_parent_names_8, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_8), .ops = &clk_rcg2_ops, }, }; @@ -954,7 +954,7 @@ static struct clk_rcg2 mdp_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "mdp_clk_src", .parent_names = gcc_parent_names_9, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_parent_names_9), .ops = &clk_rcg2_ops, }, }; @@ -973,7 +973,7 @@ static struct clk_rcg2 pcie_0_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "pcie_0_aux_clk_src", .parent_names = gcc_parent_names_10, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_10), .ops = &clk_rcg2_ops, }, }; @@ -994,7 +994,7 @@ static struct clk_rcg2 pcie_0_pipe_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "pcie_0_pipe_clk_src", .parent_names = gcc_parent_names_11, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_11), .ops = &clk_rcg2_ops, }, }; @@ -1007,7 +1007,7 @@ static struct clk_rcg2 pclk0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "pclk0_clk_src", .parent_names = gcc_parent_names_12, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_names_12), .flags = CLK_SET_RATE_PARENT, .ops = &clk_pixel_ops, }, @@ -1028,7 +1028,7 @@ static struct clk_rcg2 pdm2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "pdm2_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -1056,7 +1056,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc1_apps_clk_src", .parent_names = gcc_parent_names_13, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_parent_names_13), .ops = &clk_rcg2_floor_ops, }, }; @@ -1076,7 +1076,7 @@ static struct clk_rcg2 sdcc1_ice_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc1_ice_core_clk_src", .parent_names = gcc_parent_names_3, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_names_3), .ops = &clk_rcg2_ops, }, }; @@ -1102,7 +1102,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc2_apps_clk_src", .parent_names = gcc_parent_names_14, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_names_14), .ops = &clk_rcg2_floor_ops, }, }; @@ -1116,7 +1116,7 @@ static struct clk_rcg2 usb20_mock_utmi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "usb20_mock_utmi_clk_src", .parent_names = gcc_parent_names_1, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parent_names_1), .ops = &clk_rcg2_ops, }, }; @@ -1138,7 +1138,7 @@ static struct clk_rcg2 usb30_master_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "usb30_master_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -1152,7 +1152,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "usb30_mock_utmi_clk_src", .parent_names = gcc_parent_names_1, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parent_names_1), .ops = &clk_rcg2_ops, }, }; @@ -1166,7 +1166,7 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "usb3_phy_aux_clk_src", .parent_names = gcc_parent_names_1, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parent_names_1), .ops = &clk_rcg2_ops, }, }; @@ -1189,7 +1189,7 @@ static struct clk_rcg2 usb_hs_system_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "usb_hs_system_clk_src", .parent_names = gcc_parent_names_3, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_names_3), .ops = &clk_rcg2_ops, }, }; @@ -1203,7 +1203,7 @@ static struct clk_rcg2 vsync_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "vsync_clk_src", .parent_names = gcc_parent_names_15, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_15), .ops = &clk_rcg2_ops, }, }; @@ -1225,7 +1225,7 @@ static struct clk_rcg2 cdsp_bimc_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "cdsp_bimc_clk_src", .parent_names = gcc_parent_names_16, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_names_16), .ops = &clk_rcg2_ops, }, }; From patchwork Mon Dec 26 04:21:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 636853 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8A0AC3DA7D for ; Mon, 26 Dec 2022 04:22:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231654AbiLZEWL (ORCPT ); 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id o9-20020ac25e29000000b004b4b5da5f80sm1641129lfg.219.2022.12.25.20.21.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Dec 2022 20:21:58 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 05/16] clk: qcom: gcc-qcs404: disable gpll[04]_out_aux parents Date: Mon, 26 Dec 2022 06:21:43 +0200 Message-Id: <20221226042154.2666748-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221226042154.2666748-1-dmitry.baryshkov@linaro.org> References: <20221226042154.2666748-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On the QCS404 platform the driver for the Global Clock Controller doens't define gpll0_out_aux and gpll4_out_aux clocks, so it's not possible to use them as parents. Remove entries for these clocks. Note: backporting this patch to earlier kernels would also require a previous patch which switches the gcc driver to use ARRAY_SIZE for parent data arrays. Fixes: 652f1813c113 ("clk: qcom: gcc: Add global clock controller driver for QCS404") Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-qcs404.c | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c index f60a0ab42da1..507c42d7f753 100644 --- a/drivers/clk/qcom/gcc-qcs404.c +++ b/drivers/clk/qcom/gcc-qcs404.c @@ -25,11 +25,9 @@ enum { P_CORE_BI_PLL_TEST_SE, P_DSI0_PHY_PLL_OUT_BYTECLK, P_DSI0_PHY_PLL_OUT_DSICLK, - P_GPLL0_OUT_AUX, P_GPLL0_OUT_MAIN, P_GPLL1_OUT_MAIN, P_GPLL3_OUT_MAIN, - P_GPLL4_OUT_AUX, P_GPLL4_OUT_MAIN, P_GPLL6_OUT_AUX, P_HDMI_PHY_PLL_CLK, @@ -109,28 +107,24 @@ static const char * const gcc_parent_names_4[] = { static const struct parent_map gcc_parent_map_5[] = { { P_XO, 0 }, { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, - { P_GPLL0_OUT_AUX, 2 }, { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_5[] = { "cxo", "dsi0pll_byteclk_src", - "gpll0_out_aux", "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_6[] = { { P_XO, 0 }, { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, - { P_GPLL0_OUT_AUX, 3 }, { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_6[] = { "cxo", "dsi0_phy_pll_out_byteclk", - "gpll0_out_aux", "core_bi_pll_test_se", }; @@ -139,7 +133,6 @@ static const struct parent_map gcc_parent_map_7[] = { { P_GPLL0_OUT_MAIN, 1 }, { P_GPLL3_OUT_MAIN, 2 }, { P_GPLL6_OUT_AUX, 3 }, - { P_GPLL4_OUT_AUX, 4 }, { P_CORE_BI_PLL_TEST_SE, 7 }, }; @@ -148,7 +141,6 @@ static const char * const gcc_parent_names_7[] = { "gpll0_out_main", "gpll3_out_main", "gpll6_out_aux", - "gpll4_out_aux", "core_bi_pll_test_se", }; @@ -207,14 +199,12 @@ static const char * const gcc_parent_names_11[] = { static const struct parent_map gcc_parent_map_12[] = { { P_XO, 0 }, { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, - { P_GPLL0_OUT_AUX, 2 }, { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_12[] = { "cxo", "dsi0pll_pclk_src", - "gpll0_out_aux", "core_bi_pll_test_se", }; @@ -237,40 +227,34 @@ static const char * const gcc_parent_names_13[] = { static const struct parent_map gcc_parent_map_14[] = { { P_XO, 0 }, { P_GPLL0_OUT_MAIN, 1 }, - { P_GPLL4_OUT_AUX, 2 }, { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_14[] = { "cxo", "gpll0_out_main", - "gpll4_out_aux", "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_15[] = { { P_XO, 0 }, - { P_GPLL0_OUT_AUX, 2 }, { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_15[] = { "cxo", - "gpll0_out_aux", "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_16[] = { { P_XO, 0 }, { P_GPLL0_OUT_MAIN, 1 }, - { P_GPLL0_OUT_AUX, 2 }, { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_16[] = { "cxo", "gpll0_out_main", - "gpll0_out_aux", "core_bi_pll_test_se", }; From patchwork Mon Dec 26 04:21:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 637031 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C613C53210 for ; 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id o9-20020ac25e29000000b004b4b5da5f80sm1641129lfg.219.2022.12.25.20.21.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Dec 2022 20:21:59 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 06/16] clk: qcom: gcc-qcs404: fix names of the DSI clocks used as parents Date: Mon, 26 Dec 2022 06:21:44 +0200 Message-Id: <20221226042154.2666748-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221226042154.2666748-1-dmitry.baryshkov@linaro.org> References: <20221226042154.2666748-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The QCS404 uses 28nm LPM DSI PHY, which registers dsi0pll and dsi0pllbyte clocks. Fix all DSI PHY clock names used as parents inside the GCC driver. Fixes: 652f1813c113 ("clk: qcom: gcc: Add global clock controller driver for QCS404") Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-qcs404.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c index 507c42d7f753..67a180d688c3 100644 --- a/drivers/clk/qcom/gcc-qcs404.c +++ b/drivers/clk/qcom/gcc-qcs404.c @@ -112,7 +112,7 @@ static const struct parent_map gcc_parent_map_5[] = { static const char * const gcc_parent_names_5[] = { "cxo", - "dsi0pll_byteclk_src", + "dsi0pllbyte", "core_bi_pll_test_se", }; @@ -124,7 +124,7 @@ static const struct parent_map gcc_parent_map_6[] = { static const char * const gcc_parent_names_6[] = { "cxo", - "dsi0_phy_pll_out_byteclk", + "dsi0pllbyte", "core_bi_pll_test_se", }; @@ -167,7 +167,7 @@ static const struct parent_map gcc_parent_map_9[] = { static const char * const gcc_parent_names_9[] = { "cxo", "gpll0_out_main", - "dsi0_phy_pll_out_dsiclk", + "dsi0pll", "gpll6_out_aux", "core_bi_pll_test_se", }; @@ -204,7 +204,7 @@ static const struct parent_map gcc_parent_map_12[] = { static const char * const gcc_parent_names_12[] = { "cxo", - "dsi0pll_pclk_src", + "dsi0pll", "core_bi_pll_test_se", }; From patchwork Mon Dec 26 04:21:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 637032 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6DA45C4708E for ; Mon, 26 Dec 2022 04:22:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231648AbiLZEWL (ORCPT ); Sun, 25 Dec 2022 23:22:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55176 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231603AbiLZEWD (ORCPT ); Sun, 25 Dec 2022 23:22:03 -0500 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 298BD2BED for ; Sun, 25 Dec 2022 20:22:02 -0800 (PST) Received: by mail-lf1-x12a.google.com with SMTP id bf43so14689386lfb.6 for ; Sun, 25 Dec 2022 20:22:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+BSMHD+c2gHpfQgRvnQWh7QBxsgW6TDMIYioeA0tiyU=; b=GSG/uPASW5MnAW2J6MoCurBK4kTDfD09wDZMETAMkR2BQDSJZLXgPBxuC7WpCIsXfa bhladb55cCu6v+AxHyDcUDrg6Vj/dYL98aez4hmlJUQfAcdc/Fww2Iu000YFNU6n6gB/ Qfk6QMBHB+ttNsUOnEgK5cSXB+zDgyLQ6P4V8UQKsKM283wN8mX4TuL0N5obbTXUjCX2 Od8mib1YgWK1Pu4zgR/Lfz9P7FVPLj3XsCbFmCmyvfMB5WND4V9yaWyE6DhdYvIt6fgm VSfMjgP+DWCNG+orVpYrp5eNViOuoOAVAQXFkrBksd6yembPg6LyNsgw0u5ZEdO0f50/ ZXDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+BSMHD+c2gHpfQgRvnQWh7QBxsgW6TDMIYioeA0tiyU=; b=hHDhYEi2q6zb3v/3rH2MF9blGsUVykeM6+4kljckGNIVA+Xi6EJlcvUl3i2EdNmjer IDdx0ChQdqFs3DcfbJPQ1pmmwGbwQKjcVsMdGpVZNaOttPuckkm0IJBvq7B8ipsK+6DU EWF1VtRMY0Ze7d+POEyNtInZahERfRsYpTixyX4hkT5HKAr6zY9WobaxAb/MnWZZwscV 47SNuG89g0Yz6jlSnRnqoagCLwltl8BqFgVtbSTW9oI+blnmyQKc41TVaaKljKU/00og zV2EJmYMBjFIHboTlJ5gaUPGLCOumkFmlOh0nSfdQrR5qhyj7htOcMlEVivVrsph4aBL JbTw== X-Gm-Message-State: AFqh2kpVtbnJShIx2IVYKLid1GoHKi8OjCbBmJ863r1IHoOXD6/yZoaC sKKfhU1tkbnPkMdE88T514X2+h2CaqRSSgNNzjDoDg== X-Google-Smtp-Source: AMrXdXtny0j8UKNsOeIfUn/TQ+czvRnUPd4+0U0IkWIjg7Y9RXoIwpyLFJNU1J0wXAn08wzdm7GOvg== X-Received: by 2002:ac2:562d:0:b0:4b5:670e:b708 with SMTP id b13-20020ac2562d000000b004b5670eb708mr4155105lff.14.1672028520462; Sun, 25 Dec 2022 20:22:00 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id o9-20020ac25e29000000b004b4b5da5f80sm1641129lfg.219.2022.12.25.20.21.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Dec 2022 20:22:00 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 07/16] clk: qcom: gcc-qcs404: fix the name of the HDMI PLL clock Date: Mon, 26 Dec 2022 06:21:45 +0200 Message-Id: <20221226042154.2666748-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221226042154.2666748-1-dmitry.baryshkov@linaro.org> References: <20221226042154.2666748-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The QCS404 uses 28nm HDMI PHY. The in-kernel driver doesn't provide the PLL (yet), but the out of tree patches used the name "hdmi_pll" for it. Other Qualcomm HDMI PHYs use either the name "hdmi_pll" (8960) or "hdmipll" (8996). Thus change the expected HDMI PLL clock name to "hdmi_pll". Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-qcs404.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c index 67a180d688c3..241768da2263 100644 --- a/drivers/clk/qcom/gcc-qcs404.c +++ b/drivers/clk/qcom/gcc-qcs404.c @@ -152,7 +152,7 @@ static const struct parent_map gcc_parent_map_8[] = { static const char * const gcc_parent_names_8[] = { "cxo", - "hdmi_phy_pll_clk", + "hdmi_pll", "core_bi_pll_test_se", }; From patchwork Mon Dec 26 04:21:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 637030 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FFF9C46467 for ; Mon, 26 Dec 2022 04:22:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231621AbiLZEWQ (ORCPT ); Sun, 25 Dec 2022 23:22:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55156 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231616AbiLZEWF (ORCPT ); Sun, 25 Dec 2022 23:22:05 -0500 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B45542BF6 for ; Sun, 25 Dec 2022 20:22:02 -0800 (PST) Received: by mail-lf1-x12e.google.com with SMTP id bq39so6882976lfb.0 for ; Sun, 25 Dec 2022 20:22:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QM1NA3WnzCUzuM7DIb0MXBpOI8QpMEHVGqr4lbpcw6E=; b=ePvzrTg0SDyKWv3XcziFp1y3BAjEtmWHW0GA+1aKDoQWIHSufAbsqo/gqVd43mYIiC a1pGnvqhD2pQmtpvKi2sWN830SGZjT65qpsccCFbpkI64CyDsPrneC44V10WaXqu7fjO xi4HlgaUni/JBmaFqOS8mTaWKEDtkVyOL0i8baT/Ckoauet9D7gjTWpranLvOLGoT5Co Ksq+ZnV2iY0IhJrO17Oihss6u3N2T2+wVmZnsCr2tSoCaep9a2XWARtpdxfTw7fUnNY4 A/vrDsoammeRN5ZjLIFlE+m+5hmTC/tepjj/B4TsOUDcgRp3c8tbuLm7L+qIKF+JVGMV Oefw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QM1NA3WnzCUzuM7DIb0MXBpOI8QpMEHVGqr4lbpcw6E=; b=0MqTYM5NOOOoJMAbVfxUIlujgiHLxZvnVOvyTBtBqlqh71pxKwYt1dAncAJtSe6SCZ WG3Ay0ZB4bWiDUPZqoYRnA+ujAXcdhLlUA1jBnAyzzgz+mG9NHgt31ol1+MZTZMs1MM7 C8bCdXNheUoC+e/bKT/DLNsMLyjFLjIhZhwDI5IEQiMikb1+PwP10rPoWvPC1y2Tousy BPK01H5j+ysOdtB53ktKT8XUFh5G+1LTYKWtEFgJ04/hYv8H/kunqiHwBtrchq1hic6D qJ3CIgLSn8JSQdLLnoQfaXDxbNX0iozbfkbeMdmg9EG10UYmDGMVKbK06HA9Jl9qDoKD zLng== X-Gm-Message-State: AFqh2kr5lVs9ype3HebXroStejDCOTOfY4SSPfwxmmcxupaoYFUOTq1o SnWNy3upkMsJwyDFKsJYRdaXmg== X-Google-Smtp-Source: AMrXdXtW1nCgdkbrHXhcjicn6j2V9OWLvwvd/Dr0BDIf9EddSzEQOU0pvITg7xzFjdqMkeGI5CcTQQ== X-Received: by 2002:a05:6512:c7:b0:4cb:7c2:8cb6 with SMTP id c7-20020a05651200c700b004cb07c28cb6mr567846lfp.44.1672028521102; Sun, 25 Dec 2022 20:22:01 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id o9-20020ac25e29000000b004b4b5da5f80sm1641129lfg.219.2022.12.25.20.22.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Dec 2022 20:22:00 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Stephen Boyd Subject: [PATCH v2 08/16] clk: qcom: gcc-qcs404: get rid of the test clock Date: Mon, 26 Dec 2022 06:21:46 +0200 Message-Id: <20221226042154.2666748-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221226042154.2666748-1-dmitry.baryshkov@linaro.org> References: <20221226042154.2666748-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The test clock isn't in the bindings and apparently it's not used by anyone upstream. Remove it. Suggested-by: Stephen Boyd Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-qcs404.c | 34 ---------------------------------- 1 file changed, 34 deletions(-) diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c index 241768da2263..e1d1d3a700f7 100644 --- a/drivers/clk/qcom/gcc-qcs404.c +++ b/drivers/clk/qcom/gcc-qcs404.c @@ -22,7 +22,6 @@ #include "reset.h" enum { - P_CORE_BI_PLL_TEST_SE, P_DSI0_PHY_PLL_OUT_BYTECLK, P_DSI0_PHY_PLL_OUT_DSICLK, P_GPLL0_OUT_MAIN, @@ -39,29 +38,24 @@ enum { static const struct parent_map gcc_parent_map_0[] = { { P_XO, 0 }, { P_GPLL0_OUT_MAIN, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_0[] = { "cxo", "gpll0_out_main", - "core_bi_pll_test_se", }; static const char * const gcc_parent_names_ao_0[] = { "cxo", "gpll0_ao_out_main", - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_1[] = { { P_XO, 0 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_1[] = { "cxo", - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_2[] = { @@ -82,50 +76,42 @@ static const struct parent_map gcc_parent_map_3[] = { { P_XO, 0 }, { P_GPLL0_OUT_MAIN, 1 }, { P_GPLL6_OUT_AUX, 2 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_3[] = { "cxo", "gpll0_out_main", "gpll6_out_aux", - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_4[] = { { P_XO, 0 }, { P_GPLL1_OUT_MAIN, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_4[] = { "cxo", "gpll1_out_main", - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_5[] = { { P_XO, 0 }, { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_5[] = { "cxo", "dsi0pllbyte", - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_6[] = { { P_XO, 0 }, { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_6[] = { "cxo", "dsi0pllbyte", - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_7[] = { @@ -133,7 +119,6 @@ static const struct parent_map gcc_parent_map_7[] = { { P_GPLL0_OUT_MAIN, 1 }, { P_GPLL3_OUT_MAIN, 2 }, { P_GPLL6_OUT_AUX, 3 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_7[] = { @@ -141,19 +126,16 @@ static const char * const gcc_parent_names_7[] = { "gpll0_out_main", "gpll3_out_main", "gpll6_out_aux", - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_8[] = { { P_XO, 0 }, { P_HDMI_PHY_PLL_CLK, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_8[] = { "cxo", "hdmi_pll", - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_9[] = { @@ -161,7 +143,6 @@ static const struct parent_map gcc_parent_map_9[] = { { P_GPLL0_OUT_MAIN, 1 }, { P_DSI0_PHY_PLL_OUT_DSICLK, 2 }, { P_GPLL6_OUT_AUX, 3 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_9[] = { @@ -169,43 +150,36 @@ static const char * const gcc_parent_names_9[] = { "gpll0_out_main", "dsi0pll", "gpll6_out_aux", - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_10[] = { { P_XO, 0 }, { P_SLEEP_CLK, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_10[] = { "cxo", "sleep_clk", - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_11[] = { { P_XO, 0 }, { P_PCIE_0_PIPE_CLK, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_11[] = { "cxo", "pcie_0_pipe_clk", - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_12[] = { { P_XO, 0 }, { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_12[] = { "cxo", "dsi0pll", - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_13[] = { @@ -213,7 +187,6 @@ static const struct parent_map gcc_parent_map_13[] = { { P_GPLL0_OUT_MAIN, 1 }, { P_GPLL4_OUT_MAIN, 2 }, { P_GPLL6_OUT_AUX, 3 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_13[] = { @@ -221,41 +194,34 @@ static const char * const gcc_parent_names_13[] = { "gpll0_out_main", "gpll4_out_main", "gpll6_out_aux", - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_14[] = { { P_XO, 0 }, { P_GPLL0_OUT_MAIN, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_14[] = { "cxo", "gpll0_out_main", - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_15[] = { { P_XO, 0 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_15[] = { "cxo", - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_16[] = { { P_XO, 0 }, { P_GPLL0_OUT_MAIN, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_16[] = { "cxo", "gpll0_out_main", - "core_bi_pll_test_se", }; static struct clk_fixed_factor cxo = { From patchwork Mon Dec 26 04:21:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 636852 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8EDA0C46467 for ; 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id o9-20020ac25e29000000b004b4b5da5f80sm1641129lfg.219.2022.12.25.20.22.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Dec 2022 20:22:01 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 09/16] clk: qcom: gcc-qcs404: move PLL clocks up Date: Mon, 26 Dec 2022 06:21:47 +0200 Message-Id: <20221226042154.2666748-10-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221226042154.2666748-1-dmitry.baryshkov@linaro.org> References: <20221226042154.2666748-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Move PLL clock declarations up, before clock parent tables, so that we can use pll hw clock fields in the next commit. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-qcs404.c | 298 +++++++++++++++++----------------- 1 file changed, 149 insertions(+), 149 deletions(-) diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c index e1d1d3a700f7..9b200b378b6b 100644 --- a/drivers/clk/qcom/gcc-qcs404.c +++ b/drivers/clk/qcom/gcc-qcs404.c @@ -35,6 +35,155 @@ enum { P_XO, }; +static struct clk_fixed_factor cxo = { + .mult = 1, + .div = 1, + .hw.init = &(struct clk_init_data){ + .name = "cxo", + .parent_names = (const char *[]){ "xo-board" }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + }, +}; + +static struct clk_alpha_pll gpll0_sleep_clk_src = { + .offset = 0x21000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr = { + .enable_reg = 0x45008, + .enable_mask = BIT(23), + .enable_is_inverted = true, + .hw.init = &(struct clk_init_data){ + .name = "gpll0_sleep_clk_src", + .parent_names = (const char *[]){ "cxo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_alpha_pll gpll0_out_main = { + .offset = 0x21000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .flags = SUPPORTS_FSM_MODE, + .clkr = { + .enable_reg = 0x45000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpll0_out_main", + .parent_names = (const char *[]) + { "cxo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_alpha_pll gpll0_ao_out_main = { + .offset = 0x21000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .flags = SUPPORTS_FSM_MODE, + .clkr = { + .enable_reg = 0x45000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpll0_ao_out_main", + .parent_names = (const char *[]){ "cxo" }, + .num_parents = 1, + .flags = CLK_IS_CRITICAL, + .ops = &clk_alpha_pll_fixed_ops, + }, + }, +}; + +static struct clk_alpha_pll gpll1_out_main = { + .offset = 0x20000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr = { + .enable_reg = 0x45000, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gpll1_out_main", + .parent_names = (const char *[]){ "cxo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +/* 930MHz configuration */ +static const struct alpha_pll_config gpll3_config = { + .l = 48, + .alpha = 0x0, + .alpha_en_mask = BIT(24), + .post_div_mask = 0xf << 8, + .post_div_val = 0x1 << 8, + .vco_mask = 0x3 << 20, + .main_output_mask = 0x1, + .config_ctl_val = 0x4001055b, +}; + +static const struct pll_vco gpll3_vco[] = { + { 700000000, 1400000000, 0 }, +}; + +static struct clk_alpha_pll gpll3_out_main = { + .offset = 0x22000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .vco_table = gpll3_vco, + .num_vco = ARRAY_SIZE(gpll3_vco), + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gpll3_out_main", + .parent_names = (const char *[]){ "cxo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_alpha_pll gpll4_out_main = { + .offset = 0x24000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr = { + .enable_reg = 0x45000, + .enable_mask = BIT(5), + .hw.init = &(struct clk_init_data){ + .name = "gpll4_out_main", + .parent_names = (const char *[]){ "cxo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_pll gpll6 = { + .l_reg = 0x37004, + .m_reg = 0x37008, + .n_reg = 0x3700C, + .config_reg = 0x37014, + .mode_reg = 0x37000, + .status_reg = 0x3701C, + .status_bit = 17, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpll6", + .parent_names = (const char *[]){ "cxo" }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +}; + +static struct clk_regmap gpll6_out_aux = { + .enable_reg = 0x45000, + .enable_mask = BIT(7), + .hw.init = &(struct clk_init_data){ + .name = "gpll6_out_aux", + .parent_names = (const char *[]){ "gpll6" }, + .num_parents = 1, + .ops = &clk_pll_vote_ops, + }, +}; + static const struct parent_map gcc_parent_map_0[] = { { P_XO, 0 }, { P_GPLL0_OUT_MAIN, 1 }, @@ -224,155 +373,6 @@ static const char * const gcc_parent_names_16[] = { "gpll0_out_main", }; -static struct clk_fixed_factor cxo = { - .mult = 1, - .div = 1, - .hw.init = &(struct clk_init_data){ - .name = "cxo", - .parent_names = (const char *[]){ "xo-board" }, - .num_parents = 1, - .ops = &clk_fixed_factor_ops, - }, -}; - -static struct clk_alpha_pll gpll0_sleep_clk_src = { - .offset = 0x21000, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], - .clkr = { - .enable_reg = 0x45008, - .enable_mask = BIT(23), - .enable_is_inverted = true, - .hw.init = &(struct clk_init_data){ - .name = "gpll0_sleep_clk_src", - .parent_names = (const char *[]){ "cxo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_ops, - }, - }, -}; - -static struct clk_alpha_pll gpll0_out_main = { - .offset = 0x21000, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], - .flags = SUPPORTS_FSM_MODE, - .clkr = { - .enable_reg = 0x45000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gpll0_out_main", - .parent_names = (const char *[]) - { "cxo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_ops, - }, - }, -}; - -static struct clk_alpha_pll gpll0_ao_out_main = { - .offset = 0x21000, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], - .flags = SUPPORTS_FSM_MODE, - .clkr = { - .enable_reg = 0x45000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gpll0_ao_out_main", - .parent_names = (const char *[]){ "cxo" }, - .num_parents = 1, - .flags = CLK_IS_CRITICAL, - .ops = &clk_alpha_pll_fixed_ops, - }, - }, -}; - -static struct clk_alpha_pll gpll1_out_main = { - .offset = 0x20000, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], - .clkr = { - .enable_reg = 0x45000, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gpll1_out_main", - .parent_names = (const char *[]){ "cxo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_ops, - }, - }, -}; - -/* 930MHz configuration */ -static const struct alpha_pll_config gpll3_config = { - .l = 48, - .alpha = 0x0, - .alpha_en_mask = BIT(24), - .post_div_mask = 0xf << 8, - .post_div_val = 0x1 << 8, - .vco_mask = 0x3 << 20, - .main_output_mask = 0x1, - .config_ctl_val = 0x4001055b, -}; - -static const struct pll_vco gpll3_vco[] = { - { 700000000, 1400000000, 0 }, -}; - -static struct clk_alpha_pll gpll3_out_main = { - .offset = 0x22000, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], - .vco_table = gpll3_vco, - .num_vco = ARRAY_SIZE(gpll3_vco), - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "gpll3_out_main", - .parent_names = (const char *[]){ "cxo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_ops, - }, - }, -}; - -static struct clk_alpha_pll gpll4_out_main = { - .offset = 0x24000, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], - .clkr = { - .enable_reg = 0x45000, - .enable_mask = BIT(5), - .hw.init = &(struct clk_init_data){ - .name = "gpll4_out_main", - .parent_names = (const char *[]){ "cxo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_ops, - }, - }, -}; - -static struct clk_pll gpll6 = { - .l_reg = 0x37004, - .m_reg = 0x37008, - .n_reg = 0x3700C, - .config_reg = 0x37014, - .mode_reg = 0x37000, - .status_reg = 0x3701C, - .status_bit = 17, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gpll6", - .parent_names = (const char *[]){ "cxo" }, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -}; - -static struct clk_regmap gpll6_out_aux = { - .enable_reg = 0x45000, - .enable_mask = BIT(7), - .hw.init = &(struct clk_init_data){ - .name = "gpll6_out_aux", - .parent_names = (const char *[]){ "gpll6" }, - .num_parents = 1, - .ops = &clk_pll_vote_ops, - }, -}; - static const struct freq_tbl ftbl_apss_ahb_clk_src[] = { F(19200000, P_XO, 1, 0, 0), F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), From patchwork Mon Dec 26 04:21:48 2022 Content-Type: text/plain; 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id o9-20020ac25e29000000b004b4b5da5f80sm1641129lfg.219.2022.12.25.20.22.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Dec 2022 20:22:02 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 10/16] clk: qcom: gcc-qcs404: use parent_hws/_data instead of parent_names Date: Mon, 26 Dec 2022 06:21:48 +0200 Message-Id: <20221226042154.2666748-11-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221226042154.2666748-1-dmitry.baryshkov@linaro.org> References: <20221226042154.2666748-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-qcs404.c | 524 ++++++++++++++++++---------------- 1 file changed, 275 insertions(+), 249 deletions(-) diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c index 9b200b378b6b..2726a48f2d5c 100644 --- a/drivers/clk/qcom/gcc-qcs404.c +++ b/drivers/clk/qcom/gcc-qcs404.c @@ -21,6 +21,15 @@ #include "common.h" #include "reset.h" +enum { + DT_XO, + DT_SLEEP_CLK, + DT_PCIE_0_PIPE_CLK, + DT_DSI0_PHY_PLL_OUT_DSICLK, + DT_DSI0_PHY_PLL_OUT_BYTECLK, + DT_HDMI_PHY_PLL_CLK, +}; + enum { P_DSI0_PHY_PLL_OUT_BYTECLK, P_DSI0_PHY_PLL_OUT_DSICLK, @@ -40,7 +49,9 @@ static struct clk_fixed_factor cxo = { .div = 1, .hw.init = &(struct clk_init_data){ .name = "cxo", - .parent_names = (const char *[]){ "xo-board" }, + .parent_data = &(const struct clk_parent_data) { + .name = "xo-board", + }, .num_parents = 1, .ops = &clk_fixed_factor_ops, }, @@ -55,7 +66,9 @@ static struct clk_alpha_pll gpll0_sleep_clk_src = { .enable_is_inverted = true, .hw.init = &(struct clk_init_data){ .name = "gpll0_sleep_clk_src", - .parent_names = (const char *[]){ "cxo" }, + .parent_data = &(const struct clk_parent_data) { + .hw = &cxo.hw, + }, .num_parents = 1, .ops = &clk_alpha_pll_ops, }, @@ -71,8 +84,9 @@ static struct clk_alpha_pll gpll0_out_main = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpll0_out_main", - .parent_names = (const char *[]) - { "cxo" }, + .parent_data = &(const struct clk_parent_data) { + .hw = &cxo.hw, + }, .num_parents = 1, .ops = &clk_alpha_pll_ops, }, @@ -88,7 +102,9 @@ static struct clk_alpha_pll gpll0_ao_out_main = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpll0_ao_out_main", - .parent_names = (const char *[]){ "cxo" }, + .parent_data = &(const struct clk_parent_data) { + .hw = &cxo.hw, + }, .num_parents = 1, .flags = CLK_IS_CRITICAL, .ops = &clk_alpha_pll_fixed_ops, @@ -104,7 +120,9 @@ static struct clk_alpha_pll gpll1_out_main = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gpll1_out_main", - .parent_names = (const char *[]){ "cxo" }, + .parent_data = &(const struct clk_parent_data) { + .hw = &cxo.hw, + }, .num_parents = 1, .ops = &clk_alpha_pll_ops, }, @@ -135,7 +153,9 @@ static struct clk_alpha_pll gpll3_out_main = { .clkr = { .hw.init = &(struct clk_init_data){ .name = "gpll3_out_main", - .parent_names = (const char *[]){ "cxo" }, + .parent_data = &(const struct clk_parent_data) { + .hw = &cxo.hw, + }, .num_parents = 1, .ops = &clk_alpha_pll_ops, }, @@ -150,7 +170,9 @@ static struct clk_alpha_pll gpll4_out_main = { .enable_mask = BIT(5), .hw.init = &(struct clk_init_data){ .name = "gpll4_out_main", - .parent_names = (const char *[]){ "cxo" }, + .parent_data = &(const struct clk_parent_data) { + .hw = &cxo.hw, + }, .num_parents = 1, .ops = &clk_alpha_pll_ops, }, @@ -167,7 +189,9 @@ static struct clk_pll gpll6 = { .status_bit = 17, .clkr.hw.init = &(struct clk_init_data){ .name = "gpll6", - .parent_names = (const char *[]){ "cxo" }, + .parent_data = &(const struct clk_parent_data) { + .hw = &cxo.hw, + }, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -178,7 +202,9 @@ static struct clk_regmap gpll6_out_aux = { .enable_mask = BIT(7), .hw.init = &(struct clk_init_data){ .name = "gpll6_out_aux", - .parent_names = (const char *[]){ "gpll6" }, + .parent_hws = (const struct clk_hw*[]) { + &gpll6.clkr.hw, + }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, @@ -189,22 +215,22 @@ static const struct parent_map gcc_parent_map_0[] = { { P_GPLL0_OUT_MAIN, 1 }, }; -static const char * const gcc_parent_names_0[] = { - "cxo", - "gpll0_out_main", +static const struct clk_parent_data gcc_parent_data_0[] = { + { .hw = &cxo.hw }, + { .hw = &gpll0_out_main.clkr.hw }, }; -static const char * const gcc_parent_names_ao_0[] = { - "cxo", - "gpll0_ao_out_main", +static const struct clk_parent_data gcc_parent_data_ao_0[] = { + { .hw = &cxo.hw }, + { .hw = &gpll0_ao_out_main.clkr.hw }, }; static const struct parent_map gcc_parent_map_1[] = { { P_XO, 0 }, }; -static const char * const gcc_parent_names_1[] = { - "cxo", +static const struct clk_parent_data gcc_parent_data_1[] = { + { .hw = &cxo.hw }, }; static const struct parent_map gcc_parent_map_2[] = { @@ -214,11 +240,11 @@ static const struct parent_map gcc_parent_map_2[] = { { P_SLEEP_CLK, 6 }, }; -static const char * const gcc_parent_names_2[] = { - "cxo", - "gpll0_out_main", - "gpll6_out_aux", - "sleep_clk", +static const struct clk_parent_data gcc_parent_data_2[] = { + { .hw = &cxo.hw }, + { .hw = &gpll0_out_main.clkr.hw }, + { .hw = &gpll6_out_aux.hw }, + { .index = DT_SLEEP_CLK, .name = "sleep_clk" }, }; static const struct parent_map gcc_parent_map_3[] = { @@ -227,10 +253,10 @@ static const struct parent_map gcc_parent_map_3[] = { { P_GPLL6_OUT_AUX, 2 }, }; -static const char * const gcc_parent_names_3[] = { - "cxo", - "gpll0_out_main", - "gpll6_out_aux", +static const struct clk_parent_data gcc_parent_data_3[] = { + { .hw = &cxo.hw }, + { .hw = &gpll0_out_main.clkr.hw }, + { .hw = &gpll6_out_aux.hw }, }; static const struct parent_map gcc_parent_map_4[] = { @@ -238,9 +264,9 @@ static const struct parent_map gcc_parent_map_4[] = { { P_GPLL1_OUT_MAIN, 1 }, }; -static const char * const gcc_parent_names_4[] = { - "cxo", - "gpll1_out_main", +static const struct clk_parent_data gcc_parent_data_4[] = { + { .hw = &cxo.hw }, + { .hw = &gpll1_out_main.clkr.hw }, }; static const struct parent_map gcc_parent_map_5[] = { @@ -248,9 +274,9 @@ static const struct parent_map gcc_parent_map_5[] = { { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, }; -static const char * const gcc_parent_names_5[] = { - "cxo", - "dsi0pllbyte", +static const struct clk_parent_data gcc_parent_data_5[] = { + { .hw = &cxo.hw }, + { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK, .name = "dsi0pllbyte" }, }; static const struct parent_map gcc_parent_map_6[] = { @@ -258,9 +284,9 @@ static const struct parent_map gcc_parent_map_6[] = { { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, }; -static const char * const gcc_parent_names_6[] = { - "cxo", - "dsi0pllbyte", +static const struct clk_parent_data gcc_parent_data_6[] = { + { .hw = &cxo.hw }, + { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK, .name = "dsi0pllbyte" }, }; static const struct parent_map gcc_parent_map_7[] = { @@ -270,11 +296,11 @@ static const struct parent_map gcc_parent_map_7[] = { { P_GPLL6_OUT_AUX, 3 }, }; -static const char * const gcc_parent_names_7[] = { - "cxo", - "gpll0_out_main", - "gpll3_out_main", - "gpll6_out_aux", +static const struct clk_parent_data gcc_parent_data_7[] = { + { .hw = &cxo.hw }, + { .hw = &gpll0_out_main.clkr.hw }, + { .hw = &gpll3_out_main.clkr.hw }, + { .hw = &gpll6_out_aux.hw }, }; static const struct parent_map gcc_parent_map_8[] = { @@ -282,9 +308,9 @@ static const struct parent_map gcc_parent_map_8[] = { { P_HDMI_PHY_PLL_CLK, 1 }, }; -static const char * const gcc_parent_names_8[] = { - "cxo", - "hdmi_pll", +static const struct clk_parent_data gcc_parent_data_8[] = { + { .hw = &cxo.hw }, + { .index = DT_HDMI_PHY_PLL_CLK, .name = "hdmi_pll" }, }; static const struct parent_map gcc_parent_map_9[] = { @@ -294,11 +320,11 @@ static const struct parent_map gcc_parent_map_9[] = { { P_GPLL6_OUT_AUX, 3 }, }; -static const char * const gcc_parent_names_9[] = { - "cxo", - "gpll0_out_main", - "dsi0pll", - "gpll6_out_aux", +static const struct clk_parent_data gcc_parent_data_9[] = { + { .hw = &cxo.hw }, + { .hw = &gpll0_out_main.clkr.hw }, + { .index = DT_DSI0_PHY_PLL_OUT_DSICLK, .name = "dsi0pll" }, + { .hw = &gpll6_out_aux.hw }, }; static const struct parent_map gcc_parent_map_10[] = { @@ -306,9 +332,9 @@ static const struct parent_map gcc_parent_map_10[] = { { P_SLEEP_CLK, 1 }, }; -static const char * const gcc_parent_names_10[] = { - "cxo", - "sleep_clk", +static const struct clk_parent_data gcc_parent_data_10[] = { + { .hw = &cxo.hw }, + { .index = DT_SLEEP_CLK, .name = "sleep_clk" }, }; static const struct parent_map gcc_parent_map_11[] = { @@ -316,9 +342,9 @@ static const struct parent_map gcc_parent_map_11[] = { { P_PCIE_0_PIPE_CLK, 1 }, }; -static const char * const gcc_parent_names_11[] = { - "cxo", - "pcie_0_pipe_clk", +static const struct clk_parent_data gcc_parent_data_11[] = { + { .hw = &cxo.hw }, + { .fw_name = "pcie_0_pipe_clk", .name = "pcie_0_pipe_clk" }, }; static const struct parent_map gcc_parent_map_12[] = { @@ -326,9 +352,9 @@ static const struct parent_map gcc_parent_map_12[] = { { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, }; -static const char * const gcc_parent_names_12[] = { - "cxo", - "dsi0pll", +static const struct clk_parent_data gcc_parent_data_12[] = { + { .hw = &cxo.hw }, + { .index = DT_DSI0_PHY_PLL_OUT_DSICLK, .name = "dsi0pll" }, }; static const struct parent_map gcc_parent_map_13[] = { @@ -338,11 +364,11 @@ static const struct parent_map gcc_parent_map_13[] = { { P_GPLL6_OUT_AUX, 3 }, }; -static const char * const gcc_parent_names_13[] = { - "cxo", - "gpll0_out_main", - "gpll4_out_main", - "gpll6_out_aux", +static const struct clk_parent_data gcc_parent_data_13[] = { + { .hw = &cxo.hw }, + { .hw = &gpll0_out_main.clkr.hw }, + { .hw = &gpll4_out_main.clkr.hw }, + { .hw = &gpll6_out_aux.hw }, }; static const struct parent_map gcc_parent_map_14[] = { @@ -350,17 +376,17 @@ static const struct parent_map gcc_parent_map_14[] = { { P_GPLL0_OUT_MAIN, 1 }, }; -static const char * const gcc_parent_names_14[] = { - "cxo", - "gpll0_out_main", +static const struct clk_parent_data gcc_parent_data_14[] = { + { .hw = &cxo.hw }, + { .hw = &gpll0_out_main.clkr.hw }, }; static const struct parent_map gcc_parent_map_15[] = { { P_XO, 0 }, }; -static const char * const gcc_parent_names_15[] = { - "cxo", +static const struct clk_parent_data gcc_parent_data_15[] = { + { .hw = &cxo.hw }, }; static const struct parent_map gcc_parent_map_16[] = { @@ -368,9 +394,9 @@ static const struct parent_map gcc_parent_map_16[] = { { P_GPLL0_OUT_MAIN, 1 }, }; -static const char * const gcc_parent_names_16[] = { - "cxo", - "gpll0_out_main", +static const struct clk_parent_data gcc_parent_data_16[] = { + { .hw = &cxo.hw }, + { .hw = &gpll0_out_main.clkr.hw }, }; static const struct freq_tbl ftbl_apss_ahb_clk_src[] = { @@ -389,8 +415,8 @@ static struct clk_rcg2 apss_ahb_clk_src = { .freq_tbl = ftbl_apss_ahb_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "apss_ahb_clk_src", - .parent_names = gcc_parent_names_ao_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_ao_0), + .parent_data = gcc_parent_data_ao_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_ao_0), .flags = CLK_IS_CRITICAL, .ops = &clk_rcg2_ops, }, @@ -410,8 +436,8 @@ static struct clk_rcg2 blsp1_qup0_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup0_i2c_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -435,8 +461,8 @@ static struct clk_rcg2 blsp1_qup0_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup0_spi_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -449,8 +475,8 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup1_i2c_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -474,8 +500,8 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup1_spi_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -488,8 +514,8 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup2_i2c_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -514,8 +540,8 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup2_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup2_spi_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -528,8 +554,8 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup3_i2c_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -542,8 +568,8 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup3_spi_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -556,8 +582,8 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup4_i2c_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -570,8 +596,8 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup4_spi_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -604,8 +630,8 @@ static struct clk_rcg2 blsp1_uart0_apps_clk_src = { .freq_tbl = ftbl_blsp1_uart0_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart0_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -618,8 +644,8 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = { .freq_tbl = ftbl_blsp1_uart0_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart1_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -632,8 +658,8 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = { .freq_tbl = ftbl_blsp1_uart0_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart2_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -647,8 +673,8 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = { .freq_tbl = ftbl_blsp1_uart0_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart3_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -661,8 +687,8 @@ static struct clk_rcg2 blsp2_qup0_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup0_i2c_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -675,8 +701,8 @@ static struct clk_rcg2 blsp2_qup0_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup0_spi_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -689,8 +715,8 @@ static struct clk_rcg2 blsp2_uart0_apps_clk_src = { .freq_tbl = ftbl_blsp1_uart0_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart0_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -702,8 +728,8 @@ static struct clk_rcg2 byte0_clk_src = { .parent_map = gcc_parent_map_5, .clkr.hw.init = &(struct clk_init_data){ .name = "byte0_clk_src", - .parent_names = gcc_parent_names_5, - .num_parents = ARRAY_SIZE(gcc_parent_names_5), + .parent_data = gcc_parent_data_5, + .num_parents = ARRAY_SIZE(gcc_parent_data_5), .flags = CLK_SET_RATE_PARENT, .ops = &clk_byte2_ops, }, @@ -725,8 +751,8 @@ static struct clk_rcg2 emac_clk_src = { .freq_tbl = ftbl_emac_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "emac_clk_src", - .parent_names = gcc_parent_names_4, - .num_parents = ARRAY_SIZE(gcc_parent_names_4), + .parent_data = gcc_parent_data_4, + .num_parents = ARRAY_SIZE(gcc_parent_data_4), .ops = &clk_rcg2_ops, }, }; @@ -746,8 +772,8 @@ static struct clk_rcg2 emac_ptp_clk_src = { .freq_tbl = ftbl_emac_ptp_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "emac_ptp_clk_src", - .parent_names = gcc_parent_names_4, - .num_parents = ARRAY_SIZE(gcc_parent_names_4), + .parent_data = gcc_parent_data_4, + .num_parents = ARRAY_SIZE(gcc_parent_data_4), .ops = &clk_rcg2_ops, }, }; @@ -765,8 +791,8 @@ static struct clk_rcg2 esc0_clk_src = { .freq_tbl = ftbl_esc0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "esc0_clk_src", - .parent_names = gcc_parent_names_6, - .num_parents = ARRAY_SIZE(gcc_parent_names_6), + .parent_data = gcc_parent_data_6, + .num_parents = ARRAY_SIZE(gcc_parent_data_6), .ops = &clk_rcg2_ops, }, }; @@ -799,8 +825,8 @@ static struct clk_rcg2 gfx3d_clk_src = { .freq_tbl = ftbl_gfx3d_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gfx3d_clk_src", - .parent_names = gcc_parent_names_7, - .num_parents = ARRAY_SIZE(gcc_parent_names_7), + .parent_data = gcc_parent_data_7, + .num_parents = ARRAY_SIZE(gcc_parent_data_7), .ops = &clk_rcg2_ops, }, }; @@ -820,8 +846,8 @@ static struct clk_rcg2 gp1_clk_src = { .freq_tbl = ftbl_gp1_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gp1_clk_src", - .parent_names = gcc_parent_names_2, - .num_parents = ARRAY_SIZE(gcc_parent_names_2), + .parent_data = gcc_parent_data_2, + .num_parents = ARRAY_SIZE(gcc_parent_data_2), .ops = &clk_rcg2_ops, }, }; @@ -834,8 +860,8 @@ static struct clk_rcg2 gp2_clk_src = { .freq_tbl = ftbl_gp1_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gp2_clk_src", - .parent_names = gcc_parent_names_2, - .num_parents = ARRAY_SIZE(gcc_parent_names_2), + .parent_data = gcc_parent_data_2, + .num_parents = ARRAY_SIZE(gcc_parent_data_2), .ops = &clk_rcg2_ops, }, }; @@ -848,8 +874,8 @@ static struct clk_rcg2 gp3_clk_src = { .freq_tbl = ftbl_gp1_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gp3_clk_src", - .parent_names = gcc_parent_names_2, - .num_parents = ARRAY_SIZE(gcc_parent_names_2), + .parent_data = gcc_parent_data_2, + .num_parents = ARRAY_SIZE(gcc_parent_data_2), .ops = &clk_rcg2_ops, }, }; @@ -862,8 +888,8 @@ static struct clk_rcg2 hdmi_app_clk_src = { .freq_tbl = ftbl_esc0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "hdmi_app_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = ARRAY_SIZE(gcc_parent_names_1), + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }, }; @@ -876,8 +902,8 @@ static struct clk_rcg2 hdmi_pclk_clk_src = { .freq_tbl = ftbl_esc0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "hdmi_pclk_clk_src", - .parent_names = gcc_parent_names_8, - .num_parents = ARRAY_SIZE(gcc_parent_names_8), + .parent_data = gcc_parent_data_8, + .num_parents = ARRAY_SIZE(gcc_parent_data_8), .ops = &clk_rcg2_ops, }, }; @@ -903,8 +929,8 @@ static struct clk_rcg2 mdp_clk_src = { .freq_tbl = ftbl_mdp_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "mdp_clk_src", - .parent_names = gcc_parent_names_9, - .num_parents = ARRAY_SIZE(gcc_parent_names_9), + .parent_data = gcc_parent_data_9, + .num_parents = ARRAY_SIZE(gcc_parent_data_9), .ops = &clk_rcg2_ops, }, }; @@ -922,8 +948,8 @@ static struct clk_rcg2 pcie_0_aux_clk_src = { .freq_tbl = ftbl_pcie_0_aux_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "pcie_0_aux_clk_src", - .parent_names = gcc_parent_names_10, - .num_parents = ARRAY_SIZE(gcc_parent_names_10), + .parent_data = gcc_parent_data_10, + .num_parents = ARRAY_SIZE(gcc_parent_data_10), .ops = &clk_rcg2_ops, }, }; @@ -943,8 +969,8 @@ static struct clk_rcg2 pcie_0_pipe_clk_src = { .freq_tbl = ftbl_pcie_0_pipe_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "pcie_0_pipe_clk_src", - .parent_names = gcc_parent_names_11, - .num_parents = ARRAY_SIZE(gcc_parent_names_11), + .parent_data = gcc_parent_data_11, + .num_parents = ARRAY_SIZE(gcc_parent_data_11), .ops = &clk_rcg2_ops, }, }; @@ -956,8 +982,8 @@ static struct clk_rcg2 pclk0_clk_src = { .parent_map = gcc_parent_map_12, .clkr.hw.init = &(struct clk_init_data){ .name = "pclk0_clk_src", - .parent_names = gcc_parent_names_12, - .num_parents = ARRAY_SIZE(gcc_parent_names_12), + .parent_data = gcc_parent_data_12, + .num_parents = ARRAY_SIZE(gcc_parent_data_12), .flags = CLK_SET_RATE_PARENT, .ops = &clk_pixel_ops, }, @@ -977,8 +1003,8 @@ static struct clk_rcg2 pdm2_clk_src = { .freq_tbl = ftbl_pdm2_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "pdm2_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -1005,8 +1031,8 @@ static struct clk_rcg2 sdcc1_apps_clk_src = { .freq_tbl = ftbl_sdcc1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc1_apps_clk_src", - .parent_names = gcc_parent_names_13, - .num_parents = ARRAY_SIZE(gcc_parent_names_13), + .parent_data = gcc_parent_data_13, + .num_parents = ARRAY_SIZE(gcc_parent_data_13), .ops = &clk_rcg2_floor_ops, }, }; @@ -1025,8 +1051,8 @@ static struct clk_rcg2 sdcc1_ice_core_clk_src = { .freq_tbl = ftbl_sdcc1_ice_core_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc1_ice_core_clk_src", - .parent_names = gcc_parent_names_3, - .num_parents = ARRAY_SIZE(gcc_parent_names_3), + .parent_data = gcc_parent_data_3, + .num_parents = ARRAY_SIZE(gcc_parent_data_3), .ops = &clk_rcg2_ops, }, }; @@ -1051,8 +1077,8 @@ static struct clk_rcg2 sdcc2_apps_clk_src = { .freq_tbl = ftbl_sdcc2_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc2_apps_clk_src", - .parent_names = gcc_parent_names_14, - .num_parents = ARRAY_SIZE(gcc_parent_names_14), + .parent_data = gcc_parent_data_14, + .num_parents = ARRAY_SIZE(gcc_parent_data_14), .ops = &clk_rcg2_floor_ops, }, }; @@ -1065,8 +1091,8 @@ static struct clk_rcg2 usb20_mock_utmi_clk_src = { .freq_tbl = ftbl_esc0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "usb20_mock_utmi_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = ARRAY_SIZE(gcc_parent_names_1), + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }, }; @@ -1087,8 +1113,8 @@ static struct clk_rcg2 usb30_master_clk_src = { .freq_tbl = ftbl_usb30_master_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "usb30_master_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -1101,8 +1127,8 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = { .freq_tbl = ftbl_esc0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "usb30_mock_utmi_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = ARRAY_SIZE(gcc_parent_names_1), + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }, }; @@ -1115,8 +1141,8 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = { .freq_tbl = ftbl_pcie_0_aux_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "usb3_phy_aux_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = ARRAY_SIZE(gcc_parent_names_1), + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }, }; @@ -1138,8 +1164,8 @@ static struct clk_rcg2 usb_hs_system_clk_src = { .freq_tbl = ftbl_usb_hs_system_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "usb_hs_system_clk_src", - .parent_names = gcc_parent_names_3, - .num_parents = ARRAY_SIZE(gcc_parent_names_3), + .parent_data = gcc_parent_data_3, + .num_parents = ARRAY_SIZE(gcc_parent_data_3), .ops = &clk_rcg2_ops, }, }; @@ -1152,8 +1178,8 @@ static struct clk_rcg2 vsync_clk_src = { .freq_tbl = ftbl_esc0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "vsync_clk_src", - .parent_names = gcc_parent_names_15, - .num_parents = ARRAY_SIZE(gcc_parent_names_15), + .parent_data = gcc_parent_data_15, + .num_parents = ARRAY_SIZE(gcc_parent_data_15), .ops = &clk_rcg2_ops, }, }; @@ -1174,8 +1200,8 @@ static struct clk_rcg2 cdsp_bimc_clk_src = { .freq_tbl = ftbl_cdsp_bimc_clk_src, .clkr.hw.init = &(struct clk_init_data) { .name = "cdsp_bimc_clk_src", - .parent_names = gcc_parent_names_16, - .num_parents = ARRAY_SIZE(gcc_parent_names_16), + .parent_data = gcc_parent_data_16, + .num_parents = ARRAY_SIZE(gcc_parent_data_16), .ops = &clk_rcg2_ops, }, }; @@ -1188,8 +1214,8 @@ static struct clk_branch gcc_apss_ahb_clk = { .enable_mask = BIT(14), .hw.init = &(struct clk_init_data){ .name = "gcc_apss_ahb_clk", - .parent_names = (const char *[]){ - "apss_ahb_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &apss_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1220,8 +1246,8 @@ static struct clk_branch gcc_bimc_gfx_clk = { .hw.init = &(struct clk_init_data){ .name = "gcc_bimc_gfx_clk", .ops = &clk_branch2_ops, - .parent_names = (const char *[]){ - "gcc_apss_tcu_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_apss_tcu_clk.clkr.hw, }, }, @@ -1249,8 +1275,8 @@ static struct clk_branch gcc_bimc_cdsp_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "gcc_bimc_cdsp_clk", - .parent_names = (const char *[]) { - "cdsp_bimc_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &cdsp_bimc_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1319,8 +1345,8 @@ static struct clk_branch gcc_blsp1_qup0_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup0_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup0_i2c_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp1_qup0_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1337,8 +1363,8 @@ static struct clk_branch gcc_blsp1_qup0_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup0_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup0_spi_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp1_qup0_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1355,8 +1381,8 @@ static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup1_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup1_i2c_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp1_qup1_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1373,8 +1399,8 @@ static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup1_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup1_spi_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp1_qup1_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1391,8 +1417,8 @@ static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup2_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup2_i2c_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp1_qup2_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1409,8 +1435,8 @@ static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup2_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup2_spi_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp1_qup2_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1427,8 +1453,8 @@ static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup3_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup3_i2c_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp1_qup3_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1445,8 +1471,8 @@ static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup3_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup3_spi_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp1_qup3_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1463,8 +1489,8 @@ static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup4_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup4_i2c_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp1_qup4_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1481,8 +1507,8 @@ static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup4_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup4_spi_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp1_qup4_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1499,8 +1525,8 @@ static struct clk_branch gcc_blsp1_uart0_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_uart0_apps_clk", - .parent_names = (const char *[]){ - "blsp1_uart0_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp1_uart0_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1517,8 +1543,8 @@ static struct clk_branch gcc_blsp1_uart1_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_uart1_apps_clk", - .parent_names = (const char *[]){ - "blsp1_uart1_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp1_uart1_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1535,8 +1561,8 @@ static struct clk_branch gcc_blsp1_uart2_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_uart2_apps_clk", - .parent_names = (const char *[]){ - "blsp1_uart2_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp1_uart2_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1553,8 +1579,8 @@ static struct clk_branch gcc_blsp1_uart3_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_uart3_apps_clk", - .parent_names = (const char *[]){ - "blsp1_uart3_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp1_uart3_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1584,8 +1610,8 @@ static struct clk_branch gcc_blsp2_qup0_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup0_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup0_i2c_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp2_qup0_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1602,8 +1628,8 @@ static struct clk_branch gcc_blsp2_qup0_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup0_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup0_spi_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp2_qup0_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1620,8 +1646,8 @@ static struct clk_branch gcc_blsp2_uart0_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_uart0_apps_clk", - .parent_names = (const char *[]){ - "blsp2_uart0_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp2_uart0_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1703,8 +1729,8 @@ static struct clk_branch gcc_eth_ptp_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_eth_ptp_clk", - .parent_names = (const char *[]){ - "emac_ptp_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &emac_ptp_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1721,8 +1747,8 @@ static struct clk_branch gcc_eth_rgmii_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_eth_rgmii_clk", - .parent_names = (const char *[]){ - "emac_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &emac_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1804,8 +1830,8 @@ static struct clk_branch gcc_cdsp_tbu_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data) { .name = "gcc_cdsp_tbu_clk", - .parent_names = (const char *[]) { - "cdsp_bimc_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &cdsp_bimc_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1822,8 +1848,8 @@ static struct clk_branch gcc_gp1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp1_clk", - .parent_names = (const char *[]){ - "gp1_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &gp1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1840,8 +1866,8 @@ static struct clk_branch gcc_gp2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp2_clk", - .parent_names = (const char *[]){ - "gp2_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &gp2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1858,8 +1884,8 @@ static struct clk_branch gcc_gp3_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp3_clk", - .parent_names = (const char *[]){ - "gp3_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &gp3_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1928,8 +1954,8 @@ static struct clk_branch gcc_mdss_byte0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mdss_byte0_clk", - .parent_names = (const char *[]){ - "byte0_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &byte0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1946,8 +1972,8 @@ static struct clk_branch gcc_mdss_esc0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mdss_esc0_clk", - .parent_names = (const char *[]){ - "esc0_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &esc0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1964,8 +1990,8 @@ static struct clk_branch gcc_mdss_hdmi_app_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mdss_hdmi_app_clk", - .parent_names = (const char *[]){ - "hdmi_app_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &hdmi_app_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1982,8 +2008,8 @@ static struct clk_branch gcc_mdss_hdmi_pclk_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mdss_hdmi_pclk_clk", - .parent_names = (const char *[]){ - "hdmi_pclk_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &hdmi_pclk_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2000,8 +2026,8 @@ static struct clk_branch gcc_mdss_mdp_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mdss_mdp_clk", - .parent_names = (const char *[]){ - "mdp_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &mdp_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2018,8 +2044,8 @@ static struct clk_branch gcc_mdss_pclk0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mdss_pclk0_clk", - .parent_names = (const char *[]){ - "pclk0_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &pclk0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2036,8 +2062,8 @@ static struct clk_branch gcc_mdss_vsync_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mdss_vsync_clk", - .parent_names = (const char *[]){ - "vsync_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &vsync_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2067,8 +2093,8 @@ static struct clk_branch gcc_oxili_gfx3d_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_oxili_gfx3d_clk", - .parent_names = (const char *[]){ - "gfx3d_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &gfx3d_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2085,8 +2111,8 @@ static struct clk_branch gcc_pcie_0_aux_clk = { .enable_mask = BIT(27), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_aux_clk", - .parent_names = (const char *[]){ - "pcie_0_aux_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &pcie_0_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2129,8 +2155,8 @@ static struct clk_branch gcc_pcie_0_pipe_clk = { .enable_mask = BIT(28), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_pipe_clk", - .parent_names = (const char *[]){ - "pcie_0_pipe_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &pcie_0_pipe_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2188,8 +2214,8 @@ static struct clk_branch gcc_pdm2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pdm2_clk", - .parent_names = (const char *[]){ - "pdm2_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &pdm2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2298,8 +2324,8 @@ static struct clk_branch gcc_sdcc1_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc1_apps_clk", - .parent_names = (const char *[]){ - "sdcc1_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &sdcc1_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2316,8 +2342,8 @@ static struct clk_branch gcc_sdcc1_ice_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc1_ice_core_clk", - .parent_names = (const char *[]){ - "sdcc1_ice_core_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &sdcc1_ice_core_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2360,8 +2386,8 @@ static struct clk_branch gcc_sdcc2_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc2_apps_clk", - .parent_names = (const char *[]){ - "sdcc2_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &sdcc2_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2391,8 +2417,8 @@ static struct clk_branch gcc_sys_noc_usb3_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sys_noc_usb3_clk", - .parent_names = (const char *[]){ - "usb30_master_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &usb30_master_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -2421,8 +2447,8 @@ static struct clk_branch gcc_usb20_mock_utmi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb20_mock_utmi_clk", - .parent_names = (const char *[]){ - "usb20_mock_utmi_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &usb20_mock_utmi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2452,8 +2478,8 @@ static struct clk_branch gcc_usb30_master_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb30_master_clk", - .parent_names = (const char *[]){ - "usb30_master_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &usb30_master_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2470,8 +2496,8 @@ static struct clk_branch gcc_usb30_mock_utmi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb30_mock_utmi_clk", - .parent_names = (const char *[]){ - "usb30_mock_utmi_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &usb30_mock_utmi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2501,8 +2527,8 @@ static struct clk_branch gcc_usb3_phy_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb3_phy_aux_clk", - .parent_names = (const char *[]){ - "usb3_phy_aux_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &usb3_phy_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2544,8 +2570,8 @@ static struct clk_branch gcc_usb_hs_system_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb_hs_system_clk", - .parent_names = (const char *[]){ - "usb_hs_system_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &usb_hs_system_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, From patchwork Mon Dec 26 04:21:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 637029 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2549EC4708D for ; Mon, 26 Dec 2022 04:22:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231588AbiLZEWV (ORCPT ); Sun, 25 Dec 2022 23:22:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55396 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231590AbiLZEWH (ORCPT ); Sun, 25 Dec 2022 23:22:07 -0500 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BC97B2DD4 for ; Sun, 25 Dec 2022 20:22:04 -0800 (PST) Received: by mail-lf1-x12d.google.com with SMTP id bp15so14652207lfb.13 for ; Sun, 25 Dec 2022 20:22:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iIx7HE1YspqQa0r7eyhFqYmEA7OT5Q00tyYl8HNz71o=; b=P769JKfcvOl1osNUabAk5YEWH+3F1uiHZd2AeXE6GDTZkzdTAapQG73SkPZkMcEAgh dcLZ12Er8hF8fH/D6VnnUgQIUVwPxHcSU8WHQq+A4QpETbancey5P4WskWDNqJxin9Yb mZrTU8ANnnHHANzbE2T6Bn6MI/rpKYEk8eorc9vi19lSKbn4cMYM/Ua51fi4cVtkI6z/ VOOtA1Qg/UisRVHN9Id1pzc6K1wpi7uKwSPqpjXzFz2V53Kt8GekjiyLlsswGA82JA3h UCVB7xKy08sdYKa1MRCjNZS1jJI3nndM3DM36QXTNFvX3jYokIJ89yzOlEmFkKlueWIV y/ug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iIx7HE1YspqQa0r7eyhFqYmEA7OT5Q00tyYl8HNz71o=; b=Q4byjekB09dJ/ShziuFypcWvONjn5honfkUzd8e5L9/YBdyQ1Lx23Xv7/+a6f4NZaC lG3TCSRIuRNoWvUGAe+7NwhMoo5sdli5LdPcCKnFprGJn9HoTTTBkepBeFR9gz4KN0wA mccc96wQrmI0iD7kx/Ql+s0/IoCmgygNeP2gK4sI2kgcI/KE19RiJELKcMogCDLAl+T9 RbS38+qrJYC3XdNXGI9Ch/FPAKCJ1JtNuEBRbzzpWwS7nOHJzi0e5at0tWkQIDls/n9m S9f6XCEp6oRQ/I0wsCBl3mo5TmG0oVTh8XdS1B8LzN4CY5Y/dtY+bN79/u95jQELksY2 5uEw== X-Gm-Message-State: AFqh2krjOXkaEGXro7sa3lQfYjWO8jrXXhfuWnyDHuKaXLjMp/8gBgrU ys4ytD8urz6YXiVBY438a/D/eg== X-Google-Smtp-Source: AMrXdXvM8Xjb4IO/VgqQFticH+n2U5q4Oo7gwg1mGjiILkj/vwLcssm8UygiVxipnL42LtlWIQu7GA== X-Received: by 2002:a05:6512:3601:b0:4b5:9bfa:801a with SMTP id f1-20020a056512360100b004b59bfa801amr4287240lfs.46.1672028523110; Sun, 25 Dec 2022 20:22:03 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id o9-20020ac25e29000000b004b4b5da5f80sm1641129lfg.219.2022.12.25.20.22.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Dec 2022 20:22:02 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 11/16] clk: qcom: gcc-qcs404: sort out the cxo clock Date: Mon, 26 Dec 2022 06:21:49 +0200 Message-Id: <20221226042154.2666748-12-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221226042154.2666748-1-dmitry.baryshkov@linaro.org> References: <20221226042154.2666748-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The GCC driver registers the cxo clock as a thin wrapper around board's xo_board clock. Nowadays we can use the xo_board directly in all the clocks that use it. Use the fw_name "cxo" for this clock. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-qcs404.c | 97 +++++++++++++++-------------------- 1 file changed, 41 insertions(+), 56 deletions(-) diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c index 2726a48f2d5c..fa2adf242648 100644 --- a/drivers/clk/qcom/gcc-qcs404.c +++ b/drivers/clk/qcom/gcc-qcs404.c @@ -44,14 +44,21 @@ enum { P_XO, }; +static const struct parent_map gcc_parent_map_1[] = { + { P_XO, 0 }, +}; + +static const struct clk_parent_data gcc_parent_data_1[] = { + { .index = DT_XO, .name = "xo-board" }, +}; + static struct clk_fixed_factor cxo = { .mult = 1, .div = 1, .hw.init = &(struct clk_init_data){ .name = "cxo", - .parent_data = &(const struct clk_parent_data) { - .name = "xo-board", - }, + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), .num_parents = 1, .ops = &clk_fixed_factor_ops, }, @@ -66,10 +73,8 @@ static struct clk_alpha_pll gpll0_sleep_clk_src = { .enable_is_inverted = true, .hw.init = &(struct clk_init_data){ .name = "gpll0_sleep_clk_src", - .parent_data = &(const struct clk_parent_data) { - .hw = &cxo.hw, - }, - .num_parents = 1, + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_alpha_pll_ops, }, }, @@ -84,10 +89,8 @@ static struct clk_alpha_pll gpll0_out_main = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpll0_out_main", - .parent_data = &(const struct clk_parent_data) { - .hw = &cxo.hw, - }, - .num_parents = 1, + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_alpha_pll_ops, }, }, @@ -102,10 +105,8 @@ static struct clk_alpha_pll gpll0_ao_out_main = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpll0_ao_out_main", - .parent_data = &(const struct clk_parent_data) { - .hw = &cxo.hw, - }, - .num_parents = 1, + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), .flags = CLK_IS_CRITICAL, .ops = &clk_alpha_pll_fixed_ops, }, @@ -120,10 +121,8 @@ static struct clk_alpha_pll gpll1_out_main = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gpll1_out_main", - .parent_data = &(const struct clk_parent_data) { - .hw = &cxo.hw, - }, - .num_parents = 1, + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_alpha_pll_ops, }, }, @@ -153,10 +152,8 @@ static struct clk_alpha_pll gpll3_out_main = { .clkr = { .hw.init = &(struct clk_init_data){ .name = "gpll3_out_main", - .parent_data = &(const struct clk_parent_data) { - .hw = &cxo.hw, - }, - .num_parents = 1, + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_alpha_pll_ops, }, }, @@ -170,10 +167,8 @@ static struct clk_alpha_pll gpll4_out_main = { .enable_mask = BIT(5), .hw.init = &(struct clk_init_data){ .name = "gpll4_out_main", - .parent_data = &(const struct clk_parent_data) { - .hw = &cxo.hw, - }, - .num_parents = 1, + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_alpha_pll_ops, }, }, @@ -189,10 +184,8 @@ static struct clk_pll gpll6 = { .status_bit = 17, .clkr.hw.init = &(struct clk_init_data){ .name = "gpll6", - .parent_data = &(const struct clk_parent_data) { - .hw = &cxo.hw, - }, - .num_parents = 1, + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_pll_ops, }, }; @@ -216,23 +209,15 @@ static const struct parent_map gcc_parent_map_0[] = { }; static const struct clk_parent_data gcc_parent_data_0[] = { - { .hw = &cxo.hw }, + { .index = DT_XO, .name = "xo-board" }, { .hw = &gpll0_out_main.clkr.hw }, }; static const struct clk_parent_data gcc_parent_data_ao_0[] = { - { .hw = &cxo.hw }, + { .index = DT_XO, .name = "xo-board" }, { .hw = &gpll0_ao_out_main.clkr.hw }, }; -static const struct parent_map gcc_parent_map_1[] = { - { P_XO, 0 }, -}; - -static const struct clk_parent_data gcc_parent_data_1[] = { - { .hw = &cxo.hw }, -}; - static const struct parent_map gcc_parent_map_2[] = { { P_XO, 0 }, { P_GPLL0_OUT_MAIN, 1 }, @@ -241,7 +226,7 @@ static const struct parent_map gcc_parent_map_2[] = { }; static const struct clk_parent_data gcc_parent_data_2[] = { - { .hw = &cxo.hw }, + { .index = DT_XO, .name = "xo-board" }, { .hw = &gpll0_out_main.clkr.hw }, { .hw = &gpll6_out_aux.hw }, { .index = DT_SLEEP_CLK, .name = "sleep_clk" }, @@ -254,7 +239,7 @@ static const struct parent_map gcc_parent_map_3[] = { }; static const struct clk_parent_data gcc_parent_data_3[] = { - { .hw = &cxo.hw }, + { .index = DT_XO, .name = "xo-board" }, { .hw = &gpll0_out_main.clkr.hw }, { .hw = &gpll6_out_aux.hw }, }; @@ -265,7 +250,7 @@ static const struct parent_map gcc_parent_map_4[] = { }; static const struct clk_parent_data gcc_parent_data_4[] = { - { .hw = &cxo.hw }, + { .index = DT_XO, .name = "xo-board" }, { .hw = &gpll1_out_main.clkr.hw }, }; @@ -275,7 +260,7 @@ static const struct parent_map gcc_parent_map_5[] = { }; static const struct clk_parent_data gcc_parent_data_5[] = { - { .hw = &cxo.hw }, + { .index = DT_XO, .name = "xo-board" }, { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK, .name = "dsi0pllbyte" }, }; @@ -285,7 +270,7 @@ static const struct parent_map gcc_parent_map_6[] = { }; static const struct clk_parent_data gcc_parent_data_6[] = { - { .hw = &cxo.hw }, + { .index = DT_XO, .name = "xo-board" }, { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK, .name = "dsi0pllbyte" }, }; @@ -297,7 +282,7 @@ static const struct parent_map gcc_parent_map_7[] = { }; static const struct clk_parent_data gcc_parent_data_7[] = { - { .hw = &cxo.hw }, + { .index = DT_XO, .name = "xo-board" }, { .hw = &gpll0_out_main.clkr.hw }, { .hw = &gpll3_out_main.clkr.hw }, { .hw = &gpll6_out_aux.hw }, @@ -309,7 +294,7 @@ static const struct parent_map gcc_parent_map_8[] = { }; static const struct clk_parent_data gcc_parent_data_8[] = { - { .hw = &cxo.hw }, + { .index = DT_XO, .name = "xo-board" }, { .index = DT_HDMI_PHY_PLL_CLK, .name = "hdmi_pll" }, }; @@ -321,7 +306,7 @@ static const struct parent_map gcc_parent_map_9[] = { }; static const struct clk_parent_data gcc_parent_data_9[] = { - { .hw = &cxo.hw }, + { .index = DT_XO, .name = "xo-board" }, { .hw = &gpll0_out_main.clkr.hw }, { .index = DT_DSI0_PHY_PLL_OUT_DSICLK, .name = "dsi0pll" }, { .hw = &gpll6_out_aux.hw }, @@ -333,7 +318,7 @@ static const struct parent_map gcc_parent_map_10[] = { }; static const struct clk_parent_data gcc_parent_data_10[] = { - { .hw = &cxo.hw }, + { .index = DT_XO, .name = "xo-board" }, { .index = DT_SLEEP_CLK, .name = "sleep_clk" }, }; @@ -343,7 +328,7 @@ static const struct parent_map gcc_parent_map_11[] = { }; static const struct clk_parent_data gcc_parent_data_11[] = { - { .hw = &cxo.hw }, + { .index = DT_XO, .name = "xo-board" }, { .fw_name = "pcie_0_pipe_clk", .name = "pcie_0_pipe_clk" }, }; @@ -353,7 +338,7 @@ static const struct parent_map gcc_parent_map_12[] = { }; static const struct clk_parent_data gcc_parent_data_12[] = { - { .hw = &cxo.hw }, + { .index = DT_XO, .name = "xo-board" }, { .index = DT_DSI0_PHY_PLL_OUT_DSICLK, .name = "dsi0pll" }, }; @@ -365,7 +350,7 @@ static const struct parent_map gcc_parent_map_13[] = { }; static const struct clk_parent_data gcc_parent_data_13[] = { - { .hw = &cxo.hw }, + { .index = DT_XO, .name = "xo-board" }, { .hw = &gpll0_out_main.clkr.hw }, { .hw = &gpll4_out_main.clkr.hw }, { .hw = &gpll6_out_aux.hw }, @@ -377,7 +362,7 @@ static const struct parent_map gcc_parent_map_14[] = { }; static const struct clk_parent_data gcc_parent_data_14[] = { - { .hw = &cxo.hw }, + { .index = DT_XO, .name = "xo-board" }, { .hw = &gpll0_out_main.clkr.hw }, }; @@ -386,7 +371,7 @@ static const struct parent_map gcc_parent_map_15[] = { }; static const struct clk_parent_data gcc_parent_data_15[] = { - { .hw = &cxo.hw }, + { .index = DT_XO, .name = "xo-board" }, }; static const struct parent_map gcc_parent_map_16[] = { @@ -395,7 +380,7 @@ static const struct parent_map gcc_parent_map_16[] = { }; static const struct clk_parent_data gcc_parent_data_16[] = { - { .hw = &cxo.hw }, + { .index = DT_XO, .name = "xo-board" }, { .hw = &gpll0_out_main.clkr.hw }, }; From patchwork Mon Dec 26 04:21:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 636850 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BEF4AC3DA7D for ; Mon, 26 Dec 2022 04:22:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231631AbiLZEWX (ORCPT ); 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id o9-20020ac25e29000000b004b4b5da5f80sm1641129lfg.219.2022.12.25.20.22.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Dec 2022 20:22:03 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 12/16] clk: qcom: gcc-qcs404: add support for GDSCs Date: Mon, 26 Dec 2022 06:21:50 +0200 Message-Id: <20221226042154.2666748-13-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221226042154.2666748-1-dmitry.baryshkov@linaro.org> References: <20221226042154.2666748-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for two GDSCs provided by this clock controller. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-qcs404.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c index fa2adf242648..5f58dd82d3fe 100644 --- a/drivers/clk/qcom/gcc-qcs404.c +++ b/drivers/clk/qcom/gcc-qcs404.c @@ -19,6 +19,7 @@ #include "clk-rcg.h" #include "clk-regmap.h" #include "common.h" +#include "gdsc.h" #include "reset.h" enum { @@ -2591,6 +2592,22 @@ static struct clk_branch gcc_wdsp_q6ss_axim_clk = { }, }; +static struct gdsc mdss_gdsc = { + .gdscr = 0x4d078, + .pd = { + .name = "mdss", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc oxili_gdsc = { + .gdscr = 0x5901c, + .pd = { + .name = "oxili", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + static struct clk_hw *gcc_qcs404_hws[] = { &cxo.hw, }; @@ -2741,6 +2758,11 @@ static struct clk_regmap *gcc_qcs404_clocks[] = { }; +static struct gdsc *gcc_qcs404_gdscs[] = { + [MDSS_GDSC] = &mdss_gdsc, + [OXILI_GDSC] = &oxili_gdsc, +}; + static const struct qcom_reset_map gcc_qcs404_resets[] = { [GCC_GENI_IR_BCR] = { 0x0F000 }, [GCC_CDSP_RESTART] = { 0x18000 }, @@ -2783,6 +2805,8 @@ static const struct qcom_cc_desc gcc_qcs404_desc = { .num_resets = ARRAY_SIZE(gcc_qcs404_resets), .clk_hws = gcc_qcs404_hws, .num_clk_hws = ARRAY_SIZE(gcc_qcs404_hws), + .gdscs = gcc_qcs404_gdscs, + .num_gdscs = ARRAY_SIZE(gcc_qcs404_gdscs), }; static const struct of_device_id gcc_qcs404_match_table[] = { From patchwork Mon Dec 26 04:21:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 636851 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2BFF2C3DA7D for ; Mon, 26 Dec 2022 04:22:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231684AbiLZEWU (ORCPT ); Sun, 25 Dec 2022 23:22:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55152 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231588AbiLZEWH (ORCPT ); Sun, 25 Dec 2022 23:22:07 -0500 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DBB3DF0E for ; Sun, 25 Dec 2022 20:22:04 -0800 (PST) Received: by mail-lf1-x12a.google.com with SMTP id j17so5171858lfr.3 for ; Sun, 25 Dec 2022 20:22:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=K3Cjy9s6gypFp3ghKgty1JYd6DQSNA1Ltc9upzL/NcE=; b=ort+xNiFTW1OLCtBf9mySYVPp/oh2y0W7fcdvsiGLVD8ffg2068oh/jBCHfBngMXLk 9a216O+Mvxwcgi42b0wNcGdy/UHsj0IHZL1HMO01zTsS8TCL7KRyj7TmMqsjMRISTNMs brPoNwt0kcRrVJKeCmolumLDAcwl+W0ViDnbnlz0P3m6/0ux6XhwBER+DWnZk8i+rapl MEMOwS57bV1Q81OkFY27I9F5uueu+i7HHlZqF8xBWq4kEEjsxMm99Wf2IbqC6Pra94D4 g6YAGTEtrVU8gBOMKQES9swUgR3QfAJWiqQF3lm5oPZ3VmwN9EBF/lpnKZw4XHvYFzv3 0YJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=K3Cjy9s6gypFp3ghKgty1JYd6DQSNA1Ltc9upzL/NcE=; b=M5Z7O1LxkLIxyD1foSdi9R6QTM4cdr7pbmFlFISRzTQQbnCN+nb/vKxVAFnWbLGWXr IpiOc7x2jLms9eZIYckhVN3vBlr6oUbA9e5GXm2csKsv7+W4qieOHwRqd+DyG2Z84wqL ePU9JeEkS8pFRd8hl1De2gmfJ60HlR1urDq8WI12V2WroGHzE2TUAdgXwUp+DGZ5uZno 0FtxKLkkDR4iNhWjcW9f+/Ul8V3RQkXsaJ6BlJwM/flq4C9REtVPW281nkH58ViUnKk4 cpmnwTSoe5rUf/aDcD2x9tqkLhuGp2V07GgEOuIOYCQSaeuHBAQORfFWZPNqxMNbjUf+ DdmA== X-Gm-Message-State: AFqh2krHRGOfYKQ02E5IQ2uSZoXbmcXYxQKR2sPO8s4rtMbl0oWzod0j GbburERTZ21Kmd5VSY47mw4Deg== X-Google-Smtp-Source: AMrXdXttQJDfNNEbtYq/mZaOMKWs7K3DAmhknVeOeKGMe+SZhCQ3+Zm7jCfw/DTE33ixK2oVZg6TLQ== X-Received: by 2002:a05:6512:2102:b0:4ca:f9bd:3390 with SMTP id q2-20020a056512210200b004caf9bd3390mr2247565lfr.31.1672028524475; Sun, 25 Dec 2022 20:22:04 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id o9-20020ac25e29000000b004b4b5da5f80sm1641129lfg.219.2022.12.25.20.22.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Dec 2022 20:22:04 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 13/16] arm64: dts: qcom: qcs404: use symbol names for PCIe resets Date: Mon, 26 Dec 2022 06:21:51 +0200 Message-Id: <20221226042154.2666748-14-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221226042154.2666748-1-dmitry.baryshkov@linaro.org> References: <20221226042154.2666748-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The commit e5bbbff5b7d7 ("clk: gcc-qcs404: Add PCIe resets") added names for PCIe resets, but it did not change the existing qcs404.dtsi to use these names. Do it now and use symbol names to make it easier to check and modify the dtsi in future. Fixes: e5bbbff5b7d7 ("clk: gcc-qcs404: Add PCIe resets") Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index ffffaa7507cf..ffc4b081bb62 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -806,7 +806,7 @@ pcie_phy: phy@7786000 { clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, - <&gcc 21>; + <&gcc GCC_PCIE_0_PIPE_ARES>; reset-names = "phy", "pipe"; clock-output-names = "pcie_0_pipe_clk"; @@ -1337,12 +1337,12 @@ pcie: pci@10000000 { <&gcc GCC_PCIE_0_SLV_AXI_CLK>; clock-names = "iface", "aux", "master_bus", "slave_bus"; - resets = <&gcc 18>, - <&gcc 17>, - <&gcc 15>, - <&gcc 19>, + resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>, + <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>, + <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>, + <&gcc GCC_PCIE_0_CORE_STICKY_ARES>, <&gcc GCC_PCIE_0_BCR>, - <&gcc 16>; + <&gcc GCC_PCIE_0_AHB_ARES>; reset-names = "axi_m", "axi_s", "axi_m_sticky", From patchwork Mon Dec 26 04:21:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 637028 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2EA03C4708D for ; Mon, 26 Dec 2022 04:22:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231638AbiLZEW3 (ORCPT ); Sun, 25 Dec 2022 23:22:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55432 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231644AbiLZEWJ (ORCPT ); Sun, 25 Dec 2022 23:22:09 -0500 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8FB342DF0 for ; Sun, 25 Dec 2022 20:22:05 -0800 (PST) Received: by mail-lf1-x132.google.com with SMTP id g13so14672703lfv.7 for ; Sun, 25 Dec 2022 20:22:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bYtAPbaOIrpvmuNd+Z18UO1jiB4rVtL7fqIVx9X8Dkw=; b=xijE81+qRG/+QaiHQUIrDo2nHp8Q1dJL8Ql4C5JNlw753HBQ3O5S/YpuZIZqCStDwS ZdX3V88sgNikYIMeyqZP7DfvGPfCrnJq2/mNa6CnwilYPm0OJDE+rReKYbqgCIP51uHp X95f/iS2fBm9HFmvcVAlahTlqF3UZV54F+5z62O3PyJ/uit8CwWQxS9yVMRuYPAwZJJn 6D+F7/mpXgjE1eD5MfQM92j8di0qwhKqwEfepXxFkpJ411qW7oylxYODP8TelsmnFqZu lAkZxTMJhZlHfORpiTQ+27EO1vKCvp8JtWp6eqrdKsE+8G4nplC9zggZ6NRC/A3V8ml3 jJmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bYtAPbaOIrpvmuNd+Z18UO1jiB4rVtL7fqIVx9X8Dkw=; b=aHTG3d2eTUo7PIdSkc4Ofq9WXmKoHeX2cKHC3CTu3gimS3YHBvOHETUXug/OoFqeA0 bn0ng8YPhYjSlijexWXuvituqEwBVR6LG4NAUjiIo9LB2Ey4rLeje0CRmFo96LH8uYa4 nZSKED25NRq989zMLBkkwqjP58dx7Q4mV7kkw5CpfuZra7coBHMoGCHE0MaURoaoVebY X87MXsjsuO5k89QkaHeV5QJP4GnNOx34jtmjHS9uvs68mVtgMEq9MAjSaSJNB2buZcy6 kf76CWqXl+U1jja4t406cnsPq1NiDxR2W3cIc/8SlGVIAHXzFmE5IR8Vdmo3NXUgUMXq sz4w== X-Gm-Message-State: AFqh2kqrbMmZIYO7FEeg+C35qrKqavarbXAZUVTWNwIlIlZJDQfXbdAU r3aWsyG9QYyDvp5J0vH89t1SpsdG3bxSDk/imUvqPA== X-Google-Smtp-Source: AMrXdXtZFjRronhgYVZ5q4X6RAAPYK1UKVSP5s1hEQv9hUf3v2yfLOkSIuo9uN5Cb68mERnspmFs8A== X-Received: by 2002:a05:6512:b14:b0:4ca:f5a1:8896 with SMTP id w20-20020a0565120b1400b004caf5a18896mr4290367lfu.37.1672028525134; Sun, 25 Dec 2022 20:22:05 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id o9-20020ac25e29000000b004b4b5da5f80sm1641129lfg.219.2022.12.25.20.22.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Dec 2022 20:22:04 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 14/16] arm64: dts: qcom: qcs404: add power-domains-cells to gcc node Date: Mon, 26 Dec 2022 06:21:52 +0200 Message-Id: <20221226042154.2666748-15-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221226042154.2666748-1-dmitry.baryshkov@linaro.org> References: <20221226042154.2666748-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org As gcc now provides two GDSCs, add #power-domain-cells property to the gcc device node. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index ffc4b081bb62..b72542631337 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -729,6 +729,7 @@ gcc: clock-controller@1800000 { reg = <0x01800000 0x80000>; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; assigned-clock-rates = <19200000>; From patchwork Mon Dec 26 04:21:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 637027 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DB60C4708D for ; Mon, 26 Dec 2022 04:22:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231720AbiLZEWa (ORCPT ); Sun, 25 Dec 2022 23:22:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55468 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231646AbiLZEWL (ORCPT ); Sun, 25 Dec 2022 23:22:11 -0500 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3950D38AF for ; Sun, 25 Dec 2022 20:22:06 -0800 (PST) Received: by mail-lf1-x12b.google.com with SMTP id g13so14672714lfv.7 for ; Sun, 25 Dec 2022 20:22:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=C/K3RoFVEkUUUw0DjLS0gT74F0yinCMJe2iA2VdQ2lI=; b=atNI4M2yBuG99VOUYNrGxI77gagHmcuwTpqPUYjH0S7MqBQjtqbsY8kDIJRqMhbbls 0QlGX5d4pIpK9fe870P2yJstUxrrtz50oAqtZyYboaihEKnL0Z58ep4iVJIRlxPSgKhx jk+yUPMxngfL76w4Ji4ZdU+WmHrQOXs2xq/wW/1Ve5/nDB+FWRHZbWBahG6zQqVonE0z O2/hpCBwKSr3wN04uA7lhI78o7GKpdcUB7PJmrHE6JAqKVTbHi4xvHVMh45BLE4bqoj6 LcZafTWWCjgYzpZ+l9Qgtj5E/a3V+jJAqGLHKkJ+bFJ1pSk7y/905dG+S6w2bxGVc0aq rYOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=C/K3RoFVEkUUUw0DjLS0gT74F0yinCMJe2iA2VdQ2lI=; b=W2dHSbSKPrQwn0UdoPQBG069xRNEN26gJzMeukQ5rlEJFfGsm/39ECx5usef7ABrT3 D9fmgExh5RvTT0SWwy+5s0YcGarVXC0xRBtTQNxsbHDllSP7lVyl264QQxndtPPfabPt aNo6lbn7iOoEOUCU+X+q3hQkbacUCKGM8K1z7fusoN9EBYG2SztNKC0Amhk75dx9Td0b MeYYR4mP9sCMdLoYxF3pMEM4KMRe/IPjxSyhqU9oI+/FQX8MyCjxkI63gY1NZAllHyOx GgG2pos0leI7PwulvX5F7Y57ahO3CVWNOv5bm0R53xybhS5I1QsEOEZkJOYxlHCiLRZM O2pg== X-Gm-Message-State: AFqh2koFSrRQbthFmqVir0knlIY5rC3yWsgq9ak5ws90IBM5vNVJCZ27 /+MNFNEyh7mqfDAGdWDWPFGmfg== X-Google-Smtp-Source: AMrXdXtgnAdvs6Bhe5nsUVzwTXoAOHs+6uPb0RY8k5M3CsSbbKB7Gp6wYIG5W3Oi9iSMkJ+zgDG+nQ== X-Received: by 2002:a05:6512:3a8f:b0:4b5:8a01:570e with SMTP id q15-20020a0565123a8f00b004b58a01570emr5288504lfu.45.1672028525821; Sun, 25 Dec 2022 20:22:05 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id o9-20020ac25e29000000b004b4b5da5f80sm1641129lfg.219.2022.12.25.20.22.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Dec 2022 20:22:05 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 15/16] arm64: dts: qcom: qcs404: add clocks to the gcc node Date: Mon, 26 Dec 2022 06:21:53 +0200 Message-Id: <20221226042154.2666748-16-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221226042154.2666748-1-dmitry.baryshkov@linaro.org> References: <20221226042154.2666748-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Populate the gcc node with the clocks and clock-names properties to enable DT-based lookups for the parent clocks. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index b72542631337..9206ab13977f 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -731,6 +731,13 @@ gcc: clock-controller@1800000 { #reset-cells = <1>; #power-domain-cells = <1>; + clocks = <&xo_board>, + <&sleep_clk>, + <&pcie_phy>, + <0>, + <0>, + <0>; + assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; assigned-clock-rates = <19200000>; }; From patchwork Mon Dec 26 04:21:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 636848 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 242C3C3DA79 for ; Mon, 26 Dec 2022 04:22:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231653AbiLZEWi (ORCPT ); Sun, 25 Dec 2022 23:22:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55188 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231658AbiLZEWN (ORCPT ); Sun, 25 Dec 2022 23:22:13 -0500 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C8E0E5F43 for ; Sun, 25 Dec 2022 20:22:06 -0800 (PST) Received: by mail-lf1-x12b.google.com with SMTP id bq39so6883125lfb.0 for ; Sun, 25 Dec 2022 20:22:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oaGBZm9XOHdhHqe4KYTQ28e7yXtOmnBOw61TUxGxm5k=; b=qLsODe8ZuxYPrZAbOtyb38xp9A89wzwHpEyrUQYCs6ckZrrWVMhGl8dZCPZOTGH8eR m7BqgjioD8Fej5vIysG6MkdS8LSVZsfsmv2aMnOrC7zEdEWWFnHWRa81vpepshAmrE4N e9v0Eda3CvBhEffCGSxZuZHiqAlYsDfRV55NaVs0vuqGIRfpsPEWM9emzRJ4iA4AYdle 4//qzUqXQsWrMB29Fz0Dtruv1OOeB5AXoJHKNsX3ku1ouUx/9SWqnwrfpDWq5e6Yhm+x QAdfQqT/u1vQuukvy629JLDf7M9Pe/WCd7iMtzAFFE3LXhtdBd0KzDqEZyuhon382ePH 8rfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oaGBZm9XOHdhHqe4KYTQ28e7yXtOmnBOw61TUxGxm5k=; b=5d4QHlZHq47qW0mnAEyEewr1T9o8oyxuHe0uaW2IY5NYuqc6kBnmBF27Sudx446VSC fNY+GJExRIRNiQ8Px0je8QlE0o2Y1Msb1RmZlpFkQPG5ROJecgN8OO4z7EMgKtp/HHaX AK6Ci8EU+3Ug/la5PbdLmCsVAN5x3NSI43kiQyfx6fmS4VHTih6O/1MIy9X4xi4bsx/h pEyvlvCzMSmHftu/t7uwOjo3/MsJn/vBH/LpAMexrdMEkonu0Dx0lDKkqSRa+Rk2LCZL 0c4V5phq2Mlkr2p7Bw1J2zI/x0JGIu2QBp51uBzCNz7M11oaYVNRnNHpETHnpOcemRUD SF6A== X-Gm-Message-State: AFqh2kq791r1ELLZ+UO3w1gQxLO3slMLBKBeG35odJpdbRpXJo9ui7F0 rt5fm6QLDn5QVyrhJwTTRhIWUA== X-Google-Smtp-Source: AMrXdXvtiRo+vqrragM5g1xfti7wxlrI/SLa8CIobg4X6HXpizWrlLQhDUPkAHap8ev/H68xOLQXYg== X-Received: by 2002:a05:6512:1094:b0:4a4:68b9:19e7 with SMTP id j20-20020a056512109400b004a468b919e7mr5402453lfg.15.1672028526406; Sun, 25 Dec 2022 20:22:06 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id o9-20020ac25e29000000b004b4b5da5f80sm1641129lfg.219.2022.12.25.20.22.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Dec 2022 20:22:06 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 16/16] arm64: dts: qcom: qcs404: add xo clock to rpm clock controller Date: Mon, 26 Dec 2022 06:21:54 +0200 Message-Id: <20221226042154.2666748-17-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221226042154.2666748-1-dmitry.baryshkov@linaro.org> References: <20221226042154.2666748-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Populate the rpm clock controller node with clocks and clock-names properties. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 9206ab13977f..4721b3139df0 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -230,6 +230,8 @@ rpm_requests: glink-channel { rpmcc: clock-controller { compatible = "qcom,rpmcc-qcs404", "qcom,rpmcc"; #clock-cells = <1>; + clocks = <&xo_board>; + clock-names = "xo"; }; rpmpd: power-controller {