From patchwork Thu Dec 22 10:04:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gatien CHEVALLIER X-Patchwork-Id: 636135 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD393C4332F for ; Thu, 22 Dec 2022 10:07:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235039AbiLVKHv (ORCPT ); Thu, 22 Dec 2022 05:07:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59612 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230451AbiLVKHs (ORCPT ); Thu, 22 Dec 2022 05:07:48 -0500 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B63A41E735; Thu, 22 Dec 2022 02:07:43 -0800 (PST) Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2BM7iScL006623; Thu, 22 Dec 2022 11:07:14 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=selector1; bh=9lEWHCTpXo5muG8dgTfW1ehUGbdevBxdGvchXuIYBYI=; b=nLUae81sb/B8nEHkWezYe+qRi2cU/EkcAw+VzkgN5FzXyDa3HUuAyOPI7il9eK0s2ife IZepCuwAquTbAkfkHS2Sb8U8epqvqm0NmreppoVWXK/u/txgi9Z+WRvohtpPEzau0lRo rGCWPOTXYXu6P18wrK+1T0vP6ZfXI7K+R7LmkvjN+wkj+ztl5GzsdeEa985sX1bzmNII Sa65oXvvyNS3d+KM9iHq1LKijNe9maHXcvz5dtRKBpGkrn4upSCAGZmKDSwbPuGSgSC8 rx197s/xTyyFamqbMbdkvX8b70ApAxKygUF88NEYZJhwVmhTSAPMyIiEXfNkCkchxDiL Mg== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3mkc8jdtvc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 22 Dec 2022 11:07:14 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 8638810004B; Thu, 22 Dec 2022 11:07:11 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 1BC9A21D3C9; Thu, 22 Dec 2022 11:06:14 +0100 (CET) Received: from localhost (10.201.21.217) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.13; Thu, 22 Dec 2022 11:06:13 +0100 From: Gatien Chevallier To: , , , , CC: , , , , , , , , Oleksii Moisieiev Subject: [RFC PATCH v2 1/7] dt-bindings: Document common device controller bindings Date: Thu, 22 Dec 2022 11:04:58 +0100 Message-ID: <20221222100504.68247-2-gatien.chevallier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222100504.68247-1-gatien.chevallier@foss.st.com> References: <20221222100504.68247-1-gatien.chevallier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.21.217] X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-22_05,2022-12-21_01,2022-06-22_01 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Oleksii Moisieiev Introducing of the common device controller bindings for the controller provider and consumer devices. Those bindings are intended to allow divided system on chip into muliple domains, that can be used to configure hardware permissions. Signed-off-by: Oleksii Moisieiev --- .../feature-domain-controller.yaml | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml diff --git a/Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml b/Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml new file mode 100644 index 000000000000..90a7c38c833c --- /dev/null +++ b/Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/feature-controllers/feature-domain-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic Domain Controller bindings + +maintainers: + - Oleksii Moisieiev + +description: |+ + Common Feature Domains Controller bindings properties + + Domain controllers allow to divided system on chip into multiple feature + domains that can be used to select by who hardware blocks could be accessed. + A feature domain could be a cluster of CPUs (or coprocessors), a range of + addresses or a group of hardware blocks. + + This device tree bindings can be used to bind feature domain consumer devices + with their feature domains provided by feature-domains controllers. + Feature omain controller provider can be represened by any node in the + device tree and can provide one or more configuration parameters, needed to + control parameters of the consumer device. A consumer node can refer to the + provider by phandle and a set of phandle arguments, specified by + '#feature-domain-cells' property in the device controller provider node. + + Device controllers are typically used to set the permissions of the hardware + block. The contents of the feature-domains configuration properties are + defined by the binding for the individual feature-domains controller device. + + Each node can be a consumer for the several providers. The first + configuration of 'feature-domains' or the one named 'default' is applied + before probing the device itself. + +# always select the core schema +select: true + +properties: + '#feature-domain-cells': + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Number of cells in a feature-domains controller specifier; + Can be any value as specified by device tree binding documentation + of a particular provider. + + feature-domain-controller: + description: + Indicates that the node is feature-domain-controller provider. + + feature-domain-names: + $ref: '/schemas/types.yaml#/definitions/string-array' + description: + A list of feature-domains names, sorted in the same order as + feature-domains entries. Consumer drivers will use feature-domain-names + to match with existing feature-domains entries. + + feature-domains: + $ref: "/schemas/types.yaml#/definitions/phandle-array" + description: + A list of feature-domains controller specifiers, as defined by the + bindings of the feature-domain-controller provider. + +additionalProperties: true + +examples: + - | + ctrl0: ctrl@100 { + feature-domain-controller; + reg = <0x100 0x10>; + #feature-domain-cells = <2>; + }; + + ctrl1: ctrl@110 { + feature-domain-controller; + reg = <0x110 0x10>; + #feature-domain-cells = <3>; + }; + + foo@0 { + reg = <0x0 0x1>; + feature-domains = <&ctrl0 1 2>, <&ctrl1 3 4 5>; + feature-domain-names = "default", "unbind"; + }; From patchwork Thu Dec 22 10:05:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gatien CHEVALLIER X-Patchwork-Id: 636136 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F057C4332F for ; Thu, 22 Dec 2022 10:07:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235038AbiLVKHt (ORCPT ); Thu, 22 Dec 2022 05:07:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59608 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230014AbiLVKHs (ORCPT ); Thu, 22 Dec 2022 05:07:48 -0500 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 27EA61E70C; Thu, 22 Dec 2022 02:07:43 -0800 (PST) Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2BM7i883006364; Thu, 22 Dec 2022 11:07:14 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=selector1; bh=pnk0AODRWy9qchWqvydC204yIzXNjeaL4loMfcA2TJ0=; b=6cHh5eTfqfjphJSLtwtPEB8wHGVRojwoHHW+Y4ZtH4YNftfD4sgnJwuBBZqv7y7n3Yd/ UG8wfWCFd24/4V653OzMbnKHqTWfFco9QmQeB+RSYI+EhFNbXbHNw3cK/hFp05YeN2xi Rem7SLZbWJQ2XcGFr/wydIfuAPO+yDzeDNXlTZ6ovJLu375KXvRKFQyg0PkTiXUffDkY 5ToMLX+ZwgkVyq2Z/Za+mBiitjDrTw+ycgNP8t3ipZHp13yO8xJMy7/9pB0QbUEPiEu1 UhPlGb4SHjzOraQOmZkLNVOSVgWwJPt/gKR3IAKxvF4NJNTZHvrGwHVN1gPbV2BIpsjw zA== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3mkc8jdtva-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 22 Dec 2022 11:07:14 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 85F7410004A; Thu, 22 Dec 2022 11:07:11 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 9A42D21ED2E; Thu, 22 Dec 2022 11:06:55 +0100 (CET) Received: from localhost (10.201.21.217) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.13; Thu, 22 Dec 2022 11:06:55 +0100 From: Gatien Chevallier To: , , , , CC: , , , , , , , Subject: [RFC PATCH v2 4/7] dt-bindings: bus: add STM32MP13 ETZPC firewall bus bindings Date: Thu, 22 Dec 2022 11:05:01 +0100 Message-ID: <20221222100504.68247-5-gatien.chevallier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222100504.68247-1-gatien.chevallier@foss.st.com> References: <20221222100504.68247-1-gatien.chevallier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.21.217] X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-22_05,2022-12-21_01,2022-06-22_01 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Adds the list of peripherals IDs under firewall bus on STM32MP13. Signed-off-by: Gatien Chevallier --- include/dt-bindings/bus/stm32mp13_sys_bus.h | 60 +++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 include/dt-bindings/bus/stm32mp13_sys_bus.h diff --git a/include/dt-bindings/bus/stm32mp13_sys_bus.h b/include/dt-bindings/bus/stm32mp13_sys_bus.h new file mode 100644 index 000000000000..1160de87bc4a --- /dev/null +++ b/include/dt-bindings/bus/stm32mp13_sys_bus.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + */ +#ifndef _DT_BINDINGS_BUS_STM32MP13_SYS_BUS_H +#define _DT_BINDINGS_BUS_STM32MP13_SYS_BUS_H + +/* ETZPC IDs */ +#define STM32MP1_ETZPC_VREFBUF_ID 0 +#define STM32MP1_ETZPC_LPTIM2_ID 1 +#define STM32MP1_ETZPC_LPTIM3_ID 2 +#define STM32MP1_ETZPC_LTDC_ID 3 +#define STM32MP1_ETZPC_DCMIPP_ID 4 +#define STM32MP1_ETZPC_USBPHYCTRL_ID 5 +#define STM32MP1_ETZPC_DDRCTRLPHY_ID 6 +/* IDs 7-11 reserved */ +#define STM32MP1_ETZPC_IWDG1_ID 12 +#define STM32MP1_ETZPC_STGENC_ID 13 +/* IDs 14-15 reserved */ +#define STM32MP1_ETZPC_USART1_ID 16 +#define STM32MP1_ETZPC_USART2_ID 17 +#define STM32MP1_ETZPC_SPI4_ID 18 +#define STM32MP1_ETZPC_SPI5_ID 19 +#define STM32MP1_ETZPC_I2C3_ID 20 +#define STM32MP1_ETZPC_I2C4_ID 21 +#define STM32MP1_ETZPC_I2C5_ID 22 +#define STM32MP1_ETZPC_TIM12_ID 23 +#define STM32MP1_ETZPC_TIM13_ID 24 +#define STM32MP1_ETZPC_TIM14_ID 25 +#define STM32MP1_ETZPC_TIM15_ID 26 +#define STM32MP1_ETZPC_TIM16_ID 27 +#define STM32MP1_ETZPC_TIM17_ID 28 +/* IDs 29-31 reserved */ +#define STM32MP1_ETZPC_ADC1_ID 32 +#define STM32MP1_ETZPC_ADC2_ID 33 +#define STM32MP1_ETZPC_OTG_ID 34 +/* IDs 35-39 reserved */ +#define STM32MP1_ETZPC_TSC_ID 37 +#define STM32MP1_ETZPC_RNG_ID 40 +#define STM32MP1_ETZPC_HASH_ID 41 +#define STM32MP1_ETZPC_CRYP_ID 42 +#define STM32MP1_ETZPC_SAES_ID 43 +#define STM32MP1_ETZPC_PKA_ID 44 +#define STM32MP1_ETZPC_BKPSRAM_ID 45 +/* IDs 46-47 reserved */ +#define STM32MP1_ETZPC_ETH1_ID 48 +#define STM32MP1_ETZPC_ETH2_ID 49 +#define STM32MP1_ETZPC_SDMMC1_ID 50 +#define STM32MP1_ETZPC_SDMMC2_ID 51 +/* ID 52 reserved */ +#define STM32MP1_ETZPC_MCE_ID 53 +#define STM32MP1_ETZPC_FMC_ID 54 +#define STM32MP1_ETZPC_QSPI_ID 55 +/* IDs 56-59 reserved */ +#define STM32MP1_ETZPC_SRAM1_ID 60 +#define STM32MP1_ETZPC_SRAM2_ID 61 +#define STM32MP1_ETZPC_SRAM3_ID 62 +/* ID 63 reserved */ + +#endif /* _DT_BINDINGS_BUS_STM32MP13_SYS_BUS_H */ From patchwork Thu Dec 22 10:07:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gatien CHEVALLIER X-Patchwork-Id: 636134 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F878C4332F for ; Thu, 22 Dec 2022 10:09:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235153AbiLVKJU (ORCPT ); Thu, 22 Dec 2022 05:09:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60536 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235305AbiLVKIx (ORCPT ); Thu, 22 Dec 2022 05:08:53 -0500 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 172DE27926; Thu, 22 Dec 2022 02:08:32 -0800 (PST) Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2BM7i86C006371; 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Thu, 22 Dec 2022 11:08:15 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 8EE4521D3C8; Thu, 22 Dec 2022 11:08:15 +0100 (CET) Received: from localhost (10.201.21.217) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.13; Thu, 22 Dec 2022 11:08:15 +0100 From: Gatien Chevallier To: , , , , CC: , , , , , , , Subject: [RFC PATCH v2 7/7] ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards Date: Thu, 22 Dec 2022 11:07:15 +0100 Message-ID: <20221222100715.69233-8-gatien.chevallier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222100715.69233-6-gatien.chevallier@foss.st.com> References: <20221222100715.69233-6-gatien.chevallier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.21.217] X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-22_05,2022-12-21_01,2022-06-22_01 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The STM32 System Bus is an internal bus on which devices are connected. ETZPC is a peripheral overseeing the firewall bus that configures and control access to the peripherals connected on it. For more information on which peripheral is securable, please read the STM32MP13 reference manual. Signed-off-by: Gatien Chevallier --- arch/arm/boot/dts/stm32mp131.dtsi | 242 ++++++++++++++++-------------- 1 file changed, 130 insertions(+), 112 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi index dd35a607073d..0b3934fe6c34 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -3,6 +3,7 @@ * Copyright (C) STMicroelectronics 2021 - All Rights Reserved * Author: Alexandre Torgue for STMicroelectronics. */ +#include #include #include #include @@ -231,88 +232,6 @@ dmamux1: dma-router@48002000 { dma-channels = <16>; }; - spi4: spi@4c002000 { - compatible = "st,stm32h7-spi"; - reg = <0x4c002000 0x400>; - interrupts = ; - clocks = <&rcc SPI4_K>; - resets = <&rcc SPI4_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 83 0x400 0x01>, - <&dmamux1 84 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi5: spi@4c003000 { - compatible = "st,stm32h7-spi"; - reg = <0x4c003000 0x400>; - interrupts = ; - clocks = <&rcc SPI5_K>; - resets = <&rcc SPI5_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 85 0x400 0x01>, - <&dmamux1 86 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c3: i2c@4c004000 { - compatible = "st,stm32mp13-i2c"; - reg = <0x4c004000 0x400>; - interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C3_K>; - resets = <&rcc I2C3_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 73 0x400 0x1>, - <&dmamux1 74 0x400 0x1>; - dma-names = "rx", "tx"; - st,syscfg-fmp = <&syscfg 0x4 0x4>; - i2c-analog-filter; - status = "disabled"; - }; - - i2c4: i2c@4c005000 { - compatible = "st,stm32mp13-i2c"; - reg = <0x4c005000 0x400>; - interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C4_K>; - resets = <&rcc I2C4_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 75 0x400 0x1>, - <&dmamux1 76 0x400 0x1>; - dma-names = "rx", "tx"; - st,syscfg-fmp = <&syscfg 0x4 0x8>; - i2c-analog-filter; - status = "disabled"; - }; - - i2c5: i2c@4c006000 { - compatible = "st,stm32mp13-i2c"; - reg = <0x4c006000 0x400>; - interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C5_K>; - resets = <&rcc I2C5_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 115 0x400 0x1>, - <&dmamux1 116 0x400 0x1>; - dma-names = "rx", "tx"; - st,syscfg-fmp = <&syscfg 0x4 0x10>; - i2c-analog-filter; - status = "disabled"; - }; - rcc: rcc@50000000 { compatible = "st,stm32mp13-rcc", "syscon"; reg = <0x50000000 0x1000>; @@ -349,36 +268,6 @@ mdma: dma-controller@58000000 { dma-requests = <48>; }; - sdmmc1: mmc@58005000 { - compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x20253180>; - reg = <0x58005000 0x1000>, <0x58006000 0x1000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&rcc SDMMC1_K>; - clock-names = "apb_pclk"; - resets = <&rcc SDMMC1_R>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <130000000>; - status = "disabled"; - }; - - sdmmc2: mmc@58007000 { - compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x20253180>; - reg = <0x58007000 0x1000>, <0x58008000 0x1000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&rcc SDMMC2_K>; - clock-names = "apb_pclk"; - resets = <&rcc SDMMC2_R>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <130000000>; - status = "disabled"; - }; - iwdg2: watchdog@5a002000 { compatible = "st,stm32mp1-iwdg"; reg = <0x5a002000 0x400>; @@ -414,6 +303,135 @@ ts_cal2: calib@5e { }; }; + etzpc: etzpc@5c007000 { + compatible = "st,stm32mp13-sys-bus"; + reg = <0x5c007000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + feature-domain-controller; + #feature-domain-cells = <2>; + ranges; + + spi4: spi@4c002000 { + compatible = "st,stm32h7-spi"; + reg = <0x4c002000 0x400>; + interrupts = ; + clocks = <&rcc SPI4_K>; + resets = <&rcc SPI4_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 83 0x400 0x01>, + <&dmamux1 84 0x400 0x01>; + dma-names = "rx", "tx"; + feature-domains = <&etzpc STM32MP1_ETZPC_SPI4_ID>; + status = "disabled"; + }; + + spi5: spi@4c003000 { + compatible = "st,stm32h7-spi"; + reg = <0x4c003000 0x400>; + interrupts = ; + clocks = <&rcc SPI5_K>; + resets = <&rcc SPI5_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 85 0x400 0x01>, + <&dmamux1 86 0x400 0x01>; + dma-names = "rx", "tx"; + feature-domains = <&etzpc STM32MP1_ETZPC_SPI5_ID>; + status = "disabled"; + }; + + i2c3: i2c@4c004000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x4c004000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C3_K>; + resets = <&rcc I2C3_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 73 0x400 0x1>, + <&dmamux1 74 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x4>; + i2c-analog-filter; + feature-domains = <&etzpc STM32MP1_ETZPC_I2C3_ID>; + status = "disabled"; + }; + + i2c4: i2c@4c005000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x4c005000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C4_K>; + resets = <&rcc I2C4_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 75 0x400 0x1>, + <&dmamux1 76 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x8>; + i2c-analog-filter; + feature-domains = <&etzpc STM32MP1_ETZPC_I2C4_ID>; + status = "disabled"; + }; + + i2c5: i2c@4c006000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x4c006000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C5_K>; + resets = <&rcc I2C5_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 115 0x400 0x1>, + <&dmamux1 116 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x10>; + i2c-analog-filter; + feature-domains = <&etzpc STM32MP1_ETZPC_I2C5_ID>; + status = "disabled"; + }; + + sdmmc1: mmc@58005000 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x20253180>; + reg = <0x58005000 0x1000>, <0x58006000 0x1000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&rcc SDMMC1_K>; + clock-names = "apb_pclk"; + resets = <&rcc SDMMC1_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <130000000>; + feature-domains = <&etzpc STM32MP1_ETZPC_SDMMC1_ID>; + status = "disabled"; + }; + + sdmmc2: mmc@58007000 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x20253180>; + reg = <0x58007000 0x1000>, <0x58008000 0x1000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&rcc SDMMC2_K>; + clock-names = "apb_pclk"; + resets = <&rcc SDMMC2_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <130000000>; + feature-domains = <&etzpc STM32MP1_ETZPC_SDMMC2_ID>; + status = "disabled"; + }; + + }; /* * Break node order to solve dependency probe issue between * pinctrl and exti.